From patchwork Thu Feb 1 14:19:16 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Geert Uytterhoeven X-Patchwork-Id: 13541175 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 92A91C4828F for ; Thu, 1 Feb 2024 14:19:45 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:MIME-Version:References:In-Reply-To: Message-Id:Date:Subject:Cc:To:From:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; bh=K8JcnXxT/9Ws6GHYXWVkjRQ0EOwa4zfJWT80vpMYrDg=; b=WNYTb8d5vARbwS dHK0PUZ8sz8wr89SBk1WHrD8YF4Hh9npcnzRw4l1e/ekJFR8BxiFpkFzCwFbnTC3d0BOTC40exQAD 3JIpgyV0apN9SKWuO+L3vh02kCz4JPD+eTqzA8+yE+VwT76hr4ltiC3ZUGp8Ka+/+t3zMGc2aXJMO afWOFiB6j3pbhyfo3TUUUTe5eWrLWTY7UC+8TUYVh6oLFvEI3tnkfnOUhwdctvO7q9WAISEwlTSmN 8iki+AN8u/c17S0/UTBtSD0X8jJToBw7xQvlZ1TyoYlIWDJHOwKSzpqDW23MeTsja5YHEVPYoFg7Q Kev3gPUfcSrh/780ouHQ==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.97.1 #2 (Red Hat Linux)) id 1rVXug-00000008G1L-0n9I; Thu, 01 Feb 2024 14:19:34 +0000 Received: from laurent.telenet-ops.be ([2a02:1800:110:4::f00:19]) by bombadil.infradead.org with esmtps (Exim 4.97.1 #2 (Red Hat Linux)) id 1rVXuY-00000008Fum-41oW for linux-arm-kernel@lists.infradead.org; Thu, 01 Feb 2024 14:19:29 +0000 Received: from ramsan.of.borg ([IPv6:2a02:1810:ac12:ed40:88f0:c83b:bafa:cdc3]) by laurent.telenet-ops.be with bizsmtp id hqKM2B0074efzLr01qKM6R; Thu, 01 Feb 2024 15:19:21 +0100 Received: from rox.of.borg ([192.168.97.57]) by ramsan.of.borg with esmtp (Exim 4.95) (envelope-from ) id 1rVXtc-00Gv4Z-2m; Thu, 01 Feb 2024 15:19:21 +0100 Received: from geert by rox.of.borg with local (Exim 4.95) (envelope-from ) id 1rVXuT-00AXdJ-2M; Thu, 01 Feb 2024 15:19:21 +0100 From: Geert Uytterhoeven To: linux-renesas-soc@vger.kernel.org Cc: linux-arm-kernel@lists.infradead.org, Duy Nguyen , Geert Uytterhoeven Subject: [PATCH 1/5] arm64: dts: renesas: r8a779h0: Add L3 cache controller Date: Thu, 1 Feb 2024 15:19:16 +0100 Message-Id: <9d56a46892c5e0957d244370e6809013cf815905.1706796979.git.geert+renesas@glider.be> X-Mailer: git-send-email 2.34.1 In-Reply-To: References: MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20240201_061927_239275_1E6FA4AE X-CRM114-Status: GOOD ( 10.19 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org From: Duy Nguyen Describe the cache configuration for the first Cortex-A76 CPU core on the Renesas R-Car V4M (R8A779H0) SoC. Signed-off-by: Duy Nguyen Signed-off-by: Geert Uytterhoeven --- Changes compared to the BSP: - Rename L3_CA76_0 label to L3_CA76, - Rename cache-controller-0 node to cache-controller. --- arch/arm64/boot/dts/renesas/r8a779h0.dtsi | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/arch/arm64/boot/dts/renesas/r8a779h0.dtsi b/arch/arm64/boot/dts/renesas/r8a779h0.dtsi index eb555cbf51a41001..f47695158d991288 100644 --- a/arch/arm64/boot/dts/renesas/r8a779h0.dtsi +++ b/arch/arm64/boot/dts/renesas/r8a779h0.dtsi @@ -23,6 +23,14 @@ a76_0: cpu@0 { reg = <0>; device_type = "cpu"; power-domains = <&sysc R8A779H0_PD_A1E0D0C0>; + next-level-cache = <&L3_CA76>; + }; + + L3_CA76: cache-controller { + compatible = "cache"; + power-domains = <&sysc R8A779H0_PD_A2E0D0>; + cache-unified; + cache-level = <3>; }; }; From patchwork Thu Feb 1 14:19:17 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Geert Uytterhoeven X-Patchwork-Id: 13541176 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id B44B9C48291 for ; Thu, 1 Feb 2024 14:19:46 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:MIME-Version:References:In-Reply-To: Message-Id:Date:Subject:Cc:To:From:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; bh=dh6v97cM7Dw8DBHCpquhkkpDXbfO3IUcDO0KSQXIzm0=; b=saglUiLEUIyOf9 jcnlW+wHFyB8oohVjTHCnlSJXtoHHxhTzb7CRP4TYwkKUJZ/UaXdlzkSCE4hTSv/loXeKBsIn4USh x8ToFJWt/1+1tlwkrtfTqjdyNaHIqgDoAPMdRIcVVS9AqCRhoWUd+TkJOQ4tu+nCOr5RjTOtFH/JH rzCPYLvDycFHjsyTkZnunRkSE2N9rSyF8TlEJxwRSgOuGmSyXmOZtmTsV+tGb92Or8gTDd8Mn9tZT zPjtWnAv73IKvCQF3FdoNP97x3SnrVzup9vrMqeuWrZoNZTHi/YmpfyHhklP2CK53UyG5dzmsyxcC rfJucBWY09fW1s10pDTA==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.97.1 #2 (Red Hat Linux)) id 1rVXub-00000008Fyo-3PXP; Thu, 01 Feb 2024 14:19:29 +0000 Received: from xavier.telenet-ops.be ([2a02:1800:120:4::f00:14]) by bombadil.infradead.org with esmtps (Exim 4.97.1 #2 (Red Hat Linux)) id 1rVXuY-00000008Fug-2WUn for linux-arm-kernel@lists.infradead.org; Thu, 01 Feb 2024 14:19:28 +0000 Received: from ramsan.of.borg ([IPv6:2a02:1810:ac12:ed40:88f0:c83b:bafa:cdc3]) by xavier.telenet-ops.be with bizsmtp id hqKM2B0074efzLr01qKMiD; Thu, 01 Feb 2024 15:19:21 +0100 Received: from rox.of.borg ([192.168.97.57]) by ramsan.of.borg with esmtp (Exim 4.95) (envelope-from ) id 1rVXtc-00Gv4c-3P; Thu, 01 Feb 2024 15:19:21 +0100 Received: from geert by rox.of.borg with local (Exim 4.95) (envelope-from ) id 1rVXuT-00AXdM-30; Thu, 01 Feb 2024 15:19:21 +0100 From: Geert Uytterhoeven To: linux-renesas-soc@vger.kernel.org Cc: linux-arm-kernel@lists.infradead.org, Duy Nguyen , Geert Uytterhoeven Subject: [PATCH 2/5] arm64: dts: renesas: r8a779h0: Add secondary CA76 CPU cores Date: Thu, 1 Feb 2024 15:19:17 +0100 Message-Id: X-Mailer: git-send-email 2.34.1 In-Reply-To: References: MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20240201_061926_856836_BF8AE729 X-CRM114-Status: GOOD ( 10.13 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org From: Duy Nguyen Complete the description of the Cortex-A76 CPU cores and L3 cache controllers on the Renesas R-Car V4M (R8A779H0) SoC, including CPU topology and PSCI support for enabling CPU cores. Signed-off-by: Duy Nguyen Signed-off-by: Geert Uytterhoeven --- Changes compared to the BSP: - Rename L3_CA76_0 label to L3_CA76, - Move psci node to preserve sort order (alphabetical), - Drop GIC_CPU_MASK_SIMPLE changes, as GICv3 PPI interrupt specifiers have no such masks. --- arch/arm64/boot/dts/renesas/r8a779h0.dtsi | 50 +++++++++++++++++++++++ 1 file changed, 50 insertions(+) diff --git a/arch/arm64/boot/dts/renesas/r8a779h0.dtsi b/arch/arm64/boot/dts/renesas/r8a779h0.dtsi index f47695158d991288..88c5dcbc38d59dab 100644 --- a/arch/arm64/boot/dts/renesas/r8a779h0.dtsi +++ b/arch/arm64/boot/dts/renesas/r8a779h0.dtsi @@ -18,12 +18,57 @@ cpus { #address-cells = <1>; #size-cells = <0>; + cpu-map { + cluster0 { + core0 { + cpu = <&a76_0>; + }; + core1 { + cpu = <&a76_1>; + }; + core2 { + cpu = <&a76_2>; + }; + core3 { + cpu = <&a76_3>; + }; + }; + }; + a76_0: cpu@0 { compatible = "arm,cortex-a76"; reg = <0>; device_type = "cpu"; power-domains = <&sysc R8A779H0_PD_A1E0D0C0>; next-level-cache = <&L3_CA76>; + enable-method = "psci"; + }; + + a76_1: cpu@100 { + compatible = "arm,cortex-a76"; + reg = <0x100>; + device_type = "cpu"; + power-domains = <&sysc R8A779H0_PD_A1E0D0C1>; + next-level-cache = <&L3_CA76>; + enable-method = "psci"; + }; + + a76_2: cpu@200 { + compatible = "arm,cortex-a76"; + reg = <0x200>; + device_type = "cpu"; + power-domains = <&sysc R8A779H0_PD_A1E0D0C2>; + next-level-cache = <&L3_CA76>; + enable-method = "psci"; + }; + + a76_3: cpu@300 { + compatible = "arm,cortex-a76"; + reg = <0x300>; + device_type = "cpu"; + power-domains = <&sysc R8A779H0_PD_A1E0D0C3>; + next-level-cache = <&L3_CA76>; + enable-method = "psci"; }; L3_CA76: cache-controller { @@ -53,6 +98,11 @@ pmu-a76 { interrupts-extended = <&gic GIC_PPI 7 IRQ_TYPE_LEVEL_LOW>; }; + psci { + compatible = "arm,psci-1.0", "arm,psci-0.2"; + method = "smc"; + }; + /* External SCIF clock - to be overridden by boards that provide it */ scif_clk: scif-clk { compatible = "fixed-clock"; From patchwork Thu Feb 1 14:19:18 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Geert Uytterhoeven X-Patchwork-Id: 13541178 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id C274DC48292 for ; Thu, 1 Feb 2024 14:19:48 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:MIME-Version:References:In-Reply-To: Message-Id:Date:Subject:Cc:To:From:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; bh=GyFF5CBwZYlNQEibFDAZk4+ojBAt7FxeTLtPDKVKWUg=; b=I5w5JCPvClJr89 Q74mDPP+QqJNNs4e/jtZQqHm6fFby6BoUSrF2tksDR/NcD05GMbLOGHkCW73pRaBVXKXXPVdEANrL G4+Xi6OH/XXpFPI8Cqsqze+eDHjD/xNXzdareoeyWekwNWZAVhNIs1CdcrwKT1fVt/EhjsXaVI20v 4bt3B6JfTGkvxm6Jf65xj6mVgNxiJmucjQPCf8dEsuuzhShCX7Ojw7D/iQM34ylLpIMdtp+7ZommR hlo0dib7Bvmt4i/4lSWvAO1cy73isrwdiVn9TDABY/+kh6ebme7E8nwNfZXMa0EgiI/j/XBa/erv5 pCUR8FxtjiJmsJk82bVw==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.97.1 #2 (Red Hat Linux)) id 1rVXuf-00000008G0Z-1AEh; Thu, 01 Feb 2024 14:19:33 +0000 Received: from laurent.telenet-ops.be ([2a02:1800:110:4::f00:19]) by bombadil.infradead.org with esmtps (Exim 4.97.1 #2 (Red Hat Linux)) id 1rVXuY-00000008Ful-40xE for linux-arm-kernel@lists.infradead.org; Thu, 01 Feb 2024 14:19:29 +0000 Received: from ramsan.of.borg ([IPv6:2a02:1810:ac12:ed40:88f0:c83b:bafa:cdc3]) by laurent.telenet-ops.be with bizsmtp id hqKM2B0084efzLr01qKM6S; Thu, 01 Feb 2024 15:19:21 +0100 Received: from rox.of.borg ([192.168.97.57]) by ramsan.of.borg with esmtp (Exim 4.95) (envelope-from ) id 1rVXtc-00Gv4i-4c; Thu, 01 Feb 2024 15:19:21 +0100 Received: from geert by rox.of.borg with local (Exim 4.95) (envelope-from ) id 1rVXuT-00AXdR-3k; Thu, 01 Feb 2024 15:19:21 +0100 From: Geert Uytterhoeven To: linux-renesas-soc@vger.kernel.org Cc: linux-arm-kernel@lists.infradead.org, Duy Nguyen , Geert Uytterhoeven Subject: [PATCH 3/5] arm64: dts: renesas: r8a779h0: Add CPUIdle support Date: Thu, 1 Feb 2024 15:19:18 +0100 Message-Id: <848d176bdbcaf3bc44e5dae555afa9c812a19fd1.1706796979.git.geert+renesas@glider.be> X-Mailer: git-send-email 2.34.1 In-Reply-To: References: MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20240201_061927_220625_90882711 X-CRM114-Status: UNSURE ( 8.99 ) X-CRM114-Notice: Please train this message. X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org From: Duy Nguyen Support CPUIdle for ARM Cortex-A76 on R-Car V4M. Signed-off-by: Duy Nguyen Signed-off-by: Geert Uytterhoeven --- arch/arm64/boot/dts/renesas/r8a779h0.dtsi | 17 +++++++++++++++++ 1 file changed, 17 insertions(+) diff --git a/arch/arm64/boot/dts/renesas/r8a779h0.dtsi b/arch/arm64/boot/dts/renesas/r8a779h0.dtsi index 88c5dcbc38d59dab..b3255bba69e3e6da 100644 --- a/arch/arm64/boot/dts/renesas/r8a779h0.dtsi +++ b/arch/arm64/boot/dts/renesas/r8a779h0.dtsi @@ -42,6 +42,7 @@ a76_0: cpu@0 { power-domains = <&sysc R8A779H0_PD_A1E0D0C0>; next-level-cache = <&L3_CA76>; enable-method = "psci"; + cpu-idle-states = <&CPU_SLEEP_0>; }; a76_1: cpu@100 { @@ -51,6 +52,7 @@ a76_1: cpu@100 { power-domains = <&sysc R8A779H0_PD_A1E0D0C1>; next-level-cache = <&L3_CA76>; enable-method = "psci"; + cpu-idle-states = <&CPU_SLEEP_0>; }; a76_2: cpu@200 { @@ -60,6 +62,7 @@ a76_2: cpu@200 { power-domains = <&sysc R8A779H0_PD_A1E0D0C2>; next-level-cache = <&L3_CA76>; enable-method = "psci"; + cpu-idle-states = <&CPU_SLEEP_0>; }; a76_3: cpu@300 { @@ -69,6 +72,20 @@ a76_3: cpu@300 { power-domains = <&sysc R8A779H0_PD_A1E0D0C3>; next-level-cache = <&L3_CA76>; enable-method = "psci"; + cpu-idle-states = <&CPU_SLEEP_0>; + }; + + idle-states { + entry-method = "psci"; + + CPU_SLEEP_0: cpu-sleep-0 { + compatible = "arm,idle-state"; + arm,psci-suspend-param = <0x0010000>; + local-timer-stop; + entry-latency-us = <400>; + exit-latency-us = <500>; + min-residency-us = <4000>; + }; }; L3_CA76: cache-controller { From patchwork Thu Feb 1 14:19:19 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Geert Uytterhoeven X-Patchwork-Id: 13541177 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 1F5D2C4828D for ; Thu, 1 Feb 2024 14:19:48 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:MIME-Version:References:In-Reply-To: Message-Id:Date:Subject:Cc:To:From:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; bh=CfwgCbI1w5Nmqbu47Zc7vvYaAB/NaBz7VTu3ivsO+ak=; b=LxdHgeCPYK/BPg xDqlN0UL+j6a9YHysIW1ViLFk75L+x5RCmRcHrb6W5mV8RZ+HzHd3AT8FGibQUsBkHB4CilE4TECS byAYJPGwGnfWgKCg4Y2sB8/CLJI7FUPCGo0PVrA7c/8vEu9nxc1tTtB13ADYYI6rGgLN6cbvDNRk8 rzhyCmn8Q553sB8vB+muoLR55Lr4/YZb0myx14keUlZeBnsmAW6AyoroQhetRO/flsKd6jsa3F4xw h9Jhl5mAbXC9lNBYFaQIQCRFCpIiHrkjt09rV8rPDIoyQC2reeQozqkTySMhhoXx0WZdxTPlyL/9K zF3XExd8d03iDrYkgN5Q==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.97.1 #2 (Red Hat Linux)) id 1rVXud-00000008FzI-1zLn; Thu, 01 Feb 2024 14:19:31 +0000 Received: from xavier.telenet-ops.be ([2a02:1800:120:4::f00:14]) by bombadil.infradead.org with esmtps (Exim 4.97.1 #2 (Red Hat Linux)) id 1rVXuY-00000008Fui-2WUV for linux-arm-kernel@lists.infradead.org; Thu, 01 Feb 2024 14:19:29 +0000 Received: from ramsan.of.borg ([IPv6:2a02:1810:ac12:ed40:88f0:c83b:bafa:cdc3]) by xavier.telenet-ops.be with bizsmtp id hqKM2B0084efzLr01qKMiE; Thu, 01 Feb 2024 15:19:21 +0100 Received: from rox.of.borg ([192.168.97.57]) by ramsan.of.borg with esmtp (Exim 4.95) (envelope-from ) id 1rVXtc-00Gv4l-5P; Thu, 01 Feb 2024 15:19:21 +0100 Received: from geert by rox.of.borg with local (Exim 4.95) (envelope-from ) id 1rVXuT-00AXdV-4V; Thu, 01 Feb 2024 15:19:21 +0100 From: Geert Uytterhoeven To: linux-renesas-soc@vger.kernel.org Cc: linux-arm-kernel@lists.infradead.org, Duy Nguyen , Geert Uytterhoeven Subject: [PATCH 4/5] arm64: dts: renesas: r8a779h0: Add CPU core clocks Date: Thu, 1 Feb 2024 15:19:19 +0100 Message-Id: X-Mailer: git-send-email 2.34.1 In-Reply-To: References: MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20240201_061926_887489_1F15F308 X-CRM114-Status: UNSURE ( 8.55 ) X-CRM114-Notice: Please train this message. X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org From: Duy Nguyen Describe the clocks for the four Cortex-A76 CPU cores. CA76 CPU cores 0,1,2,3 are clocked by ZC0,ZC1,ZC2,ZC3. Signed-off-by: Duy Nguyen Signed-off-by: Geert Uytterhoeven --- arch/arm64/boot/dts/renesas/r8a779h0.dtsi | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/arch/arm64/boot/dts/renesas/r8a779h0.dtsi b/arch/arm64/boot/dts/renesas/r8a779h0.dtsi index b3255bba69e3e6da..622775f6160f55bd 100644 --- a/arch/arm64/boot/dts/renesas/r8a779h0.dtsi +++ b/arch/arm64/boot/dts/renesas/r8a779h0.dtsi @@ -43,6 +43,7 @@ a76_0: cpu@0 { next-level-cache = <&L3_CA76>; enable-method = "psci"; cpu-idle-states = <&CPU_SLEEP_0>; + clocks = <&cpg CPG_CORE R8A779H0_CLK_ZC0>; }; a76_1: cpu@100 { @@ -53,6 +54,7 @@ a76_1: cpu@100 { next-level-cache = <&L3_CA76>; enable-method = "psci"; cpu-idle-states = <&CPU_SLEEP_0>; + clocks = <&cpg CPG_CORE R8A779H0_CLK_ZC1>; }; a76_2: cpu@200 { @@ -63,6 +65,7 @@ a76_2: cpu@200 { next-level-cache = <&L3_CA76>; enable-method = "psci"; cpu-idle-states = <&CPU_SLEEP_0>; + clocks = <&cpg CPG_CORE R8A779H0_CLK_ZC2>; }; a76_3: cpu@300 { @@ -73,6 +76,7 @@ a76_3: cpu@300 { next-level-cache = <&L3_CA76>; enable-method = "psci"; cpu-idle-states = <&CPU_SLEEP_0>; + clocks = <&cpg CPG_CORE R8A779H0_CLK_ZC3>; }; idle-states { From patchwork Thu Feb 1 14:19:20 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Geert Uytterhoeven X-Patchwork-Id: 13541173 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 32D91C4828F for ; Thu, 1 Feb 2024 14:19:43 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:MIME-Version:References:In-Reply-To: Message-Id:Date:Subject:Cc:To:From:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; bh=p3diFWegM97xEHehw4uHR3OvNUvAjipj1A5X485HBO8=; b=YbSYP+v/uX7ppv 83E+kSDHWxC9JyMi0y6z8rmxNMY6UPC2OGBo/1sL3xaBQzJWUyxRgNM6p9fOr0a9Db9EJIjeWrg80 7cgbMJPjXuWemGixzeHe/uvEM4eWnPKxFnYssjX8tvbSW83TIhNC2r6FLeA2HCqcmWu5zVQQJhkyq YEXigpT6+1pTuJDI8GBG8jNpIyL2kIvrHTdLWyBGd6cuCZHENCSXwZMYBuU5eLLMzrwDOga1HdW2f VZoN8g2xSVzefdVHt6QUyy4oDroia6QwxlhoCBScLKt1Q+SBNwkQwlCOeT/wPpYpUWhc7hJ5aW+qJ eidZ+k7L312GY4CEt7Rg==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.97.1 #2 (Red Hat Linux)) id 1rVXuY-00000008Fwj-40Nu; Thu, 01 Feb 2024 14:19:26 +0000 Received: from andre.telenet-ops.be ([2a02:1800:120:4::f00:15]) by bombadil.infradead.org with esmtps (Exim 4.97.1 #2 (Red Hat Linux)) id 1rVXuV-00000008Fuj-0kqm for linux-arm-kernel@lists.infradead.org; Thu, 01 Feb 2024 14:19:24 +0000 Received: from ramsan.of.borg ([IPv6:2a02:1810:ac12:ed40:88f0:c83b:bafa:cdc3]) by andre.telenet-ops.be with bizsmtp id hqKM2B0054efzLr01qKMYG; Thu, 01 Feb 2024 15:19:21 +0100 Received: from rox.of.borg ([192.168.97.57]) by ramsan.of.borg with esmtp (Exim 4.95) (envelope-from ) id 1rVXtc-00Gv4r-6n; Thu, 01 Feb 2024 15:19:21 +0100 Received: from geert by rox.of.borg with local (Exim 4.95) (envelope-from ) id 1rVXuT-00AXdZ-5r; Thu, 01 Feb 2024 15:19:21 +0100 From: Geert Uytterhoeven To: linux-renesas-soc@vger.kernel.org Cc: linux-arm-kernel@lists.infradead.org, Duy Nguyen , Geert Uytterhoeven Subject: [PATCH 5/5] arm64: dts: renesas: r8a779h0: Add CA76 operating points Date: Thu, 1 Feb 2024 15:19:20 +0100 Message-Id: <736b5836ec2b54e8b36712866309dc1b7ee1fc48.1706796979.git.geert+renesas@glider.be> X-Mailer: git-send-email 2.34.1 In-Reply-To: References: MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20240201_061923_415911_BB113218 X-CRM114-Status: UNSURE ( 9.82 ) X-CRM114-Notice: Please train this message. X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org From: Duy Nguyen Add operating points for running the Cortex-A76 CPU cores on R-Car V4M at various speeds, up to the Normal (1.0 GHz). Signed-off-by: Duy Nguyen Signed-off-by: Geert Uytterhoeven --- arch/arm64/boot/dts/renesas/r8a779h0.dtsi | 20 ++++++++++++++++++++ 1 file changed, 20 insertions(+) diff --git a/arch/arm64/boot/dts/renesas/r8a779h0.dtsi b/arch/arm64/boot/dts/renesas/r8a779h0.dtsi index 622775f6160f55bd..4e9e487ec51661fd 100644 --- a/arch/arm64/boot/dts/renesas/r8a779h0.dtsi +++ b/arch/arm64/boot/dts/renesas/r8a779h0.dtsi @@ -14,6 +14,22 @@ / { #address-cells = <2>; #size-cells = <2>; + cluster0_opp: opp-table-0 { + compatible = "operating-points-v2"; + opp-shared; + + opp-500000000 { + opp-hz = /bits/ 64 <500000000>; + opp-microvolt = <825000>; + clock-latency-ns = <500000>; + }; + opp-1000000000 { + opp-hz = /bits/ 64 <1000000000>; + opp-microvolt = <825000>; + clock-latency-ns = <500000>; + }; + }; + cpus { #address-cells = <1>; #size-cells = <0>; @@ -44,6 +60,7 @@ a76_0: cpu@0 { enable-method = "psci"; cpu-idle-states = <&CPU_SLEEP_0>; clocks = <&cpg CPG_CORE R8A779H0_CLK_ZC0>; + operating-points-v2 = <&cluster0_opp>; }; a76_1: cpu@100 { @@ -55,6 +72,7 @@ a76_1: cpu@100 { enable-method = "psci"; cpu-idle-states = <&CPU_SLEEP_0>; clocks = <&cpg CPG_CORE R8A779H0_CLK_ZC1>; + operating-points-v2 = <&cluster0_opp>; }; a76_2: cpu@200 { @@ -66,6 +84,7 @@ a76_2: cpu@200 { enable-method = "psci"; cpu-idle-states = <&CPU_SLEEP_0>; clocks = <&cpg CPG_CORE R8A779H0_CLK_ZC2>; + operating-points-v2 = <&cluster0_opp>; }; a76_3: cpu@300 { @@ -77,6 +96,7 @@ a76_3: cpu@300 { enable-method = "psci"; cpu-idle-states = <&CPU_SLEEP_0>; clocks = <&cpg CPG_CORE R8A779H0_CLK_ZC3>; + operating-points-v2 = <&cluster0_opp>; }; idle-states {