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Fri, 2 Feb 2024 13:21:53 -0500 (EST) From: Jiaxun Yang Date: Fri, 02 Feb 2024 18:21:40 +0000 Subject: [PATCH 1/8] MIPS: Probe toolchain support of -msym32 Precedence: bulk X-Mailing-List: linux-mips@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-Id: <20240202-llvm-msym32-v1-1-52f0631057d6@flygoat.com> References: <20240202-llvm-msym32-v1-0-52f0631057d6@flygoat.com> In-Reply-To: <20240202-llvm-msym32-v1-0-52f0631057d6@flygoat.com> To: Thomas Bogendoerfer , Nathan Chancellor , Nick Desaulniers , Bill Wendling , Justin Stitt Cc: linux-mips@vger.kernel.org, linux-kernel@vger.kernel.org, llvm@lists.linux.dev, Jiaxun Yang X-Mailer: b4 0.12.4 X-Developer-Signature: v=1; a=openpgp-sha256; l=753; i=jiaxun.yang@flygoat.com; h=from:subject:message-id; bh=G7pEwmE2rBW0Y6l+YNkudDnlODmTUfzEzQVNoJ8fF9c=; b=owGbwMvMwCXmXMhTe71c8zDjabUkhtS9RrsNmDc1yE7SXiVesZxhCmt20av+NeUXthrxHjZcN /+9vqpFRwkLgxgXg6yYIkuIgFLfhsaLC64/yPoDM4eVCWQIAxenAEyE8ycjw3O32RMmsbVfTb5w YmXt838fOa5zb1xxRdlUfKW72wHnLfMZflxrcFzIkqgYr8a0PvDEvDWyu2zzfyg8Fbp3WnJtN58 nHwA= X-Developer-Key: i=jiaxun.yang@flygoat.com; a=openpgp; fpr=980379BEFEBFBF477EA04EF9C111949073FC0F67 msym32 is not supported by LLVM toolchain. Workaround by probe toolchain support of msym32 for KBUILD_SYM32 feature. Link: https://github.com/ClangBuiltLinux/linux/issues/1544 Signed-off-by: Jiaxun Yang --- arch/mips/Makefile | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/mips/Makefile b/arch/mips/Makefile index f49807e1f19b..0888074f4dfe 100644 --- a/arch/mips/Makefile +++ b/arch/mips/Makefile @@ -299,7 +299,7 @@ drivers-$(CONFIG_PCI) += arch/mips/pci/ ifdef CONFIG_64BIT ifndef KBUILD_SYM32 ifeq ($(shell expr $(load-y) \< 0xffffffff80000000), 0) - KBUILD_SYM32 = y + KBUILD_SYM32 = $(call cc-option-yn, -msym32) endif endif From patchwork Fri Feb 2 18:21:41 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jiaxun Yang X-Patchwork-Id: 13543252 Received: from wout5-smtp.messagingengine.com (wout5-smtp.messagingengine.com [64.147.123.21]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 2EE79150986; Fri, 2 Feb 2024 18:21:59 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; 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Fri, 2 Feb 2024 13:21:56 -0500 (EST) From: Jiaxun Yang Date: Fri, 02 Feb 2024 18:21:41 +0000 Subject: [PATCH 2/8] MIPS: Remove cc-option checks for -march=octeon Precedence: bulk X-Mailing-List: linux-mips@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-Id: <20240202-llvm-msym32-v1-2-52f0631057d6@flygoat.com> References: <20240202-llvm-msym32-v1-0-52f0631057d6@flygoat.com> In-Reply-To: <20240202-llvm-msym32-v1-0-52f0631057d6@flygoat.com> To: Thomas Bogendoerfer , Nathan Chancellor , Nick Desaulniers , Bill Wendling , Justin Stitt Cc: linux-mips@vger.kernel.org, linux-kernel@vger.kernel.org, llvm@lists.linux.dev, Jiaxun Yang X-Mailer: b4 0.12.4 X-Developer-Signature: v=1; a=openpgp-sha256; l=1156; i=jiaxun.yang@flygoat.com; h=from:subject:message-id; bh=dISe+F7C2E/OK8vn8VrH+/L47GTB4CFDBhY7zPjHwyE=; b=owGbwMvMwCXmXMhTe71c8zDjabUkhtS9Rns+XGj/k285+dCeH281Hx8W+tVWu+uLj+8k+wfHm 48uyDil3FHKwiDGxSArpsgSIqDUt6Hx4oLrD7L+wMxhZQIZwsDFKQATMahjZPhw5c/m701u/ow5 W6Z9nspU+fHQgtmBJWHr/n9sn2hUbO7EyNC4aMm9PdLPnF+vEz57rj5mywXeIj4fgemrP5aZWDy w3sUIAA== X-Developer-Key: i=jiaxun.yang@flygoat.com; a=openpgp; fpr=980379BEFEBFBF477EA04EF9C111949073FC0F67 Nowadays our minimal supported GCC/Clang all support -march=octeon. Remove cc-option checks to simplify code. Signed-off-by: Jiaxun Yang --- v0: https://lore.kernel.org/all/20230414080701.15503-6-jiaxun.yang@flygoat.com/ --- arch/mips/Makefile | 5 +---- 1 file changed, 1 insertion(+), 4 deletions(-) diff --git a/arch/mips/Makefile b/arch/mips/Makefile index 0888074f4dfe..daa569ca4372 100644 --- a/arch/mips/Makefile +++ b/arch/mips/Makefile @@ -174,10 +174,7 @@ cflags-$(CONFIG_CPU_SB1) += $(call cc-option,-mno-mdmx) cflags-$(CONFIG_CPU_SB1) += $(call cc-option,-mno-mips3d) cflags-$(CONFIG_CPU_R10000) += $(call cc-option,-march=r10000,-march=r8000) \ -Wa,--trap -cflags-$(CONFIG_CPU_CAVIUM_OCTEON) += $(call cc-option,-march=octeon) -Wa,--trap -ifeq (,$(findstring march=octeon, $(cflags-$(CONFIG_CPU_CAVIUM_OCTEON)))) -cflags-$(CONFIG_CPU_CAVIUM_OCTEON) += -Wa,-march=octeon -endif +cflags-$(CONFIG_CPU_CAVIUM_OCTEON) += -march=octeon -Wa,--trap cflags-$(CONFIG_CAVIUM_CN63XXP1) += -Wa,-mfix-cn63xxp1 cflags-$(CONFIG_CPU_BMIPS) += -march=mips32 -Wa,-mips32 -Wa,--trap From patchwork Fri Feb 2 18:21:42 2024 Content-Type: text/plain; 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Fri, 2 Feb 2024 13:21:59 -0500 (EST) From: Jiaxun Yang Date: Fri, 02 Feb 2024 18:21:42 +0000 Subject: [PATCH 3/8] MIPS: Fallback CPU -march flag to ISA level if unsupported Precedence: bulk X-Mailing-List: linux-mips@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-Id: <20240202-llvm-msym32-v1-3-52f0631057d6@flygoat.com> References: <20240202-llvm-msym32-v1-0-52f0631057d6@flygoat.com> In-Reply-To: <20240202-llvm-msym32-v1-0-52f0631057d6@flygoat.com> To: Thomas Bogendoerfer , Nathan Chancellor , Nick Desaulniers , Bill Wendling , Justin Stitt Cc: linux-mips@vger.kernel.org, linux-kernel@vger.kernel.org, llvm@lists.linux.dev, Jiaxun Yang X-Mailer: b4 0.12.4 X-Developer-Signature: v=1; a=openpgp-sha256; l=4062; i=jiaxun.yang@flygoat.com; h=from:subject:message-id; bh=3pIaTRooovaG0E4dcQJ7FyxUskX83he+uJFNra6jZ64=; b=owGbwMvMwCXmXMhTe71c8zDjabUkhtS9Rnts7QrWMnn7PVFYoXRr2sJa8bSnH67+32D1YkavW 8sVldwlHaUsDGJcDLJiiiwhAkp9GxovLrj+IOsPzBxWJpAhDFycAjCRrQcZGe6p/Ph06O5q53+i xofyy1Y5RRxXmLWjqcx36s37uTsbdisx/K9S2mThPvWkWE4e26aHNsbee56klf1I5L3g9jNiWcx jOV4A X-Developer-Key: i=jiaxun.yang@flygoat.com; a=openpgp; fpr=980379BEFEBFBF477EA04EF9C111949073FC0F67 LLVM does not implement some of -march options. However those options are not mandatory for kernel to build for those CPUs. Fallback -march CFLAG to ISA level if unsupported by toolchain so we can get those kernel to build with LLVM. Link: https://github.com/ClangBuiltLinux/linux/issues/1544 Reported-by: Nathan Chancellor Signed-off-by: Jiaxun Yang --- v0: https://lore.kernel.org/all/20230414080701.15503-7-jiaxun.yang@flygoat.com/ v1: Fix SB1 arch level to mips64 --- arch/mips/Makefile | 30 +++++++++++++++++------------- 1 file changed, 17 insertions(+), 13 deletions(-) diff --git a/arch/mips/Makefile b/arch/mips/Makefile index daa569ca4372..91470931a5b8 100644 --- a/arch/mips/Makefile +++ b/arch/mips/Makefile @@ -148,10 +148,10 @@ cflags-y += $(call cc-option,-Wa$(comma)-mno-fix-loongson3-llsc,) # # CPU-dependent compiler/assembler options for optimization. # -cflags-$(CONFIG_CPU_R3000) += -march=r3000 -cflags-$(CONFIG_CPU_R4300) += -march=r4300 -Wa,--trap -cflags-$(CONFIG_CPU_R4X00) += -march=r4600 -Wa,--trap -cflags-$(CONFIG_CPU_TX49XX) += -march=r4600 -Wa,--trap +cflags-$(CONFIG_CPU_R3000) += $(call cc-option,-march=r3000,-march=mips1) +cflags-$(CONFIG_CPU_R4300) += $(call cc-option,-march=r4300,-march=mips3) -Wa,--trap +cflags-$(CONFIG_CPU_R4X00) += $(call cc-option,-march=r4600,-march=mips3) -Wa,--trap +cflags-$(CONFIG_CPU_TX49XX) += $(call cc-option,-march=r4600,-march=mips3) -Wa,--trap cflags-$(CONFIG_CPU_MIPS32_R1) += -march=mips32 -Wa,--trap cflags-$(CONFIG_CPU_MIPS32_R2) += -march=mips32r2 -Wa,--trap cflags-$(CONFIG_CPU_MIPS32_R5) += -march=mips32r5 -Wa,--trap -modd-spreg @@ -160,26 +160,30 @@ cflags-$(CONFIG_CPU_MIPS64_R1) += -march=mips64 -Wa,--trap cflags-$(CONFIG_CPU_MIPS64_R2) += -march=mips64r2 -Wa,--trap cflags-$(CONFIG_CPU_MIPS64_R5) += -march=mips64r5 -Wa,--trap cflags-$(CONFIG_CPU_MIPS64_R6) += -march=mips64r6 -Wa,--trap -cflags-$(CONFIG_CPU_P5600) += -march=p5600 -Wa,--trap -modd-spreg -cflags-$(CONFIG_CPU_R5000) += -march=r5000 -Wa,--trap -cflags-$(CONFIG_CPU_R5500) += $(call cc-option,-march=r5500,-march=r5000) \ +cflags-$(CONFIG_CPU_P5600) += $(call cc-option,-march=p5600,-march=mips32r5) \ + -Wa,--trap -modd-spreg +cflags-$(CONFIG_CPU_R5000) += $(call cc-option,-march=r5000,-march=mips4) \ -Wa,--trap -cflags-$(CONFIG_CPU_NEVADA) += $(call cc-option,-march=rm5200,-march=r5000) \ +cflags-$(CONFIG_CPU_R5500) += $(call cc-option,-march=r5500,-march=mips4) \ -Wa,--trap -cflags-$(CONFIG_CPU_RM7000) += $(call cc-option,-march=rm7000,-march=r5000) \ +cflags-$(CONFIG_CPU_NEVADA) += $(call cc-option,-march=rm5200,-march=mips4) \ -Wa,--trap -cflags-$(CONFIG_CPU_SB1) += $(call cc-option,-march=sb1,-march=r5000) \ +cflags-$(CONFIG_CPU_RM7000) += $(call cc-option,-march=rm7000,-march=mips4) \ + -Wa,--trap +cflags-$(CONFIG_CPU_SB1) += $(call cc-option,-march=sb1,-march=mips64) \ -Wa,--trap cflags-$(CONFIG_CPU_SB1) += $(call cc-option,-mno-mdmx) cflags-$(CONFIG_CPU_SB1) += $(call cc-option,-mno-mips3d) -cflags-$(CONFIG_CPU_R10000) += $(call cc-option,-march=r10000,-march=r8000) \ +cflags-$(CONFIG_CPU_R10000) += $(call cc-option,-march=r10000,-march=mips4) \ -Wa,--trap cflags-$(CONFIG_CPU_CAVIUM_OCTEON) += -march=octeon -Wa,--trap cflags-$(CONFIG_CAVIUM_CN63XXP1) += -Wa,-mfix-cn63xxp1 cflags-$(CONFIG_CPU_BMIPS) += -march=mips32 -Wa,-mips32 -Wa,--trap -cflags-$(CONFIG_CPU_LOONGSON2E) += -march=loongson2e -Wa,--trap -cflags-$(CONFIG_CPU_LOONGSON2F) += -march=loongson2f -Wa,--trap +cflags-$(CONFIG_CPU_LOONGSON2E) += \ + $(call cc-option,-march=loongson2e,-march=mips3) -Wa,--trap +cflags-$(CONFIG_CPU_LOONGSON2F) += \ + $(call cc-option,-march=loongson2f,-march=mips3) -Wa,--trap # Some -march= flags enable MMI instructions, and GCC complains about that # support being enabled alongside -msoft-float. Thus explicitly disable MMI. cflags-$(CONFIG_CPU_LOONGSON2EF) += $(call cc-option,-mno-loongson-mmi) From patchwork Fri Feb 2 18:21:43 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jiaxun Yang X-Patchwork-Id: 13543254 Received: from wout5-smtp.messagingengine.com (wout5-smtp.messagingengine.com [64.147.123.21]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id CD6911509B2; Fri, 2 Feb 2024 18:22:06 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=64.147.123.21 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1706898128; cv=none; b=M2zyxCuzVIix7tVkJtir/Jmr9nP2Tb6E9LO65PAQLO4I2GDgOPjDda6q0rmZY1Hrh4VknGWb9sJVjwuVbUr8EWZW6fpXMNJ6du6C8uDNgo3P4mcLETUi3wiZEPPIiPUo8GKtIXuH54KLDNMGPPHSuvrEUXg1QoR3d2Vw2kNb5C4= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; 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Fri, 2 Feb 2024 13:22:03 -0500 (EST) From: Jiaxun Yang Date: Fri, 02 Feb 2024 18:21:43 +0000 Subject: [PATCH 4/8] MIPS: BMIPS: Drop unnecessary assembler flag Precedence: bulk X-Mailing-List: linux-mips@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-Id: <20240202-llvm-msym32-v1-4-52f0631057d6@flygoat.com> References: <20240202-llvm-msym32-v1-0-52f0631057d6@flygoat.com> In-Reply-To: <20240202-llvm-msym32-v1-0-52f0631057d6@flygoat.com> To: Thomas Bogendoerfer , Nathan Chancellor , Nick Desaulniers , Bill Wendling , Justin Stitt Cc: linux-mips@vger.kernel.org, linux-kernel@vger.kernel.org, llvm@lists.linux.dev, Jiaxun Yang X-Mailer: b4 0.12.4 X-Developer-Signature: v=1; a=openpgp-sha256; l=1386; i=jiaxun.yang@flygoat.com; h=from:subject:message-id; bh=371ht8cjT3hC6+X+HE+TEFeE+DMZEi/5TF0EdLjCURA=; b=owGbwMvMwCXmXMhTe71c8zDjabUkhtS9RnsMr0qGsOV8PLTcXGSx9VYmzoXG9haPWlNOX037X TWJc+GRjlIWBjEuBlkxRZYQAaW+DY0XF1x/kPUHZg4rE8gQBi5OAZhI8DlGhivTbnh2c6ZuLV/l /m+l00aB45ZiJzsm3l5xvnn747tPT/MzMvTrzxIM2a+TkHZJU/1sPVf0ScdjjIme2/U7mxmP5m5 cwAcA X-Developer-Key: i=jiaxun.yang@flygoat.com; a=openpgp; fpr=980379BEFEBFBF477EA04EF9C111949073FC0F67 Nowadays GCC will always pass -march flag to gas, so there is no need to pass another mips32 flag to assembler. Signed-off-by: Jiaxun Yang --- arch/mips/Makefile | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/arch/mips/Makefile b/arch/mips/Makefile index 91470931a5b8..5a078c5487d6 100644 --- a/arch/mips/Makefile +++ b/arch/mips/Makefile @@ -170,7 +170,7 @@ cflags-$(CONFIG_CPU_NEVADA) += $(call cc-option,-march=rm5200,-march=mips4) \ -Wa,--trap cflags-$(CONFIG_CPU_RM7000) += $(call cc-option,-march=rm7000,-march=mips4) \ -Wa,--trap -cflags-$(CONFIG_CPU_SB1) += $(call cc-option,-march=sb1,-march=mips64) \ +cflags-$(CONFIG_CPU_SB1) += $(call cc-option,-march=sb1,-march=mips64r1) \ -Wa,--trap cflags-$(CONFIG_CPU_SB1) += $(call cc-option,-mno-mdmx) cflags-$(CONFIG_CPU_SB1) += $(call cc-option,-mno-mips3d) @@ -178,7 +178,7 @@ cflags-$(CONFIG_CPU_R10000) += $(call cc-option,-march=r10000,-march=mips4) \ -Wa,--trap cflags-$(CONFIG_CPU_CAVIUM_OCTEON) += -march=octeon -Wa,--trap cflags-$(CONFIG_CAVIUM_CN63XXP1) += -Wa,-mfix-cn63xxp1 -cflags-$(CONFIG_CPU_BMIPS) += -march=mips32 -Wa,-mips32 -Wa,--trap +cflags-$(CONFIG_CPU_BMIPS) += -march=mips32 -Wa,--trap cflags-$(CONFIG_CPU_LOONGSON2E) += \ $(call cc-option,-march=loongson2e,-march=mips3) -Wa,--trap From patchwork Fri Feb 2 18:21:44 2024 Content-Type: text/plain; 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Fri, 2 Feb 2024 13:22:06 -0500 (EST) From: Jiaxun Yang Date: Fri, 02 Feb 2024 18:21:44 +0000 Subject: [PATCH 5/8] MIPS: Loongson64: test for -march=loongson3a cflag Precedence: bulk X-Mailing-List: linux-mips@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-Id: <20240202-llvm-msym32-v1-5-52f0631057d6@flygoat.com> References: <20240202-llvm-msym32-v1-0-52f0631057d6@flygoat.com> In-Reply-To: <20240202-llvm-msym32-v1-0-52f0631057d6@flygoat.com> To: Thomas Bogendoerfer , Nathan Chancellor , Nick Desaulniers , Bill Wendling , Justin Stitt Cc: linux-mips@vger.kernel.org, linux-kernel@vger.kernel.org, llvm@lists.linux.dev, Jiaxun Yang X-Mailer: b4 0.12.4 X-Developer-Signature: v=1; a=openpgp-sha256; l=1172; i=jiaxun.yang@flygoat.com; h=from:subject:message-id; bh=v3fm5XNxNbZ/kFpT9LC1Qs1K1vIdZfDhhfNiJ9dOdaE=; b=owGbwMvMwCXmXMhTe71c8zDjabUkhtS9Rnv4ejglhHL17eUe7177ou1bs0d41Mlm5wWpPXum+ ma1lxV3lLIwiHExyIopsoQIKPVtaLy44PqDrD8wc1iZQIYwcHEKwER6/zD8U+6WiWT+vzPmWs6k 5JsTZp3Iti5/FDDlW2/T5ontQQ18UowMZ0I/7bH98uhg/+WvtmFK2at2FBox7U/ycBWrVNTrddz NDQA= X-Developer-Key: i=jiaxun.yang@flygoat.com; a=openpgp; fpr=980379BEFEBFBF477EA04EF9C111949073FC0F67 Currently march flag is hardcoded to loongson3a for GCC and mips64r2 for clang. We can actually test it to simplify the code. Signed-off-by: Jiaxun Yang --- arch/mips/Makefile | 7 ++----- 1 file changed, 2 insertions(+), 5 deletions(-) diff --git a/arch/mips/Makefile b/arch/mips/Makefile index 5a078c5487d6..80aecba24892 100644 --- a/arch/mips/Makefile +++ b/arch/mips/Makefile @@ -187,11 +187,8 @@ cflags-$(CONFIG_CPU_LOONGSON2F) += \ # Some -march= flags enable MMI instructions, and GCC complains about that # support being enabled alongside -msoft-float. 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Fri, 2 Feb 2024 13:22:09 -0500 (EST) From: Jiaxun Yang Date: Fri, 02 Feb 2024 18:21:45 +0000 Subject: [PATCH 6/8] MIPS: Limit MIPS_MT_SMP support by ISA reversion Precedence: bulk X-Mailing-List: linux-mips@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-Id: <20240202-llvm-msym32-v1-6-52f0631057d6@flygoat.com> References: <20240202-llvm-msym32-v1-0-52f0631057d6@flygoat.com> In-Reply-To: <20240202-llvm-msym32-v1-0-52f0631057d6@flygoat.com> To: Thomas Bogendoerfer , Nathan Chancellor , Nick Desaulniers , Bill Wendling , Justin Stitt Cc: linux-mips@vger.kernel.org, linux-kernel@vger.kernel.org, llvm@lists.linux.dev, Jiaxun Yang , Guenter Roeck X-Mailer: b4 0.12.4 X-Developer-Signature: v=1; a=openpgp-sha256; l=961; i=jiaxun.yang@flygoat.com; h=from:subject:message-id; bh=N59Bj8/WdhFntIwAd6AT31VUOMyxOe1WmRe/HYmvrls=; b=owGbwMvMwCXmXMhTe71c8zDjabUkhtS9RnvO13XHvSx4mP4hUsvI3d41drnz7bkC4T88Du/0Y J7/gD2so5SFQYyLQVZMkSVEQKlvQ+PFBdcfZP2BmcPKBDKEgYtTACZS28fI8G1ujlNJ00vR6ZJe m47ujC6+98d0MsNBr1lJHw969UikMTAyvJ/zQDpGds+n1etCTS2Wv36tyKAQqbLl+tuDLb86GWR 52AE= X-Developer-Key: i=jiaxun.yang@flygoat.com; a=openpgp; fpr=980379BEFEBFBF477EA04EF9C111949073FC0F67 MIPS MT ASE is only available on ISA between Release 1 and Release 5. Add ISA level dependency to Kconfig to fix build. Reported-by: Guenter Roeck Signed-off-by: Jiaxun Yang --- v0: https://lore.kernel.org/all/20230414080701.15503-8-jiaxun.yang@flygoat.com/ --- arch/mips/Kconfig | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/arch/mips/Kconfig b/arch/mips/Kconfig index 797ae590ebdb..c44358a6d93e 100644 --- a/arch/mips/Kconfig +++ b/arch/mips/Kconfig @@ -2171,7 +2171,8 @@ config CPU_R4K_CACHE_TLB config MIPS_MT_SMP bool "MIPS MT SMP support (1 TC on each available VPE)" default y - depends on SYS_SUPPORTS_MULTITHREADING && !CPU_MIPSR6 && !CPU_MICROMIPS + depends on TARGET_ISA_REV > 0 && TARGET_ISA_REV < 6 + depends on SYS_SUPPORTS_MULTITHREADING && !CPU_MICROMIPS select CPU_MIPSR2_IRQ_VI select CPU_MIPSR2_IRQ_EI select SYNC_R4K From patchwork Fri Feb 2 18:21:46 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Jiaxun Yang X-Patchwork-Id: 13543257 Received: from wout5-smtp.messagingengine.com (wout5-smtp.messagingengine.com [64.147.123.21]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id EF712151CCA; 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Fri, 2 Feb 2024 13:22:13 -0500 (EST) From: Jiaxun Yang Date: Fri, 02 Feb 2024 18:21:46 +0000 Subject: [PATCH 7/8] MIPS: Implement microMIPS MT ASE helpers Precedence: bulk X-Mailing-List: linux-mips@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-Id: <20240202-llvm-msym32-v1-7-52f0631057d6@flygoat.com> References: <20240202-llvm-msym32-v1-0-52f0631057d6@flygoat.com> In-Reply-To: <20240202-llvm-msym32-v1-0-52f0631057d6@flygoat.com> To: Thomas Bogendoerfer , Nathan Chancellor , Nick Desaulniers , Bill Wendling , Justin Stitt Cc: linux-mips@vger.kernel.org, linux-kernel@vger.kernel.org, llvm@lists.linux.dev, Jiaxun Yang X-Mailer: b4 0.12.4 X-Developer-Signature: v=1; a=openpgp-sha256; l=14695; i=jiaxun.yang@flygoat.com; h=from:subject:message-id; bh=YjTBZ8cpVs/d0tQGcFu2zYjjAAYAPyu7887lmJOQ2iU=; b=owGbwMvMwCXmXMhTe71c8zDjabUkhtS9Rnv4OWzvTmaJkpXasfP1xvsTJq2O6o/PuOj34MCW8 1eK71240FHKwiDGxSArpsgSIqDUt6Hx4oLrD7L+wMxhZQIZwsDFKQATudbAyPBVbbdhRtW+3evD GcuOPF72sexd69Zbgdeb+jaYsa2pqrrAyDD5gwzDQc0+XusCr+BVFatq42Z7vU3cqRml2DPtzSr uHC4A X-Developer-Key: i=jiaxun.yang@flygoat.com; a=openpgp; fpr=980379BEFEBFBF477EA04EF9C111949073FC0F67 Implement various microMIPS MT ASE helpers accroading to: MIPS® Architecture for Programmers Volume IV-f: The MIPS® MT Module for the microMIPS32™ Architecture Fixes build error: {standard input}:2616: Error: branch to a symbol in another ISA mode This make MT ASE available on microMIPS as well. Boot tested on M5150 with microMIPS enabled on M5150. Signed-off-by: Jiaxun Yang --- v1: MTTGPR takes register name as rt --- arch/mips/include/asm/asmmacro.h | 22 ++-- arch/mips/include/asm/mipsmtregs.h | 256 ++++++++++++++++++++++--------------- arch/mips/include/asm/mipsregs.h | 9 ++ arch/mips/kernel/vpe-mt.c | 4 +- 4 files changed, 179 insertions(+), 112 deletions(-) diff --git a/arch/mips/include/asm/asmmacro.h b/arch/mips/include/asm/asmmacro.h index 067a635d3bc8..18c2ae58cdf3 100644 --- a/arch/mips/include/asm/asmmacro.h +++ b/arch/mips/include/asm/asmmacro.h @@ -216,27 +216,33 @@ * Temporary until all gas have MT ASE support */ .macro DMT reg=0 - .word 0x41600bc1 | (\reg << 16) + insn_if_mips 0x41600bc1 | (\reg << 16) + insn32_if_mm 0x0000057C | (\reg << 21) .endm .macro EMT reg=0 - .word 0x41600be1 | (\reg << 16) + insn_if_mips 0x41600be1 | (\reg << 16) + insn32_if_mm 0x0000257C | (\reg << 21) .endm .macro DVPE reg=0 - .word 0x41600001 | (\reg << 16) + insn_if_mips 0x41600001 | (\reg << 16) + insn32_if_mm 0x0000157C | (\reg << 21) .endm .macro EVPE reg=0 - .word 0x41600021 | (\reg << 16) + insn_if_mips 0x41600021 | (\reg << 16) + insn32_if_mm 0x0000357C | (\reg << 21) .endm - .macro MFTR rt=0, rd=0, u=0, sel=0 - .word 0x41000000 | (\rt << 16) | (\rd << 11) | (\u << 5) | (\sel) + .macro MFTR rs=0, rt=0, u=0, sel=0 + insn_if_mips 0x41000000 | (\rt << 16) | (\rs << 11) | (\u << 5) | (\sel) + insn32_if_mm 0x0000000E | (\rt << 21) | (\rs << 16) | (\u << 10) | (\sel << 4) .endm - .macro MTTR rt=0, rd=0, u=0, sel=0 - .word 0x41800000 | (\rt << 16) | (\rd << 11) | (\u << 5) | (\sel) + .macro MTTR rt=0, rs=0, u=0, sel=0 + insn_if_mips 0x41800000 | (\rt << 16) | (\rs << 11) | (\u << 5) | (\sel) + insn32_if_mm 0x00000006 | (\rt << 21) | (\rs << 16) | (\u << 10) | (\sel << 4) .endm #ifdef TOOLCHAIN_SUPPORTS_MSA diff --git a/arch/mips/include/asm/mipsmtregs.h b/arch/mips/include/asm/mipsmtregs.h index a8d67c2f4f7b..30e86861c206 100644 --- a/arch/mips/include/asm/mipsmtregs.h +++ b/arch/mips/include/asm/mipsmtregs.h @@ -189,19 +189,24 @@ static inline unsigned core_nvpes(void) return ((conf0 & MVPCONF0_PVPE) >> MVPCONF0_PVPE_SHIFT) + 1; } +#define _ASM_SET_DVPE \ + _ASM_MACRO_1R(dvpe, rt, \ + _ASM_INSN_IF_MIPS(0x41600001 | __rt << 16) \ + _ASM_INSN32_IF_MM(0x0000157C | __rt << 21)) +#define _ASM_UNSET_DVPE ".purgem dvpe\n\t" + static inline unsigned int dvpe(void) { int res = 0; __asm__ __volatile__( - " .set push \n" - " .set noreorder \n" - " .set noat \n" - " .set mips32r2 \n" - " .word 0x41610001 # dvpe $1 \n" - " move %0, $1 \n" - " ehb \n" - " .set pop \n" + " .set push \n" + " .set "MIPS_ISA_LEVEL" \n" + _ASM_SET_DVPE + " dvpe %0 \n" + " ehb \n" + _ASM_UNSET_DVPE + " .set pop \n" : "=r" (res)); instruction_hazard(); @@ -209,16 +214,22 @@ static inline unsigned int dvpe(void) return res; } +#define _ASM_SET_EVPE \ + _ASM_MACRO_1R(evpe, rt, \ + _ASM_INSN_IF_MIPS(0x41600021 | __rt << 16) \ + _ASM_INSN32_IF_MM(0x0000357C | __rt << 21)) +#define _ASM_UNSET_EVPE ".purgem evpe\n\t" + static inline void __raw_evpe(void) { __asm__ __volatile__( - " .set push \n" - " .set noreorder \n" - " .set noat \n" - " .set mips32r2 \n" - " .word 0x41600021 # evpe \n" - " ehb \n" - " .set pop \n"); + " .set push \n" + " .set "MIPS_ISA_LEVEL" \n" + _ASM_SET_EVPE + " evpe $0 \n" + " ehb \n" + _ASM_UNSET_EVPE + " .set pop \n"); } /* Enable virtual processor execution if previous suggested it should be. @@ -232,18 +243,24 @@ static inline void evpe(int previous) __raw_evpe(); } +#define _ASM_SET_DMT \ + _ASM_MACRO_1R(dmt, rt, \ + _ASM_INSN_IF_MIPS(0x41600bc1 | __rt << 16) \ + _ASM_INSN32_IF_MM(0x0000057C | __rt << 21)) +#define _ASM_UNSET_DMT ".purgem dmt\n\t" + static inline unsigned int dmt(void) { int res; __asm__ __volatile__( - " .set push \n" - " .set mips32r2 \n" - " .set noat \n" - " .word 0x41610BC1 # dmt $1 \n" - " ehb \n" - " move %0, $1 \n" - " .set pop \n" + " .set push \n" + " .set "MIPS_ISA_LEVEL" \n" + _ASM_SET_DMT + " dmt %0 \n" + " ehb \n" + _ASM_UNSET_DMT + " .set pop \n" : "=r" (res)); instruction_hazard(); @@ -251,14 +268,21 @@ static inline unsigned int dmt(void) return res; } +#define _ASM_SET_EMT \ + _ASM_MACRO_1R(emt, rt, \ + _ASM_INSN_IF_MIPS(0x41600be1 | __rt << 16) \ + _ASM_INSN32_IF_MM(0x0000257C | __rt << 21)) +#define _ASM_UNSET_EMT ".purgem emt\n\t" + static inline void __raw_emt(void) { __asm__ __volatile__( - " .set push \n" - " .set noreorder \n" - " .set mips32r2 \n" - " .word 0x41600be1 # emt \n" - " ehb \n" + " .set push \n" + " .set "MIPS_ISA_LEVEL" \n" + _ASM_SET_EMT + " emt $0 \n" + _ASM_UNSET_EMT + " ehb \n" " .set pop"); } @@ -276,41 +300,55 @@ static inline void emt(int previous) static inline void ehb(void) { __asm__ __volatile__( - " .set push \n" - " .set mips32r2 \n" - " ehb \n" - " .set pop \n"); + " .set push \n" + " .set "MIPS_ISA_LEVEL" \n" + " ehb \n" + " .set pop \n"); } -#define mftc0(rt,sel) \ +#define _ASM_SET_MFTC0 \ + _ASM_MACRO_2R_1S(mftc0, rs, rt, sel, \ + _ASM_INSN_IF_MIPS(0x41000000 | __rt << 16 | \ + __rs << 11 | \\sel) \ + _ASM_INSN32_IF_MM(0x0000000E | __rt << 21 | \ + __rs << 16 | \\sel << 4)) +#define _ASM_UNSET_MFTC0 ".purgem mftc0\n\t" + +#define mftc0(rt, sel) \ ({ \ - unsigned long __res; \ + unsigned long __res; \ \ __asm__ __volatile__( \ - " .set push \n" \ - " .set mips32r2 \n" \ - " .set noat \n" \ - " # mftc0 $1, $" #rt ", " #sel " \n" \ - " .word 0x41000800 | (" #rt " << 16) | " #sel " \n" \ - " move %0, $1 \n" \ - " .set pop \n" \ + " .set push \n" \ + " .set "MIPS_ISA_LEVEL" \n" \ + _ASM_SET_MFTC0 \ + " mftc0 $1, " #rt ", " #sel " \n" \ + _ASM_UNSET_MFTC0 \ + " .set pop \n" \ : "=r" (__res)); \ \ __res; \ }) +#define _ASM_SET_MFTGPR \ + _ASM_MACRO_2R(mftgpr, rs, rt, \ + _ASM_INSN_IF_MIPS(0x41000020 | __rt << 16 | \ + __rs << 11) \ + _ASM_INSN32_IF_MM(0x0000040E | __rt << 21 | \ + __rs << 16)) +#define _ASM_UNSET_MFTGPR ".purgem mftgpr\n\t" + #define mftgpr(rt) \ ({ \ unsigned long __res; \ \ __asm__ __volatile__( \ - " .set push \n" \ - " .set noat \n" \ - " .set mips32r2 \n" \ - " # mftgpr $1," #rt " \n" \ - " .word 0x41000820 | (" #rt " << 16) \n" \ - " move %0, $1 \n" \ - " .set pop \n" \ + " .set push \n" \ + " .set "MIPS_ISA_LEVEL" \n" \ + _ASM_SET_MFTGPR \ + " mftgpr %0," #rt " \n" \ + _ASM_UNSET_MFTGPR \ + " .set pop \n" \ : "=r" (__res)); \ \ __res; \ @@ -321,35 +359,49 @@ static inline void ehb(void) unsigned long __res; \ \ __asm__ __volatile__( \ - " mftr %0, " #rt ", " #u ", " #sel " \n" \ + " mftr %0, " #rt ", " #u ", " #sel " \n" \ : "=r" (__res)); \ \ __res; \ }) -#define mttgpr(rd,v) \ +#define _ASM_SET_MTTGPR \ + _ASM_MACRO_2R(mttgpr, rt, rs, \ + _ASM_INSN_IF_MIPS(0x41800020 | __rt << 16 | \ + __rs << 11) \ + _ASM_INSN32_IF_MM(0x00000406 | __rt << 21 | \ + __rs << 16)) +#define _ASM_UNSET_MTTGPR ".purgem mttgpr\n\t" + +#define mttgpr(rs, v) \ do { \ __asm__ __volatile__( \ - " .set push \n" \ - " .set mips32r2 \n" \ - " .set noat \n" \ - " move $1, %0 \n" \ - " # mttgpr $1, " #rd " \n" \ - " .word 0x41810020 | (" #rd " << 11) \n" \ - " .set pop \n" \ + " .set push \n" \ + " .set "MIPS_ISA_LEVEL" \n" \ + _ASM_SET_MTTGPR \ + " mttgpr %0, " #rs " \n" \ + _ASM_UNSET_MTTGPR \ + " .set pop \n" \ : : "r" (v)); \ } while (0) -#define mttc0(rd, sel, v) \ +#define _ASM_SET_MTTC0 \ + _ASM_MACRO_2R_1S(mttc0, rt, rs, sel, \ + _ASM_INSN_IF_MIPS(0x41800000 | __rt << 16 | \ + __rs << 11 | \\sel) \ + _ASM_INSN32_IF_MM(0x0000040E | __rt << 21 | \ + __rs << 16 | \\sel << 4)) +#define _ASM_UNSET_MTTC0 ".purgem mttc0\n\t" + +#define mttc0(rs, sel, v) \ ({ \ __asm__ __volatile__( \ - " .set push \n" \ - " .set mips32r2 \n" \ - " .set noat \n" \ - " move $1, %0 \n" \ - " # mttc0 %0," #rd ", " #sel " \n" \ - " .word 0x41810000 | (" #rd " << 11) | " #sel " \n" \ - " .set pop \n" \ + " .set push \n" \ + " .set "MIPS_ISA_LEVEL" \n" \ + _ASM_SET_MTTC0 \ + " mttc0 %0," #rs ", " #sel " \n" \ + _ASM_UNSET_MTTC0 \ + " .set pop \n" \ : \ : "r" (v)); \ }) @@ -371,49 +423,49 @@ do { \ /* you *must* set the target tc (settc) before trying to use these */ -#define read_vpe_c0_vpecontrol() mftc0(1, 1) -#define write_vpe_c0_vpecontrol(val) mttc0(1, 1, val) -#define read_vpe_c0_vpeconf0() mftc0(1, 2) -#define write_vpe_c0_vpeconf0(val) mttc0(1, 2, val) -#define read_vpe_c0_vpeconf1() mftc0(1, 3) -#define write_vpe_c0_vpeconf1(val) mttc0(1, 3, val) -#define read_vpe_c0_count() mftc0(9, 0) -#define write_vpe_c0_count(val) mttc0(9, 0, val) -#define read_vpe_c0_status() mftc0(12, 0) -#define write_vpe_c0_status(val) mttc0(12, 0, val) -#define read_vpe_c0_cause() mftc0(13, 0) -#define write_vpe_c0_cause(val) mttc0(13, 0, val) -#define read_vpe_c0_config() mftc0(16, 0) -#define write_vpe_c0_config(val) mttc0(16, 0, val) -#define read_vpe_c0_config1() mftc0(16, 1) -#define write_vpe_c0_config1(val) mttc0(16, 1, val) -#define read_vpe_c0_config7() mftc0(16, 7) -#define write_vpe_c0_config7(val) mttc0(16, 7, val) -#define read_vpe_c0_ebase() mftc0(15, 1) -#define write_vpe_c0_ebase(val) mttc0(15, 1, val) -#define write_vpe_c0_compare(val) mttc0(11, 0, val) -#define read_vpe_c0_badvaddr() mftc0(8, 0) -#define read_vpe_c0_epc() mftc0(14, 0) -#define write_vpe_c0_epc(val) mttc0(14, 0, val) +#define read_vpe_c0_vpecontrol() mftc0($1, 1) +#define write_vpe_c0_vpecontrol(val) mttc0($1, 1, val) +#define read_vpe_c0_vpeconf0() mftc0($1, 2) +#define write_vpe_c0_vpeconf0(val) mttc0($1, 2, val) +#define read_vpe_c0_vpeconf1() mftc0($1, 3) +#define write_vpe_c0_vpeconf1(val) mttc0($1, 3, val) +#define read_vpe_c0_count() mftc0($9, 0) +#define write_vpe_c0_count(val) mttc0($9, 0, val) +#define read_vpe_c0_status() mftc0($12, 0) +#define write_vpe_c0_status(val) mttc0($12, 0, val) +#define read_vpe_c0_cause() mftc0($13, 0) +#define write_vpe_c0_cause(val) mttc0($13, 0, val) +#define read_vpe_c0_config() mftc0($16, 0) +#define write_vpe_c0_config(val) mttc0($16, 0, val) +#define read_vpe_c0_config1() mftc0($16, 1) +#define write_vpe_c0_config1(val) mttc0($16, 1, val) +#define read_vpe_c0_config7() mftc0($16, 7) +#define write_vpe_c0_config7(val) mttc0($16, 7, val) +#define read_vpe_c0_ebase() mftc0($15, 1) +#define write_vpe_c0_ebase(val) mttc0($15, 1, val) +#define write_vpe_c0_compare(val) mttc0($11, 0, val) +#define read_vpe_c0_badvaddr() mftc0($8, 0) +#define read_vpe_c0_epc() mftc0($14, 0) +#define write_vpe_c0_epc(val) mttc0($14, 0, val) /* TC */ -#define read_tc_c0_tcstatus() mftc0(2, 1) -#define write_tc_c0_tcstatus(val) mttc0(2, 1, val) -#define read_tc_c0_tcbind() mftc0(2, 2) -#define write_tc_c0_tcbind(val) mttc0(2, 2, val) -#define read_tc_c0_tcrestart() mftc0(2, 3) -#define write_tc_c0_tcrestart(val) mttc0(2, 3, val) -#define read_tc_c0_tchalt() mftc0(2, 4) -#define write_tc_c0_tchalt(val) mttc0(2, 4, val) -#define read_tc_c0_tccontext() mftc0(2, 5) -#define write_tc_c0_tccontext(val) mttc0(2, 5, val) +#define read_tc_c0_tcstatus() mftc0($2, 1) +#define write_tc_c0_tcstatus(val) mttc0($2, 1, val) +#define read_tc_c0_tcbind() mftc0($2, 2) +#define write_tc_c0_tcbind(val) mttc0($2, 2, val) +#define read_tc_c0_tcrestart() mftc0($2, 3) +#define write_tc_c0_tcrestart(val) mttc0($2, 3, val) +#define read_tc_c0_tchalt() mftc0($2, 4) +#define write_tc_c0_tchalt(val) mttc0($2, 4, val) +#define read_tc_c0_tccontext() mftc0($2, 5) +#define write_tc_c0_tccontext(val) mttc0($2, 5, val) /* GPR */ -#define read_tc_gpr_sp() mftgpr(29) -#define write_tc_gpr_sp(val) mttgpr(29, val) -#define read_tc_gpr_gp() mftgpr(28) -#define write_tc_gpr_gp(val) mttgpr(28, val) +#define read_tc_gpr_sp() mftgpr($29) +#define write_tc_gpr_sp(val) mttgpr($29, val) +#define read_tc_gpr_gp() mftgpr($28) +#define write_tc_gpr_gp(val) mttgpr($28, val) __BUILD_SET_C0(mvpcontrol) diff --git a/arch/mips/include/asm/mipsregs.h b/arch/mips/include/asm/mipsregs.h index ec58cb76d076..dfb268f8aef8 100644 --- a/arch/mips/include/asm/mipsregs.h +++ b/arch/mips/include/asm/mipsregs.h @@ -1307,6 +1307,15 @@ static inline int mm_insn_16bit(u16 insn) * the ENC encodings. */ +/* Instructions with 1 register operand */ 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enucfjughrpefhfffugggtgffkfhgjvfevofesthejredtredtjeenucfhrhhomheplfhi rgiguhhnucgjrghnghcuoehjihgrgihunhdrhigrnhhgsehflhihghhorghtrdgtohhmqe enucggtffrrghtthgvrhhnpedvkeeihfefveekueevteefleffkeegudeghfdtuddugefh ueevgeffgedukeejleenucevlhhushhtvghrufhiiigvpedtnecurfgrrhgrmhepmhgrih hlfhhrohhmpehjihgrgihunhdrhigrnhhgsehflhihghhorghtrdgtohhm X-ME-Proxy: Feedback-ID: ifd894703:Fastmail Received: by mail.messagingengine.com (Postfix) with ESMTPA; Fri, 2 Feb 2024 13:22:16 -0500 (EST) From: Jiaxun Yang Date: Fri, 02 Feb 2024 18:21:47 +0000 Subject: [PATCH 8/8] MIPS: mipsregs: Set proper ISA level for virt extensions Precedence: bulk X-Mailing-List: linux-mips@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-Id: <20240202-llvm-msym32-v1-8-52f0631057d6@flygoat.com> References: <20240202-llvm-msym32-v1-0-52f0631057d6@flygoat.com> In-Reply-To: <20240202-llvm-msym32-v1-0-52f0631057d6@flygoat.com> To: Thomas Bogendoerfer , Nathan Chancellor , Nick Desaulniers , Bill Wendling , Justin Stitt Cc: linux-mips@vger.kernel.org, linux-kernel@vger.kernel.org, llvm@lists.linux.dev, Jiaxun Yang X-Mailer: b4 0.12.4 X-Developer-Signature: v=1; a=openpgp-sha256; l=2256; i=jiaxun.yang@flygoat.com; h=from:subject:message-id; bh=K9jVRbvoC4pJRRadOkCl26uHM4IaJfzZZjnpU9UIQlI=; b=owGbwMvMwCXmXMhTe71c8zDjabUkhtS9Rnu2nixsmCM6O+rPS4duvg/WzatLZL9zHnsst0Ne4 87kaUW7O0pZGMS4GGTFFFlCBJT6NjReXHD9QdYfmDmsTCBDGLg4BWAiH2IYGW4+uxO2UihTf96V q4adJ4scPk6f23Z618q+KHvBQ2eKNasZGe6IH1jJb1rA7McmvyxwUcykieyV8squk3UdpL7sXB+ pzAAA X-Developer-Key: i=jiaxun.yang@flygoat.com; a=openpgp; fpr=980379BEFEBFBF477EA04EF9C111949073FC0F67 c994a3ec7ecc ("MIPS: set mips32r5 for virt extensions") setted some instructions in virt extensions to ISA level mips32r5. However TLB related vz instructions was leftover, also this shouldn't be done to a R5 or R6 kernel buid. Reorg macros to set ISA level as needed when _ASM_SET_VIRT is called. Signed-off-by: Jiaxun Yang --- arch/mips/include/asm/mipsregs.h | 13 ++++++++----- 1 file changed, 8 insertions(+), 5 deletions(-) diff --git a/arch/mips/include/asm/mipsregs.h b/arch/mips/include/asm/mipsregs.h index dfb268f8aef8..6e97811fa936 100644 --- a/arch/mips/include/asm/mipsregs.h +++ b/arch/mips/include/asm/mipsregs.h @@ -2087,7 +2087,14 @@ do { \ _ASM_INSN_IF_MIPS(0x4200000c) \ _ASM_INSN32_IF_MM(0x0000517c) #else /* !TOOLCHAIN_SUPPORTS_VIRT */ -#define _ASM_SET_VIRT ".set\tvirt\n\t" +#if MIPS_ISA_REV >= 5 +#define _ASM_SET_VIRT_ISA +#elif defined(CONFIG_64BIT) +#define _ASM_SET_VIRT_ISA ".set\tmips64r5\n\t" +#else +#define _ASM_SET_VIRT_ISA ".set\tmips32r5\n\t" +#endif +#define _ASM_SET_VIRT _ASM_SET_VIRT_ISA ".set\tvirt\n\t" #define _ASM_SET_MFGC0 _ASM_SET_VIRT #define _ASM_SET_DMFGC0 _ASM_SET_VIRT #define _ASM_SET_MTGC0 _ASM_SET_VIRT @@ -2108,7 +2115,6 @@ do { \ ({ int __res; \ __asm__ __volatile__( \ ".set\tpush\n\t" \ - ".set\tmips32r5\n\t" \ _ASM_SET_MFGC0 \ "mfgc0\t%0, " #source ", %1\n\t" \ _ASM_UNSET_MFGC0 \ @@ -2122,7 +2128,6 @@ do { \ ({ unsigned long long __res; \ __asm__ __volatile__( \ ".set\tpush\n\t" \ - ".set\tmips64r5\n\t" \ _ASM_SET_DMFGC0 \ "dmfgc0\t%0, " #source ", %1\n\t" \ _ASM_UNSET_DMFGC0 \ @@ -2136,7 +2141,6 @@ do { \ do { \ __asm__ __volatile__( \ ".set\tpush\n\t" \ - ".set\tmips32r5\n\t" \ _ASM_SET_MTGC0 \ "mtgc0\t%z0, " #register ", %1\n\t" \ _ASM_UNSET_MTGC0 \ @@ -2149,7 +2153,6 @@ do { \ do { \ __asm__ __volatile__( \ ".set\tpush\n\t" \ - ".set\tmips64r5\n\t" \ _ASM_SET_DMTGC0 \ "dmtgc0\t%z0, " #register ", %1\n\t" \ _ASM_UNSET_DMTGC0 \