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[37.8.245.233]) by smtp.gmail.com with ESMTPSA id jy13-20020a170907762d00b00a2b1a20e662sm1396594ejc.34.2024.02.02.16.10.14 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 02 Feb 2024 16:10:15 -0800 (PST) From: Konrad Dybcio Date: Sat, 03 Feb 2024 01:10:11 +0100 Subject: [PATCH v2] arm64: dts: qcom: sm8550: Switch UFS from opp-table-hz to opp-v2 Precedence: bulk X-Mailing-List: linux-arm-msm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-Id: <20240203-topic-8550_ufs_oppv2-v2-1-b0bef2a73e6c@linaro.org> X-B4-Tracking: v=1; b=H4sIAGKEvWUC/x2N0QqDMAwAf0XyvECJVsp+ZQxpa5wBaUszZSD++ 4qPd3DcCcpVWOHZnVD5EJWcGtCjg7j69GGUuTGQocGQ6fGbi0R01pppX3TKpRyEITg3j70fonX Q0uCVMVSf4tritG9bk6XyIr/79Xpf1x9/k6ByewAAAA== To: Bjorn Andersson , Rob Herring , Krzysztof Kozlowski , Conor Dooley Cc: Marijn Suijten , linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Neil Armstrong , Konrad Dybcio X-Mailer: b4 0.12.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1706919014; l=2714; i=konrad.dybcio@linaro.org; s=20230215; h=from:subject:message-id; bh=lYrl0fMGsQMv4kqgDrYyuon4dy2WZcZ4nXzIifz7B8c=; b=D8EXau7qLW2FEu0QWtjBIB2g9tGLro6lg8B0M7x5mNj8s6R8DKRpY8zY+JUe1ksDpFPcAliVb VSrQ2IxN6o5CDOljZLF+ZgZl2DWuwBs+HVnXFOc4G945qznfSH6AqGl X-Developer-Key: i=konrad.dybcio@linaro.org; a=ed25519; pk=iclgkYvtl2w05SSXO5EjjSYlhFKsJ+5OSZBjOkQuEms= Now that the non-legacy form of OPP is supported within the UFS driver, go ahead and switch to it, adding support for more intermediate freq/power states. Signed-off-by: Konrad Dybcio Reviewed-by: Neil Armstrong Tested-by: Neil Armstrong # on SM8550-QRD --- Extracted out of: https://lore.kernel.org/linux-arm-msm/15d2bd66-29f3-435b-8494-d82ec4036413@linaro.org/#t Changes since v1: - Set the reference clock rate to 0 in opp entries, it doesn't support ratesetting anyway. Confirmed UFS still works. --- arch/arm64/boot/dts/qcom/sm8550.dtsi | 50 +++++++++++++++++++++++++++++------- 1 file changed, 41 insertions(+), 9 deletions(-) --- base-commit: 076d56d74f17e625b3d63cf4743b3d7d02180379 change-id: 20240203-topic-8550_ufs_oppv2-bb88d63a4c58 Best regards, diff --git a/arch/arm64/boot/dts/qcom/sm8550.dtsi b/arch/arm64/boot/dts/qcom/sm8550.dtsi index c89d8f3dad21..144e20edf237 100644 --- a/arch/arm64/boot/dts/qcom/sm8550.dtsi +++ b/arch/arm64/boot/dts/qcom/sm8550.dtsi @@ -1966,6 +1966,7 @@ ufs_mem_hc: ufs@1d84000 { iommus = <&apps_smmu 0x60 0x0>; dma-coherent; + operating-points-v2 = <&ufs_opp_table>; interconnects = <&aggre1_noc MASTER_UFS_MEM 0 &mc_virt SLAVE_EBI1 0>, <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_UFS_MEM_CFG 0>; @@ -1986,18 +1987,49 @@ ufs_mem_hc: ufs@1d84000 { <&gcc GCC_UFS_PHY_TX_SYMBOL_0_CLK>, <&gcc GCC_UFS_PHY_RX_SYMBOL_0_CLK>, <&gcc GCC_UFS_PHY_RX_SYMBOL_1_CLK>; - freq-table-hz = - <75000000 300000000>, - <0 0>, - <0 0>, - <75000000 300000000>, - <100000000 403000000>, - <0 0>, - <0 0>, - <0 0>; qcom,ice = <&ice>; status = "disabled"; + + ufs_opp_table: opp-table { + compatible = "operating-points-v2"; + + opp-75000000 { + opp-hz = /bits/ 64 <75000000>, + /bits/ 64 <0>, + /bits/ 64 <0>, + /bits/ 64 <75000000>, + /bits/ 64 <0>, + /bits/ 64 <0>, + /bits/ 64 <0>, + /bits/ 64 <0>; + required-opps = <&rpmhpd_opp_low_svs>; + }; + + opp-150000000 { + opp-hz = /bits/ 64 <150000000>, + /bits/ 64 <0>, + /bits/ 64 <0>, + /bits/ 64 <150000000>, + /bits/ 64 <0>, + /bits/ 64 <0>, + /bits/ 64 <0>, + /bits/ 64 <0>; + required-opps = <&rpmhpd_opp_svs>; + }; + + opp-300000000 { + opp-hz = /bits/ 64 <300000000>, + /bits/ 64 <0>, + /bits/ 64 <0>, + /bits/ 64 <300000000>, + /bits/ 64 <0>, + /bits/ 64 <0>, + /bits/ 64 <0>, + /bits/ 64 <0>; + required-opps = <&rpmhpd_opp_nom>; + }; + }; }; ice: crypto@1d88000 {