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X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: pmlNihy9pPGizQpLdLACM87jaUs209YEm9Lb7Z5c6FymDkp58gW1Z4f2bdcmZIm8A3BMwIq/ygoGf6JUQL+pnAjCJjE8p0JFEe+1A852vwtphWwOoNQq7v3CQUsvUSafvWfruL783hHrlB9oILp3bdDDipvloBoqj9SQuZp3XKuusFXps7JWqN2z5b9koV7ZPJ0HiNI81JUcNnm/ap9gao9a+W9oQnBBtZnVbr9X3YuLywkIeNAvp3mDQx7j4qscFCV/of6lvrMdJ8D2gbPB2UAH8PNxwWadMfmcXa7sXGg7JfK6AJZkuFg6QwVKba/NpcU5I+6DpOvNQetgq6bCq27EzHGhv/q44hmva3Lcl2zmM1exyquOWn6yNpWXwsdZ4gKa/DO5ScUvfH9p0N3TTMKeMQ2SEZHJcO9Y71KDoa2Pe1850IeQPI4QswJzgpviMx0xatTK9vaZ2OiUzDjKyzLYggWRaptS0YZY932T3DI5PXFCTKpO3IwHggOZavhhUQJTOuOWqv2b/lQLH3K0SmtJwP9sdfGZjedO5yZW13/2fF4X3xfKTKbzDiOszm89cp8l/QKzNkfl0yfFCSpSSLF0II5+4C3PbzgA4rl7QDcn1zPA89oOLPjfvUzRVtEgf8tdc0eowsw5QG51zyLuLl7LTZBZNCEoHT5NbF/Wg7itB8cObYyP6dwsGkquSWZPumlTB7BVUZyHc++yY7Tj/H8HyySmMKaozOVYe1I3aJ8jboRKQ7SCA9UI8MEc+7ykgmGvrDOyfYrGcR0O2FN1g3S++1pkZQIU2wls5jjHGsjc9Ei4efX/OZ7oXDX7ZCD1vb7kDbdEHbO1ut6BUUEJQGmys6dCMW3LJsLYBo4YA6hf+JgEqJFP4KV3UBl+wGtOrV5Oo+ySODkzaDdFCOYKKOM1Z1SvGmVutqYRZMLZbdc/pLQqS8VVsKgOSkza8bSijpTNZ1enzOimoHUFP5S07+hfRzCZ/aNGT94G06vZgRbiDS4+gxGucwW3IJdkJV+AkSTuGSU9Xgl1um5h/2dmsHg96Ayxj1Eh/vVxwIfMWzeVPltwocK4lhFtFK/RdP6vUIFpQiMsxnwKMRqo0nuZBYPyxtrR6EW769qsbRUGvF8BfF+RkbpUK+5jmY/YVPJENK+DkCZOnlbBhNcR1BrQtGURGbULdGnCdHaClpv1eN7LdNZanHZRG+mBr6H1dXK5sdT9BTRxjMjq0lOo5HV01Vy6xHfMpEadpCkUWrb0cGu2lZRHFlprG3kFNY8dmdVw2a1yFHGRBUiDEpnnm4K/s2vVaF6N8sgJB26BxvHbl9wqYeC501H7a6FnV95+Zy/D8TqOVHlOcTo9nMkGS19+3I6cN7GdFnyUti467d0Nfjlf9IEJnASk2OyjHpDgBTI2BAChe7XjLQ9SjHcbzDzUcgERbpFf/IDzrE774ap5eluviS2/XAB6pCbE3Pnx8tvDDD/a5mNzmF9TMa0kFA9JC1HKeOUXlbKp0+xnVywuql4D5doZ7P1WMgqBQGrYtoROwRmTqQcddhFbefzkGAZdJ7qDiGOVXG7OTWhZeqwwigtf/k2MbZ5so6BVXSEAIQLEWh1H5uJsZNZZolwntIqTzt6FLeeOuzXr0OtOHHZeXog= X-OriginatorOrg: os.amperecomputing.com X-MS-Exchange-CrossTenant-Network-Message-Id: 74c5ceb8-afd3-4e3f-2720-08dc27bbea06 X-MS-Exchange-CrossTenant-AuthSource: SJ2PR01MB8101.prod.exchangelabs.com X-MS-Exchange-CrossTenant-AuthAs: Internal X-MS-Exchange-CrossTenant-OriginalArrivalTime: 07 Feb 2024 09:05:21.9962 (UTC) X-MS-Exchange-CrossTenant-FromEntityHeader: Hosted X-MS-Exchange-CrossTenant-Id: 3bc2b170-fd94-476d-b0ce-4229bdc904a7 X-MS-Exchange-CrossTenant-MailboxType: HOSTED X-MS-Exchange-CrossTenant-UserPrincipalName: A6yTL7g8OXA4t02xbLPe5iH23qRnwdObQ76NqJrwOiVM0c/QGgKa2SdZA1Dd7ng8pg4nvQLbSJgx1UZAHLhKASC5fG5exa6emiEL7WkyePWDYsM0cvzMNaMxU9OLcv+H X-MS-Exchange-Transport-CrossTenantHeadersStamped: SN4PR01MB7518 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20240207_010534_076674_9E3D87BB X-CRM114-Status: GOOD ( 16.36 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org AmpereOne implementation is doing tlb flush when ever there is a write to vttbr_el2. As per KVM implementation, vttbr_el2 is updated with VM's S2-MMU while return to VM. This is not necessary when there is no VM context switch and a just return to same Guest. Adding a check to avoid the vttbr_el2 write if the same value already exist to prevent needless tlb flush. Signed-off-by: Ganapatrao Kulkarni --- Documentation/arch/arm64/silicon-errata.rst | 2 ++ arch/arm64/Kconfig | 13 +++++++++++++ arch/arm64/include/asm/kvm_mmu.h | 8 +++++++- arch/arm64/kernel/cpu_errata.c | 7 +++++++ arch/arm64/tools/cpucaps | 1 + 5 files changed, 30 insertions(+), 1 deletion(-) diff --git a/Documentation/arch/arm64/silicon-errata.rst b/Documentation/arch/arm64/silicon-errata.rst index e8c2ce1f9df6..8924e84358c9 100644 --- a/Documentation/arch/arm64/silicon-errata.rst +++ b/Documentation/arch/arm64/silicon-errata.rst @@ -54,6 +54,8 @@ stable kernels. +----------------+-----------------+-----------------+-----------------------------+ | Ampere | AmpereOne | AC03_CPU_38 | AMPERE_ERRATUM_AC03_CPU_38 | +----------------+-----------------+-----------------+-----------------------------+ +| Ampere | AmpereOne | N/A | AMPERE_AC03_REDUCE_TLB_FLUSH| ++----------------+-----------------+-----------------+-----------------------------+ +----------------+-----------------+-----------------+-----------------------------+ | ARM | Cortex-A510 | #2457168 | ARM64_ERRATUM_2457168 | +----------------+-----------------+-----------------+-----------------------------+ diff --git a/arch/arm64/Kconfig b/arch/arm64/Kconfig index aa7c1d435139..77485d0322e4 100644 --- a/arch/arm64/Kconfig +++ b/arch/arm64/Kconfig @@ -436,6 +436,19 @@ config AMPERE_ERRATUM_AC03_CPU_38 If unsure, say Y. +config AMPERE_AC03_REDUCE_TLB_FLUSH + bool "AmpereOne: Minimize the writes to vttbr_el2 register" + default y + help + On AmpereOne, any writes to vttbr_el2 results in TLB flush. + It can be avoided to improve the performance when there is no VM + context switches and a just return to same VM from the hypervisor. + + This option adds a check to avoid rewrite of the same value + to vttbr_el2. + + If unsure, say Y. + config ARM64_WORKAROUND_CLEAN_CACHE bool diff --git a/arch/arm64/include/asm/kvm_mmu.h b/arch/arm64/include/asm/kvm_mmu.h index e3e793d0ec30..da39e4749434 100644 --- a/arch/arm64/include/asm/kvm_mmu.h +++ b/arch/arm64/include/asm/kvm_mmu.h @@ -317,8 +317,14 @@ static __always_inline u64 kvm_get_vttbr(struct kvm_s2_mmu *mmu) static __always_inline void __load_stage2(struct kvm_s2_mmu *mmu, struct kvm_arch *arch) { + u64 vttbr; + + vttbr = kvm_get_vttbr(mmu); write_sysreg(mmu->vtcr, vtcr_el2); - write_sysreg(kvm_get_vttbr(mmu), vttbr_el2); + + if (!cpus_have_final_cap(ARM64_WORKAROUND_AMPERE_AC03_TLB_FLUSH) || + read_sysreg(vttbr_el2) != vttbr) + write_sysreg(vttbr, vttbr_el2); /* * ARM errata 1165522 and 1530923 require the actual execution of the diff --git a/arch/arm64/kernel/cpu_errata.c b/arch/arm64/kernel/cpu_errata.c index 967c7c7a4e7d..f612975e0cb5 100644 --- a/arch/arm64/kernel/cpu_errata.c +++ b/arch/arm64/kernel/cpu_errata.c @@ -740,6 +740,13 @@ const struct arm64_cpu_capabilities arm64_errata[] = { .capability = ARM64_WORKAROUND_AMPERE_AC03_CPU_38, ERRATA_MIDR_ALL_VERSIONS(MIDR_AMPERE1), }, +#endif +#ifdef CONFIG_AMPERE_AC03_REDUCE_TLB_FLUSH + { + .desc = "AmpereOne, minimize tlb flush due to vttbr write", + .capability = ARM64_WORKAROUND_AMPERE_AC03_TLB_FLUSH, + ERRATA_MIDR_ALL_VERSIONS(MIDR_AMPERE1), + }, #endif { } diff --git a/arch/arm64/tools/cpucaps b/arch/arm64/tools/cpucaps index b912b1409fc0..b4bee37d0527 100644 --- a/arch/arm64/tools/cpucaps +++ b/arch/arm64/tools/cpucaps @@ -85,6 +85,7 @@ WORKAROUND_2457168 WORKAROUND_2645198 WORKAROUND_2658417 WORKAROUND_AMPERE_AC03_CPU_38 +WORKAROUND_AMPERE_AC03_TLB_FLUSH WORKAROUND_TRBE_OVERWRITE_FILL_MODE WORKAROUND_TSB_FLUSH_FAILURE WORKAROUND_TRBE_WRITE_OUT_OF_RANGE