From patchwork Mon Feb 12 02:26:14 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Samuel Holland X-Patchwork-Id: 13552676 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id AA355C4829B for ; Mon, 12 Feb 2024 02:26:54 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:MIME-Version:Message-ID:Date:Subject:Cc :To:From:Reply-To:Content-ID:Content-Description:Resent-Date:Resent-From: Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID:In-Reply-To:References: List-Owner; bh=klJkeMLc7/RkAZtV2EGHtv/VE123KMSoUB2QHdVRDiU=; b=cQN8Cyr8l4u0/3 Rn46SO8YRWcoWFjeZF39MayTd51jb9V6X+UtJdQSaU5G6KuGR/NzpqqDo4J2lvZqV9/9KZtrEyuv7 Rs7OO3HgeEhisamPsPURPvuizTgdjxS2x2h55czXGQBrVYue7p0ER73O4Q8+ku7WvG+6JFmOtQ1mJ 8F1iTrKHUlFy+2r+N1Vtsmx57WIqvC0hf6vZCNUlLImeGs8ki2Wmgy7SKZPepJvcldLwHyOd7skNa 0gsgwB0MXdNsXqKQKZEX6+sB9TGPp04uoJhLtoSgCvb+nCOZDW+4TYTg9utvOO+X2VZC/0Kywm6md 8c/5ghL2n6Gp1Ru1dJIw==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.97.1 #2 (Red Hat Linux)) id 1rZM1x-0000000489o-1TNN; Mon, 12 Feb 2024 02:26:49 +0000 Received: from mail-pl1-x630.google.com ([2607:f8b0:4864:20::630]) by bombadil.infradead.org with esmtps (Exim 4.97.1 #2 (Red Hat Linux)) id 1rZM1u-0000000488S-17KX for linux-riscv@lists.infradead.org; Mon, 12 Feb 2024 02:26:47 +0000 Received: by mail-pl1-x630.google.com with SMTP id d9443c01a7336-1d7431e702dso22447045ad.1 for ; Sun, 11 Feb 2024 18:26:45 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=sifive.com; s=google; t=1707704804; x=1708309604; darn=lists.infradead.org; h=content-transfer-encoding:mime-version:message-id:date:subject:cc :to:from:from:to:cc:subject:date:message-id:reply-to; bh=+kIZpNvKn1kQfhO8EuiKdYkkbsLjW1fhO0uLZ9v9zVM=; b=Q/JczOvIyuAwhmjuYJVHVhMG/DHxK5QDVAFZ4x1Xc8ObIXdgFwEKJRd3ZYuQmeyD78 iJlMuonSV181r6909wAWlptmqq8csRBo3VAdP0ETb/6AiuN045HvCNQso0V02RL/SeUo Xw9N/7xZr3Cg9RWdMOPgXwpBodNmBHkP67E1L5tksgCRhUwkfZB4edS+u0dos6s1IsQd 0V2XWcbU2NCkaF2ZYpXM5y7ddy7qZyqld6w4wK91hlj3xEKsyhOGH9Ft4gPnNB6IGj6i MepV9l+FSVMGRWHMLxs1DYiClWSyrRAVoGJmzk/DFh+IMINzuDyn0rTLub8F/qk2k5SK 4GUA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1707704804; x=1708309604; h=content-transfer-encoding:mime-version:message-id:date:subject:cc :to:from:x-gm-message-state:from:to:cc:subject:date:message-id :reply-to; bh=+kIZpNvKn1kQfhO8EuiKdYkkbsLjW1fhO0uLZ9v9zVM=; b=RPfTn0D1dxQQjJ0+bMzF/8W8Pf9ksT1FAbTRPyXiq35m/6rMi/V8X+6/bSqC+NR8rD S0bwTcz6x0Zze6hTe6fyqRzho93iLUtxGqZ/ODnwXdzXvtz5fAPhZpzPNYf4ITPvnXjE 8UMcEoTZVk7jD48NG9S38yKcNWDK+YVFLFxiwCOCofSiIebWVkoZ1iyStot6odPQNxWY Lsh94TtgPyspvj2Ddb2la64GQSo0CjDJ4M9kZPCE2Ekn0ldVFiCBLpTZotBkV79d/8bM QMatyIQSAcUf9FTQbW6YZyq5tWkyGMi5awAuH4eF67uqcP/HI4sxGT+PftQ4s/T4oGKE vafw== X-Gm-Message-State: AOJu0YxOcrJzuJQoxr3llItN0ckeEzT4Wji9u8buHbyB6MLPSH6rf0aJ 4McSjbyk+9s+1Yvr/hRtjseSaE4U09YGqNA2/LTyOBOgUhfsuRZnku+guCwtG5g= X-Google-Smtp-Source: AGHT+IGPtKmdFrCoAXwq0IynPe2vhdhsmEWzTlOxO+M0NscVcWz7/5WgR2aYGbS2vfq/fGcYE/Bqvw== X-Received: by 2002:a17:902:ce8a:b0:1d9:5f11:d018 with SMTP id f10-20020a170902ce8a00b001d95f11d018mr6165050plg.1.1707704804598; Sun, 11 Feb 2024 18:26:44 -0800 (PST) X-Forwarded-Encrypted: i=1; AJvYcCUfdeKz8qQ1Wm/LNrWafjLgkv2+Xkl8QrY/iZkgowaE8IySyAhm6B7a9c9c/cifytyBUKmSpQly+vFAnwjO1HIVW1XVe+DkIvqGaDhJ43ypOJnuMyTSRDRJMdhMKGU+Az55/4QPqYlZXa82EICvNRAepdBnJg4jItKVtMxdi7IV5ihxUtDCkD/VY9r2gLvJ Received: from sw06.internal.sifive.com ([4.53.31.132]) by smtp.gmail.com with ESMTPSA id mg8-20020a170903348800b001da27cbcf5dsm1719624plb.228.2024.02.11.18.26.43 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 11 Feb 2024 18:26:44 -0800 (PST) From: Samuel Holland To: Andrew Jones , Palmer Dabbelt Cc: linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org, Samuel Holland , stable@kernel.org Subject: [PATCH -fixes 1/2] riscv: Fix enabling cbo.zero when running in M-mode Date: Sun, 11 Feb 2024 18:26:14 -0800 Message-ID: <20240212022642.1968739-1-samuel.holland@sifive.com> X-Mailer: git-send-email 2.43.0 MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20240211_182646_356646_4E23B03B X-CRM114-Status: UNSURE ( 9.92 ) X-CRM114-Notice: Please train this message. X-BeenThere: linux-riscv@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-riscv" Errors-To: linux-riscv-bounces+linux-riscv=archiver.kernel.org@lists.infradead.org When the kernel is running in M-mode, the CBZE bit must be set in the menvcfg CSR, not in senvcfg. Cc: stable@kernel.org Fixes: 43c16d51a19b ("RISC-V: Enable cbo.zero in usermode") Signed-off-by: Samuel Holland Reviewed-by: Andrew Jones --- arch/riscv/include/asm/csr.h | 2 ++ arch/riscv/kernel/cpufeature.c | 2 +- 2 files changed, 3 insertions(+), 1 deletion(-) diff --git a/arch/riscv/include/asm/csr.h b/arch/riscv/include/asm/csr.h index 510014051f5d..2468c55933cd 100644 --- a/arch/riscv/include/asm/csr.h +++ b/arch/riscv/include/asm/csr.h @@ -424,6 +424,7 @@ # define CSR_STATUS CSR_MSTATUS # define CSR_IE CSR_MIE # define CSR_TVEC CSR_MTVEC +# define CSR_ENVCFG CSR_MENVCFG # define CSR_SCRATCH CSR_MSCRATCH # define CSR_EPC CSR_MEPC # define CSR_CAUSE CSR_MCAUSE @@ -448,6 +449,7 @@ # define CSR_STATUS CSR_SSTATUS # define CSR_IE CSR_SIE # define CSR_TVEC CSR_STVEC +# define CSR_ENVCFG CSR_SENVCFG # define CSR_SCRATCH CSR_SSCRATCH # define CSR_EPC CSR_SEPC # define CSR_CAUSE CSR_SCAUSE diff --git a/arch/riscv/kernel/cpufeature.c b/arch/riscv/kernel/cpufeature.c index 89920f84d0a3..c5b13f7dd482 100644 --- a/arch/riscv/kernel/cpufeature.c +++ b/arch/riscv/kernel/cpufeature.c @@ -950,7 +950,7 @@ arch_initcall(check_unaligned_access_all_cpus); void riscv_user_isa_enable(void) { if (riscv_cpu_has_extension_unlikely(smp_processor_id(), RISCV_ISA_EXT_ZICBOZ)) - csr_set(CSR_SENVCFG, ENVCFG_CBZE); + csr_set(CSR_ENVCFG, ENVCFG_CBZE); } #ifdef CONFIG_RISCV_ALTERNATIVE From patchwork Mon Feb 12 02:26:15 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Samuel Holland X-Patchwork-Id: 13552687 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 815CDC4829A for ; Mon, 12 Feb 2024 03:30:23 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:MIME-Version:References:In-Reply-To: Message-ID:Date:Subject:Cc:To:From:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; 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Sun, 11 Feb 2024 18:26:45 -0800 (PST) X-Forwarded-Encrypted: i=1; AJvYcCXPOvgu3XozXDl5roe3CqjO7iyXASdEDHaHVU0+Ex493nHL6cFs8XhrJP3Nw6Jml5gLkIEGeMHeoGP+fR19E/IMBqsvBbVPKMFYcWiMVNcMGCFbDcaB4j71OWOlEiJZGk8nvSUzQNGobocCBcSIqBwO4/N7dqTUK21uJVKTzKcqsUMsVj0F76zf4Z3xuUTR Received: from sw06.internal.sifive.com ([4.53.31.132]) by smtp.gmail.com with ESMTPSA id mg8-20020a170903348800b001da27cbcf5dsm1719624plb.228.2024.02.11.18.26.45 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 11 Feb 2024 18:26:45 -0800 (PST) From: Samuel Holland To: Andrew Jones , Palmer Dabbelt Cc: linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org, Samuel Holland , stable@kernel.org Subject: [PATCH -fixes 2/2] riscv: Save/restore envcfg CSR during CPU suspend Date: Sun, 11 Feb 2024 18:26:15 -0800 Message-ID: <20240212022642.1968739-2-samuel.holland@sifive.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20240212022642.1968739-1-samuel.holland@sifive.com> References: <20240212022642.1968739-1-samuel.holland@sifive.com> MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20240211_182646_906521_F8FB88C0 X-CRM114-Status: GOOD ( 14.64 ) X-BeenThere: linux-riscv@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-riscv" Errors-To: linux-riscv-bounces+linux-riscv=archiver.kernel.org@lists.infradead.org The value of the [ms]envcfg CSR is lost when entering a nonretentive idle state, so the CSR must be rewritten when resuming the CPU. Because the [ms]envcfg CSR is part of the base RISC-V privileged ISA specification, it cannot be detected from the ISA string. However, most existing hardware is too old to implement this CSR. As a result, it must be probed at runtime. Extend the logic for the Zicsr ISA extension to probe for the presence of specific CSRs. Since the CSR number is encoded as an immediate value within the csrr instruction, a switch case is necessary for any CSR that must be probed this way. Use the exception table to handle the illegal instruction exception raised when the CSR is not implemented. Cc: stable@kernel.org Fixes: 43c16d51a19b ("RISC-V: Enable cbo.zero in usermode") Signed-off-by: Samuel Holland Reviewed-by: Andrew Jones --- arch/riscv/include/asm/csr.h | 23 +++++++++++++++++++++++ arch/riscv/include/asm/suspend.h | 1 + arch/riscv/kernel/cpufeature.c | 23 +++++++++++++++++++++++ arch/riscv/kernel/suspend.c | 2 ++ 4 files changed, 49 insertions(+) diff --git a/arch/riscv/include/asm/csr.h b/arch/riscv/include/asm/csr.h index 2468c55933cd..daff95feb817 100644 --- a/arch/riscv/include/asm/csr.h +++ b/arch/riscv/include/asm/csr.h @@ -542,6 +542,29 @@ : "memory"); \ }) +#define ALT_CSR_READ(csr) \ +({ \ + unsigned long __v; \ + __asm__ __volatile__ ( \ + ALTERNATIVE("li %[v], 0", "csrr %[v], %[r]", 0, \ + csr << 16 | RISCV_ISA_EXT_ZICSR, 1) \ + : [v] "=r" (__v) \ + : [r] "i" (csr) \ + : "memory"); \ + __v; \ +}) + +#define ALT_CSR_WRITE(csr, val) \ +({ \ + unsigned long __v = (unsigned long)(val); \ + __asm__ __volatile__ ( \ + ALTERNATIVE("nop", "csrw %[r], %[v]", 0, \ + csr << 16 | RISCV_ISA_EXT_ZICSR, 1) \ + : : [r] "i" (csr), [v] "rK" (__v) \ + : "memory"); \ + __v; \ +}) + #endif /* __ASSEMBLY__ */ #endif /* _ASM_RISCV_CSR_H */ diff --git a/arch/riscv/include/asm/suspend.h b/arch/riscv/include/asm/suspend.h index 02f87867389a..491296a335d0 100644 --- a/arch/riscv/include/asm/suspend.h +++ b/arch/riscv/include/asm/suspend.h @@ -14,6 +14,7 @@ struct suspend_context { struct pt_regs regs; /* Saved and restored by high-level functions */ unsigned long scratch; + unsigned long envcfg; unsigned long tvec; unsigned long ie; #ifdef CONFIG_MMU diff --git a/arch/riscv/kernel/cpufeature.c b/arch/riscv/kernel/cpufeature.c index c5b13f7dd482..934090270ae5 100644 --- a/arch/riscv/kernel/cpufeature.c +++ b/arch/riscv/kernel/cpufeature.c @@ -954,6 +954,27 @@ void riscv_user_isa_enable(void) } #ifdef CONFIG_RISCV_ALTERNATIVE +static bool riscv_cpufeature_probe_csr(u16 csr) +{ + bool ret = false; + + switch (csr) { +#define PROBE_CSR_CASE(_csr) \ + case _csr: \ + asm("1: csrr zero, %[csr]\n" \ + " li %[r], 1\n" \ + "2:\n" \ + _ASM_EXTABLE(1b, 2b) \ + : [r] "+r" (ret) \ + : [csr] "i" (_csr)); \ + break + PROBE_CSR_CASE(CSR_ENVCFG); +#undef PROBE_CSR_CASE + } + + return ret; +} + /* * Alternative patch sites consider 48 bits when determining when to patch * the old instruction sequence with the new. These bits are broken into a @@ -974,6 +995,8 @@ static bool riscv_cpufeature_patch_check(u16 id, u16 value) return true; switch (id) { + case RISCV_ISA_EXT_ZICSR: + return riscv_cpufeature_probe_csr(value); case RISCV_ISA_EXT_ZICBOZ: /* * Zicboz alternative applications provide the maximum diff --git a/arch/riscv/kernel/suspend.c b/arch/riscv/kernel/suspend.c index 239509367e42..fe544f12a5c5 100644 --- a/arch/riscv/kernel/suspend.c +++ b/arch/riscv/kernel/suspend.c @@ -15,6 +15,7 @@ void suspend_save_csrs(struct suspend_context *context) { context->scratch = csr_read(CSR_SCRATCH); + context->envcfg = ALT_CSR_READ(CSR_ENVCFG); context->tvec = csr_read(CSR_TVEC); context->ie = csr_read(CSR_IE); @@ -36,6 +37,7 @@ void suspend_save_csrs(struct suspend_context *context) void suspend_restore_csrs(struct suspend_context *context) { csr_write(CSR_SCRATCH, context->scratch); + ALT_CSR_WRITE(CSR_ENVCFG, context->envcfg); csr_write(CSR_TVEC, context->tvec); csr_write(CSR_IE, context->ie);