From patchwork Mon Feb 12 11:37:08 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Biju Das X-Patchwork-Id: 13552970 X-Patchwork-Delegate: geert@linux-m68k.org Received: from relmlie5.idc.renesas.com (relmlor1.renesas.com [210.160.252.171]) by smtp.subspace.kernel.org (Postfix) with ESMTP id 4E18824B57 for ; Mon, 12 Feb 2024 11:37:26 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=210.160.252.171 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1707737849; cv=none; b=ct5DI28fY4RVWtBBFM2vPU16z0K24fr5tfZ6tzH9CsPdmYXMeVgkzDUsHPYXfDPNU/79KO96ysWULzN38OMsnX/KO739WekhSfhy4gAE5wxWmNlLZfV0uv7RmjnuA499uUGQPyZ6YBqAhKzwlkiNYTPcJhquYIBO5j8IVZvznwI= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1707737849; c=relaxed/simple; bh=RIVxkBsMCAi17kQFjBPikwksQcnIJ9vrtIR7V3mK8U4=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=FDnFRUAwCdEWFWMpR91jXkmxUjovFV+S5Ob+3OaiRmW/gGZrLM8OinsOvbydOVpDA32iN2fO1sHzf8WtaVtMt3fTHozY8Xu7UDlO4hK7LCLndrXeJ6kgkDuAx1Em2dkutNiMEAP87Q2oCtxEIIMfKGxE/k9HUApGROntxA89hhk= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=bp.renesas.com; spf=pass smtp.mailfrom=bp.renesas.com; arc=none smtp.client-ip=210.160.252.171 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=bp.renesas.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=bp.renesas.com X-IronPort-AV: E=Sophos;i="6.05,263,1701097200"; d="scan'208";a="193656664" Received: from unknown (HELO relmlir6.idc.renesas.com) ([10.200.68.152]) by relmlie5.idc.renesas.com with ESMTP; 12 Feb 2024 20:37:20 +0900 Received: from localhost.localdomain (unknown [10.226.92.40]) by relmlir6.idc.renesas.com (Postfix) with ESMTP id 4874641A9A9B; Mon, 12 Feb 2024 20:37:18 +0900 (JST) From: Biju Das To: Thomas Gleixner Cc: Biju Das , Lad Prabhakar , Marc Zyngier , Geert Uytterhoeven , Biju Das , linux-renesas-soc@vger.kernel.org Subject: [PATCH 1/5] irqchip/renesas-rzg2l: Prevent IRQ HW race Date: Mon, 12 Feb 2024 11:37:08 +0000 Message-Id: <20240212113712.71878-2-biju.das.jz@bp.renesas.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20240212113712.71878-1-biju.das.jz@bp.renesas.com> References: <20240212113712.71878-1-biju.das.jz@bp.renesas.com> Precedence: bulk X-Mailing-List: linux-renesas-soc@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 As per section "8.8.2 Clear Timing of Interrupt Cause" of the RZ/G2L hardware manual (Rev.1.45 Jan, 2024), it is mentioned that we need to clear the interrupt cause flag in the isr. It takes some time for the cpu to clear the interrupt cause flag. Therefore, to prevent another occurrence of interrupt due to this delay, the interrupt cause flag is read after clearing. Fixes: 3fed09559cd8 ("irqchip: Add RZ/G2L IA55 Interrupt Controller driver") Signed-off-by: Biju Das --- drivers/irqchip/irq-renesas-rzg2l.c | 5 ++++- 1 file changed, 4 insertions(+), 1 deletion(-) diff --git a/drivers/irqchip/irq-renesas-rzg2l.c b/drivers/irqchip/irq-renesas-rzg2l.c index 9494fc26259c..46f9b07e0e8a 100644 --- a/drivers/irqchip/irq-renesas-rzg2l.c +++ b/drivers/irqchip/irq-renesas-rzg2l.c @@ -111,8 +111,11 @@ static void rzg2l_tint_eoi(struct irq_data *d) u32 reg; reg = readl_relaxed(priv->base + TSCR); - if (reg & bit) + if (reg & bit) { writel_relaxed(reg & ~bit, priv->base + TSCR); + /* Read to avoid irq generation due to irq clearing delay */ + readl_relaxed(priv->base + TSCR); + } } static void rzg2l_irqc_eoi(struct irq_data *d) From patchwork Mon Feb 12 11:37:09 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Biju Das X-Patchwork-Id: 13552972 X-Patchwork-Delegate: geert@linux-m68k.org Received: from relmlie6.idc.renesas.com (relmlor2.renesas.com [210.160.252.172]) by smtp.subspace.kernel.org (Postfix) with ESMTP id 5B49B39843 for ; Mon, 12 Feb 2024 11:37:29 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=210.160.252.172 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1707737852; cv=none; b=LFV6LiPfiiLWgzaAKHRqdWbm0oh0MwWbQdTzyMfH2z8geUcPviEkCORvr30Hl8ApgkfJnTUnP8CmD1DeSxpzQssQqE0Q8+hvW8XhlRcjTBDOBjws+W0HDSmd+LVGyE/nuCa2gwQM3UZ1uCtEtaCHjatx287PqTL4QE0tnAAQkUg= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1707737852; c=relaxed/simple; bh=dHYkbNy0rqXKoKhOrkeAWaX2PGmX+UlSFCrXuGbrQ1E=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=swuQ5Udhvr4Yi9pRauQ+HFlMBaeYormvp7tonxM3PLeoPpqf66ZHkjNP45Z8tJ7GeVxeJdXRNPuD2CuMhxPR/eSpnvBgZ97Dy8hDE6IBcPK+wtq/7iOaNWJv9+5Bv2TYc3PvqUsSwtuPKwenT53XjujWHD9T+9uAeSJa1l4E660= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=bp.renesas.com; spf=pass smtp.mailfrom=bp.renesas.com; arc=none smtp.client-ip=210.160.252.172 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=bp.renesas.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=bp.renesas.com X-IronPort-AV: E=Sophos;i="6.06,263,1705330800"; d="scan'208";a="197568523" Received: from unknown (HELO relmlir6.idc.renesas.com) ([10.200.68.152]) by relmlie6.idc.renesas.com with ESMTP; 12 Feb 2024 20:37:23 +0900 Received: from localhost.localdomain (unknown [10.226.92.40]) by relmlir6.idc.renesas.com (Postfix) with ESMTP id 26DC841A9A88; Mon, 12 Feb 2024 20:37:20 +0900 (JST) From: Biju Das To: Thomas Gleixner Cc: Biju Das , Lad Prabhakar , Marc Zyngier , Geert Uytterhoeven , Biju Das , linux-renesas-soc@vger.kernel.org Subject: [PATCH 2/5] irqchip/renesas-rzg2l: Rename rzg2l_tint_eoi() Date: Mon, 12 Feb 2024 11:37:09 +0000 Message-Id: <20240212113712.71878-3-biju.das.jz@bp.renesas.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20240212113712.71878-1-biju.das.jz@bp.renesas.com> References: <20240212113712.71878-1-biju.das.jz@bp.renesas.com> Precedence: bulk X-Mailing-List: linux-renesas-soc@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Rename rzg2l_tint_eoi->rzg2l_clear_tint_int and simplify the code by removing redundant priv and hw_irq local variables. Signed-off-by: Biju Das Reviewed-by: Geert Uytterhoeven --- drivers/irqchip/irq-renesas-rzg2l.c | 9 ++++----- 1 file changed, 4 insertions(+), 5 deletions(-) diff --git a/drivers/irqchip/irq-renesas-rzg2l.c b/drivers/irqchip/irq-renesas-rzg2l.c index 46f9b07e0e8a..74c8cbb790e9 100644 --- a/drivers/irqchip/irq-renesas-rzg2l.c +++ b/drivers/irqchip/irq-renesas-rzg2l.c @@ -103,11 +103,10 @@ static void rzg2l_irq_eoi(struct irq_data *d) writel_relaxed(iscr & ~bit, priv->base + ISCR); } -static void rzg2l_tint_eoi(struct irq_data *d) +static void rzg2l_clear_tint_int(struct rzg2l_irqc_priv *priv, + unsigned int hwirq) { - unsigned int hw_irq = irqd_to_hwirq(d) - IRQC_TINT_START; - struct rzg2l_irqc_priv *priv = irq_data_to_priv(d); - u32 bit = BIT(hw_irq); + u32 bit = BIT(hwirq - IRQC_TINT_START); u32 reg; reg = readl_relaxed(priv->base + TSCR); @@ -127,7 +126,7 @@ static void rzg2l_irqc_eoi(struct irq_data *d) if (hw_irq >= IRQC_IRQ_START && hw_irq <= IRQC_IRQ_COUNT) rzg2l_irq_eoi(d); else if (hw_irq >= IRQC_TINT_START && hw_irq < IRQC_NUM_IRQ) - rzg2l_tint_eoi(d); + rzg2l_clear_tint_int(priv, hw_irq); raw_spin_unlock(&priv->lock); irq_chip_eoi_parent(d); } From patchwork Mon Feb 12 11:37:10 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Biju Das X-Patchwork-Id: 13552971 X-Patchwork-Delegate: geert@linux-m68k.org Received: from relmlie5.idc.renesas.com (relmlor1.renesas.com [210.160.252.171]) by smtp.subspace.kernel.org (Postfix) with ESMTP id 77AD638FB2 for ; Mon, 12 Feb 2024 11:37:27 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=210.160.252.171 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1707737850; cv=none; b=KB1hjaIvE+DHyB31g+jgW0IrsvlX1I7T3Igl01JnyV/4/BI3ZuOyXcLV6JeW0keMFGUNvrpXnijDiVaft+ARCgsYUle9fxwySk4JrkczuLMFPOEfUjZVQf9GxlqaC+KdSIE9UL6yL0NX2UsLAPk2rbnoxshX4e2SgdIfJnVBO2A= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1707737850; c=relaxed/simple; bh=gSvCi7qd29H+tj2NAmf+fBPay38d9/OwVw4izpJKzoo=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=WCC176k0IqBvjirEKsFTNDBnz8NVKrG3IgbVl0ZiZolGWxyrOTGySUyNZDHhTXB+0ioQBCqnyxAe+pfZlAazIp+nM2rm1yzlvC+FY7n/OdfsXAZFMacI3/hZQpflyQmRM0NspOtwSNn/elF0r3STzd2mNam65gAMshFnptg0P0U= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=bp.renesas.com; spf=pass smtp.mailfrom=bp.renesas.com; arc=none smtp.client-ip=210.160.252.171 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=bp.renesas.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=bp.renesas.com X-IronPort-AV: E=Sophos;i="6.05,263,1701097200"; d="scan'208";a="193656668" Received: from unknown (HELO relmlir6.idc.renesas.com) ([10.200.68.152]) by relmlie5.idc.renesas.com with ESMTP; 12 Feb 2024 20:37:26 +0900 Received: from localhost.localdomain (unknown [10.226.92.40]) by relmlir6.idc.renesas.com (Postfix) with ESMTP id 09F7141A9A83; Mon, 12 Feb 2024 20:37:23 +0900 (JST) From: Biju Das To: Thomas Gleixner Cc: Biju Das , Lad Prabhakar , Marc Zyngier , Geert Uytterhoeven , Biju Das , linux-renesas-soc@vger.kernel.org Subject: [PATCH 3/5] irqchip/renesas-rzg2l: Fix spurious TINT IRQ Date: Mon, 12 Feb 2024 11:37:10 +0000 Message-Id: <20240212113712.71878-4-biju.das.jz@bp.renesas.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20240212113712.71878-1-biju.das.jz@bp.renesas.com> References: <20240212113712.71878-1-biju.das.jz@bp.renesas.com> Precedence: bulk X-Mailing-List: linux-renesas-soc@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 As per RZ/G2L hardware manual Rev.1.45 section 8.8.3 Precaution when changing interrupt settings, we need to mask the interrupts while setting the interrupt detection method. Apart from this we need to clear interrupt status after setting TINT interrupt detection method to the edge type. First disable TINT enable and then set TINT source. After that set edge type and then clear the interrupt status register. Fixes: 3fed09559cd8 ("irqchip: Add RZ/G2L IA55 Interrupt Controller driver") Signed-off-by: Biju Das --- drivers/irqchip/irq-renesas-rzg2l.c | 46 ++++++++++++++++++++++++++++- 1 file changed, 45 insertions(+), 1 deletion(-) diff --git a/drivers/irqchip/irq-renesas-rzg2l.c b/drivers/irqchip/irq-renesas-rzg2l.c index 74c8cbb790e9..c48c8e836dd1 100644 --- a/drivers/irqchip/irq-renesas-rzg2l.c +++ b/drivers/irqchip/irq-renesas-rzg2l.c @@ -117,6 +117,40 @@ static void rzg2l_clear_tint_int(struct rzg2l_irqc_priv *priv, } } +static void rzg2l_tint_endisable(struct rzg2l_irqc_priv *priv, u32 reg, + u32 tssr_offset, u32 tssr_index, + bool enable) +{ + if (enable) + reg |= TIEN << TSSEL_SHIFT(tssr_offset); + else + reg &= ~(TIEN << TSSEL_SHIFT(tssr_offset)); + + writel_relaxed(reg, priv->base + TSSR(tssr_index)); +} + +static void rzg2l_disable_tint_and_set_tint_source(struct irq_data *d, + struct rzg2l_irqc_priv *priv, + u32 reg, u32 tssr_offset, + u8 tssr_index) +{ + unsigned long tint = (uintptr_t)irq_data_get_irq_chip_data(d); + u32 val; + + rzg2l_tint_endisable(priv, reg, tssr_offset, tssr_index, false); + val = (reg >> TSSEL_SHIFT(tssr_offset)) & ~TIEN; + if (tint != val) { + reg |= tint << TSSEL_SHIFT(tssr_offset); + writel_relaxed(reg, priv->base + TSSR(tssr_index)); + } +} + +static bool rzg2l_is_tint_enabled(struct rzg2l_irqc_priv *priv, u32 reg, + u32 tssr_offset) +{ + return !!(reg & (TIEN << TSSEL_SHIFT(tssr_offset))); +} + static void rzg2l_irqc_eoi(struct irq_data *d) { struct rzg2l_irqc_priv *priv = irq_data_to_priv(d); @@ -214,8 +248,11 @@ static int rzg2l_tint_set_edge(struct irq_data *d, unsigned int type) struct rzg2l_irqc_priv *priv = irq_data_to_priv(d); unsigned int hwirq = irqd_to_hwirq(d); u32 titseln = hwirq - IRQC_TINT_START; + u32 tssr_offset = TSSR_OFFSET(titseln); + u8 tssr_index = TSSR_INDEX(titseln); + bool tint_enable; u8 index, sense; - u32 reg; + u32 reg, tssr; switch (type & IRQ_TYPE_SENSE_MASK) { case IRQ_TYPE_EDGE_RISING: @@ -237,10 +274,17 @@ static int rzg2l_tint_set_edge(struct irq_data *d, unsigned int type) } raw_spin_lock(&priv->lock); + tssr = readl_relaxed(priv->base + TSSR(tssr_index)); + tint_enable = rzg2l_is_tint_enabled(priv, tssr, tssr_offset); + rzg2l_disable_tint_and_set_tint_source(d, priv, tssr, + tssr_offset, tssr_index); reg = readl_relaxed(priv->base + TITSR(index)); reg &= ~(IRQ_MASK << (titseln * TITSEL_WIDTH)); reg |= sense << (titseln * TITSEL_WIDTH); writel_relaxed(reg, priv->base + TITSR(index)); + rzg2l_clear_tint_int(priv, hwirq); + if (tint_enable) + rzg2l_tint_endisable(priv, tssr, tssr_offset, tssr_index, true); raw_spin_unlock(&priv->lock); return 0; From patchwork Mon Feb 12 11:37:11 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Biju Das X-Patchwork-Id: 13552973 X-Patchwork-Delegate: geert@linux-m68k.org Received: from relmlie6.idc.renesas.com (relmlor2.renesas.com [210.160.252.172]) by smtp.subspace.kernel.org (Postfix) with ESMTP id 51AA839857 for ; Mon, 12 Feb 2024 11:37:32 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; 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spf=pass smtp.mailfrom=bp.renesas.com X-IronPort-AV: E=Sophos;i="6.06,263,1705330800"; d="scan'208";a="197568527" Received: from unknown (HELO relmlir6.idc.renesas.com) ([10.200.68.152]) by relmlie6.idc.renesas.com with ESMTP; 12 Feb 2024 20:37:29 +0900 Received: from localhost.localdomain (unknown [10.226.92.40]) by relmlir6.idc.renesas.com (Postfix) with ESMTP id DD75741A9A88; Mon, 12 Feb 2024 20:37:26 +0900 (JST) From: Biju Das To: Thomas Gleixner Cc: Biju Das , Lad Prabhakar , Marc Zyngier , Geert Uytterhoeven , Biju Das , linux-renesas-soc@vger.kernel.org Subject: [PATCH 4/5] irqchip/renesas-rzg2l: Use TIEN for enable/disable Date: Mon, 12 Feb 2024 11:37:11 +0000 Message-Id: <20240212113712.71878-5-biju.das.jz@bp.renesas.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20240212113712.71878-1-biju.das.jz@bp.renesas.com> References: <20240212113712.71878-1-biju.das.jz@bp.renesas.com> Precedence: bulk X-Mailing-List: linux-renesas-soc@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Use TIEN for enable/disable and avoid modifying TINT source selection register. Signed-off-by: Biju Das --- drivers/irqchip/irq-renesas-rzg2l.c | 8 ++------ 1 file changed, 2 insertions(+), 6 deletions(-) diff --git a/drivers/irqchip/irq-renesas-rzg2l.c b/drivers/irqchip/irq-renesas-rzg2l.c index c48c8e836dd1..fbee400985a9 100644 --- a/drivers/irqchip/irq-renesas-rzg2l.c +++ b/drivers/irqchip/irq-renesas-rzg2l.c @@ -35,7 +35,6 @@ #define TSSR(n) (0x30 + ((n) * 4)) #define TIEN BIT(7) #define TSSEL_SHIFT(n) (8 * (n)) -#define TSSEL_MASK GENMASK(7, 0) #define IRQ_MASK 0x3 #define TSSR_OFFSET(n) ((n) % 4) @@ -178,8 +177,7 @@ static void rzg2l_irqc_irq_disable(struct irq_data *d) raw_spin_lock(&priv->lock); reg = readl_relaxed(priv->base + TSSR(tssr_index)); - reg &= ~(TSSEL_MASK << TSSEL_SHIFT(tssr_offset)); - writel_relaxed(reg, priv->base + TSSR(tssr_index)); + rzg2l_tint_endisable(priv, reg, tssr_offset, tssr_index, false); raw_spin_unlock(&priv->lock); } irq_chip_disable_parent(d); @@ -190,7 +188,6 @@ static void rzg2l_irqc_irq_enable(struct irq_data *d) unsigned int hw_irq = irqd_to_hwirq(d); if (hw_irq >= IRQC_TINT_START && hw_irq < IRQC_NUM_IRQ) { - unsigned long tint = (uintptr_t)irq_data_get_irq_chip_data(d); struct rzg2l_irqc_priv *priv = irq_data_to_priv(d); u32 offset = hw_irq - IRQC_TINT_START; u32 tssr_offset = TSSR_OFFSET(offset); @@ -199,8 +196,7 @@ static void rzg2l_irqc_irq_enable(struct irq_data *d) raw_spin_lock(&priv->lock); reg = readl_relaxed(priv->base + TSSR(tssr_index)); - reg |= (TIEN | tint) << TSSEL_SHIFT(tssr_offset); - writel_relaxed(reg, priv->base + TSSR(tssr_index)); + rzg2l_tint_endisable(priv, reg, tssr_offset, tssr_index, true); raw_spin_unlock(&priv->lock); } irq_chip_enable_parent(d); From patchwork Mon Feb 12 11:37:12 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Biju Das X-Patchwork-Id: 13552974 X-Patchwork-Delegate: geert@linux-m68k.org Received: from relmlie5.idc.renesas.com (relmlor1.renesas.com [210.160.252.171]) by smtp.subspace.kernel.org (Postfix) with ESMTP id 9B53E39843 for ; Mon, 12 Feb 2024 11:37:33 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=210.160.252.171 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1707737855; cv=none; b=CUuIcAnSdZOqN2eM63Pr76gMSLXwoqgDWZrEGGgMquGUh0vVPjRhZtxvj1Lf8AUrAJOtNe4FjwxA8lMcC3jNBsuxzQAUM6ce8fhGfCOgHlUtpXk1whJfNMj2nIvvwI1X4iY4JDwM14llt8pwBPfzXqXMQNeCiTAySVbpSv9k9YU= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1707737855; c=relaxed/simple; bh=vEEAnlGYzCjMLHkQe/STbJ3xSxHiNog/FQ0K7+D2Vok=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=JXZi8xBacQQVneluIRKW9R6Q9iOLJh1P8sXZaESuMK6dLyiAe74RXclb+CUtTPzoLyqWL8Tn+HlVw7brGTtVb5jVlJGE1hxmN/vn7EQJ6a2hp0dbXjcwBfpUSd0lIfC99E+CF70ZT+VPCs+aLdOrrtVXXZEw9Tg/KaJKeVlcsEw= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=bp.renesas.com; spf=pass smtp.mailfrom=bp.renesas.com; arc=none smtp.client-ip=210.160.252.171 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=bp.renesas.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=bp.renesas.com X-IronPort-AV: E=Sophos;i="6.05,263,1701097200"; d="scan'208";a="193656674" Received: from unknown (HELO relmlir6.idc.renesas.com) ([10.200.68.152]) by relmlie5.idc.renesas.com with ESMTP; 12 Feb 2024 20:37:32 +0900 Received: from localhost.localdomain (unknown [10.226.92.40]) by relmlir6.idc.renesas.com (Postfix) with ESMTP id C94B941A9A88; Mon, 12 Feb 2024 20:37:29 +0900 (JST) From: Biju Das To: Thomas Gleixner Cc: Biju Das , Lad Prabhakar , Marc Zyngier , Geert Uytterhoeven , Biju Das , linux-renesas-soc@vger.kernel.org Subject: [PATCH 5/5] irqchip/renesas-rzg2l: Simplify rzg2l_irqc_irq_{en,dis}able() Date: Mon, 12 Feb 2024 11:37:12 +0000 Message-Id: <20240212113712.71878-6-biju.das.jz@bp.renesas.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20240212113712.71878-1-biju.das.jz@bp.renesas.com> References: <20240212113712.71878-1-biju.das.jz@bp.renesas.com> Precedence: bulk X-Mailing-List: linux-renesas-soc@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Simplify rzg2l_irqc_irq_{en,dis}able() by moving common code to rzg2l_tint_irq_endisable(). Signed-off-by: Biju Das --- drivers/irqchip/irq-renesas-rzg2l.c | 24 ++++++++---------------- 1 file changed, 8 insertions(+), 16 deletions(-) diff --git a/drivers/irqchip/irq-renesas-rzg2l.c b/drivers/irqchip/irq-renesas-rzg2l.c index fbee400985a9..bfac2c0ecf01 100644 --- a/drivers/irqchip/irq-renesas-rzg2l.c +++ b/drivers/irqchip/irq-renesas-rzg2l.c @@ -164,7 +164,7 @@ static void rzg2l_irqc_eoi(struct irq_data *d) irq_chip_eoi_parent(d); } -static void rzg2l_irqc_irq_disable(struct irq_data *d) +static void rzg2l_tint_irq_endisable(struct irq_data *d, bool enable) { unsigned int hw_irq = irqd_to_hwirq(d); @@ -177,28 +177,20 @@ static void rzg2l_irqc_irq_disable(struct irq_data *d) raw_spin_lock(&priv->lock); reg = readl_relaxed(priv->base + TSSR(tssr_index)); - rzg2l_tint_endisable(priv, reg, tssr_offset, tssr_index, false); + rzg2l_tint_endisable(priv, reg, tssr_offset, tssr_index, enable); raw_spin_unlock(&priv->lock); } +} + +static void rzg2l_irqc_irq_disable(struct irq_data *d) +{ + rzg2l_tint_irq_endisable(d, false); irq_chip_disable_parent(d); } static void rzg2l_irqc_irq_enable(struct irq_data *d) { - unsigned int hw_irq = irqd_to_hwirq(d); - - if (hw_irq >= IRQC_TINT_START && hw_irq < IRQC_NUM_IRQ) { - struct rzg2l_irqc_priv *priv = irq_data_to_priv(d); - u32 offset = hw_irq - IRQC_TINT_START; - u32 tssr_offset = TSSR_OFFSET(offset); - u8 tssr_index = TSSR_INDEX(offset); - u32 reg; - - raw_spin_lock(&priv->lock); - reg = readl_relaxed(priv->base + TSSR(tssr_index)); - rzg2l_tint_endisable(priv, reg, tssr_offset, tssr_index, true); - raw_spin_unlock(&priv->lock); - } + rzg2l_tint_irq_endisable(d, true); irq_chip_enable_parent(d); }