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Such design pattern permitted to re-define the original method and use the weak implementation in the new function. A similar approach was introduced in the framework of another arch-specific programmable interface: mips_cm_phys_base() and __mips_cm_phys_base(). The only difference is that the underscored method of the later couple was declared in the "asm/mips-cm.h" header file, but it wasn't done for the CM L2-sync methods in the subject. Due to the missing the global function declaration the "missing prototype" warning was spotted in the framework of the commit 9a2036724cd6 ("mips: mark local function static if possible") and fixed just be re-qualifying the weak method as static. Doing that broke what was originally implied by having the weak implementation globally defined. Fix that by dropping the static qualifier and adding the __mips_cm_l2sync_phys_base() prototype declared in the "asm/mips-cm.h" header file. Fixes: 9a2036724cd6 ("mips: mark local function static if possible") Signed-off-by: Serge Semin --- Note seeing there is no user of the pattern described above we can convert it to having just weakly defined methods. Let me know if that would be a better alternative. --- arch/mips/include/asm/mips-cm.h | 14 ++++++++++++++ arch/mips/kernel/mips-cm.c | 2 +- 2 files changed, 15 insertions(+), 1 deletion(-) diff --git a/arch/mips/include/asm/mips-cm.h b/arch/mips/include/asm/mips-cm.h index 23c67c0871b1..1f143dfad7a2 100644 --- a/arch/mips/include/asm/mips-cm.h +++ b/arch/mips/include/asm/mips-cm.h @@ -33,6 +33,20 @@ extern void __iomem *mips_cm_l2sync_base; */ extern phys_addr_t __mips_cm_phys_base(void); +/** + * __mips_cm_l2sync_phys_base - retrieve the physical base address of the CM + * L2-sync region + * + * This function returns the physical base address of the Coherence Manager + * L2-cache only region. It provides a default implementation which reads the + * CMGCRL2OnlySyncBase register where available or returns a 4K region just + * behind the CM GCR base address. It may be overridden by platforms which + * determine this address in a different way by defining a function with the + * same prototype except for the name mips_cm_l2sync_phys_base (without + * underscores). + */ +extern phys_addr_t __mips_cm_l2sync_phys_base(void); + /* * mips_cm_is64 - determine CM register width * diff --git a/arch/mips/kernel/mips-cm.c b/arch/mips/kernel/mips-cm.c index 84b3affb9de8..3f00788b0871 100644 --- a/arch/mips/kernel/mips-cm.c +++ b/arch/mips/kernel/mips-cm.c @@ -201,7 +201,7 @@ phys_addr_t __mips_cm_phys_base(void) phys_addr_t mips_cm_phys_base(void) __attribute__((weak, alias("__mips_cm_phys_base"))); -static phys_addr_t __mips_cm_l2sync_phys_base(void) +phys_addr_t __mips_cm_l2sync_phys_base(void) { u32 base_reg; From patchwork Thu Feb 15 17:17:27 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Serge Semin X-Patchwork-Id: 13558866 Received: from mail-lf1-f45.google.com (mail-lf1-f45.google.com [209.85.167.45]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 711B2136983; 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Thu, 15 Feb 2024 09:17:54 -0800 (PST) Received: from localhost ([178.176.56.174]) by smtp.gmail.com with ESMTPSA id x21-20020ac24895000000b00511570772f1sm309401lfc.303.2024.02.15.09.17.53 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 15 Feb 2024 09:17:53 -0800 (PST) From: Serge Semin To: Thomas Bogendoerfer , Greg Kroah-Hartman , Jiri Slaby , Arnd Bergmann , Jiaxun Yang Cc: Serge Semin , Alexey Malahov , Stephen Rothwell , Andrew Morton , linux-mips@vger.kernel.org, linux-serial@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH 2/4] mips: cm: Add CM GCR and L2-sync base address getters declarations Date: Thu, 15 Feb 2024 20:17:27 +0300 Message-ID: <20240215171740.14550-3-fancer.lancer@gmail.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20240215171740.14550-1-fancer.lancer@gmail.com> References: <20240215171740.14550-1-fancer.lancer@gmail.com> Precedence: bulk X-Mailing-List: linux-mips@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Based on the design pattern utilized in the CM GCR and L2-sync base address getters implementation the platform-specific code is capable to re-define the getters and re-use the weakly defined initial versions. But since the re-definition is supposed to be done in another source file the interface methods have been globally defined which in its turn causes the "no previous prototype" warning printed should the re-definition is finally introduced. Since without the global declarations the pattern can be considered as incomplete and causing the warning printed, fix it by providing the respective methods prototype declarations in "arch/mips/include/asm/mips-cm.h". Signed-off-by: Serge Semin --- Note as I mentioned in the previous patch, since the weak implementation of the getters isn't utilized other than as a default implementation of the original methods, we can convert the denoted pattern to a simple __weak attributed methods. Let me know if that would be more preferable. --- arch/mips/include/asm/mips-cm.h | 2 ++ 1 file changed, 2 insertions(+) diff --git a/arch/mips/include/asm/mips-cm.h b/arch/mips/include/asm/mips-cm.h index 1f143dfad7a2..6dbe74dc323d 100644 --- a/arch/mips/include/asm/mips-cm.h +++ b/arch/mips/include/asm/mips-cm.h @@ -32,6 +32,7 @@ extern void __iomem *mips_cm_l2sync_base; * name mips_cm_phys_base (without underscores). */ extern phys_addr_t __mips_cm_phys_base(void); +extern phys_addr_t mips_cm_phys_base(void); /** * __mips_cm_l2sync_phys_base - retrieve the physical base address of the CM @@ -46,6 +47,7 @@ extern phys_addr_t __mips_cm_phys_base(void); * underscores). */ extern phys_addr_t __mips_cm_l2sync_phys_base(void); +extern phys_addr_t mips_cm_l2sync_phys_base(void); /* * mips_cm_is64 - determine CM register width From patchwork Thu Feb 15 17:17:28 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Serge Semin X-Patchwork-Id: 13558867 Received: from mail-lf1-f47.google.com (mail-lf1-f47.google.com [209.85.167.47]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 26F0D137C21; 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Thu, 15 Feb 2024 09:17:56 -0800 (PST) Received: from localhost ([178.176.56.174]) by smtp.gmail.com with ESMTPSA id w7-20020a05651234c700b00511503f9ac5sm308277lfr.231.2024.02.15.09.17.55 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 15 Feb 2024 09:17:55 -0800 (PST) From: Serge Semin To: Thomas Bogendoerfer , Greg Kroah-Hartman , Jiri Slaby , Arnd Bergmann , Jiaxun Yang Cc: Serge Semin , Alexey Malahov , Stephen Rothwell , Andrew Morton , linux-mips@vger.kernel.org, linux-serial@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH 3/4] mips: zboot: Fix "no previous prototype" build warning Date: Thu, 15 Feb 2024 20:17:28 +0300 Message-ID: <20240215171740.14550-4-fancer.lancer@gmail.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20240215171740.14550-1-fancer.lancer@gmail.com> References: <20240215171740.14550-1-fancer.lancer@gmail.com> Precedence: bulk X-Mailing-List: linux-mips@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Without having the putc() prototype forwardly declared the next build-warning is printed: arch/mips/boot/compressed/uart-prom.c:6:6: warning: no previous prototype for ‘putc’ [-Wmissing-prototypes] ... Fix that by adding the "decompress.h" header file with the putc() function declaration to the source files which have the method redefined. Signed-off-by: Serge Semin --- arch/mips/boot/compressed/uart-16550.c | 2 ++ arch/mips/boot/compressed/uart-alchemy.c | 2 ++ arch/mips/boot/compressed/uart-prom.c | 2 ++ 3 files changed, 6 insertions(+) diff --git a/arch/mips/boot/compressed/uart-16550.c b/arch/mips/boot/compressed/uart-16550.c index 09dcd2c561d9..db618e72a0c4 100644 --- a/arch/mips/boot/compressed/uart-16550.c +++ b/arch/mips/boot/compressed/uart-16550.c @@ -8,6 +8,8 @@ #include +#include "decompress.h" + #if defined(CONFIG_MACH_LOONGSON64) || defined(CONFIG_MIPS_MALTA) #define UART_BASE 0x1fd003f8 #define PORT(offset) (CKSEG1ADDR(UART_BASE) + (offset)) diff --git a/arch/mips/boot/compressed/uart-alchemy.c b/arch/mips/boot/compressed/uart-alchemy.c index 8ec63011e7dc..003967c084b3 100644 --- a/arch/mips/boot/compressed/uart-alchemy.c +++ b/arch/mips/boot/compressed/uart-alchemy.c @@ -1,6 +1,8 @@ // SPDX-License-Identifier: GPL-2.0 #include +#include "decompress.h" + void putc(char c) { alchemy_uart_putchar(AU1000_UART0_PHYS_ADDR, c); diff --git a/arch/mips/boot/compressed/uart-prom.c b/arch/mips/boot/compressed/uart-prom.c index a8a0a32e05d1..5fa3b9945333 100644 --- a/arch/mips/boot/compressed/uart-prom.c +++ b/arch/mips/boot/compressed/uart-prom.c @@ -1,6 +1,8 @@ // SPDX-License-Identifier: GPL-2.0 #include +#include "decompress.h" + void putc(char c) { prom_putchar(c); From patchwork Thu Feb 15 17:17:29 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Serge Semin X-Patchwork-Id: 13558868 Received: from mail-lf1-f54.google.com (mail-lf1-f54.google.com [209.85.167.54]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id C8DC313848E; Thu, 15 Feb 2024 17:17:59 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.167.54 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1708017481; cv=none; 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Thu, 15 Feb 2024 09:17:57 -0800 (PST) Received: from localhost ([178.176.56.174]) by smtp.gmail.com with ESMTPSA id f4-20020ac251a4000000b00511ad5c3487sm309263lfk.276.2024.02.15.09.17.57 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 15 Feb 2024 09:17:57 -0800 (PST) From: Serge Semin To: Thomas Bogendoerfer , Greg Kroah-Hartman , Jiri Slaby , Arnd Bergmann , Jiaxun Yang Cc: Serge Semin , Alexey Malahov , Stephen Rothwell , Andrew Morton , linux-mips@vger.kernel.org, linux-serial@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH 4/4] tty: mips_ejtag_fdc: Fix passing incompatible pointer type warning Date: Thu, 15 Feb 2024 20:17:29 +0300 Message-ID: <20240215171740.14550-5-fancer.lancer@gmail.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20240215171740.14550-1-fancer.lancer@gmail.com> References: <20240215171740.14550-1-fancer.lancer@gmail.com> Precedence: bulk X-Mailing-List: linux-mips@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 mips_ejtag_fdc_encode() method expects having a first argument passed of the "u8 **" type, meanwhile the driver passes the "const char **" type. That causes the next build-warning: drivers/tty/mips_ejtag_fdc.c: In function ‘mips_ejtag_fdc_console_write’: drivers/tty/mips_ejtag_fdc.c:343:32: error: passing argument 1 of ‘mips_ejtag_fdc_encode’ from incompatible pointer type [-Werror=incompatible-pointer-types] word = mips_ejtag_fdc_encode(&buf_ptr, &buf_len, 1); ^ drivers/tty/mips_ejtag_fdc.c:216:24: note: expected ‘const u8 ** {aka const unsigned char **}’ but argument is of type ‘const char **’ static struct fdc_word mips_ejtag_fdc_encode(const u8 **ptrs, ^~~~~~~~~~~~~~~~~~~~~ Fix it by altering the type of the pointer which is passed to the mips_ejtag_fdc_encode() method. Fixes: ce7cbd9a6c81 ("tty: mips_ejtag_fdc: use u8 for character pointers") Signed-off-by: Serge Semin --- drivers/tty/mips_ejtag_fdc.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/tty/mips_ejtag_fdc.c b/drivers/tty/mips_ejtag_fdc.c index aac80b69a069..afbf7738c7c4 100644 --- a/drivers/tty/mips_ejtag_fdc.c +++ b/drivers/tty/mips_ejtag_fdc.c @@ -309,7 +309,7 @@ static void mips_ejtag_fdc_console_write(struct console *c, const char *s, unsigned int i, buf_len, cpu; bool done_cr = false; char buf[4]; - const char *buf_ptr = buf; + const u8 *buf_ptr = buf; /* Number of bytes of input data encoded up to each byte in buf */ u8 inc[4];