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Fri, 16 Feb 2024 09:35:02 -0800 (PST) From: Manivannan Sadhasivam Date: Fri, 16 Feb 2024 23:04:40 +0530 Subject: [PATCH v2 1/5] PCI: dwc: Refactor dw_pcie_edma_find_chip() API Precedence: bulk X-Mailing-List: linux-renesas-soc@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-Id: <20240216-dw-hdma-v2-1-b42329003f43@linaro.org> References: <20240216-dw-hdma-v2-0-b42329003f43@linaro.org> In-Reply-To: <20240216-dw-hdma-v2-0-b42329003f43@linaro.org> To: Jingoo Han , Gustavo Pimentel , Lorenzo Pieralisi , =?utf-8?q?Krzysztof_Wilczy?= =?utf-8?q?=C5=84ski?= , Rob Herring , Bjorn Helgaas , Marek Vasut , Yoshihiro Shimoda , Kishon Vijay Abraham I Cc: Serge Semin , linux-pci@vger.kernel.org, linux-kernel@vger.kernel.org, linux-renesas-soc@vger.kernel.org, linux-arm-msm@vger.kernel.org, mhi@lists.linux.dev, Manivannan Sadhasivam X-Mailer: b4 0.12.4 X-Developer-Signature: v=1; a=openpgp-sha256; l=2569; i=manivannan.sadhasivam@linaro.org; h=from:subject:message-id; bh=m8AOqRiSHCcO5mZcayvtN8wItwmC4U+br9OIM450sVs=; b=owEBbQGS/pANAwAKAVWfEeb+kc71AcsmYgBlz5y9jEZ2MRbDlRIXAc5qpjEUTe25c9uY3Tc10 XimLXNNSDmJATMEAAEKAB0WIQRnpUMqgUjL2KRYJ5dVnxHm/pHO9QUCZc+cvQAKCRBVnxHm/pHO 9WCIB/4h1XrbJ1DWyjTcM1TdQqqfBBN+Z+xZG3crirTEU5kZDMjdNtqocFqZeRGAFIt5i/hlpZu kplHDhsJEkzg+SX5kiNzDxQi31ohbsHNuSAE6w9rq5cFHUnskEGVaZQe2m4swo/DoQth1mmkBTf va7X+7V/pMxdJngff46zw/cTgD7ijo07T1OWTh7GHHZfZVmLYDfrBmkIIaaxI44hWkiAlfs9AFr NdeJA1V/r3iVv1n/NiXmyEq8B+v5Kiv5m5HwXkyKP0qEA7BLGRtuydpaNt3guQ/LHGBNY12g3V2 T4U32kGOxzkpF2ZjXdBGm0K5kjhldjuVtsVNMhYsJoJdEWoL X-Developer-Key: i=manivannan.sadhasivam@linaro.org; a=openpgp; fpr=C668AEC3C3188E4C611465E7488550E901166008 In order to add support for Hyper DMA (HDMA), let's refactor the existing dw_pcie_edma_find_chip() API by moving the common code to separate functions. No functional change. Suggested-by: Serge Semin Signed-off-by: Manivannan Sadhasivam --- drivers/pci/controller/dwc/pcie-designware.c | 40 +++++++++++++++++++++++----- 1 file changed, 33 insertions(+), 7 deletions(-) diff --git a/drivers/pci/controller/dwc/pcie-designware.c b/drivers/pci/controller/dwc/pcie-designware.c index 250cf7f40b85..3a26dfc5368f 100644 --- a/drivers/pci/controller/dwc/pcie-designware.c +++ b/drivers/pci/controller/dwc/pcie-designware.c @@ -880,7 +880,17 @@ static struct dw_edma_plat_ops dw_pcie_edma_ops = { .irq_vector = dw_pcie_edma_irq_vector, }; -static int dw_pcie_edma_find_chip(struct dw_pcie *pci) +static void dw_pcie_edma_init_data(struct dw_pcie *pci) +{ + pci->edma.dev = pci->dev; + + if (!pci->edma.ops) + pci->edma.ops = &dw_pcie_edma_ops; + + pci->edma.flags |= DW_EDMA_CHIP_LOCAL; +} + +static int dw_pcie_edma_find_mf(struct dw_pcie *pci) { u32 val; @@ -902,8 +912,6 @@ static int dw_pcie_edma_find_chip(struct dw_pcie *pci) if (val == 0xFFFFFFFF && pci->edma.reg_base) { pci->edma.mf = EDMA_MF_EDMA_UNROLL; - - val = dw_pcie_readl_dma(pci, PCIE_DMA_CTRL); } else if (val != 0xFFFFFFFF) { pci->edma.mf = EDMA_MF_EDMA_LEGACY; @@ -912,12 +920,17 @@ static int dw_pcie_edma_find_chip(struct dw_pcie *pci) return -ENODEV; } - pci->edma.dev = pci->dev; + return 0; +} - if (!pci->edma.ops) - pci->edma.ops = &dw_pcie_edma_ops; +static int dw_pcie_edma_find_channels(struct dw_pcie *pci) +{ + u32 val; - pci->edma.flags |= DW_EDMA_CHIP_LOCAL; + if (pci->edma.mf == EDMA_MF_EDMA_LEGACY) + val = dw_pcie_readl_dbi(pci, PCIE_DMA_VIEWPORT_BASE + PCIE_DMA_CTRL); + else + val = dw_pcie_readl_dma(pci, PCIE_DMA_CTRL); pci->edma.ll_wr_cnt = FIELD_GET(PCIE_DMA_NUM_WR_CHAN, val); pci->edma.ll_rd_cnt = FIELD_GET(PCIE_DMA_NUM_RD_CHAN, val); @@ -930,6 +943,19 @@ static int dw_pcie_edma_find_chip(struct dw_pcie *pci) return 0; } +static int dw_pcie_edma_find_chip(struct dw_pcie *pci) +{ + int ret; + + dw_pcie_edma_init_data(pci); + + ret = dw_pcie_edma_find_mf(pci); + if (ret) + return ret; + + return dw_pcie_edma_find_channels(pci); +} + static int dw_pcie_edma_irq_verify(struct dw_pcie *pci) { struct platform_device *pdev = to_platform_device(pci->dev); From patchwork Fri Feb 16 17:34:41 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Manivannan Sadhasivam X-Patchwork-Id: 13560369 X-Patchwork-Delegate: geert@linux-m68k.org Received: from mail-pl1-f173.google.com (mail-pl1-f173.google.com [209.85.214.173]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 84ED513247C for ; Fri, 16 Feb 2024 17:35:08 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.214.173 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1708104911; cv=none; b=B73hkk4fYGPPtPj15NH0KGLNN0udANn+R6AS3/1U3j5uHmqMEwHjE/g0D1aXyZTcp5BtF3nSW5bNXbdzNfymHrT3ESOM59WzQEaPhI8RoWwHgQfYUnbmg7OeSxZPQO3cvrS9XTQjPLM97sYuIkgFnhsgtfgr0z2L8kRZOLkf2e8= ARC-Message-Signature: i=1; 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Fri, 16 Feb 2024 09:35:07 -0800 (PST) From: Manivannan Sadhasivam Date: Fri, 16 Feb 2024 23:04:41 +0530 Subject: [PATCH v2 2/5] PCI: dwc: Skip finding eDMA channels count if glue drivers have passed them Precedence: bulk X-Mailing-List: linux-renesas-soc@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-Id: <20240216-dw-hdma-v2-2-b42329003f43@linaro.org> References: <20240216-dw-hdma-v2-0-b42329003f43@linaro.org> In-Reply-To: <20240216-dw-hdma-v2-0-b42329003f43@linaro.org> To: Jingoo Han , Gustavo Pimentel , Lorenzo Pieralisi , =?utf-8?q?Krzysztof_Wilczy?= =?utf-8?q?=C5=84ski?= , Rob Herring , Bjorn Helgaas , Marek Vasut , Yoshihiro Shimoda , Kishon Vijay Abraham I Cc: Serge Semin , linux-pci@vger.kernel.org, linux-kernel@vger.kernel.org, linux-renesas-soc@vger.kernel.org, linux-arm-msm@vger.kernel.org, mhi@lists.linux.dev, Manivannan Sadhasivam X-Mailer: b4 0.12.4 X-Developer-Signature: v=1; a=openpgp-sha256; l=1927; i=manivannan.sadhasivam@linaro.org; h=from:subject:message-id; bh=RekqSZtiSMFVKlk/3EkQASVDRUVZ9OTERPK+baLtHhE=; b=owEBbQGS/pANAwAKAVWfEeb+kc71AcsmYgBlz5y9/dWOuITX0EUn0FvBzx7o7bYPq2sZ8rd6q kD80Y0LWmeJATMEAAEKAB0WIQRnpUMqgUjL2KRYJ5dVnxHm/pHO9QUCZc+cvQAKCRBVnxHm/pHO 9fm+CACfgHz+JvCH4MmxxLzx+X9AeL4F72MbLIqnXLvjCirHbczvAebR7r+yhtXRUQZrW8pABKb dEEbsW9yeC4uZGj8aeX9HLzfyUS1eCLIefMV2CTm+K/OiV0HlsY9xvWwxuxmqfEb/71eo1hnSXU d4QqxAFnw+JMN6csdpz6mood7odPKeTbAlxDnbdSuYw9lHzACeDXsVMjyANSnLAwd+B6LK9JWAV +ClaAClq6lmt67AY+JMZ5yOjztGgnPBYaRarTTfAUa9rY8zVpjrh3UbcO01JVFb69+DQ4wmKgIl HI/URt8Q7o0QamMyaBg2ZyFodnp5SjhvSt8jJg/Vg47Tej2w X-Developer-Key: i=manivannan.sadhasivam@linaro.org; a=openpgp; fpr=C668AEC3C3188E4C611465E7488550E901166008 In the case of Hyper DMA (HDMA) present in DWC controllers, there is no way the drivers can auto detect the number of read/write channels as like its predecessor embedded DMA (eDMA). So the glue drivers making use of HDMA have to pass the channels count during probe. To accommodate that, let's skip finding the channels if the channels count were already passed by glue drivers. If the channels count passed were wrong in any form, then the existing sanity check will catch it. Suggested-by: Serge Semin Signed-off-by: Manivannan Sadhasivam Reviewed-by: Siddharth Vadapalli --- drivers/pci/controller/dwc/pcie-designware.c | 16 +++++++++------- 1 file changed, 9 insertions(+), 7 deletions(-) diff --git a/drivers/pci/controller/dwc/pcie-designware.c b/drivers/pci/controller/dwc/pcie-designware.c index 3a26dfc5368f..d07747b75947 100644 --- a/drivers/pci/controller/dwc/pcie-designware.c +++ b/drivers/pci/controller/dwc/pcie-designware.c @@ -927,13 +927,15 @@ static int dw_pcie_edma_find_channels(struct dw_pcie *pci) { u32 val; - if (pci->edma.mf == EDMA_MF_EDMA_LEGACY) - val = dw_pcie_readl_dbi(pci, PCIE_DMA_VIEWPORT_BASE + PCIE_DMA_CTRL); - else - val = dw_pcie_readl_dma(pci, PCIE_DMA_CTRL); - - pci->edma.ll_wr_cnt = FIELD_GET(PCIE_DMA_NUM_WR_CHAN, val); - pci->edma.ll_rd_cnt = FIELD_GET(PCIE_DMA_NUM_RD_CHAN, val); + if (!pci->edma.ll_wr_cnt || !pci->edma.ll_rd_cnt) { + if (pci->edma.mf == EDMA_MF_EDMA_LEGACY) + val = dw_pcie_readl_dbi(pci, PCIE_DMA_VIEWPORT_BASE + PCIE_DMA_CTRL); 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Fri, 16 Feb 2024 09:35:13 -0800 (PST) Received: from [127.0.1.1] ([120.138.12.48]) by smtp.gmail.com with ESMTPSA id v9-20020a170902b7c900b001db5241100fsm118592plz.183.2024.02.16.09.35.08 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 16 Feb 2024 09:35:12 -0800 (PST) From: Manivannan Sadhasivam Date: Fri, 16 Feb 2024 23:04:42 +0530 Subject: [PATCH v2 3/5] PCI: dwc: Pass the eDMA mapping format flag directly from glue drivers Precedence: bulk X-Mailing-List: linux-renesas-soc@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-Id: <20240216-dw-hdma-v2-3-b42329003f43@linaro.org> References: <20240216-dw-hdma-v2-0-b42329003f43@linaro.org> In-Reply-To: <20240216-dw-hdma-v2-0-b42329003f43@linaro.org> To: Jingoo Han , Gustavo Pimentel , Lorenzo Pieralisi , =?utf-8?q?Krzysztof_Wilczy?= =?utf-8?q?=C5=84ski?= , Rob Herring , Bjorn Helgaas , Marek Vasut , Yoshihiro Shimoda , Kishon Vijay Abraham I Cc: Serge Semin , linux-pci@vger.kernel.org, linux-kernel@vger.kernel.org, linux-renesas-soc@vger.kernel.org, linux-arm-msm@vger.kernel.org, mhi@lists.linux.dev, Manivannan Sadhasivam X-Mailer: b4 0.12.4 X-Developer-Signature: v=1; a=openpgp-sha256; l=3317; i=manivannan.sadhasivam@linaro.org; h=from:subject:message-id; bh=bNnVXR6L3kcnzQ1W5qCDxOjLhMtpGjDiA8ja4nbUZBM=; b=owEBbQGS/pANAwAKAVWfEeb+kc71AcsmYgBlz5y9ST0H2R6ShbbqEzDuD117Tis4bX9tke/qy ZDo5Q/SdWKJATMEAAEKAB0WIQRnpUMqgUjL2KRYJ5dVnxHm/pHO9QUCZc+cvQAKCRBVnxHm/pHO 9Zk+B/wK63dSxW1bW2CzlTD3p4svLzBTxAAADKqa5609ZLV2lzA5c+F1+wWIaGjeORKNzMdbMSJ f6z7IcaFqqwvDrScULenCSF6eunG88xP41wIg1EF/p21hcTwjh1eVvXy2LtnTizeXQSMzp9PgRQ qokAbMVPf2XINZMTsYjYLxLQyjTw6V4DPMC087YNu0W/S6ABi3kLAZFYIobL+byp6f/gXeJmzzT fXl4XLkjnJ2POiJR+xFmY4IoVJeqRc6p4Y6Q+rwxM3yf3ihyDxI8l1levR/Qy93poZH9lVI8WNR qkkH950uk6qnrTrEuhXF1nxP3kFlbgDj3TLIBYgNy5vdLVC1 X-Developer-Key: i=manivannan.sadhasivam@linaro.org; a=openpgp; fpr=C668AEC3C3188E4C611465E7488550E901166008 Instead of maintaining a separate capability for glue drivers that cannot support auto detection of the eDMA mapping format, let's pass the mapping format directly from them. This will simplify the code and also allow adding HDMA support that also doesn't support auto detection of mapping format. Suggested-by: Serge Semin Signed-off-by: Manivannan Sadhasivam Reviewed-by: Siddharth Vadapalli --- drivers/pci/controller/dwc/pcie-designware.c | 16 +++++++++------- drivers/pci/controller/dwc/pcie-designware.h | 5 ++--- drivers/pci/controller/dwc/pcie-rcar-gen4.c | 2 +- 3 files changed, 12 insertions(+), 11 deletions(-) diff --git a/drivers/pci/controller/dwc/pcie-designware.c b/drivers/pci/controller/dwc/pcie-designware.c index d07747b75947..54ecd536756d 100644 --- a/drivers/pci/controller/dwc/pcie-designware.c +++ b/drivers/pci/controller/dwc/pcie-designware.c @@ -894,18 +894,20 @@ static int dw_pcie_edma_find_mf(struct dw_pcie *pci) { u32 val; + /* + * Bail out finding the mapping format if it is already set by the glue + * driver. Also ensure that the edma.reg_base is pointing to a valid + * memory region. + */ + if (pci->edma.mf != EDMA_MF_EDMA_LEGACY) + return pci->edma.reg_base ? 0 : -ENODEV; + /* * Indirect eDMA CSRs access has been completely removed since v5.40a * thus no space is now reserved for the eDMA channels viewport and * former DMA CTRL register is no longer fixed to FFs. - * - * Note that Renesas R-Car S4-8's PCIe controllers for unknown reason - * have zeros in the eDMA CTRL register even though the HW-manual - * explicitly states there must FFs if the unrolled mapping is enabled. - * For such cases the low-level drivers are supposed to manually - * activate the unrolled mapping to bypass the auto-detection procedure. */ - if (dw_pcie_ver_is_ge(pci, 540A) || dw_pcie_cap_is(pci, EDMA_UNROLL)) + if (dw_pcie_ver_is_ge(pci, 540A)) val = 0xFFFFFFFF; else val = dw_pcie_readl_dbi(pci, PCIE_DMA_VIEWPORT_BASE + PCIE_DMA_CTRL); diff --git a/drivers/pci/controller/dwc/pcie-designware.h b/drivers/pci/controller/dwc/pcie-designware.h index 26dae4837462..995805279021 100644 --- a/drivers/pci/controller/dwc/pcie-designware.h +++ b/drivers/pci/controller/dwc/pcie-designware.h @@ -51,9 +51,8 @@ /* DWC PCIe controller capabilities */ #define DW_PCIE_CAP_REQ_RES 0 -#define DW_PCIE_CAP_EDMA_UNROLL 1 -#define DW_PCIE_CAP_IATU_UNROLL 2 -#define DW_PCIE_CAP_CDM_CHECK 3 +#define DW_PCIE_CAP_IATU_UNROLL 1 +#define DW_PCIE_CAP_CDM_CHECK 2 #define dw_pcie_cap_is(_pci, _cap) \ test_bit(DW_PCIE_CAP_ ## _cap, &(_pci)->caps) diff --git a/drivers/pci/controller/dwc/pcie-rcar-gen4.c b/drivers/pci/controller/dwc/pcie-rcar-gen4.c index e9166619b1f9..3c535ef5ea91 100644 --- a/drivers/pci/controller/dwc/pcie-rcar-gen4.c +++ b/drivers/pci/controller/dwc/pcie-rcar-gen4.c @@ -255,7 +255,7 @@ static struct rcar_gen4_pcie *rcar_gen4_pcie_alloc(struct platform_device *pdev) rcar->dw.ops = &dw_pcie_ops; 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Fri, 16 Feb 2024 09:35:18 -0800 (PST) From: Manivannan Sadhasivam Date: Fri, 16 Feb 2024 23:04:43 +0530 Subject: [PATCH v2 4/5] PCI: qcom-ep: Add HDMA support for SA8775P SoC Precedence: bulk X-Mailing-List: linux-renesas-soc@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-Id: <20240216-dw-hdma-v2-4-b42329003f43@linaro.org> References: <20240216-dw-hdma-v2-0-b42329003f43@linaro.org> In-Reply-To: <20240216-dw-hdma-v2-0-b42329003f43@linaro.org> To: Jingoo Han , Gustavo Pimentel , Lorenzo Pieralisi , =?utf-8?q?Krzysztof_Wilczy?= =?utf-8?q?=C5=84ski?= , Rob Herring , Bjorn Helgaas , Marek Vasut , Yoshihiro Shimoda , Kishon Vijay Abraham I Cc: Serge Semin , linux-pci@vger.kernel.org, linux-kernel@vger.kernel.org, linux-renesas-soc@vger.kernel.org, linux-arm-msm@vger.kernel.org, mhi@lists.linux.dev, Manivannan Sadhasivam , Mrinmay Sarkar X-Mailer: b4 0.12.4 X-Developer-Signature: v=1; a=openpgp-sha256; l=2739; i=manivannan.sadhasivam@linaro.org; h=from:subject:message-id; bh=nXwtjZgaLVb1yQW3aqg87REEZqq+9dwelHeQLVIhVBw=; b=owEBbQGS/pANAwAKAVWfEeb+kc71AcsmYgBlz5y9nALO/R45p88goO+jxnDd/1jR9FIj1mQZv 56FeDJI+YSJATMEAAEKAB0WIQRnpUMqgUjL2KRYJ5dVnxHm/pHO9QUCZc+cvQAKCRBVnxHm/pHO 9Y9PB/4sM5xn3fpFHVSMmeBrJPxp6PToCC+fAVwgs7YTxlPeCCDB2V+Cas8Ftechwl69m6ZcDH5 eBOpdSzVLLWdSebMsuzIZaHwt01C2Qt6LQHGl9xmJZ0N+eGX2Ie44RfJCixHbT0h+7kR7BtHw1N K+/mTkp4Quv976/RPfPC5XY9cRiwFEul7X5VGumL0IUtWdSe5vjMg2obgSxA3EMP4C5WHFvtytC KNbCh+z9zWaj3liVek9GvASZG8KkUjllO2vLUGJbRwmNwiN+cUIHBZ5ZoheAO5D7/5fbksCbDYo 69P0ckD8LtImRu3yr182nKfki+n2fC4HrdQLsaC35nN9PUWY X-Developer-Key: i=manivannan.sadhasivam@linaro.org; a=openpgp; fpr=C668AEC3C3188E4C611465E7488550E901166008 From: Mrinmay Sarkar SA8775P SoC supports the new Hyper DMA (HDMA) DMA Engine inside the DWC IP. Let's add support for it by passing the mapping format and the number of read/write channels count. The PCIe EP controller used on this SoC is of version 1.34.0, so a separate config struct is introduced for the sake of enabling HDMA conditionally. It should be noted that for the eDMA support (predecessor of HDMA), there are no mapping format and channels count specified. That is because eDMA supports auto detection of both parameters, whereas HDMA doesn't. Signed-off-by: Mrinmay Sarkar [mani: Reworded commit message, added kdoc, and minor cleanups] Signed-off-by: Manivannan Sadhasivam Reviewed-by: Siddharth Vadapalli --- drivers/pci/controller/dwc/pcie-qcom-ep.c | 23 ++++++++++++++++++++++- 1 file changed, 22 insertions(+), 1 deletion(-) diff --git a/drivers/pci/controller/dwc/pcie-qcom-ep.c b/drivers/pci/controller/dwc/pcie-qcom-ep.c index 45008e054e31..89d06a3e6e06 100644 --- a/drivers/pci/controller/dwc/pcie-qcom-ep.c +++ b/drivers/pci/controller/dwc/pcie-qcom-ep.c @@ -149,6 +149,14 @@ enum qcom_pcie_ep_link_status { QCOM_PCIE_EP_LINK_DOWN, }; +/** + * struct qcom_pcie_ep_cfg - Per SoC config struct + * @hdma_support: HDMA support on this SoC + */ +struct qcom_pcie_ep_cfg { + bool hdma_support; +}; + /** * struct qcom_pcie_ep - Qualcomm PCIe Endpoint Controller * @pci: Designware PCIe controller struct @@ -803,6 +811,7 @@ static const struct dw_pcie_ep_ops pci_ep_ops = { static int qcom_pcie_ep_probe(struct platform_device *pdev) { + const struct qcom_pcie_ep_cfg *cfg; struct device *dev = &pdev->dev; struct qcom_pcie_ep *pcie_ep; char *name; @@ -816,6 +825,14 @@ static int qcom_pcie_ep_probe(struct platform_device *pdev) pcie_ep->pci.ops = &pci_ops; pcie_ep->pci.ep.ops = &pci_ep_ops; pcie_ep->pci.edma.nr_irqs = 1; + + cfg = of_device_get_match_data(dev); + if (cfg && cfg->hdma_support) { + pcie_ep->pci.edma.ll_wr_cnt = 8; + pcie_ep->pci.edma.ll_rd_cnt = 8; + pcie_ep->pci.edma.mf = EDMA_MF_HDMA_NATIVE; + } + platform_set_drvdata(pdev, pcie_ep); ret = qcom_pcie_ep_get_resources(pdev, pcie_ep); @@ -874,8 +891,12 @@ static void qcom_pcie_ep_remove(struct platform_device *pdev) qcom_pcie_disable_resources(pcie_ep); } +static const struct qcom_pcie_ep_cfg cfg_1_34_0 = { + .hdma_support = true, +}; + static const struct of_device_id qcom_pcie_ep_match[] = { - { .compatible = "qcom,sa8775p-pcie-ep", }, + { .compatible = "qcom,sa8775p-pcie-ep", .data = &cfg_1_34_0}, { .compatible = "qcom,sdx55-pcie-ep", }, { .compatible = "qcom,sm8450-pcie-ep", }, { } From patchwork Fri Feb 16 17:34:44 2024 Content-Type: text/plain; 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a=openpgp-sha256; l=919; i=manivannan.sadhasivam@linaro.org; h=from:subject:message-id; bh=l9TZl5f3ruMfAhDvync60x+vuqThCg8E95q3H1HbSYw=; b=owEBbQGS/pANAwAKAVWfEeb+kc71AcsmYgBlz5y+NwBcDBvMsgLY/9ArhUeU4RtpAOkSNOPA0 cL+6HT1tTCJATMEAAEKAB0WIQRnpUMqgUjL2KRYJ5dVnxHm/pHO9QUCZc+cvgAKCRBVnxHm/pHO 9YdiB/9TA+DKLXxIZYpi/4hnMyIkUsM2WJIWyQ6w7vRVyPe9xkvRVouAEDo3kakdlZprxiUhdRE RVaU7JFkgelmHQuyS7am0hGDZJpDmEmPrmuGigJlrygDliRLE85n5WP2vnnN7WKQuYN+W8HQnv0 l0f9zuR0+G+HEp9D1og10j/2BOueS6fmgssxK8rtfpi2VW+6FgY0KiiqpsWdUq7od5/Ucw2nR1F NbjzPj1POiJNg12Bi3HrhcTLZjvb0KwfS/lV5Mj1NKvbtl2anyrbqaqqbejjAuqCSzx91cCovSW ddbe/L2NDfdpqcgHjOuBkoP+92IIH3SP4KN6C52nTmQjmNqV X-Developer-Key: i=manivannan.sadhasivam@linaro.org; a=openpgp; fpr=C668AEC3C3188E4C611465E7488550E901166008 From: Mrinmay Sarkar SA8775P SoC supports Hyper DMA (HDMA) DMA Engine present in the DWC IP. So, let's enable it in the EPF driver so that the DMA Engine APIs can be used for data transfer. Signed-off-by: Mrinmay Sarkar [mani: reworded commit message] Signed-off-by: Manivannan Sadhasivam Reviewed-by: Siddharth Vadapalli --- drivers/pci/endpoint/functions/pci-epf-mhi.c | 1 + 1 file changed, 1 insertion(+) diff --git a/drivers/pci/endpoint/functions/pci-epf-mhi.c b/drivers/pci/endpoint/functions/pci-epf-mhi.c index 2c54d80107cf..570c1d1fb12e 100644 --- a/drivers/pci/endpoint/functions/pci-epf-mhi.c +++ b/drivers/pci/endpoint/functions/pci-epf-mhi.c @@ -137,6 +137,7 @@ static const struct pci_epf_mhi_ep_info sa8775p_info = { .epf_flags = PCI_BASE_ADDRESS_MEM_TYPE_32, .msi_count = 32, .mru = 0x8000, + .flags = MHI_EPF_USE_DMA, }; struct pci_epf_mhi {