From patchwork Wed Feb 20 07:43:18 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Sugaya Taichi X-Patchwork-Id: 10821571 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 0448C1575 for ; Wed, 20 Feb 2019 07:42:42 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id DF18A2D693 for ; Wed, 20 Feb 2019 07:42:41 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id D2D972D6BD; Wed, 20 Feb 2019 07:42:41 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-2.9 required=2.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,MAILING_LIST_MULTI,MIME_HEADER_CTYPE_ONLY,RCVD_IN_DNSWL_LOW, T_TVD_MIME_NO_HEADERS autolearn=no version=3.3.1 Received: from web01.groups.io (web01.groups.io [66.175.222.12]) (using TLSv1.2 with cipher AES128-SHA (128/128 bits)) (No client certificate requested) by mail.wl.linuxfoundation.org (Postfix) with ESMTPS id 8027A2D693 for ; Wed, 20 Feb 2019 07:42:41 +0000 (UTC) X-Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by groups.io with SMTP; Tue, 19 Feb 2019 23:42:41 -0800 X-Received: by mail.kernel.org (Postfix) id D40B821773; Wed, 20 Feb 2019 07:42:40 +0000 (UTC) X-Received: from mx.socionext.com (mx.socionext.com [202.248.49.38]) by mail.kernel.org (Postfix) with ESMTP id 6F21D20449; Wed, 20 Feb 2019 07:42:40 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org 6F21D20449 X-Received: from unknown (HELO iyokan-ex.css.socionext.com) ([172.31.9.54]) by mx.socionext.com with ESMTP; 20 Feb 2019 16:42:39 +0900 X-Received: from mail.mfilter.local (m-filter-2 [10.213.24.62]) by iyokan-ex.css.socionext.com (Postfix) with ESMTP id C727B6117D; Wed, 20 Feb 2019 16:42:39 +0900 (JST) X-Received: from 172.31.9.53 (172.31.9.53) by m-FILTER with ESMTP; Wed, 20 Feb 2019 16:42:39 +0900 X-Received: from yuzu.css.socionext.com (yuzu [172.31.8.45]) by iyokan.css.socionext.com (Postfix) with ESMTP id 3BCED40368; Wed, 20 Feb 2019 16:42:39 +0900 (JST) X-Received: from M20VSDK.e01.socionext.com (unknown [10.213.118.34]) by yuzu.css.socionext.com (Postfix) with ESMTP id 23959120459; Wed, 20 Feb 2019 16:42:39 +0900 (JST) From: Sugaya Taichi To: Linuxkernel+Patchwork-Soc via Email Integration Cc: Rob Herring , Mark Rutland , Takao Orito , Kazuhiro Kasai , Shinji Kanematsu , Jassi Brar , Masami Hiramatsu , Sugaya Taichi Subject: [PATCH v3 1/9] dt-bindings: sram: milbeaut: Add binding for Milbeaut smp-sram Date: Wed, 20 Feb 2019 16:43:18 +0900 Message-Id: <1550648598-10192-1-git-send-email-sugaya.taichi@socionext.com> Precedence: Bulk List-Unsubscribe: Sender: patchwork-soc@linux.kernel.org List-Id: Mailing-List: list patchwork-soc@linux.kernel.org; contact patchwork-soc+owner@linux.kernel.org Delivered-To: mailing list patchwork-soc@linux.kernel.org Reply-To: patchwork-soc+owner@linux.kernel.org DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=linux.kernel.org; q=dns/txt; s=20140610; t=1550648561; bh=vjfpHb7z0RcNg5044vH1XsxpIzFhS5sGtd8Zoy58oJA=; h=Cc:Content-Type:Date:From:Reply-To:Subject:To; b=Av5RLgzhBUQz7hcs+VxotQuR04/v/AihdAHslnPhsWf7KRgZBXZo3oF5jmnfE8kRjy3 Sph83hPKS0OJMSHr+aDo2FZBz+85LkAAp5GmRWiTKmQzFQ9NP2j/3pUjnjcnpw3K0tDUf XhqrycWNWdyHTvVQpaDyNMFzEzSvQhZu4G0= X-Virus-Scanned: ClamAV using ClamSMTP The Milbeaut M10V SoC needs a part of sram for smp, so this adds the M10V sram compatible and binding. Signed-off-by: Sugaya Taichi Reviewed-by: Rob Herring --- .../devicetree/bindings/sram/milbeaut-smp-sram.txt | 24 ++++++++++++++++++++++ 1 file changed, 24 insertions(+) create mode 100644 Documentation/devicetree/bindings/sram/milbeaut-smp-sram.txt diff --git a/Documentation/devicetree/bindings/sram/milbeaut-smp-sram.txt b/Documentation/devicetree/bindings/sram/milbeaut-smp-sram.txt new file mode 100644 index 0000000..194f6a3 --- /dev/null +++ b/Documentation/devicetree/bindings/sram/milbeaut-smp-sram.txt @@ -0,0 +1,24 @@ +Milbeaut SRAM for smp bringup + +Milbeaut SoCs use a part of the sram for the bringup of the secondary cores. +Once they get powered up in the bootloader, they stay at the specific part +of the sram. +Therefore the part needs to be added as the sub-node of mmio-sram. + +Required sub-node properties: +- compatible : should be "socionext,milbeaut-smp-sram" + +Example: + + sram: sram@0 { + compatible = "mmio-sram"; + reg = <0x0 0x10000>; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0 0x0 0x10000>; + + smp-sram@f100 { + compatible = "socionext,milbeaut-smp-sram"; + reg = <0xf100 0x20>; + }; + }; From patchwork Wed Feb 20 07:43:28 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Sugaya Taichi X-Patchwork-Id: 10821573 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 5DCFB6C2 for ; Wed, 20 Feb 2019 07:42:52 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 458A72D693 for ; Wed, 20 Feb 2019 07:42:52 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id 393372D6BD; Wed, 20 Feb 2019 07:42:52 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-2.9 required=2.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,MAILING_LIST_MULTI,MIME_HEADER_CTYPE_ONLY,RCVD_IN_DNSWL_LOW, T_TVD_MIME_NO_HEADERS autolearn=no version=3.3.1 Received: from web01.groups.io (web01.groups.io [66.175.222.12]) (using TLSv1.2 with cipher AES128-SHA (128/128 bits)) (No client certificate requested) by mail.wl.linuxfoundation.org (Postfix) with ESMTPS id E9D742D693 for ; Wed, 20 Feb 2019 07:42:51 +0000 (UTC) X-Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by groups.io with SMTP; Tue, 19 Feb 2019 23:42:51 -0800 X-Received: by mail.kernel.org (Postfix) id 2DD9821773; Wed, 20 Feb 2019 07:42:51 +0000 (UTC) X-Received: from mx.socionext.com (mx.socionext.com [202.248.49.38]) by mail.kernel.org (Postfix) with ESMTP id C248E20449; Wed, 20 Feb 2019 07:42:50 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org C248E20449 X-Received: from unknown (HELO kinkan-ex.css.socionext.com) ([172.31.9.52]) by mx.socionext.com with ESMTP; 20 Feb 2019 16:42:50 +0900 X-Received: from mail.mfilter.local (m-filter-2 [10.213.24.62]) by kinkan-ex.css.socionext.com (Postfix) with ESMTP id 2203E180097; Wed, 20 Feb 2019 16:42:50 +0900 (JST) X-Received: from 172.31.9.53 (172.31.9.53) by m-FILTER with ESMTP; Wed, 20 Feb 2019 16:42:50 +0900 X-Received: from yuzu.css.socionext.com (yuzu [172.31.8.45]) by iyokan.css.socionext.com (Postfix) with ESMTP id E0D4E40368; Wed, 20 Feb 2019 16:42:49 +0900 (JST) X-Received: from M20VSDK.e01.socionext.com (unknown [10.213.118.34]) by yuzu.css.socionext.com (Postfix) with ESMTP id CBE6F120459; Wed, 20 Feb 2019 16:42:49 +0900 (JST) From: Sugaya Taichi To: Linuxkernel+Patchwork-Soc via Email Integration Cc: Rob Herring , Mark Rutland , Takao Orito , Kazuhiro Kasai , Shinji Kanematsu , Jassi Brar , Masami Hiramatsu , Sugaya Taichi Subject: [PATCH v3 2/9] dt-bindings: arm: Add SMP enable-method for Milbeaut Date: Wed, 20 Feb 2019 16:43:28 +0900 Message-Id: <1550648608-10343-1-git-send-email-sugaya.taichi@socionext.com> Precedence: Bulk List-Unsubscribe: Sender: patchwork-soc@linux.kernel.org List-Id: Mailing-List: list patchwork-soc@linux.kernel.org; contact patchwork-soc+owner@linux.kernel.org Delivered-To: mailing list patchwork-soc@linux.kernel.org Reply-To: patchwork-soc+owner@linux.kernel.org DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=linux.kernel.org; q=dns/txt; s=20140610; t=1550648571; bh=7Uh2ErUYsr7Gy2mR9UxE452BtNhti8vLJWZjb27aJnk=; h=Cc:Content-Type:Date:From:Reply-To:Subject:To; b=Wom69ApjL1h0DxLenxTFul/XNznOtonq9VLDLIll2EMoIRtSPFo0G3/19ILG2ZVv0st GKK1DfwV3MYDwrulJ5c45G+GMv4+JnOOmQzjGW9G3yh52MoTbOJw/odHPNKK0vuFA9St0 JQ1qFmyaKsIeGq3ZJNUNM44O/87PfhezuS4= X-Virus-Scanned: ClamAV using ClamSMTP This adds a compatible string "socionext,milbeaut-m10v-smp" for Milbeaut M10V to the 32 bit ARM CPU device tree binding. Signed-off-by: Sugaya Taichi Reviewed-by: Rob Herring --- Documentation/devicetree/bindings/arm/cpus.yaml | 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/arm/cpus.yaml b/Documentation/devicetree/bindings/arm/cpus.yaml index 298c17b..365dcf3 100644 --- a/Documentation/devicetree/bindings/arm/cpus.yaml +++ b/Documentation/devicetree/bindings/arm/cpus.yaml @@ -228,6 +228,7 @@ patternProperties: - renesas,r9a06g032-smp - rockchip,rk3036-smp - rockchip,rk3066-smp + - socionext,milbeaut-m10v-smp - ste,dbx500-smp cpu-release-addr: From patchwork Wed Feb 20 07:43:42 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Sugaya Taichi X-Patchwork-Id: 10821575 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id E2B316C2 for ; Wed, 20 Feb 2019 07:43:04 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id C759A2D693 for ; Wed, 20 Feb 2019 07:43:04 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id B70922D6BD; Wed, 20 Feb 2019 07:43:04 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-2.9 required=2.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,MAILING_LIST_MULTI,MIME_HEADER_CTYPE_ONLY,RCVD_IN_DNSWL_LOW, T_TVD_MIME_NO_HEADERS autolearn=no version=3.3.1 Received: from web01.groups.io (web01.groups.io [66.175.222.12]) (using TLSv1.2 with cipher AES128-SHA (128/128 bits)) (No client certificate requested) by mail.wl.linuxfoundation.org (Postfix) with ESMTPS id 5F7B82D693 for ; Wed, 20 Feb 2019 07:43:04 +0000 (UTC) X-Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by groups.io with SMTP; Tue, 19 Feb 2019 23:43:03 -0800 X-Received: by mail.kernel.org (Postfix) id 7853B21773; Wed, 20 Feb 2019 07:43:03 +0000 (UTC) X-Received: from mx.socionext.com (mx.socionext.com [202.248.49.38]) by mail.kernel.org (Postfix) with ESMTP id 097F320449; Wed, 20 Feb 2019 07:43:02 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org 097F320449 X-Received: from unknown (HELO kinkan-ex.css.socionext.com) ([172.31.9.52]) by mx.socionext.com with ESMTP; 20 Feb 2019 16:43:02 +0900 X-Received: from mail.mfilter.local (m-filter-1 [10.213.24.61]) by kinkan-ex.css.socionext.com (Postfix) with ESMTP id 51910180097; Wed, 20 Feb 2019 16:43:02 +0900 (JST) X-Received: from 172.31.9.51 (172.31.9.51) by m-FILTER with ESMTP; Wed, 20 Feb 2019 16:43:02 +0900 X-Received: from yuzu.css.socionext.com (yuzu [172.31.8.45]) by kinkan.css.socionext.com (Postfix) with ESMTP id 11AFD1A04E0; Wed, 20 Feb 2019 16:43:02 +0900 (JST) X-Received: from M20VSDK.e01.socionext.com (unknown [10.213.118.34]) by yuzu.css.socionext.com (Postfix) with ESMTP id EF891120459; Wed, 20 Feb 2019 16:43:01 +0900 (JST) From: Sugaya Taichi To: Linuxkernel+Patchwork-Soc via Email Integration Cc: Rob Herring , Mark Rutland , Takao Orito , Kazuhiro Kasai , Shinji Kanematsu , Jassi Brar , Masami Hiramatsu , Sugaya Taichi Subject: [PATCH v3 3/9] dt-bindings: Add documentation for Milbeaut SoCs Date: Wed, 20 Feb 2019 16:43:42 +0900 Message-Id: <1550648622-10541-1-git-send-email-sugaya.taichi@socionext.com> Precedence: Bulk List-Unsubscribe: Sender: patchwork-soc@linux.kernel.org List-Id: Mailing-List: list patchwork-soc@linux.kernel.org; contact patchwork-soc+owner@linux.kernel.org Delivered-To: mailing list patchwork-soc@linux.kernel.org Reply-To: patchwork-soc+owner@linux.kernel.org DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=linux.kernel.org; q=dns/txt; s=20140610; t=1550648584; bh=G54aT/VBv4FzfDU4224nXJJaD7c90563Q2OPkmfSntk=; h=Cc:Content-Type:Date:From:Reply-To:Subject:To; b=cetJPETDksEcK3WxHzCSa+jZ8JIK0wfWqym/34whjVZ7G4hdyZlxPplR8ymxTg7Lg2g Mw/uM2Uf9swbEj0L+mz9vxll6bj4UiOF9YmhlXpXeKbFKZ9sWJ0Zsy+u+DaNYP6LFwnVo uYj53kXKpxWp6hEJfwzJmj9Y/rcrbJzmLTs= X-Virus-Scanned: ClamAV using ClamSMTP This adds a DT binding documentation for the M10V and its evaluation board. Signed-off-by: Sugaya Taichi --- .../bindings/arm/socionext/milbeaut.yaml | 22 ++++++++++++++++++++++ 1 file changed, 22 insertions(+) create mode 100644 Documentation/devicetree/bindings/arm/socionext/milbeaut.yaml diff --git a/Documentation/devicetree/bindings/arm/socionext/milbeaut.yaml b/Documentation/devicetree/bindings/arm/socionext/milbeaut.yaml new file mode 100644 index 0000000..522396f --- /dev/null +++ b/Documentation/devicetree/bindings/arm/socionext/milbeaut.yaml @@ -0,0 +1,22 @@ +# SPDX-License-Identifier: GPL-2.0 +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/arm/milbeaut.yaml# +$schema: http://devicetree.org/meta-schemas/milbeaut.yaml# + +title: Milbeaut platforms device tree bindings + +maintainers: + - Taichi Sugaya + - Takao Orito + +properties: + $nodename: + const: '/' + compatible: + oneOf: + - items: + - enum: + - socionext,milbeaut-m10v-evb + - const: socionext,sc2000a +... From patchwork Wed Feb 20 07:43:50 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Sugaya Taichi X-Patchwork-Id: 10821579 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 599841575 for ; Wed, 20 Feb 2019 07:43:16 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 411C82D693 for ; Wed, 20 Feb 2019 07:43:16 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id 347432D6BD; Wed, 20 Feb 2019 07:43:16 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-2.9 required=2.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,MAILING_LIST_MULTI,MIME_HEADER_CTYPE_ONLY,RCVD_IN_DNSWL_LOW, T_TVD_MIME_NO_HEADERS autolearn=no version=3.3.1 Received: from web01.groups.io (web01.groups.io [66.175.222.12]) (using TLSv1.2 with cipher AES128-SHA (128/128 bits)) (No client certificate requested) by mail.wl.linuxfoundation.org (Postfix) with ESMTPS id A80F82D693 for ; Wed, 20 Feb 2019 07:43:15 +0000 (UTC) X-Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by groups.io with SMTP; Tue, 19 Feb 2019 23:43:15 -0800 X-Received: by mail.kernel.org (Postfix) id EB56A21773; Wed, 20 Feb 2019 07:43:14 +0000 (UTC) X-Received: from mx.socionext.com (mx.socionext.com [202.248.49.38]) by mail.kernel.org (Postfix) with ESMTP id 8E33A20449 for ; Wed, 20 Feb 2019 07:43:14 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org 8E33A20449 X-Received: from unknown (HELO kinkan-ex.css.socionext.com) ([172.31.9.52]) by mx.socionext.com with ESMTP; 20 Feb 2019 16:43:13 +0900 X-Received: from mail.mfilter.local (m-filter-2 [10.213.24.62]) by kinkan-ex.css.socionext.com (Postfix) with ESMTP id DE83C180097; Wed, 20 Feb 2019 16:43:13 +0900 (JST) X-Received: from 172.31.9.51 (172.31.9.51) by m-FILTER with ESMTP; Wed, 20 Feb 2019 16:43:13 +0900 X-Received: from yuzu.css.socionext.com (yuzu [172.31.8.45]) by kinkan.css.socionext.com (Postfix) with ESMTP id 560471A04E0; Wed, 20 Feb 2019 16:43:13 +0900 (JST) X-Received: from M20VSDK.e01.socionext.com (unknown [10.213.118.34]) by yuzu.css.socionext.com (Postfix) with ESMTP id 38DAC120459; Wed, 20 Feb 2019 16:43:13 +0900 (JST) From: Sugaya Taichi To: Linuxkernel+Patchwork-Soc via Email Integration Cc: Arnd Bergmann , Takao Orito , Kazuhiro Kasai , Shinji Kanematsu , Jassi Brar , Masami Hiramatsu , Sugaya Taichi Subject: [PATCH v3 4/9] ARM: milbeaut: Add basic support for Milbeaut m10v SoC Date: Wed, 20 Feb 2019 16:43:50 +0900 Message-Id: <1550648630-10669-1-git-send-email-sugaya.taichi@socionext.com> Precedence: Bulk List-Unsubscribe: Sender: patchwork-soc@linux.kernel.org List-Id: Mailing-List: list patchwork-soc@linux.kernel.org; contact patchwork-soc+owner@linux.kernel.org Delivered-To: mailing list patchwork-soc@linux.kernel.org Reply-To: patchwork-soc+owner@linux.kernel.org DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=linux.kernel.org; q=dns/txt; s=20140610; t=1550648595; bh=qIg/QWf+2J6FARWrC5PrKs2cu0V6RiV+SugSp+X6dag=; h=Cc:Content-Type:Date:From:Reply-To:Subject:To; b=sz5eWcE2UleD/25Uw2vIWoE92JMYYGKDjPeDqiFYrJEUVWgGieNYmJ8xgoZL8RjzjpA OMmmMHK3CRbSOxa/t19tDqJeNSSVIeEzO+g9KGU+Gh2TjUGMxdEy/KvVN000U3PPzW/3R +wSzo0jpn2nh8rzNe3N8o2uHyKK+QfVifJQ= X-Virus-Scanned: ClamAV using ClamSMTP This adds the basic M10V SoC support under arch/arm. Since all cores are activated in the custom bootloader before booting linux, it is necessary to wait for the secondary-cores using cpu-enable- method and special sram. Signed-off-by: Sugaya Taichi --- arch/arm/Kconfig | 2 + arch/arm/Makefile | 1 + arch/arm/mach-milbeaut/Kconfig | 20 ++++++ arch/arm/mach-milbeaut/Makefile | 1 + arch/arm/mach-milbeaut/platsmp.c | 143 +++++++++++++++++++++++++++++++++++++++ 5 files changed, 167 insertions(+) create mode 100644 arch/arm/mach-milbeaut/Kconfig create mode 100644 arch/arm/mach-milbeaut/Makefile create mode 100644 arch/arm/mach-milbeaut/platsmp.c diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig index 664e918..c8cb752 100644 --- a/arch/arm/Kconfig +++ b/arch/arm/Kconfig @@ -750,6 +750,8 @@ source "arch/arm/mach-mediatek/Kconfig" source "arch/arm/mach-meson/Kconfig" +source "arch/arm/mach-milbeaut/Kconfig" + source "arch/arm/mach-mmp/Kconfig" source "arch/arm/mach-moxart/Kconfig" diff --git a/arch/arm/Makefile b/arch/arm/Makefile index 9db3c58..00000e9 100644 --- a/arch/arm/Makefile +++ b/arch/arm/Makefile @@ -190,6 +190,7 @@ machine-$(CONFIG_ARCH_MV78XX0) += mv78xx0 machine-$(CONFIG_ARCH_MVEBU) += mvebu machine-$(CONFIG_ARCH_MXC) += imx machine-$(CONFIG_ARCH_MEDIATEK) += mediatek +machine-$(CONFIG_ARCH_MILBEAUT) += milbeaut machine-$(CONFIG_ARCH_MXS) += mxs machine-$(CONFIG_ARCH_NETX) += netx machine-$(CONFIG_ARCH_NOMADIK) += nomadik diff --git a/arch/arm/mach-milbeaut/Kconfig b/arch/arm/mach-milbeaut/Kconfig new file mode 100644 index 0000000..6a576fd --- /dev/null +++ b/arch/arm/mach-milbeaut/Kconfig @@ -0,0 +1,20 @@ +# SPDX-License-Identifier: GPL-2.0 +menuconfig ARCH_MILBEAUT + bool "Socionext Milbeaut SoCs" + depends on ARCH_MULTI_V7 + select ARM_GIC + help + This enables support for Socionext Milbeaut SoCs + +if ARCH_MILBEAUT + +config ARCH_MILBEAUT_M10V + bool "Milbeaut SC2000/M10V platform" + select ARM_ARCH_TIMER + select MILBEAUT_TIMER + select PINCTRL + select PINCTRL_MILBEAUT + help + Support for Socionext's MILBEAUT M10V based systems + +endif diff --git a/arch/arm/mach-milbeaut/Makefile b/arch/arm/mach-milbeaut/Makefile new file mode 100644 index 0000000..ce5ea06 --- /dev/null +++ b/arch/arm/mach-milbeaut/Makefile @@ -0,0 +1 @@ +obj-$(CONFIG_SMP) += platsmp.o diff --git a/arch/arm/mach-milbeaut/platsmp.c b/arch/arm/mach-milbeaut/platsmp.c new file mode 100644 index 0000000..591543c --- /dev/null +++ b/arch/arm/mach-milbeaut/platsmp.c @@ -0,0 +1,143 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright: (C) 2018 Socionext Inc. + * Copyright: (C) 2015 Linaro Ltd. + */ + +#include +#include +#include +#include + +#include +#include +#include +#include +#include + +#define M10V_MAX_CPU 4 +#define KERNEL_UNBOOT_FLAG 0x12345678 + +static void __iomem *m10v_smp_base; + +static int m10v_boot_secondary(unsigned int l_cpu, struct task_struct *idle) +{ + unsigned int mpidr, cpu, cluster; + + if (!m10v_smp_base) + return -ENXIO; + + mpidr = cpu_logical_map(l_cpu); + cpu = MPIDR_AFFINITY_LEVEL(mpidr, 0); + cluster = MPIDR_AFFINITY_LEVEL(mpidr, 1); + + if (cpu >= M10V_MAX_CPU) + return -EINVAL; + + pr_info("%s: cpu %u l_cpu %u cluster %u\n", + __func__, cpu, l_cpu, cluster); + + writel(__pa_symbol(secondary_startup), m10v_smp_base + cpu * 4); + arch_send_wakeup_ipi_mask(cpumask_of(l_cpu)); + + return 0; +} + +static void m10v_smp_init(unsigned int max_cpus) +{ + unsigned int mpidr, cpu, cluster; + struct device_node *np; + + np = of_find_compatible_node(NULL, NULL, "socionext,milbeaut-smp-sram"); + if (!np) + return; + + m10v_smp_base = of_iomap(np, 0); + if (!m10v_smp_base) + return; + + mpidr = read_cpuid_mpidr(); + cpu = MPIDR_AFFINITY_LEVEL(mpidr, 0); + cluster = MPIDR_AFFINITY_LEVEL(mpidr, 1); + pr_info("MCPM boot on cpu_%u cluster_%u\n", cpu, cluster); + + for (cpu = 0; cpu < M10V_MAX_CPU; cpu++) + writel(KERNEL_UNBOOT_FLAG, m10v_smp_base + cpu * 4); +} + +static void m10v_cpu_die(unsigned int l_cpu) +{ + gic_cpu_if_down(0); + v7_exit_coherency_flush(louis); + wfi(); +} + +static int m10v_cpu_kill(unsigned int l_cpu) +{ + unsigned int mpidr, cpu; + + mpidr = cpu_logical_map(l_cpu); + cpu = MPIDR_AFFINITY_LEVEL(mpidr, 0); + + writel(KERNEL_UNBOOT_FLAG, m10v_smp_base + cpu * 4); + + return 1; +} + +static struct smp_operations m10v_smp_ops __initdata = { + .smp_prepare_cpus = m10v_smp_init, + .smp_boot_secondary = m10v_boot_secondary, + .cpu_die = m10v_cpu_die, + .cpu_kill = m10v_cpu_kill, +}; +CPU_METHOD_OF_DECLARE(m10v_smp, "socionext,milbeaut-m10v-smp", &m10v_smp_ops); + +static int m10v_pm_valid(suspend_state_t state) +{ + return (state == PM_SUSPEND_STANDBY) || (state == PM_SUSPEND_MEM); +} + +typedef void (*phys_reset_t)(unsigned long); +static phys_reset_t phys_reset; + +static int m10v_die(unsigned long arg) +{ + setup_mm_for_reboot(); + asm("wfi"); + /* Boot just like a secondary */ + phys_reset = (phys_reset_t)(unsigned long)virt_to_phys(cpu_reset); + phys_reset(virt_to_phys(cpu_resume)); + + return 0; +} + +static int m10v_pm_enter(suspend_state_t state) +{ + switch (state) { + case PM_SUSPEND_STANDBY: + asm("wfi"); + break; + case PM_SUSPEND_MEM: + cpu_pm_enter(); + cpu_suspend(0, m10v_die); + cpu_pm_exit(); + break; + } + return 0; +} + +static const struct platform_suspend_ops m10v_pm_ops = { + .valid = m10v_pm_valid, + .enter = m10v_pm_enter, +}; + +struct clk *m10v_clclk_register(struct device *cpu_dev); + +static int __init m10v_pm_init(void) +{ + if (of_machine_is_compatible("socionext,milbeaut-evb")) + suspend_set_ops(&m10v_pm_ops); + + return 0; +} +late_initcall(m10v_pm_init); From patchwork Wed Feb 20 07:44:02 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Sugaya Taichi X-Patchwork-Id: 10821583 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 658481575 for ; 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Wed, 20 Feb 2019 07:43:24 +0000 (UTC) X-Received: from mx.socionext.com (mx.socionext.com [202.248.49.38]) by mail.kernel.org (Postfix) with ESMTP id BBFAA20449; Wed, 20 Feb 2019 07:43:23 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org BBFAA20449 X-Received: from unknown (HELO kinkan-ex.css.socionext.com) ([172.31.9.52]) by mx.socionext.com with ESMTP; 20 Feb 2019 16:43:22 +0900 X-Received: from mail.mfilter.local (m-filter-1 [10.213.24.61]) by kinkan-ex.css.socionext.com (Postfix) with ESMTP id 0FEB4180097; Wed, 20 Feb 2019 16:43:23 +0900 (JST) X-Received: from 172.31.9.51 (172.31.9.51) by m-FILTER with ESMTP; Wed, 20 Feb 2019 16:43:23 +0900 X-Received: from yuzu.css.socionext.com (yuzu [172.31.8.45]) by kinkan.css.socionext.com (Postfix) with ESMTP id DD2ED1A04E0; Wed, 20 Feb 2019 16:43:22 +0900 (JST) X-Received: from M20VSDK.e01.socionext.com (unknown [10.213.118.34]) by yuzu.css.socionext.com (Postfix) with ESMTP id C3638120459; Wed, 20 Feb 2019 16:43:22 +0900 (JST) From: Sugaya Taichi To: Linuxkernel+Patchwork-Soc via Email Integration Cc: Daniel Lezcano , Thomas Gleixner , Rob Herring , Mark Rutland , Takao Orito , Kazuhiro Kasai , Shinji Kanematsu , Jassi Brar , Masami Hiramatsu , Sugaya Taichi Subject: [PATCH v3 5/9] dt-bindings: timer: Add Milbeaut M10V timer description Date: Wed, 20 Feb 2019 16:44:02 +0900 Message-Id: <1550648642-10802-1-git-send-email-sugaya.taichi@socionext.com> Precedence: Bulk List-Unsubscribe: Sender: patchwork-soc@linux.kernel.org List-Id: Mailing-List: list patchwork-soc@linux.kernel.org; contact patchwork-soc+owner@linux.kernel.org Delivered-To: mailing list patchwork-soc@linux.kernel.org Reply-To: patchwork-soc+owner@linux.kernel.org DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=linux.kernel.org; q=dns/txt; s=20140610; t=1550648604; bh=iVHD1a/ruWHvpeFZT/4+qzWnqlNChaUx5UhL6f+Yv4s=; h=Cc:Content-Type:Date:From:Reply-To:Subject:To; b=ui4vXkz3lvDJJn5fQlgf43sl7Ql9KkaNoXECsnhTrfr+uSI5i3wI5ndfjY3lg+xkGHR 3aVSb6w8rd6UQeQXWlu/HqdQxUNKuBRu3zAlcOLWB7glen4IbiaNavInwvlKmcMRNoyY+ 88TnhaOTMdsCOahQLOrhnlRrc0hE1Lv+wrc= X-Virus-Scanned: ClamAV using ClamSMTP Add DT bindings document for Milbeaut M10V timer. Signed-off-by: Sugaya Taichi Reviewed-by: Rob Herring --- .../bindings/timer/socionext,milbeaut-timer.txt | 17 +++++++++++++++++ 1 file changed, 17 insertions(+) create mode 100644 Documentation/devicetree/bindings/timer/socionext,milbeaut-timer.txt diff --git a/Documentation/devicetree/bindings/timer/socionext,milbeaut-timer.txt b/Documentation/devicetree/bindings/timer/socionext,milbeaut-timer.txt new file mode 100644 index 0000000..ac44c4b --- /dev/null +++ b/Documentation/devicetree/bindings/timer/socionext,milbeaut-timer.txt @@ -0,0 +1,17 @@ +Milbeaut SoCs Timer Controller + +Required properties: + +- compatible : should be "socionext,milbeaut-timer". +- reg : Specifies base physical address and size of the registers. +- interrupts : The interrupt of the first timer. +- clocks: phandle to the input clk. + +Example: + +timer { + compatible = "socionext,milbeaut-timer"; + reg = <0x1e000050 0x20> + interrupts = <0 91 4>; + clocks = <&clk 4>; +}; From patchwork Wed Feb 20 07:44:16 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Sugaya Taichi X-Patchwork-Id: 10821587 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 4F5466C2 for ; Wed, 20 Feb 2019 07:43:40 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 357842D6BD for ; Wed, 20 Feb 2019 07:43:40 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id 29A232D6FC; Wed, 20 Feb 2019 07:43:40 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-2.9 required=2.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,MAILING_LIST_MULTI,MIME_HEADER_CTYPE_ONLY,RCVD_IN_DNSWL_LOW, T_TVD_MIME_NO_HEADERS autolearn=no version=3.3.1 Received: from web01.groups.io (web01.groups.io [66.175.222.12]) (using TLSv1.2 with cipher AES128-SHA (128/128 bits)) (No client certificate requested) by mail.wl.linuxfoundation.org (Postfix) with ESMTPS id A792F2D6BD for ; Wed, 20 Feb 2019 07:43:39 +0000 (UTC) X-Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by groups.io with SMTP; Tue, 19 Feb 2019 23:43:39 -0800 X-Received: by mail.kernel.org (Postfix) id C290B2183F; Wed, 20 Feb 2019 07:43:38 +0000 (UTC) X-Received: from mx.socionext.com (mx.socionext.com [202.248.49.38]) by mail.kernel.org (Postfix) with ESMTP id 65B2C20449 for ; Wed, 20 Feb 2019 07:43:38 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org 65B2C20449 X-Received: from unknown (HELO iyokan-ex.css.socionext.com) ([172.31.9.54]) by mx.socionext.com with ESMTP; 20 Feb 2019 16:43:37 +0900 X-Received: from mail.mfilter.local (m-filter-2 [10.213.24.62]) by iyokan-ex.css.socionext.com (Postfix) with ESMTP id B50CA6117D; Wed, 20 Feb 2019 16:43:37 +0900 (JST) X-Received: from 172.31.9.53 (172.31.9.53) by m-FILTER with ESMTP; Wed, 20 Feb 2019 16:43:37 +0900 X-Received: from yuzu.css.socionext.com (yuzu [172.31.8.45]) by iyokan.css.socionext.com (Postfix) with ESMTP id 495A640368; Wed, 20 Feb 2019 16:43:37 +0900 (JST) X-Received: from M20VSDK.e01.socionext.com (unknown [10.213.118.34]) by yuzu.css.socionext.com (Postfix) with ESMTP id 34994120459; Wed, 20 Feb 2019 16:43:37 +0900 (JST) From: Sugaya Taichi To: Linuxkernel+Patchwork-Soc via Email Integration Cc: Daniel Lezcano , Thomas Gleixner , Takao Orito , Kazuhiro Kasai , Shinji Kanematsu , Jassi Brar , Masami Hiramatsu , Sugaya Taichi Subject: [PATCH v3 6/9] clocksource/drivers/timer-milbeaut: Introduce timer for Milbeaut SoCs Date: Wed, 20 Feb 2019 16:44:16 +0900 Message-Id: <1550648656-10929-1-git-send-email-sugaya.taichi@socionext.com> Precedence: Bulk List-Unsubscribe: Sender: patchwork-soc@linux.kernel.org List-Id: Mailing-List: list patchwork-soc@linux.kernel.org; contact patchwork-soc+owner@linux.kernel.org Delivered-To: mailing list patchwork-soc@linux.kernel.org Reply-To: patchwork-soc+owner@linux.kernel.org DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=linux.kernel.org; q=dns/txt; s=20140610; t=1550648619; bh=djz9NJrp1cxPHqVEB3T9B8NlhRHVacuLqJHE1tgq2p0=; h=Cc:Content-Type:Date:From:Reply-To:Subject:To; b=LvYU/uCv6dpWKintLbY1pgPta8fxCpvoYkrf+ULR6pYbOCDwZHOYKKVAtOVyiyFxrit BdR2G+DJfVH9pAESV0gBBj9Crs9j0DiyEkvWmFdFl7VnzwzjvwPSTP3A38ZL2VF6JK/wI xzsRVjmL8P9pyPrc6X2U0gKZBmbnf38Dw5w= X-Virus-Scanned: ClamAV using ClamSMTP Add timer driver for Milbeaut SoCs series. The timer has two 32-bit width down counters, one of which is configured as a clockevent device and the other is configured as a clock source. Signed-off-by: Sugaya Taichi Acked-by: Daniel Lezcano --- drivers/clocksource/Kconfig | 9 ++ drivers/clocksource/Makefile | 1 + drivers/clocksource/timer-milbeaut.c | 161 +++++++++++++++++++++++++++++++++++ 3 files changed, 171 insertions(+) create mode 100644 drivers/clocksource/timer-milbeaut.c diff --git a/drivers/clocksource/Kconfig b/drivers/clocksource/Kconfig index a9e26f6..9101b8f 100644 --- a/drivers/clocksource/Kconfig +++ b/drivers/clocksource/Kconfig @@ -634,4 +634,13 @@ config GX6605S_TIMER help This option enables support for gx6605s SOC's timer. +config MILBEAUT_TIMER + bool "Milbeaut timer driver" if COMPILE_TEST + depends on OF + depends on ARM + select TIMER_OF + select CLKSRC_MMIO + help + Enables the support for Milbeaut timer driver. + endmenu diff --git a/drivers/clocksource/Makefile b/drivers/clocksource/Makefile index cdd210f..6f2543b 100644 --- a/drivers/clocksource/Makefile +++ b/drivers/clocksource/Makefile @@ -55,6 +55,7 @@ obj-$(CONFIG_CLKSRC_TI_32K) += timer-ti-32k.o obj-$(CONFIG_CLKSRC_NPS) += timer-nps.o obj-$(CONFIG_OXNAS_RPS_TIMER) += timer-oxnas-rps.o obj-$(CONFIG_OWL_TIMER) += timer-owl.o +obj-$(CONFIG_MILBEAUT_TIMER) += timer-milbeaut.o obj-$(CONFIG_SPRD_TIMER) += timer-sprd.o obj-$(CONFIG_NPCM7XX_TIMER) += timer-npcm7xx.o obj-$(CONFIG_RDA_TIMER) += timer-rda.o diff --git a/drivers/clocksource/timer-milbeaut.c b/drivers/clocksource/timer-milbeaut.c new file mode 100644 index 0000000..f2019a8 --- /dev/null +++ b/drivers/clocksource/timer-milbeaut.c @@ -0,0 +1,161 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (C) 2018 Socionext Inc. + */ + +#include +#include +#include +#include +#include +#include "timer-of.h" + +#define MLB_TMR_TMCSR_OFS 0x0 +#define MLB_TMR_TMR_OFS 0x4 +#define MLB_TMR_TMRLR1_OFS 0x8 +#define MLB_TMR_TMRLR2_OFS 0xc +#define MLB_TMR_REGSZPCH 0x10 + +#define MLB_TMR_TMCSR_OUTL BIT(5) +#define MLB_TMR_TMCSR_RELD BIT(4) +#define MLB_TMR_TMCSR_INTE BIT(3) +#define MLB_TMR_TMCSR_UF BIT(2) +#define MLB_TMR_TMCSR_CNTE BIT(1) +#define MLB_TMR_TMCSR_TRG BIT(0) + +#define MLB_TMR_TMCSR_CSL_DIV2 0 +#define MLB_TMR_DIV_CNT 2 + +#define MLB_TMR_SRC_CH (1) +#define MLB_TMR_EVT_CH (0) + +#define MLB_TMR_SRC_CH_OFS (MLB_TMR_REGSZPCH * MLB_TMR_SRC_CH) +#define MLB_TMR_EVT_CH_OFS (MLB_TMR_REGSZPCH * MLB_TMR_EVT_CH) + +#define MLB_TMR_SRC_TMCSR_OFS (MLB_TMR_SRC_CH_OFS + MLB_TMR_TMCSR_OFS) +#define MLB_TMR_SRC_TMR_OFS (MLB_TMR_SRC_CH_OFS + MLB_TMR_TMR_OFS) +#define MLB_TMR_SRC_TMRLR1_OFS (MLB_TMR_SRC_CH_OFS + MLB_TMR_TMRLR1_OFS) +#define MLB_TMR_SRC_TMRLR2_OFS (MLB_TMR_SRC_CH_OFS + MLB_TMR_TMRLR2_OFS) + +#define MLB_TMR_EVT_TMCSR_OFS (MLB_TMR_EVT_CH_OFS + MLB_TMR_TMCSR_OFS) +#define MLB_TMR_EVT_TMR_OFS (MLB_TMR_EVT_CH_OFS + MLB_TMR_TMR_OFS) +#define MLB_TMR_EVT_TMRLR1_OFS (MLB_TMR_EVT_CH_OFS + MLB_TMR_TMRLR1_OFS) +#define MLB_TMR_EVT_TMRLR2_OFS (MLB_TMR_EVT_CH_OFS + MLB_TMR_TMRLR2_OFS) + +#define MLB_TIMER_RATING 500 + +static irqreturn_t mlb_timer_interrupt(int irq, void *dev_id) +{ + struct clock_event_device *clk = dev_id; + struct timer_of *to = to_timer_of(clk); + u32 val; + + val = readl_relaxed(timer_of_base(to) + MLB_TMR_EVT_TMCSR_OFS); + val &= ~MLB_TMR_TMCSR_UF; + writel_relaxed(val, timer_of_base(to) + MLB_TMR_EVT_TMCSR_OFS); + + clk->event_handler(clk); + + return IRQ_HANDLED; +} + +static int mlb_set_state_periodic(struct clock_event_device *clk) +{ + struct timer_of *to = to_timer_of(clk); + u32 val = MLB_TMR_TMCSR_CSL_DIV2; + + writel_relaxed(val, timer_of_base(to) + MLB_TMR_EVT_TMCSR_OFS); + + writel_relaxed(to->of_clk.period, timer_of_base(to) + + MLB_TMR_EVT_TMRLR1_OFS); + val |= MLB_TMR_TMCSR_RELD | MLB_TMR_TMCSR_CNTE | + MLB_TMR_TMCSR_TRG | MLB_TMR_TMCSR_INTE; + writel_relaxed(val, timer_of_base(to) + MLB_TMR_EVT_TMCSR_OFS); + return 0; +} + +static int mlb_set_state_oneshot(struct clock_event_device *clk) +{ + struct timer_of *to = to_timer_of(clk); + u32 val = MLB_TMR_TMCSR_CSL_DIV2; + + writel_relaxed(val, timer_of_base(to) + MLB_TMR_EVT_TMCSR_OFS); + return 0; +} + +static int mlb_clkevt_next_event(unsigned long event, + struct clock_event_device *clk) +{ + struct timer_of *to = to_timer_of(clk); + + writel_relaxed(event, timer_of_base(to) + MLB_TMR_EVT_TMRLR1_OFS); + writel_relaxed(MLB_TMR_TMCSR_CSL_DIV2 | + MLB_TMR_TMCSR_CNTE | MLB_TMR_TMCSR_INTE | + MLB_TMR_TMCSR_TRG, timer_of_base(to) + + MLB_TMR_EVT_TMCSR_OFS); + return 0; +} + +static int mlb_config_clock_source(struct timer_of *to) +{ + writel_relaxed(0, timer_of_base(to) + MLB_TMR_SRC_TMCSR_OFS); + writel_relaxed(~0, timer_of_base(to) + MLB_TMR_SRC_TMR_OFS); + writel_relaxed(~0, timer_of_base(to) + MLB_TMR_SRC_TMRLR1_OFS); + writel_relaxed(~0, timer_of_base(to) + MLB_TMR_SRC_TMRLR2_OFS); + writel_relaxed(BIT(4) | BIT(1) | BIT(0), timer_of_base(to) + + MLB_TMR_SRC_TMCSR_OFS); + return 0; +} + +static int mlb_config_clock_event(struct timer_of *to) +{ + writel_relaxed(0, timer_of_base(to) + MLB_TMR_EVT_TMCSR_OFS); + return 0; +} + +static struct timer_of to = { + .flags = TIMER_OF_IRQ | TIMER_OF_BASE | TIMER_OF_CLOCK, + + .clkevt = { + .name = "mlb-clkevt", + .rating = MLB_TIMER_RATING, + .cpumask = cpu_possible_mask, + .features = CLOCK_EVT_FEAT_DYNIRQ | CLOCK_EVT_FEAT_ONESHOT, + .set_state_oneshot = mlb_set_state_oneshot, + .set_state_periodic = mlb_set_state_periodic, + .set_next_event = mlb_clkevt_next_event, + }, + + .of_irq = { + .flags = IRQF_TIMER | IRQF_IRQPOLL, + .handler = mlb_timer_interrupt, + }, +}; + +static u64 notrace mlb_timer_sched_read(void) +{ + return ~readl_relaxed(timer_of_base(&to) + MLB_TMR_SRC_TMR_OFS); +} + +static int __init mlb_timer_init(struct device_node *node) +{ + int ret; + unsigned long rate; + + ret = timer_of_init(node, &to); + if (ret) + return ret; + + rate = timer_of_rate(&to) / MLB_TMR_DIV_CNT; + mlb_config_clock_source(&to); + clocksource_mmio_init(timer_of_base(&to) + MLB_TMR_SRC_TMR_OFS, + node->name, rate, MLB_TIMER_RATING, 32, + clocksource_mmio_readl_down); + sched_clock_register(mlb_timer_sched_read, 32, rate); + mlb_config_clock_event(&to); + clockevents_config_and_register(&to.clkevt, timer_of_rate(&to), 15, + 0xffffffff); + return 0; +} +TIMER_OF_DECLARE(mlb_peritimer, "socionext,milbeaut-timer", + mlb_timer_init); From patchwork Wed Feb 20 07:44:37 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Sugaya Taichi X-Patchwork-Id: 10821591 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id A515A6C2 for ; Wed, 20 Feb 2019 07:44:00 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 8A1C22BF28 for ; Wed, 20 Feb 2019 07:44:00 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id 7CCC92C0C0; Wed, 20 Feb 2019 07:44:00 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-2.9 required=2.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,MAILING_LIST_MULTI,MIME_HEADER_CTYPE_ONLY,RCVD_IN_DNSWL_LOW, T_TVD_MIME_NO_HEADERS autolearn=no version=3.3.1 Received: from web01.groups.io (web01.groups.io [66.175.222.12]) (using TLSv1.2 with cipher AES128-SHA (128/128 bits)) (No client certificate requested) by mail.wl.linuxfoundation.org (Postfix) with ESMTPS id 391F62BF28 for ; Wed, 20 Feb 2019 07:44:00 +0000 (UTC) X-Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by groups.io with SMTP; Tue, 19 Feb 2019 23:43:59 -0800 X-Received: by mail.kernel.org (Postfix) id 8C84E21773; Wed, 20 Feb 2019 07:43:59 +0000 (UTC) X-Received: from mx.socionext.com (mx.socionext.com [202.248.49.38]) by mail.kernel.org (Postfix) with ESMTP id 2DAA42077B; Wed, 20 Feb 2019 07:43:58 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org 2DAA42077B X-Received: from unknown (HELO iyokan-ex.css.socionext.com) ([172.31.9.54]) by mx.socionext.com with ESMTP; 20 Feb 2019 16:43:58 +0900 X-Received: from mail.mfilter.local (m-filter-2 [10.213.24.62]) by iyokan-ex.css.socionext.com (Postfix) with ESMTP id 63BB06117D; Wed, 20 Feb 2019 16:43:58 +0900 (JST) X-Received: from 172.31.9.53 (172.31.9.53) by m-FILTER with ESMTP; Wed, 20 Feb 2019 16:43:58 +0900 X-Received: from yuzu.css.socionext.com (yuzu [172.31.8.45]) by iyokan.css.socionext.com (Postfix) with ESMTP id F259B40368; Wed, 20 Feb 2019 16:43:57 +0900 (JST) X-Received: from M20VSDK.e01.socionext.com (unknown [10.213.118.34]) by yuzu.css.socionext.com (Postfix) with ESMTP id D6D71120459; Wed, 20 Feb 2019 16:43:57 +0900 (JST) From: Sugaya Taichi To: Linuxkernel+Patchwork-Soc via Email Integration Cc: Greg Kroah-Hartman , Rob Herring , Mark Rutland , Takao Orito , Kazuhiro Kasai , Shinji Kanematsu , Jassi Brar , Masami Hiramatsu , Sugaya Taichi Subject: [PATCH v3 7/9] dt-bindings: serial: Add Milbeaut serial driver description Date: Wed, 20 Feb 2019 16:44:37 +0900 Message-Id: <1550648677-11164-1-git-send-email-sugaya.taichi@socionext.com> Precedence: Bulk List-Unsubscribe: Sender: patchwork-soc@linux.kernel.org List-Id: Mailing-List: list patchwork-soc@linux.kernel.org; contact patchwork-soc+owner@linux.kernel.org Delivered-To: mailing list patchwork-soc@linux.kernel.org Reply-To: patchwork-soc+owner@linux.kernel.org DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=linux.kernel.org; q=dns/txt; s=20140610; t=1550648640; bh=weNCB1RVorVyABssaTUXyqk4goAUvapuoTM+X/8Dd5o=; h=Cc:Content-Type:Date:From:Reply-To:Subject:To; b=pfcnIz23hDCP5qJTY8TPAC9gLlCncHpgO3yu7B7F7ufkSqemQ7WJJFl8dTiU272ccGu lGhRBVP9mTFdrmQSjYzqd9AWEA6UhRbosSLjoSfWC4HQGI5BbjAnMlltdzKcaL2pHflZG bLLshEGxgt+4QTbrXJ88EwT2ABtzfL+eX/4= X-Virus-Scanned: ClamAV using ClamSMTP Add DT bindings document for Milbeaut serial driver. Signed-off-by: Sugaya Taichi Reviewed-by: Rob Herring --- .../devicetree/bindings/serial/milbeaut-uart.txt | 21 +++++++++++++++++++++ 1 file changed, 21 insertions(+) create mode 100644 Documentation/devicetree/bindings/serial/milbeaut-uart.txt diff --git a/Documentation/devicetree/bindings/serial/milbeaut-uart.txt b/Documentation/devicetree/bindings/serial/milbeaut-uart.txt new file mode 100644 index 0000000..3d2fb1a --- /dev/null +++ b/Documentation/devicetree/bindings/serial/milbeaut-uart.txt @@ -0,0 +1,21 @@ +Socionext Milbeaut UART controller + +Required properties: +- compatible: should be "socionext,milbeaut-usio-uart". +- reg: offset and length of the register set for the device. +- interrupts: two interrupts specifier. +- interrupt-names: should be "rx", "tx". +- clocks: phandle to the input clock. + +Optional properties: +- auto-flow-control: flow control enable. + +Example: + usio1: usio_uart@1e700010 { + compatible = "socionext,milbeaut-usio-uart"; + reg = <0x1e700010 0x10>; + interrupts = <0 141 0x4>, <0 149 0x4>; + interrupt-names = "rx", "tx"; + clocks = <&clk 2>; + auto-flow-control; + }; From patchwork Wed Feb 20 07:44:53 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Sugaya Taichi X-Patchwork-Id: 10821595 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 316706C2 for ; Wed, 20 Feb 2019 07:44:18 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 18E322BF28 for ; Wed, 20 Feb 2019 07:44:18 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id 09F632C0C0; Wed, 20 Feb 2019 07:44:18 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-2.9 required=2.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,MAILING_LIST_MULTI,MIME_HEADER_CTYPE_ONLY,RCVD_IN_DNSWL_LOW, T_TVD_MIME_NO_HEADERS autolearn=no version=3.3.1 Received: from web01.groups.io (web01.groups.io [66.175.222.12]) (using TLSv1.2 with cipher AES128-SHA (128/128 bits)) (No client certificate requested) by mail.wl.linuxfoundation.org (Postfix) with ESMTPS id 9F93A2BF28 for ; Wed, 20 Feb 2019 07:44:17 +0000 (UTC) X-Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by groups.io with SMTP; Tue, 19 Feb 2019 23:44:17 -0800 X-Received: by mail.kernel.org (Postfix) id F10DE2183F; Wed, 20 Feb 2019 07:44:16 +0000 (UTC) X-Received: from mx.socionext.com (mx.socionext.com [202.248.49.38]) by mail.kernel.org (Postfix) with ESMTP id 5445A20818; Wed, 20 Feb 2019 07:44:16 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org 5445A20818 X-Received: from unknown (HELO kinkan-ex.css.socionext.com) ([172.31.9.52]) by mx.socionext.com with ESMTP; 20 Feb 2019 16:44:15 +0900 X-Received: from mail.mfilter.local (m-filter-1 [10.213.24.61]) by kinkan-ex.css.socionext.com (Postfix) with ESMTP id B0E5E180097; Wed, 20 Feb 2019 16:44:15 +0900 (JST) X-Received: from 172.31.9.53 (172.31.9.53) by m-FILTER with ESMTP; Wed, 20 Feb 2019 16:44:15 +0900 X-Received: from yuzu.css.socionext.com (yuzu [172.31.8.45]) by iyokan.css.socionext.com (Postfix) with ESMTP id 2185440368; Wed, 20 Feb 2019 16:44:15 +0900 (JST) X-Received: from M20VSDK.e01.socionext.com (unknown [10.213.118.34]) by yuzu.css.socionext.com (Postfix) with ESMTP id 0A80F120459; Wed, 20 Feb 2019 16:44:15 +0900 (JST) From: Sugaya Taichi To: Linuxkernel+Patchwork-Soc via Email Integration Cc: Rob Herring , Mark Rutland , Takao Orito , Kazuhiro Kasai , Shinji Kanematsu , Jassi Brar , Masami Hiramatsu , Sugaya Taichi Subject: [PATCH v3 8/9] ARM: dts: milbeaut: Add device tree set for the Milbeaut M10V board Date: Wed, 20 Feb 2019 16:44:53 +0900 Message-Id: <1550648693-11382-1-git-send-email-sugaya.taichi@socionext.com> Precedence: Bulk List-Unsubscribe: Sender: patchwork-soc@linux.kernel.org List-Id: Mailing-List: list patchwork-soc@linux.kernel.org; contact patchwork-soc+owner@linux.kernel.org Delivered-To: mailing list patchwork-soc@linux.kernel.org Reply-To: patchwork-soc+owner@linux.kernel.org DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=linux.kernel.org; q=dns/txt; s=20140610; t=1550648657; bh=57LwKiD9z9oDTIM7sY14cp6NzqayhHNPHXyA5SZRo+w=; h=Cc:Content-Type:Date:From:Reply-To:Subject:To; b=fUHaTsyyJW6mYWje1dD+l6eBo2fvWbdVNgBYlXiIS7Hmg23uJNt5dY8KIMaFribThSl qiQx87TfjpSM9YSbuykKICifT9GA3GmrXXn+6YgdmrjKrxZRusqx+TfL1aspX7S63Axlk DndhkG0j3DQr4vo0B/nIm8By2L4epvJz7pg= X-Virus-Scanned: ClamAV using ClamSMTP Add devicetree for Milbeaut M10V SoC and M10V Evaluation board. Signed-off-by: Sugaya Taichi --- arch/arm/boot/dts/Makefile | 1 + arch/arm/boot/dts/milbeaut-m10v-evb.dts | 32 +++++++++++ arch/arm/boot/dts/milbeaut-m10v.dtsi | 95 +++++++++++++++++++++++++++++++++ 3 files changed, 128 insertions(+) create mode 100644 arch/arm/boot/dts/milbeaut-m10v-evb.dts create mode 100644 arch/arm/boot/dts/milbeaut-m10v.dtsi diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile index bd40148..f697d87 100644 --- a/arch/arm/boot/dts/Makefile +++ b/arch/arm/boot/dts/Makefile @@ -1233,6 +1233,7 @@ dtb-$(CONFIG_ARCH_MEDIATEK) += \ mt7623n-bananapi-bpi-r2.dtb \ mt8127-moose.dtb \ mt8135-evbp1.dtb +dtb-$(CONFIG_ARCH_MILBEAUT) += milbeaut-m10v-evb.dtb dtb-$(CONFIG_ARCH_ZX) += zx296702-ad1.dtb dtb-$(CONFIG_ARCH_ASPEED) += \ aspeed-ast2500-evb.dtb \ diff --git a/arch/arm/boot/dts/milbeaut-m10v-evb.dts b/arch/arm/boot/dts/milbeaut-m10v-evb.dts new file mode 100644 index 0000000..614f60c --- /dev/null +++ b/arch/arm/boot/dts/milbeaut-m10v-evb.dts @@ -0,0 +1,32 @@ +// SPDX-License-Identifier: GPL-2.0 +/* Socionext Milbeaut M10V Evaluation Board */ +/dts-v1/; +#include "milbeaut-m10v.dtsi" + +/ { + model = "Socionext M10V EVB"; + compatible = "socionext,milbeaut-m10v-evb", "socionext,sc2000a"; + + aliases { + serial0 = &uart1; + }; + + chosen { + bootargs = "rootwait earlycon"; + stdout-path = "serial0:115200n8"; + }; + + clocks { + uclk40xi: uclk40xi { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <40000000>; + }; + }; + + memory@40000000 { + device_type = "memory"; + reg = <0x40000000 0x80000000>; + }; + +}; diff --git a/arch/arm/boot/dts/milbeaut-m10v.dtsi b/arch/arm/boot/dts/milbeaut-m10v.dtsi new file mode 100644 index 0000000..aa7c6ca --- /dev/null +++ b/arch/arm/boot/dts/milbeaut-m10v.dtsi @@ -0,0 +1,95 @@ +// SPDX-License-Identifier: GPL-2.0 +#include +#include +#include +#include + +/ { + compatible = "socionext,sc2000a"; + interrupt-parent = <&gic>; + #address-cells = <1>; + #size-cells = <1>; + + cpus { + #address-cells = <1>; + #size-cells = <0>; + enable-method = "socionext,milbeaut-m10v-smp"; + cpu@f00 { + device_type = "cpu"; + compatible = "arm,cortex-a7"; + reg = <0xf00>; + }; + cpu@f01 { + device_type = "cpu"; + compatible = "arm,cortex-a7"; + reg = <0xf01>; + }; + cpu@f02 { + device_type = "cpu"; + compatible = "arm,cortex-a7"; + reg = <0xf02>; + }; + cpu@f03 { + device_type = "cpu"; + compatible = "arm,cortex-a7"; + reg = <0xf03>; + }; + }; + + timer { /* The Generic Timer */ + compatible = "arm,armv7-timer"; + interrupts = , + , + , + ; + clock-frequency = <40000000>; + always-on; + }; + + soc { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <1>; + ranges; + interrupt-parent = <&gic>; + + gic: interrupt-controller@1d000000 { + compatible = "arm,cortex-a7-gic"; + interrupt-controller; + #interrupt-cells = <3>; + reg = <0x1d001000 0x1000>, + <0x1d002000 0x1000>; /* CPU I/f base and size */ + }; + + timer@1e000050 { /* 32-bit Reload Timers */ + compatible = "socionext,milbeaut-timer"; + reg = <0x1e000050 0x20>; + interrupts = <0 91 4>; + }; + + uart1: serial@1e700010 { /* PE4, PE5 */ + /* Enable this as ttyUSI0 */ + compatible = "socionext,milbeaut-usio-uart"; + reg = <0x1e700010 0x10>; + interrupts = <0 141 0x4>, <0 149 0x4>; + interrupt-names = "rx", "tx"; + }; + + }; + + sram@0 { + compatible = "mmio-sram"; + reg = <0x0 0x10000>; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0 0x0 0x10000>; + smp-sram@f100 { + compatible = "socionext,milbeaut-smp-sram"; + reg = <0xf100 0x20>; + }; + }; +}; From patchwork Wed Feb 20 07:45:04 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Sugaya Taichi X-Patchwork-Id: 10821597 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 0BF6B1575 for ; Wed, 20 Feb 2019 07:44:28 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id E81F62C249 for ; Wed, 20 Feb 2019 07:44:27 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id DC25B2C399; Wed, 20 Feb 2019 07:44:27 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-2.9 required=2.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,MAILING_LIST_MULTI,MIME_HEADER_CTYPE_ONLY,RCVD_IN_DNSWL_LOW, T_TVD_MIME_NO_HEADERS,UPPERCASE_50_75 autolearn=no version=3.3.1 Received: from web01.groups.io (web01.groups.io [66.175.222.12]) (using TLSv1.2 with cipher AES128-SHA (128/128 bits)) (No client certificate requested) by mail.wl.linuxfoundation.org (Postfix) with ESMTPS id 77BC82C249 for ; Wed, 20 Feb 2019 07:44:27 +0000 (UTC) X-Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by groups.io with SMTP; Tue, 19 Feb 2019 23:44:27 -0800 X-Received: by mail.kernel.org (Postfix) id B820321773; Wed, 20 Feb 2019 07:44:26 +0000 (UTC) X-Received: from mx.socionext.com (mx.socionext.com [202.248.49.38]) by mail.kernel.org (Postfix) with ESMTP id 3283420818 for ; Wed, 20 Feb 2019 07:44:26 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org 3283420818 X-Received: from unknown (HELO kinkan-ex.css.socionext.com) ([172.31.9.52]) by mx.socionext.com with ESMTP; 20 Feb 2019 16:44:25 +0900 X-Received: from mail.mfilter.local (m-filter-1 [10.213.24.61]) by kinkan-ex.css.socionext.com (Postfix) with ESMTP id 87A5D180097; Wed, 20 Feb 2019 16:44:25 +0900 (JST) X-Received: from 172.31.9.51 (172.31.9.51) by m-FILTER with ESMTP; Wed, 20 Feb 2019 16:44:25 +0900 X-Received: from yuzu.css.socionext.com (yuzu [172.31.8.45]) by kinkan.css.socionext.com (Postfix) with ESMTP id EC6DD1A04E0; Wed, 20 Feb 2019 16:44:24 +0900 (JST) X-Received: from M20VSDK.e01.socionext.com (unknown [10.213.118.34]) by yuzu.css.socionext.com (Postfix) with ESMTP id CF95E120459; Wed, 20 Feb 2019 16:44:24 +0900 (JST) From: Sugaya Taichi To: Linuxkernel+Patchwork-Soc via Email Integration Cc: Arnd Bergmann , Takao Orito , Kazuhiro Kasai , Shinji Kanematsu , Jassi Brar , Masami Hiramatsu , Sugaya Taichi Subject: [PATCH v3 9/9] ARM: configs: Add Milbeaut M10V defconfig Date: Wed, 20 Feb 2019 16:45:04 +0900 Message-Id: <1550648704-11545-1-git-send-email-sugaya.taichi@socionext.com> Precedence: Bulk List-Unsubscribe: Sender: patchwork-soc@linux.kernel.org List-Id: Mailing-List: list patchwork-soc@linux.kernel.org; contact patchwork-soc+owner@linux.kernel.org Delivered-To: mailing list patchwork-soc@linux.kernel.org Reply-To: patchwork-soc+owner@linux.kernel.org DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=linux.kernel.org; q=dns/txt; s=20140610; t=1550648667; bh=J2SV/9jjfduhUo9h3Khnr31acaXkPHhaki/b7lSiVEU=; h=Cc:Content-Type:Date:From:Reply-To:Subject:To; b=MrC6+u9LH5fGXzR6W7MQbIuSiCkDdzqgppfcyHnuc9XruUBhY8VSCBCupmR5MIaUCpd IxKsLFBLk3ISBHAs1zvkIw7lH5++qRrHGYVrLiwT7EhcLnUUMIFfEsnwyECu+USjBLYnY Ga7PpVrL5PAHVxAB834RCPIItog+laVgHIY= X-Virus-Scanned: ClamAV using ClamSMTP This patch adds the minimal defconfig for the Milbeaut M10V. Signed-off-by: Sugaya Taichi --- arch/arm/configs/milbeaut_m10v_defconfig | 175 +++++++++++++++++++++++++++++++ arch/arm/configs/multi_v7_defconfig | 2 + 2 files changed, 177 insertions(+) create mode 100644 arch/arm/configs/milbeaut_m10v_defconfig diff --git a/arch/arm/configs/milbeaut_m10v_defconfig b/arch/arm/configs/milbeaut_m10v_defconfig new file mode 100644 index 0000000..a263211 --- /dev/null +++ b/arch/arm/configs/milbeaut_m10v_defconfig @@ -0,0 +1,175 @@ +# CONFIG_LOCALVERSION_AUTO is not set +CONFIG_DEBUG_SEMIHOSTING=y +CONFIG_DEFAULT_HOSTNAME="mlbel" +CONFIG_SYSVIPC=y +CONFIG_POSIX_MQUEUE=y +CONFIG_FHANDLE=y +CONFIG_NO_HZ_FULL=y +CONFIG_NO_HZ_FULL_ALL=y +CONFIG_NO_HZ_FULL_SYSIDLE=y +CONFIG_NO_HZ_FULL_SYSIDLE_SMALL=4 +CONFIG_HIGH_RES_TIMERS=y +CONFIG_BSD_PROCESS_ACCT=y +CONFIG_BSD_PROCESS_ACCT_V3=y +CONFIG_TASKSTATS=y +CONFIG_TASK_DELAY_ACCT=y +CONFIG_TASK_XACCT=y +CONFIG_TASK_IO_ACCOUNTING=y +CONFIG_IKCONFIG=y +CONFIG_IKCONFIG_PROC=y +CONFIG_CGROUPS=y +CONFIG_CGROUP_DEBUG=y +CONFIG_CPUSETS=y +CONFIG_CGROUP_SCHED=y +CONFIG_CFS_BANDWIDTH=y +CONFIG_RT_GROUP_SCHED=y +CONFIG_NAMESPACES=y +CONFIG_USER_NS=y +CONFIG_BLK_DEV_INITRD=y +CONFIG_CC_OPTIMIZE_FOR_SIZE=y +CONFIG_KALLSYMS_ALL=y +# CONFIG_COMPAT_BRK is not set +CONFIG_SLAB=y +CONFIG_PROFILING=y +# CONFIG_OPROFILE=m +CONFIG_MODULES=y +CONFIG_MODULE_UNLOAD=y +CONFIG_ARCH_MILBEAUT=y +CONFIG_ARCH_MILBEAUT_M10V=y +# CONFIG_CACHE_L2X0 is not set +CONFIG_ARM_ERRATA_754322=y +CONFIG_ARM_ERRATA_775420=y +CONFIG_SMP=y +# CONFIG_ARM_CPU_TOPOLOGY is not set +CONFIG_HAVE_ARM_ARCH_TIMER=y +CONFIG_PREEMPT=y +CONFIG_THUMB2_KERNEL=y +CONFIG_HIGHMEM=y +# CONFIG_COMPACTION is not set +CONFIG_CMA=y +# CONFIG_ATAGS is not set +CONFIG_ZBOOT_ROM_TEXT=0x0 +CONFIG_ZBOOT_ROM_BSS=0x0 +CONFIG_KEXEC=y +CONFIG_CPU_FREQ=y +CONFIG_CPU_FREQ_DEFAULT_GOV_ONDEMAND=y +CONFIG_CPUFREQ_DT=y +CONFIG_CPU_IDLE=y +CONFIG_VFP=y +CONFIG_NEON=y +CONFIG_KERNEL_MODE_NEON=y +CONFIG_WQ_POWER_EFFICIENT_DEFAULT=y +CONFIG_UNIX=y +CONFIG_DEVTMPFS=y +CONFIG_DEVTMPFS_MOUNT=y +CONFIG_DMA_CMA=y +CONFIG_CMA_SIZE_MBYTES=16 +CONFIG_BLK_DEV_LOOP=y +CONFIG_BLK_DEV_LOOP_MIN_COUNT=2 +CONFIG_BLK_DEV_RAM=y +CONFIG_SCSI=y +CONFIG_BLK_DEV_SD=y +CONFIG_VETH=y +CONFIG_INPUT_POLLDEV=y +# CONFIG_INPUT_MOUSEDEV is not set +CONFIG_INPUT_EVDEV=y +# CONFIG_INPUT_KEYBOARD is not set +# CONFIG_INPUT_MOUSE is not set +CONFIG_SERIO_LIBPS2=y +CONFIG_LEGACY_PTY_COUNT=4 +CONFIG_GPIOLIB=y +CONFIG_GPIO_SYSFS=y +# CONFIG_HWMON is not set +CONFIG_WATCHDOG=y +CONFIG_SOFT_WATCHDOG=m +CONFIG_REGULATOR=y +CONFIG_REGULATOR_DEBUG=y +CONFIG_REGULATOR_S6AP412=y +CONFIG_MEDIA_SUPPORT=y +CONFIG_MEDIA_CAMERA_SUPPORT=y +CONFIG_MEDIA_CONTROLLER=y +CONFIG_VIDEO_ADV_DEBUG=y +CONFIG_SOC_CAMERA=y +CONFIG_SOC_CAMERA_PLATFORM=y +# CONFIG_VGA_ARB is not set +CONFIG_DMADEVICES=y +CONFIG_UIO=y +# CONFIG_IOMMU_SUPPORT is not set +CONFIG_RESET_CONTROLLER=y +CONFIG_EXT4_FS=y +# CONFIG_EXT4_USE_FOR_EXT23 is not set +# CONFIG_XFS_FS is not set +CONFIG_FANOTIFY=y +CONFIG_FANOTIFY_ACCESS_PERMISSIONS=y +CONFIG_QUOTA=y +CONFIG_AUTOFS4_FS=y +# CONFIG_FUSE_FS is not set +CONFIG_FSCACHE=y +CONFIG_FSCACHE_STATS=y +CONFIG_FSCACHE_HISTOGRAM=y +CONFIG_MSDOS_FS=y +CONFIG_VFAT_FS=y +CONFIG_FAT_DEFAULT_CODEPAGE=932 +CONFIG_TMPFS=y +CONFIG_TMPFS_POSIX_ACL=y +CONFIG_ROMFS_FS=y +CONFIG_ROMFS_BACKED_BY_BOTH=y +CONFIG_NFS_FS=m +CONFIG_NLS_CODEPAGE_437=y +CONFIG_NLS_CODEPAGE_737=y +CONFIG_NLS_CODEPAGE_775=y +CONFIG_NLS_CODEPAGE_850=y +CONFIG_NLS_CODEPAGE_852=y +CONFIG_NLS_CODEPAGE_855=y +CONFIG_NLS_CODEPAGE_857=y +CONFIG_NLS_CODEPAGE_860=y +CONFIG_NLS_CODEPAGE_861=y +CONFIG_NLS_CODEPAGE_862=y +CONFIG_NLS_CODEPAGE_863=y +CONFIG_NLS_CODEPAGE_864=y +CONFIG_NLS_CODEPAGE_865=y +CONFIG_NLS_CODEPAGE_866=y +CONFIG_NLS_CODEPAGE_869=y +CONFIG_NLS_CODEPAGE_936=y +CONFIG_NLS_CODEPAGE_950=y +CONFIG_NLS_CODEPAGE_932=y +CONFIG_NLS_CODEPAGE_949=y +CONFIG_NLS_CODEPAGE_874=y +CONFIG_NLS_ISO8859_8=y +CONFIG_NLS_CODEPAGE_1250=y +CONFIG_NLS_CODEPAGE_1251=y +CONFIG_NLS_ASCII=y +CONFIG_NLS_ISO8859_1=y +CONFIG_NLS_ISO8859_2=y +CONFIG_NLS_ISO8859_3=y +CONFIG_NLS_ISO8859_4=y +CONFIG_NLS_ISO8859_5=y +CONFIG_NLS_ISO8859_6=y +CONFIG_NLS_ISO8859_7=y +CONFIG_NLS_ISO8859_9=y +CONFIG_NLS_ISO8859_13=y +CONFIG_NLS_ISO8859_14=y +CONFIG_NLS_ISO8859_15=y +CONFIG_NLS_KOI8_R=y +CONFIG_NLS_KOI8_U=y +CONFIG_NLS_MAC_ROMAN=y +CONFIG_NLS_MAC_CELTIC=y +CONFIG_NLS_MAC_CENTEURO=y +CONFIG_NLS_MAC_CROATIAN=y +CONFIG_NLS_MAC_CYRILLIC=y +CONFIG_NLS_MAC_GAELIC=y +CONFIG_NLS_MAC_GREEK=y +CONFIG_NLS_MAC_ICELAND=y +CONFIG_NLS_MAC_INUIT=y +CONFIG_NLS_MAC_ROMANIAN=y +CONFIG_NLS_MAC_TURKISH=y +CONFIG_NLS_UTF8=y +CONFIG_PRINTK_TIME=y +CONFIG_HEADERS_CHECK=y +CONFIG_RCU_TORTURE_TEST=m +CONFIG_RCU_CPU_STALL_TIMEOUT=60 +CONFIG_KGDB=y +CONFIG_KEYS=y +CONFIG_ENCRYPTED_KEYS=y +CONFIG_SECURITY=y +CONFIG_FONTS=y diff --git a/arch/arm/configs/multi_v7_defconfig b/arch/arm/configs/multi_v7_defconfig index 5bee34a..6753805 100644 --- a/arch/arm/configs/multi_v7_defconfig +++ b/arch/arm/configs/multi_v7_defconfig @@ -54,6 +54,8 @@ CONFIG_SOC_VF610=y CONFIG_ARCH_KEYSTONE=y CONFIG_ARCH_MEDIATEK=y CONFIG_ARCH_MESON=y +CONFIG_ARCH_MILBEAUT=y +CONFIG_ARCH_MILBEAUT_M10V=y CONFIG_ARCH_MVEBU=y CONFIG_MACH_ARMADA_370=y CONFIG_MACH_ARMADA_375=y