From patchwork Fri Feb 16 17:42:10 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Gregory CLEMENT X-Patchwork-Id: 13560386 Received: from relay4-d.mail.gandi.net (relay4-d.mail.gandi.net [217.70.183.196]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 94D68131E5D; Fri, 16 Feb 2024 17:42:33 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=217.70.183.196 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1708105356; cv=none; b=sFrbaJdL1qJrWrJOnjacWmzwQUmebq+ohDF8T5psi/OLDCogq3vih1W83031cEQsxXiH8wW9n5YjJdVmACQQb9WbIYYVx55NZFRHnHyMaejZilz0v3RyD69bAPb/iUFd5GzYYF2YL5hJGOH+R+2gDTOzsMt7BmpL7L3k2GjO3UQ= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1708105356; c=relaxed/simple; bh=BOyUr0UPDVUOYNogVV+QAoPG/ry4w9cdTDK057dLQUY=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=Y+JdZvPe9rs5890OCh1+Soqs7jZJ4JAZc19RoDR3CsgHt84Q4yfEdaoORTj8yPF/9HeF0cFnxnTaLDldHzDY7IlNArSO9cJJBMEjMtal+n2w7XFSGY9IuC0rnSjUZbQ915DT1XlfkmFwtPHe8Toq97PJOh/c8pYyIkmT8HdJt2k= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=bootlin.com; spf=pass smtp.mailfrom=bootlin.com; dkim=pass (2048-bit key) header.d=bootlin.com header.i=@bootlin.com header.b=LCeO7g3c; arc=none smtp.client-ip=217.70.183.196 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=bootlin.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=bootlin.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=bootlin.com header.i=@bootlin.com header.b="LCeO7g3c" Received: by mail.gandi.net (Postfix) with ESMTPSA id EAD5FE000B; Fri, 16 Feb 2024 17:42:30 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=bootlin.com; s=gm1; t=1708105351; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=Axj8HIASMHBgR5o6/moj3w8Gd2MoT6J/01JlLIK6CjU=; b=LCeO7g3cmQ8ws+ptQzzKkby+O9joy+f78CNxM51dRmhL13QhNRpzDpdv5ekU9BAHgaL4OY ampfuviabKpB7YgS8wqMILqJWjbhQ3ff977UU/SM/qcp801fEgJ4vnvvvMiJVqZrIs8JKh rK8AjsJhvQnbHRKW8iVQGiILDQ6tijpkNNEgP+W0E4JlIyE6xF6DkZ412alLOZ7q95HYfa 7eNvYHd5qg8/XCNC8ghUuiAHoQ7lUb5zprRVI5ZIAXppw8fsuHtnaK+FYj+CfArct+U/DO 9+QlL/FsEssu1cnw7tA3gH2au+VIriC+rO3+8Zv/KQuQIBWSVpJPqXLbiY9/0w== From: Gregory CLEMENT To: Paul Burton , Thomas Bogendoerfer , linux-mips@vger.kernel.org, Jiaxun Yang , Rob Herring , Krzysztof Kozlowski , devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Cc: Vladimir Kondratiev , Tawfik Bayouk , Alexandre Belloni , =?utf-8?q?Th=C3=A9o_Lebr?= =?utf-8?q?un?= , Thomas Petazzoni , Gregory CLEMENT Subject: [PATCH v8 01/14] MIPS: spaces: Define a couple of handy macros Date: Fri, 16 Feb 2024 18:42:10 +0100 Message-ID: <20240216174227.409400-2-gregory.clement@bootlin.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20240216174227.409400-1-gregory.clement@bootlin.com> References: <20240216174227.409400-1-gregory.clement@bootlin.com> Precedence: bulk X-Mailing-List: linux-mips@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-GND-Sasl: gregory.clement@bootlin.com Define KSEGX_SIZE to represent the size of each KSEG segment. Introduce CKSEG0ADDR_OR_64BIT and CKSEG1ADDR_OR_64BIT to get an XPHYS address in 64bits and CKSEG[01]ADDR() in 32 bits mode. Co-developed-by: Jiaxun Yang Signed-off-by: Gregory CLEMENT --- arch/mips/include/asm/addrspace.h | 5 +++++ arch/mips/include/asm/mach-generic/spaces.h | 4 ++++ 2 files changed, 9 insertions(+) diff --git a/arch/mips/include/asm/addrspace.h b/arch/mips/include/asm/addrspace.h index 59a48c60a065c..7e9ef01cb182b 100644 --- a/arch/mips/include/asm/addrspace.h +++ b/arch/mips/include/asm/addrspace.h @@ -47,6 +47,11 @@ */ #define KSEGX(a) ((_ACAST32_(a)) & _ACAST32_(0xe0000000)) +/* + * Gives the size of each kernel segment + */ +#define CSEGX_SIZE 0x20000000 + /* * Returns the physical address of a CKSEGx / XKPHYS address */ diff --git a/arch/mips/include/asm/mach-generic/spaces.h b/arch/mips/include/asm/mach-generic/spaces.h index b247575c5e699..f8783d339fb0d 100644 --- a/arch/mips/include/asm/mach-generic/spaces.h +++ b/arch/mips/include/asm/mach-generic/spaces.h @@ -49,6 +49,8 @@ #define HIGHMEM_START _AC(0x20000000, UL) #endif +#define CKSEG0ADDR_OR_64BIT(x) CKSEG0ADDR(x) +#define CKSEG1ADDR_OR_64BIT(x) CKSEG1ADDR(x) #endif /* CONFIG_32BIT */ #ifdef CONFIG_64BIT @@ -82,6 +84,8 @@ #define TO_CAC(x) (CAC_BASE | ((x) & TO_PHYS_MASK)) #define TO_UNCAC(x) (UNCAC_BASE | ((x) & TO_PHYS_MASK)) +#define CKSEG0ADDR_OR_64BIT(x) TO_CAC(x) +#define CKSEG1ADDR_OR_64BIT(x) TO_UNCAC(x) #endif /* CONFIG_64BIT */ /* From patchwork Fri Feb 16 17:42:11 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Gregory CLEMENT X-Patchwork-Id: 13560388 Received: from relay1-d.mail.gandi.net (relay1-d.mail.gandi.net [217.70.183.193]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id AD4D4132472; Fri, 16 Feb 2024 17:42:34 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=217.70.183.193 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1708105357; cv=none; b=HXXg1h7bXq4lGW4XoGCOZtJxVL+4AiTB9X6VmNcmVCnKuBbyloIjPSYZVPP8kUgjLn1hh0cjQLkLxtp7vYpTCUmgy53miiWC+QvqFsmThXMcTn9zU4vjBZ01BmQfTTQxS8AJScqKNplTNzvTeBZYNeWkrRFBcKKsq1RXLPaZ+7U= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1708105357; c=relaxed/simple; bh=rp7klZcscRHI7H80OaeJy1/tHR2TlRZAKcODnRytUDM=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=jFjEt+zKRG3jW9FtYv9336F9r7KKCwlowXz7eYB+AtAebduQ9gP9q21sDeka6RDd7Ej/PVTdgvFbBt0TS+IJgAzBwP26XU3iivgsCpxLookA7Hi/bHtd2hX72R8ICpw1/7uOS+0nEWPBE8uywWo/0xLvyOgerP/cdKRy6+OJIjk= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=bootlin.com; spf=pass smtp.mailfrom=bootlin.com; dkim=pass (2048-bit key) header.d=bootlin.com header.i=@bootlin.com header.b=nU9Hnxx8; arc=none smtp.client-ip=217.70.183.193 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=bootlin.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=bootlin.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=bootlin.com header.i=@bootlin.com header.b="nU9Hnxx8" Received: by mail.gandi.net (Postfix) with ESMTPSA id ED049240007; Fri, 16 Feb 2024 17:42:31 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=bootlin.com; s=gm1; t=1708105352; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=sm6ABzVaGE03VL5KhWQvFUqXceq6K/iThPKbCcwB5eM=; b=nU9Hnxx8KUt9MdyahkBYJb3afEs7DpmoJIOG4xlpTVe//fjhU/bT4rGsG2EtOf6bznCNOu GwDCNKzu67xKUdJbxJrZl67E3ZNu7JpMuw72b0bpGoylIRg5mtTgCQmRgHBbs6ZHadaO8A KaKJWMDKyL/W3+PCSsL6dbRPatUO9MzHXR63uz/m/SM3VDT6LTOLtBEmStyc3AOKpM0w4G wzIjVcyWOsdtWjndC9/9DHYg61Z55MPf7EZKcAMKl9Kvka0DQjsKzumPRQjSdfTcGsHYVE d1lOAAW51Bn0LNmCd4LBBdSzEVFtifhOy2AkdjaQMkFODEEew6tCJqHd/Pt+fg== From: Gregory CLEMENT To: Paul Burton , Thomas Bogendoerfer , linux-mips@vger.kernel.org, Jiaxun Yang , Rob Herring , Krzysztof Kozlowski , devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Cc: Vladimir Kondratiev , Tawfik Bayouk , Alexandre Belloni , =?utf-8?q?Th=C3=A9o_Lebr?= =?utf-8?q?un?= , Thomas Petazzoni , Vladimir Kondratiev , Gregory CLEMENT Subject: [PATCH v8 02/14] MIPS: Fix set_uncached_handler for ebase in XKPHYS Date: Fri, 16 Feb 2024 18:42:11 +0100 Message-ID: <20240216174227.409400-3-gregory.clement@bootlin.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20240216174227.409400-1-gregory.clement@bootlin.com> References: <20240216174227.409400-1-gregory.clement@bootlin.com> Precedence: bulk X-Mailing-List: linux-mips@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-GND-Sasl: gregory.clement@bootlin.com From: Jiaxun Yang ebase might reside in XKPHYS if memblock is unable to allocate memory within the KSEG0 physical range. To map EBASE into uncached space, we convert it back to its physical address and utilize the new CKSEG1ADDR_OR_64BIT helper for mapping. Co-developed-by: Vladimir Kondratiev Signed-off-by: Vladimir Kondratiev Co-developed-by: Gregory CLEMENT Signed-off-by: Jiaxun Yang Signed-off-by: Gregory CLEMENT --- arch/mips/kernel/traps.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/mips/kernel/traps.c b/arch/mips/kernel/traps.c index c3cc6fff9d80a..075bb08543eca 100644 --- a/arch/mips/kernel/traps.c +++ b/arch/mips/kernel/traps.c @@ -2293,7 +2293,7 @@ static const char panic_null_cerr[] = void set_uncached_handler(unsigned long offset, void *addr, unsigned long size) { - unsigned long uncached_ebase = CKSEG1ADDR(ebase); + unsigned long uncached_ebase = CKSEG1ADDR_OR_64BIT(__pa(ebase)); if (!addr) panic(panic_null_cerr); From patchwork Fri Feb 16 17:42:12 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Gregory CLEMENT X-Patchwork-Id: 13560389 Received: from relay4-d.mail.gandi.net (relay4-d.mail.gandi.net [217.70.183.196]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 5FEDF54BD3; Fri, 16 Feb 2024 17:42:35 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=217.70.183.196 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1708105358; cv=none; b=MrVl2NykLSbtUf3vJQKgZWS2WvnY3+3JZPO4XV5TBU3pwXznJ/iZQpyfg8AexkBDMR/RhhKGBr/IZ9E+1CLIR8qIllmpya+tZ9QH3GjlCs91Z7an70pCNvfl2p/gtYgZNawYhp5BSB+FvqodKEOpdRZ+iAkWZjx2jEUwJnNAoWU= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1708105358; c=relaxed/simple; bh=aczDnBlcH8thQTR/53Z5x2CXncmHDFHT9wZWb7bUsuU=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=W8FRoLOqbPlHJpfaKai11r52PU/GLL4lLibfLSIg+mXfZO4r+ygoLuj0ssv2DerDkCn8pNCQgsztDNcDv+QOO+NNVjz0uk3O7LFKXwT2yfdXW4eV5W5+iNLT6QXLJWKklYNv3Q/eJFENJxcddSjINie+I78XV6ofZpRal5MPFeU= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=bootlin.com; spf=pass smtp.mailfrom=bootlin.com; dkim=pass (2048-bit key) header.d=bootlin.com header.i=@bootlin.com header.b=CsHg0JEv; arc=none smtp.client-ip=217.70.183.196 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=bootlin.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=bootlin.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=bootlin.com header.i=@bootlin.com header.b="CsHg0JEv" Received: by mail.gandi.net (Postfix) with ESMTPSA id 22DA4E000D; Fri, 16 Feb 2024 17:42:33 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=bootlin.com; s=gm1; t=1708105353; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=kc198qyFgEX3OgSqcmQcAO5uBI5gVex748ppakKaOAA=; b=CsHg0JEvv0rS7uhyB+XZXy3cRSlUJpXDrFNbVmKDlMmSQC11qR0FginMFgd/dsv2iR4A95 dt9TmNlZN7egqepjKwtFWD+wTfj1vCIUl8pMDgfYLaEDsK6jtWPAFrkPfjVVIBsXm56vEt PjU3u+gQJ36jTj66/MWKCnuNn9katlJiHaSkkqASJUYcGo66h3tu1btyUp1tiJ2q8GDxxz YEtCdPWgh92jkSHGjt/JpOMwUP9by072XxxaDnyruEvKL83ey1VH0tyAiv7r2teD+mrZJV nbV4wvTB9pCYt7PjGfRt8nkr3rCCWt1ZFKr6ozmsoJQChf0R70lIQ60rczjmDg== From: Gregory CLEMENT To: Paul Burton , Thomas Bogendoerfer , linux-mips@vger.kernel.org, Jiaxun Yang , Rob Herring , Krzysztof Kozlowski , devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Cc: Vladimir Kondratiev , Tawfik Bayouk , Alexandre Belloni , =?utf-8?q?Th=C3=A9o_Lebr?= =?utf-8?q?un?= , Thomas Petazzoni , Gregory CLEMENT Subject: [PATCH v8 03/14] MIPS: Allows relocation exception vectors everywhere Date: Fri, 16 Feb 2024 18:42:12 +0100 Message-ID: <20240216174227.409400-4-gregory.clement@bootlin.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20240216174227.409400-1-gregory.clement@bootlin.com> References: <20240216174227.409400-1-gregory.clement@bootlin.com> Precedence: bulk X-Mailing-List: linux-mips@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-GND-Sasl: gregory.clement@bootlin.com From: Jiaxun Yang Now the exception vector for CPS systems are allocated on-fly with memblock as well. It will try to allocate from KSEG1 first, and then try to allocate in low 4G if possible. The main reset vector is now generated by uasm, to avoid tons of patches to the code. Other vectors are copied to the location later. gc: use the new macro CKSEG[0A1]DDR_OR_64BIT() move 64bits fix in an other patch fix cache issue with mips_cps_core_entry rewrite the patch to reduce the diff stat move extern in header use cache address for copying vector Signed-off-by: Jiaxun Yang Signed-off-by: Gregory CLEMENT --- arch/mips/include/asm/mips-cm.h | 1 + arch/mips/include/asm/smp-cps.h | 9 +- arch/mips/kernel/cps-vec.S | 48 ++--------- arch/mips/kernel/smp-cps.c | 141 ++++++++++++++++++++++++++------ 4 files changed, 133 insertions(+), 66 deletions(-) diff --git a/arch/mips/include/asm/mips-cm.h b/arch/mips/include/asm/mips-cm.h index 23c67c0871b17..15d8d69de4550 100644 --- a/arch/mips/include/asm/mips-cm.h +++ b/arch/mips/include/asm/mips-cm.h @@ -311,6 +311,7 @@ GCR_CX_ACCESSOR_RW(32, 0x018, other) /* GCR_Cx_RESET_BASE - Configure where powered up cores will fetch from */ GCR_CX_ACCESSOR_RW(32, 0x020, reset_base) #define CM_GCR_Cx_RESET_BASE_BEVEXCBASE GENMASK(31, 12) +#define CM_GCR_Cx_RESET_BASE_MODE BIT(1) /* GCR_Cx_ID - Identify the current core */ GCR_CX_ACCESSOR_RO(32, 0x028, id) diff --git a/arch/mips/include/asm/smp-cps.h b/arch/mips/include/asm/smp-cps.h index 22a572b70fe31..ab94e50f62b87 100644 --- a/arch/mips/include/asm/smp-cps.h +++ b/arch/mips/include/asm/smp-cps.h @@ -24,7 +24,7 @@ struct core_boot_config { extern struct core_boot_config *mips_cps_core_bootcfg; -extern void mips_cps_core_entry(void); +extern void mips_cps_core_boot(int cca, void __iomem *gcr_base); extern void mips_cps_core_init(void); extern void mips_cps_boot_vpes(struct core_boot_config *cfg, unsigned vpe); @@ -32,7 +32,12 @@ extern void mips_cps_boot_vpes(struct core_boot_config *cfg, unsigned vpe); extern void mips_cps_pm_save(void); extern void mips_cps_pm_restore(void); -extern void *mips_cps_core_entry_patch_end; +extern void excep_tlbfill(void); +extern void excep_xtlbfill(void); +extern void excep_cache(void); +extern void excep_genex(void); +extern void excep_intex(void); +extern void excep_ejtag(void); #ifdef CONFIG_MIPS_CPS diff --git a/arch/mips/kernel/cps-vec.S b/arch/mips/kernel/cps-vec.S index 64ecfdac6580b..df610c006b443 100644 --- a/arch/mips/kernel/cps-vec.S +++ b/arch/mips/kernel/cps-vec.S @@ -4,6 +4,7 @@ * Author: Paul Burton */ +#include #include #include #include @@ -82,39 +83,10 @@ .endm -.balign 0x1000 - -LEAF(mips_cps_core_entry) - /* - * These first several instructions will be patched by cps_smp_setup to load the - * CCA to use into register s0 and GCR base address to register s1. - */ - .rept CPS_ENTRY_PATCH_INSNS - nop - .endr - - .global mips_cps_core_entry_patch_end -mips_cps_core_entry_patch_end: - - /* Check whether we're here due to an NMI */ - mfc0 k0, CP0_STATUS - and k0, k0, ST0_NMI - beqz k0, not_nmi - nop - - /* This is an NMI */ - PTR_LA k0, nmi_handler - jr k0 - nop - -not_nmi: - /* Setup Cause */ - li t0, CAUSEF_IV - mtc0 t0, CP0_CAUSE - - /* Setup Status */ - li t0, ST0_CU1 | ST0_CU0 | ST0_BEV | STATUS_BITDEPS - mtc0 t0, CP0_STATUS +LEAF(mips_cps_core_boot) + /* Save CCA and GCR base */ + move s0, a0 + move s1, a1 /* We don't know how to do coherence setup on earlier ISA */ #if MIPS_ISA_REV > 0 @@ -178,49 +150,45 @@ not_nmi: PTR_L sp, VPEBOOTCFG_SP(v1) jr t1 nop - END(mips_cps_core_entry) + END(mips_cps_core_boot) -.org 0x200 + __INIT LEAF(excep_tlbfill) DUMP_EXCEP("TLB Fill") b . nop END(excep_tlbfill) -.org 0x280 LEAF(excep_xtlbfill) DUMP_EXCEP("XTLB Fill") b . nop END(excep_xtlbfill) -.org 0x300 LEAF(excep_cache) DUMP_EXCEP("Cache") b . nop END(excep_cache) -.org 0x380 LEAF(excep_genex) DUMP_EXCEP("General") b . nop END(excep_genex) -.org 0x400 LEAF(excep_intex) DUMP_EXCEP("Interrupt") b . nop END(excep_intex) -.org 0x480 LEAF(excep_ejtag) PTR_LA k0, ejtag_debug_handler jr k0 nop END(excep_ejtag) + __FINIT LEAF(mips_cps_core_init) #ifdef CONFIG_MIPS_MT_SMP diff --git a/arch/mips/kernel/smp-cps.c b/arch/mips/kernel/smp-cps.c index f6c37d407f365..9cc087dd1c194 100644 --- a/arch/mips/kernel/smp-cps.c +++ b/arch/mips/kernel/smp-cps.c @@ -7,6 +7,7 @@ #include #include #include +#include #include #include #include @@ -20,12 +21,24 @@ #include #include #include +#include #include #include #include #include +#define BEV_VEC_SIZE 0x500 +#define BEV_VEC_ALIGN 0x1000 + +enum label_id { + label_not_nmi = 1, +}; + +UASM_L_LA(_not_nmi) + static DECLARE_BITMAP(core_power, NR_CPUS); +static uint32_t core_entry_reg; +static phys_addr_t cps_vec_pa; struct core_boot_config *mips_cps_core_bootcfg; @@ -34,10 +47,100 @@ static unsigned __init core_vpe_count(unsigned int cluster, unsigned core) return min(smp_max_threads, mips_cps_numvps(cluster, core)); } +static void __init *mips_cps_build_core_entry(void *addr) +{ + extern void (*nmi_handler)(void); + u32 *p = addr; + u32 val; + struct uasm_label labels[2]; + struct uasm_reloc relocs[2]; + struct uasm_label *l = labels; + struct uasm_reloc *r = relocs; + + memset(labels, 0, sizeof(labels)); + memset(relocs, 0, sizeof(relocs)); + + uasm_i_mfc0(&p, GPR_K0, C0_STATUS); + UASM_i_LA(&p, GPR_T9, ST0_NMI); + uasm_i_and(&p, GPR_K0, GPR_K0, GPR_T9); + + uasm_il_bnez(&p, &r, GPR_K0, label_not_nmi); + uasm_i_nop(&p); + UASM_i_LA(&p, GPR_K0, (long)&nmi_handler); + + uasm_l_not_nmi(&l, p); + + val = CAUSEF_IV; + uasm_i_lui(&p, GPR_K0, val >> 16); + uasm_i_ori(&p, GPR_K0, GPR_K0, val & 0xffff); + uasm_i_mtc0(&p, GPR_K0, C0_CAUSE); + val = ST0_CU1 | ST0_CU0 | ST0_BEV | ST0_KX_IF_64; + uasm_i_lui(&p, GPR_K0, val >> 16); + uasm_i_ori(&p, GPR_K0, GPR_K0, val & 0xffff); + uasm_i_mtc0(&p, GPR_K0, C0_STATUS); + uasm_i_ehb(&p); + uasm_i_ori(&p, GPR_A0, 0, read_c0_config() & CONF_CM_CMASK); + UASM_i_LA(&p, GPR_A1, (long)mips_gcr_base); +#if defined(KBUILD_64BIT_SYM32) || defined(CONFIG_32BIT) + UASM_i_LA(&p, GPR_T9, CKSEG1ADDR(__pa_symbol(mips_cps_core_boot))); +#else + UASM_i_LA(&p, GPR_T9, TO_UNCAC(__pa_symbol(mips_cps_core_boot))); +#endif + uasm_i_jr(&p, GPR_T9); + uasm_i_nop(&p); + + uasm_resolve_relocs(relocs, labels); + + return p; +} + +static int __init allocate_cps_vecs(void) +{ + /* Try to allocate in KSEG1 first */ + cps_vec_pa = memblock_phys_alloc_range(BEV_VEC_SIZE, BEV_VEC_ALIGN, + 0x0, CSEGX_SIZE - 1); + + if (cps_vec_pa) + core_entry_reg = CKSEG1ADDR(cps_vec_pa) & + CM_GCR_Cx_RESET_BASE_BEVEXCBASE; + + if (!cps_vec_pa && mips_cm_is64) { + cps_vec_pa = memblock_phys_alloc_range(BEV_VEC_SIZE, BEV_VEC_ALIGN, + 0x0, SZ_4G - 1); + if (cps_vec_pa) + core_entry_reg = (cps_vec_pa & CM_GCR_Cx_RESET_BASE_BEVEXCBASE) | + CM_GCR_Cx_RESET_BASE_MODE; + } + + if (!cps_vec_pa) + return -ENOMEM; + + return 0; +} + +static void __init setup_cps_vecs(void) +{ + void *cps_vec; + + cps_vec = (void *)CKSEG1ADDR_OR_64BIT(cps_vec_pa); + mips_cps_build_core_entry(cps_vec); + + memcpy(cps_vec + 0x200, &excep_tlbfill, 0x80); + memcpy(cps_vec + 0x280, &excep_xtlbfill, 0x80); + memcpy(cps_vec + 0x300, &excep_cache, 0x80); + memcpy(cps_vec + 0x380, &excep_genex, 0x80); + memcpy(cps_vec + 0x400, &excep_intex, 0x80); + memcpy(cps_vec + 0x480, &excep_ejtag, 0x80); + + /* Make sure no prefetched data in cache */ + blast_inv_dcache_range(CKSEG0ADDR_OR_64BIT(cps_vec_pa), CKSEG0ADDR_OR_64BIT(cps_vec_pa) + BEV_VEC_SIZE); + bc_inv(CKSEG0ADDR_OR_64BIT(cps_vec_pa), BEV_VEC_SIZE); + __sync(); +} + static void __init cps_smp_setup(void) { unsigned int nclusters, ncores, nvpes, core_vpes; - unsigned long core_entry; int cl, c, v; /* Detect & record VPE topology */ @@ -94,10 +197,11 @@ static void __init cps_smp_setup(void) /* Make core 0 coherent with everything */ write_gcr_cl_coherence(0xff); - if (mips_cm_revision() >= CM_REV_CM3) { - core_entry = CKSEG1ADDR((unsigned long)mips_cps_core_entry); - write_gcr_bev_base(core_entry); - } + if (allocate_cps_vecs()) + pr_err("Failed to allocate CPS vectors\n"); + + if (core_entry_reg && mips_cm_revision() >= CM_REV_CM3) + write_gcr_bev_base(core_entry_reg); #ifdef CONFIG_MIPS_MT_FPAFF /* If we have an FPU, enroll ourselves in the FPU-full mask */ @@ -110,10 +214,14 @@ static void __init cps_prepare_cpus(unsigned int max_cpus) { unsigned ncores, core_vpes, c, cca; bool cca_unsuitable, cores_limited; - u32 *entry_code; mips_mt_set_cpuoptions(); + if (!core_entry_reg) { + pr_err("core_entry address unsuitable, disabling smp-cps\n"); + goto err_out; + } + /* Detect whether the CCA is unsuited to multi-core SMP */ cca = read_c0_config() & CONF_CM_CMASK; switch (cca) { @@ -145,20 +253,7 @@ static void __init cps_prepare_cpus(unsigned int max_cpus) (cca_unsuitable && cpu_has_dc_aliases) ? " & " : "", cpu_has_dc_aliases ? "dcache aliasing" : ""); - /* - * Patch the start of mips_cps_core_entry to provide: - * - * s0 = kseg0 CCA - */ - entry_code = (u32 *)&mips_cps_core_entry; - uasm_i_addiu(&entry_code, 16, 0, cca); - UASM_i_LA(&entry_code, 17, (long)mips_gcr_base); - BUG_ON((void *)entry_code > (void *)&mips_cps_core_entry_patch_end); - blast_dcache_range((unsigned long)&mips_cps_core_entry, - (unsigned long)entry_code); - bc_wback_inv((unsigned long)&mips_cps_core_entry, - (void *)entry_code - (void *)&mips_cps_core_entry); - __sync(); + setup_cps_vecs(); /* Allocate core boot configuration structs */ ncores = mips_cps_numcores(0); @@ -213,7 +308,7 @@ static void boot_core(unsigned int core, unsigned int vpe_id) mips_cm_lock_other(0, core, 0, CM_GCR_Cx_OTHER_BLOCK_LOCAL); /* Set its reset vector */ - write_gcr_co_reset_base(CKSEG1ADDR((unsigned long)mips_cps_core_entry)); + write_gcr_co_reset_base(core_entry_reg); /* Ensure its coherency is disabled */ write_gcr_co_coherence(0); @@ -290,7 +385,6 @@ static int cps_boot_secondary(int cpu, struct task_struct *idle) unsigned vpe_id = cpu_vpe_id(&cpu_data[cpu]); struct core_boot_config *core_cfg = &mips_cps_core_bootcfg[core]; struct vpe_boot_config *vpe_cfg = &core_cfg->vpe_config[vpe_id]; - unsigned long core_entry; unsigned int remote; int err; @@ -314,8 +408,7 @@ static int cps_boot_secondary(int cpu, struct task_struct *idle) if (cpu_has_vp) { mips_cm_lock_other(0, core, vpe_id, CM_GCR_Cx_OTHER_BLOCK_LOCAL); - core_entry = CKSEG1ADDR((unsigned long)mips_cps_core_entry); - write_gcr_co_reset_base(core_entry); + write_gcr_co_reset_base(core_entry_reg); mips_cm_unlock_other(); } From patchwork Fri Feb 16 17:42:13 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Gregory CLEMENT X-Patchwork-Id: 13560391 Received: from relay2-d.mail.gandi.net (relay2-d.mail.gandi.net [217.70.183.194]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id E047E132477; Fri, 16 Feb 2024 17:42:36 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; 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dmarc=pass (p=reject dis=none) header.from=bootlin.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=bootlin.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=bootlin.com header.i=@bootlin.com header.b="fndWFhQn" Received: by mail.gandi.net (Postfix) with ESMTPSA id F3E4940008; Fri, 16 Feb 2024 17:42:33 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=bootlin.com; s=gm1; t=1708105354; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=AFHP7WMf7cdabuKf8LPE+Tv/tjtS5NR+H70CJoKhySg=; b=fndWFhQnrU1dyV5z02OwK+v7yQELtD72FtNXbHj/tQ9Q8ckEc4Y3Q/TdNmGNKs5eR8pPQw N2YyCWOuTKrk23qldccCI6XH0cyzFOLOfnSnKkfcG82Ge6wkhK2ZCETF3oyORqVBAsRJKL 2Pn73urZ5OVriEHkdE8oqVAUTWTnWcCHm/Cufk6OfQGlDZLlX0jm6mKQXgtjR6J6S4A2uG X5pgmAh5StE/NkZfC0mmfDWlmCLGXvA/BOPys3ePeNXQqrlORpmo7ZiX2SsOdH+gTYAQZH zMxx3vfTQ6Bk4bXXRZ9hoU/qVMhCzmgD9BRg8uaKqJr6gk37ueBVN/QbuxVrIQ== From: Gregory CLEMENT To: Paul Burton , Thomas Bogendoerfer , linux-mips@vger.kernel.org, Jiaxun Yang , Rob Herring , Krzysztof Kozlowski , devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Cc: Vladimir Kondratiev , Tawfik Bayouk , Alexandre Belloni , =?utf-8?q?Th=C3=A9o_Lebr?= =?utf-8?q?un?= , Thomas Petazzoni , Gregory CLEMENT Subject: [PATCH v8 04/14] MIPS: traps: Give more explanations if ebase doesn't belong to KSEG0 Date: Fri, 16 Feb 2024 18:42:13 +0100 Message-ID: <20240216174227.409400-5-gregory.clement@bootlin.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20240216174227.409400-1-gregory.clement@bootlin.com> References: <20240216174227.409400-1-gregory.clement@bootlin.com> Precedence: bulk X-Mailing-List: linux-mips@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-GND-Sasl: gregory.clement@bootlin.com With the expanded support for placing the kernel in XPHYS rather than just KSEG0, scenarios where ebase doesn't belong to KSEG0 are more likely to occur. In such cases, we currently experience a substantial and perplexing stack dump without any accompanying explanation. To rectify this, we aim to replace the uninformative stack dump with a warning that offers a clear explanation of the issue. Reviewed-by: Jiaxun Yang Signed-off-by: Gregory CLEMENT --- arch/mips/kernel/traps.c | 5 ++++- 1 file changed, 4 insertions(+), 1 deletion(-) diff --git a/arch/mips/kernel/traps.c b/arch/mips/kernel/traps.c index 075bb08543eca..a9644c5e7ef4d 100644 --- a/arch/mips/kernel/traps.c +++ b/arch/mips/kernel/traps.c @@ -2345,10 +2345,13 @@ void __init trap_init(void) * EVA is special though as it allows segments to be rearranged * and to become uncached during cache error handling. */ - if (!IS_ENABLED(CONFIG_EVA) && !WARN_ON(ebase_pa >= 0x20000000)) + if (!IS_ENABLED(CONFIG_EVA) && ebase_pa < 0x20000000) ebase = CKSEG0ADDR(ebase_pa); else ebase = (unsigned long)phys_to_virt(ebase_pa); + if (ebase_pa >= 0x20000000) + pr_warn("ebase(%pa) should better be in KSeg0", + &ebase_pa); } if (cpu_has_mmips) { From patchwork Fri Feb 16 17:42:14 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Gregory CLEMENT X-Patchwork-Id: 13560390 Received: from relay2-d.mail.gandi.net (relay2-d.mail.gandi.net [217.70.183.194]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 10ADB132C1F; Fri, 16 Feb 2024 17:42:36 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=217.70.183.194 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1708105359; cv=none; b=IEhJhDDzUqsK0Hbd32O84YdDCTDUqDEEmVewZeGI1n9t2tspBvn9UrfefXxLqSlkzLKn1wDr1ChAcDV3u6RV0UdoUemsQnyhQVkeIfBM0eNtCq9j4SlriO2CLcrWZ8/QLIYw3AGbiT13HmzPsfKPHfjNTj9ow4+HNal3IkbeXVo= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1708105359; c=relaxed/simple; bh=E/90gBwLmpJXeK232Brlce3fowXySmiFqEe90Bkb9Hc=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=ofdOeZP9aqOGb2QVJkmgB+Se1LqProsfSeGWOjJ6gAGzWGFb9jVD02SaQeivBoR1i4affv5zq0/FEHf09H+1gCDqjdotkQJL7XTdeEaEOkUqTeQcIfC34li7EYMeB+syNVIkAA5vz/aMBziG164SJOWUVCn2OdDdpOnEUf8APag= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=bootlin.com; spf=pass smtp.mailfrom=bootlin.com; dkim=pass (2048-bit key) header.d=bootlin.com header.i=@bootlin.com header.b=Gu4Ezaqp; arc=none smtp.client-ip=217.70.183.194 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=bootlin.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=bootlin.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=bootlin.com header.i=@bootlin.com header.b="Gu4Ezaqp" Received: by mail.gandi.net (Postfix) with ESMTPSA id C097040009; Fri, 16 Feb 2024 17:42:34 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=bootlin.com; s=gm1; t=1708105355; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=nfmqPXyNaR+Aomf8hQQJpTdW18Oyoy4DRDDUy1YAmW8=; b=Gu4EzaqpGe9p3mjEHXSwL8mlGL+/R90ivM05jzPQB67qyT2+xZv05L2imaQPvJO+DyamZ4 6bHYkXfoHa/vzpFl0AzsLKaOjWpOCxhSEdBXrhJlyNac08V0+O6cOX99jw+hys6A7/YZsV FavGJGTrWGrO+z1u5waTBrNX1enHOoGn7rFs5w/ni8sMeSZA/8KZU/a58FGTniiUsrWZIY I381Iv8//t+bFr7qEvPEkTm8lmooE+KPAVzT1F2RMUUtF4PkmxIchItpgjG0czrPE8/jBd Z1QHNnrAqBQ2dzfc2aQUGn1WRwVUg38mf0qS45fsO7bhM5ttb7FiGKodR5gvHA== From: Gregory CLEMENT To: Paul Burton , Thomas Bogendoerfer , linux-mips@vger.kernel.org, Jiaxun Yang , Rob Herring , Krzysztof Kozlowski , devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Cc: Vladimir Kondratiev , Tawfik Bayouk , Alexandre Belloni , =?utf-8?q?Th=C3=A9o_Lebr?= =?utf-8?q?un?= , Thomas Petazzoni , Gregory CLEMENT Subject: [PATCH v8 05/14] MIPS: cps-vec: Use macros for 64bits access Date: Fri, 16 Feb 2024 18:42:14 +0100 Message-ID: <20240216174227.409400-6-gregory.clement@bootlin.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20240216174227.409400-1-gregory.clement@bootlin.com> References: <20240216174227.409400-1-gregory.clement@bootlin.com> Precedence: bulk X-Mailing-List: linux-mips@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-GND-Sasl: gregory.clement@bootlin.com Some access are 32 bits only while they seems better to be done in 64bis for 64 bit kernel. This was extract from an initial patch from Jiaxun Co-developed-by: Jiaxun Yang Signed-off-by: Gregory CLEMENT --- arch/mips/kernel/cps-vec.S | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/arch/mips/kernel/cps-vec.S b/arch/mips/kernel/cps-vec.S index df610c006b443..f876309130ad1 100644 --- a/arch/mips/kernel/cps-vec.S +++ b/arch/mips/kernel/cps-vec.S @@ -396,7 +396,7 @@ LEAF(mips_cps_boot_vpes) /* Calculate a pointer to the VPEs struct vpe_boot_config */ li t0, VPEBOOTCFG_SIZE mul t0, t0, ta1 - addu t0, t0, ta3 + PTR_ADDU t0, t0, ta3 /* Set the TC restart PC */ lw t1, VPEBOOTCFG_PC(t0) @@ -571,10 +571,10 @@ dcache_done: lw $1, TI_CPU(gp) sll $1, $1, LONGLOG PTR_LA \dest, __per_cpu_offset - addu $1, $1, \dest + PTR_ADDU $1, $1, \dest lw $1, 0($1) PTR_LA \dest, cps_cpu_state - addu \dest, \dest, $1 + PTR_ADDU \dest, \dest, $1 .set pop .endm From patchwork Fri Feb 16 17:42:15 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Gregory CLEMENT X-Patchwork-Id: 13560396 Received: from relay3-d.mail.gandi.net (relay3-d.mail.gandi.net [217.70.183.195]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id AE42454BD3; Fri, 16 Feb 2024 17:42:43 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=217.70.183.195 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1708105366; cv=none; b=ms/5KwQM5CqOrHOK+cXYIwD0H+FAtRDcL0NXFXgDejpnxbX+MLaf///ZYouKumlV2t6w3YAt16MoX8uuuoEwBEphOChvo7VEqPbhLhAFY+q4k02vN63eL7FI1Esi19LWzO7ZcxAfg4mw/zBMk6jP4T5pfe/tLXSkxoV0GGlX+4Q= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1708105366; c=relaxed/simple; bh=ixMcKFY+IUbSdpEbmhiHUnPBLE8f92Qaft2wepBV4zg=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=cz5eqmWhqzMp9TEfFFj9/XRWaPUBsl3Rmmq82qp8CaTFmffxQWwShpVez/+vstXzwoF8SAsU9utisWE7rkQtqphqK6TdSIWlOJVhALg+cquNBJGdXFMewATB1L6MIIVff4b+a5ieHd3Kp2ogxnE0yPGz1VKjXnrUVzTmKs1t2ys= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=bootlin.com; spf=pass smtp.mailfrom=bootlin.com; dkim=pass (2048-bit key) header.d=bootlin.com header.i=@bootlin.com header.b=U5AM+IIy; arc=none smtp.client-ip=217.70.183.195 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=bootlin.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=bootlin.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=bootlin.com header.i=@bootlin.com header.b="U5AM+IIy" Received: by mail.gandi.net (Postfix) with ESMTPSA id 9749360006; Fri, 16 Feb 2024 17:42:35 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=bootlin.com; s=gm1; t=1708105356; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=GD5dmA3icQ0aFc9IWzxUyFJ8W/NRInrfQ2B2LPqfRyo=; b=U5AM+IIy6md4avJJAAMXfYrFomYfUJ2NYz0D2DlzvrKlAEhC1mtZzsWbfK7eTTe5xqo1e5 I9NqxdAk5lA0mwfZhopG+b310YVrQX690Zt43Kq28oYAjEVRu7lo6zMS6/+BmDeRYeTSsK gPFkyl1+sbyFCAxZzMHRwvXB/LAQj6dJkhHSkV7EQGVgvxnN5GBUgrqG/sTt08uefgJ0ge +gkHCMzF3ua+yjZmcIHsChfLoTvP+KELgBl/7XmhMxCdJJ5sfyV47r1eduQmajjohAhhqJ JofoBINFJBMrA8/FWUBGCWaTZqRrdbOG1eTvHTiymN2SZojFtWGAhWhR1g5Vig== From: Gregory CLEMENT To: Paul Burton , Thomas Bogendoerfer , linux-mips@vger.kernel.org, Jiaxun Yang , Rob Herring , Krzysztof Kozlowski , devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Cc: Vladimir Kondratiev , Tawfik Bayouk , Alexandre Belloni , =?utf-8?q?Th=C3=A9o_Lebr?= =?utf-8?q?un?= , Thomas Petazzoni , Gregory CLEMENT , =?utf-8?q?Philippe_Mathieu-D?= =?utf-8?q?aud=C3=A9?= , Rob Herring Subject: [PATCH v8 06/14] dt-bindings: Add vendor prefix for Mobileye Vision Technologies Ltd. Date: Fri, 16 Feb 2024 18:42:15 +0100 Message-ID: <20240216174227.409400-7-gregory.clement@bootlin.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20240216174227.409400-1-gregory.clement@bootlin.com> References: <20240216174227.409400-1-gregory.clement@bootlin.com> Precedence: bulk X-Mailing-List: linux-mips@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-GND-Sasl: gregory.clement@bootlin.com Mobileye Vision Technologies Ltd. is a company developing autonomous driving technologies and advanced driver-assistance systems (ADAS) including cameras, computer chips and software. Reviewed-by: Philippe Mathieu-Daudé Acked-by: Rob Herring Signed-off-by: Gregory CLEMENT --- Documentation/devicetree/bindings/vendor-prefixes.yaml | 2 ++ 1 file changed, 2 insertions(+) diff --git a/Documentation/devicetree/bindings/vendor-prefixes.yaml b/Documentation/devicetree/bindings/vendor-prefixes.yaml index 1a0dc04f1db47..fb088d9c6f5b2 100644 --- a/Documentation/devicetree/bindings/vendor-prefixes.yaml +++ b/Documentation/devicetree/bindings/vendor-prefixes.yaml @@ -911,6 +911,8 @@ patternProperties: description: Miyoo "^mntre,.*": description: MNT Research GmbH + "^mobileye,.*": + description: Mobileye Vision Technologies Ltd. "^modtronix,.*": description: Modtronix Engineering "^moortec,.*": From patchwork Fri Feb 16 17:42:16 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Gregory CLEMENT X-Patchwork-Id: 13560398 Received: from relay9-d.mail.gandi.net (relay9-d.mail.gandi.net [217.70.183.199]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id AD443135401; Fri, 16 Feb 2024 17:42:44 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=217.70.183.199 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1708105367; cv=none; b=rajEsHaUrCUNbv9s/quzbF3ZNjnNQY3gkT2wkEk4yfHPWhBAQJuFvRCLBAIEu1c5+jaIOUFSRnsPGl7as7h0JbyJgC3NNoLutCxFXvWg2Iz067oOHETvVxqq7Iy6HlLjOmp8TW7ZFuNmdMQmaUVmOkAJjquFsU/Dp7rnT1/4ScU= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1708105367; c=relaxed/simple; bh=zkHzvVhKkqmhHXMYvIXk97BK8Hudfzm2zXC5uewsDi0=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=bjp8MLKBTXtRscwP1Q9XWnosAWGDNEkEafd/4x1lW54MXN5Z6D+cJUeXOCGf0y9nt+z2ToCtAZ0I2pjn7E0qxU8AqSza/9k+CvQ/14ZZYgykptE6ydCeRd4QRWRVwtPa+1+HAKAfanTop4DCO2n4HGYzbqt5biWe0Ea6xjECpNM= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=bootlin.com; spf=pass smtp.mailfrom=bootlin.com; dkim=pass (2048-bit key) header.d=bootlin.com header.i=@bootlin.com header.b=fHUoiYCQ; arc=none smtp.client-ip=217.70.183.199 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=bootlin.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=bootlin.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=bootlin.com header.i=@bootlin.com header.b="fHUoiYCQ" Received: by mail.gandi.net (Postfix) with ESMTPSA id A59B2FF804; Fri, 16 Feb 2024 17:42:36 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=bootlin.com; s=gm1; t=1708105357; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=lbVsbmHE4CGNjOWLyfslnCmWW1EMalEIZK9eUB8mHKE=; b=fHUoiYCQBX+G8LDk0+TzfxJnaKfFyPj/Oh5JGJSJukX3scl7nF4nswEQbA0F4Hj2EFx6RA MmQT0sW21UFPuArIKFFjjWG+/+U7iLQ+qj7Z9fcOht2Uv8cepjTaV+xy9UYWOlDMy5Ple9 4UzRRDexQmOuJHTVv68qpthL8YgCvlY3GKJaklrfPeYDG5wrLH3augQxL1m+C1fXJ1oT/+ ZsDYNyb0CJbjZcGnnZkpE9auhJW6cwmR47TJFts1+2MRroKwiWQ9XUSwpK6a1v0bd1Xymo 6Uwf1jhLF5W66ah+P85PXrUwa0yFfHCEpgPT7t+T61HY2n7ekfazNHW+RnZAeA== From: Gregory CLEMENT To: Paul Burton , Thomas Bogendoerfer , linux-mips@vger.kernel.org, Jiaxun Yang , Rob Herring , Krzysztof Kozlowski , devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Cc: Vladimir Kondratiev , Tawfik Bayouk , Alexandre Belloni , =?utf-8?q?Th=C3=A9o_Lebr?= =?utf-8?q?un?= , Thomas Petazzoni , Gregory CLEMENT , Serge Semin , Krzysztof Kozlowski Subject: [PATCH v8 07/14] dt-bindings: mips: cpus: Sort the entries Date: Fri, 16 Feb 2024 18:42:16 +0100 Message-ID: <20240216174227.409400-8-gregory.clement@bootlin.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20240216174227.409400-1-gregory.clement@bootlin.com> References: <20240216174227.409400-1-gregory.clement@bootlin.com> Precedence: bulk X-Mailing-List: linux-mips@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-GND-Sasl: gregory.clement@bootlin.com The entries were nearly sorted but there were still some entries at the wrong places. Let's fix it. Reviewed-by: Serge Semin Acked-by: Krzysztof Kozlowski Signed-off-by: Gregory CLEMENT --- Documentation/devicetree/bindings/mips/cpus.yaml | 12 ++++++------ 1 file changed, 6 insertions(+), 6 deletions(-) diff --git a/Documentation/devicetree/bindings/mips/cpus.yaml b/Documentation/devicetree/bindings/mips/cpus.yaml index cf382dea3922c..9bc47868d28b6 100644 --- a/Documentation/devicetree/bindings/mips/cpus.yaml +++ b/Documentation/devicetree/bindings/mips/cpus.yaml @@ -23,22 +23,22 @@ properties: - brcm,bmips4380 - brcm,bmips5000 - brcm,bmips5200 - - ingenic,xburst-mxu1.0 - ingenic,xburst-fpu1.0-mxu1.1 - ingenic,xburst-fpu2.0-mxu2.0 + - ingenic,xburst-mxu1.0 - ingenic,xburst2-fpu2.1-mxu2.1-smt - loongson,gs264 - mips,m14Kc - - mips,mips4Kc - - mips,mips4KEc - - mips,mips24Kc + - mips,mips1004Kc - mips,mips24KEc + - mips,mips24Kc + - mips,mips4KEc + - mips,mips4Kc - mips,mips74Kc - - mips,mips1004Kc - mti,interaptiv - - mti,mips24KEc - mti,mips14KEc - mti,mips14Kc + - mti,mips24KEc reg: maxItems: 1 From patchwork Fri Feb 16 17:42:17 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Gregory CLEMENT X-Patchwork-Id: 13560392 Received: from relay4-d.mail.gandi.net (relay4-d.mail.gandi.net [217.70.183.196]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 28628134CC2; Fri, 16 Feb 2024 17:42:39 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=217.70.183.196 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1708105362; cv=none; b=ipyJ+guwm4c6rs0TN2L1yzu69eYqpRTre2zqETNMWHcML5ElXDSSXzx2GR/Y9TZkMLK026PPco//HJidWoq17NWDqI3kuu6FSg6nnFBl+GP67w5BtraDyleynad6Ng4qsAj8jvNrQaWCg5uORCRBswdIj12HyulGDetOPPdZfTY= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1708105362; c=relaxed/simple; bh=F69lXcW+BMK3xWuWKAunG1z8qeZUfL/FLTg148TbGsU=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=Q4bEhFtXVDp0KisqZULT9Who5NBmtanL2QgxZPaf6tM7uYFyz1m+dR2sUMEGO5DcNxJyZcL/4hlBJa7+LgTdPbfgl8H9CM9qxblXZRewnDNU0aQkNKpnh/CcRO4vtGbTssvS+Mw+vltK+dbw+v/WVVX4ZzZrT/iYYlj4v4Nw0gU= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=bootlin.com; spf=pass smtp.mailfrom=bootlin.com; dkim=pass (2048-bit key) header.d=bootlin.com header.i=@bootlin.com header.b=Xp5tgQzY; arc=none smtp.client-ip=217.70.183.196 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=bootlin.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=bootlin.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=bootlin.com header.i=@bootlin.com header.b="Xp5tgQzY" Received: by mail.gandi.net (Postfix) with ESMTPSA id AE232E0011; Fri, 16 Feb 2024 17:42:37 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=bootlin.com; s=gm1; t=1708105358; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=GbsWh/XsZeOFv6yit27z5l5/TqUISO3EzDeBeQy/R68=; b=Xp5tgQzYJ99OznJpxI0Yp7ZbCZoS1DUHjanFiLNS/IC5nW3hJV5hGjLoCNzjaGDP/5uk/y Dmc7ycUf7wGzHJvO2ldJTTOvRN3CeZCt9qzth7QdCOmL1wI7fk9k7r5w6hvVZ0GKMH5dHb 39LqXT6nZg9880xf3BvJIDk5uWm4yaynygS8AIyAk4aHkmh2deBHMm++Wnr0oLfwDk3ASP cjUzDBImCrDgP3hjcq9ab8N2enXm1T3T/n4zQMtpTzAVq+zAe0DjVQaK6Mzzclt7Fsw++E /QWmpp3AA9hrpDLeD/UbFCtCEbm8pbdOFqjCIDFUg6Rll8uqtf/di4xWyWCTUg== From: Gregory CLEMENT To: Paul Burton , Thomas Bogendoerfer , linux-mips@vger.kernel.org, Jiaxun Yang , Rob Herring , Krzysztof Kozlowski , devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Cc: Vladimir Kondratiev , Tawfik Bayouk , Alexandre Belloni , =?utf-8?q?Th=C3=A9o_Lebr?= =?utf-8?q?un?= , Thomas Petazzoni , Gregory CLEMENT , Arnd Bergmann , =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= , Serge Semin , Krzysztof Kozlowski Subject: [PATCH v8 08/14] dt-bindings: mips: cpu: Add I-Class I6500 Multiprocessor Core Date: Fri, 16 Feb 2024 18:42:17 +0100 Message-ID: <20240216174227.409400-9-gregory.clement@bootlin.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20240216174227.409400-1-gregory.clement@bootlin.com> References: <20240216174227.409400-1-gregory.clement@bootlin.com> Precedence: bulk X-Mailing-List: linux-mips@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-GND-Sasl: gregory.clement@bootlin.com The MIPS Warrior I-class I6500 was announced by Imagination Technologies in 2016 and is used in the Mobileye SoC EyeQ5. Acked-by: Arnd Bergmann Reviewed-by: Philippe Mathieu-Daudé Reviewed-by: Serge Semin Acked-by: Krzysztof Kozlowski Signed-off-by: Gregory CLEMENT --- Documentation/devicetree/bindings/mips/cpus.yaml | 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/mips/cpus.yaml b/Documentation/devicetree/bindings/mips/cpus.yaml index 9bc47868d28b6..a85137add6689 100644 --- a/Documentation/devicetree/bindings/mips/cpus.yaml +++ b/Documentation/devicetree/bindings/mips/cpus.yaml @@ -23,6 +23,7 @@ properties: - brcm,bmips4380 - brcm,bmips5000 - brcm,bmips5200 + - img,i6500 - ingenic,xburst-fpu1.0-mxu1.1 - ingenic,xburst-fpu2.0-mxu2.0 - ingenic,xburst-mxu1.0 From patchwork Fri Feb 16 17:42:18 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Gregory CLEMENT X-Patchwork-Id: 13560393 Received: from relay6-d.mail.gandi.net (relay6-d.mail.gandi.net [217.70.183.198]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id A1AE11350E0; Fri, 16 Feb 2024 17:42:41 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=217.70.183.198 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1708105364; cv=none; b=YMdabmMXlPoA7aRwMEOMZlZiuMCxlFLFJyd0J+9Sa6T1rY/kN8D348sZICBTCfwK0iXrD8Wqp+TuOff7zz/jhlg8VbKm4UjeMhj3FGSIp/5xs4eFR8OhgfhTbstzkVEkVfc0Q+wJ1daa0vk0PnVuEfMA2+W6YlpY79Z9KOSwPEI= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1708105364; c=relaxed/simple; bh=10ZEAJurS12z5xoBCG/ln6uoclFy6kBUieMg+mevi/M=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=dhUVd3DFSV22n2bRYi/JASG+AWzubpzkO5EiwR4XF8Hl/y7o+Opl6rihf9A5KAlnNFnN5EHxl42XhzurTOzFZxsgWnrd2eGEmtDwWzyw1Xqe6Us69a/kZ3RXRKkMSsWE8MEh6MA8/fWH+0etgGJIDJjYznGMocR9d7GDj2MLRX4= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=bootlin.com; spf=pass smtp.mailfrom=bootlin.com; dkim=pass (2048-bit key) header.d=bootlin.com header.i=@bootlin.com header.b=Y/u5j1P2; arc=none smtp.client-ip=217.70.183.198 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=bootlin.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=bootlin.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=bootlin.com header.i=@bootlin.com header.b="Y/u5j1P2" Received: by mail.gandi.net (Postfix) with ESMTPSA id C8287C0008; Fri, 16 Feb 2024 17:42:38 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=bootlin.com; s=gm1; t=1708105359; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=KtLJx1LoT2GXTWyVjN+1FeAU3avbgKgLJY8tRT/zqqY=; b=Y/u5j1P2Yb2SgI7rdyAOzzZj7lPio26I+guYLc8DwujXJ9oWrJPwKLW3kj+/LHsV2qjcZB xLNaCUH1tgWQuagKagNHkMBKdwPeLSl0Fjiw8lMwey1KDho0GkV6cOJJHcHTSlCGr5IiTV ZWt6H9rOH2T+bG1Lq4sLlqai2ZqxbDqiWepI1LvhVTq0AQUTX0RAb2no4YOjPXkTpYgJEU NSvzBRHTOo6n8yP1/yXm0Xv43jfpH0f6CwXDVrCZM7ebOT5AHD5NrjLoGIjPndqafgDxs7 5WZrAJIgAo7YqyNC0DVpvnR35THSGxRhKQSPPghZRH9C7zJcw/NmxUkQf5JBvQ== From: Gregory CLEMENT To: Paul Burton , Thomas Bogendoerfer , linux-mips@vger.kernel.org, Jiaxun Yang , Rob Herring , Krzysztof Kozlowski , devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Cc: Vladimir Kondratiev , Tawfik Bayouk , Alexandre Belloni , =?utf-8?q?Th=C3=A9o_Lebr?= =?utf-8?q?un?= , Thomas Petazzoni , Gregory CLEMENT , Rob Herring Subject: [PATCH v8 09/14] dt-bindings: mips: Add bindings for Mobileye SoCs Date: Fri, 16 Feb 2024 18:42:18 +0100 Message-ID: <20240216174227.409400-10-gregory.clement@bootlin.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20240216174227.409400-1-gregory.clement@bootlin.com> References: <20240216174227.409400-1-gregory.clement@bootlin.com> Precedence: bulk X-Mailing-List: linux-mips@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-GND-Sasl: gregory.clement@bootlin.com Add the yaml bindings for Mobileye SoCs. Currently only EyeQ5 is supported Reviewed-by: Rob Herring Signed-off-by: Gregory CLEMENT --- .../devicetree/bindings/mips/mobileye.yaml | 32 +++++++++++++++++++ 1 file changed, 32 insertions(+) create mode 100644 Documentation/devicetree/bindings/mips/mobileye.yaml diff --git a/Documentation/devicetree/bindings/mips/mobileye.yaml b/Documentation/devicetree/bindings/mips/mobileye.yaml new file mode 100644 index 0000000000000..831975f6b479f --- /dev/null +++ b/Documentation/devicetree/bindings/mips/mobileye.yaml @@ -0,0 +1,32 @@ +# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause +# Copyright 2023 Mobileye Vision Technologies Ltd. +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/mips/mobileye.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Mobileye SoC series + +maintainers: + - Vladimir Kondratiev + - Gregory CLEMENT + - Théo Lebrun + +description: + Boards with a Mobileye SoC shall have the following properties. + +properties: + $nodename: + const: '/' + + compatible: + oneOf: + - description: Boards with Mobileye EyeQ5 SoC + items: + - enum: + - mobileye,eyeq5-epm5 + - const: mobileye,eyeq5 + +additionalProperties: true + +... From patchwork Fri Feb 16 17:42:19 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Gregory CLEMENT X-Patchwork-Id: 13560400 Received: from relay3-d.mail.gandi.net (relay3-d.mail.gandi.net [217.70.183.195]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 6DC6E137C41; Fri, 16 Feb 2024 17:42:47 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=217.70.183.195 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1708105370; cv=none; b=jSHdeY0zTaL+4Fam71h2EP9cD2zZmKaHmna8dKZ2lO3EW8B4w7Jzqmrv8DledZYaCDf7pQwLHNaWHGsdYfnK709/AepU0i7O34pPS1UjPrm62Onj6KuRVte2AYw5MKelUiwDvuL6ksPuXpiiatD0yfjPTuDT5pEgYCiLCtqB4J8= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1708105370; c=relaxed/simple; bh=8tVgkcNVLNLBRpOyAN3sTXkK2AFrbAaEOi1qJYHFBm8=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=lFuB5nlHsmNVwmrByWLbwi7VyCqnhPKNsVi+R+R3g+vcwBxEPP54tUg3GDWy+apJTL8DVYnjPQ8/dtGqZlwFsIwfYMM8jXOiPgx2DH26byZu4xLChd40+IXni7ywN6qT2hHE/SU8CSHouG90seTDn6lqRVuQAWFUJ+NOXDZY/ZU= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=bootlin.com; spf=pass smtp.mailfrom=bootlin.com; dkim=pass (2048-bit key) header.d=bootlin.com header.i=@bootlin.com header.b=IRL8UEQQ; arc=none smtp.client-ip=217.70.183.195 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=bootlin.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=bootlin.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=bootlin.com header.i=@bootlin.com header.b="IRL8UEQQ" Received: by mail.gandi.net (Postfix) with ESMTPSA id BF73B60002; Fri, 16 Feb 2024 17:42:39 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=bootlin.com; s=gm1; t=1708105360; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=J34CKJwhiUt6uvWl5wHPj2lYqq5e5b68Q2aJT1fL64Y=; b=IRL8UEQQBB8KpZQJJ6D0X3hyUHTtQzbiPQvIuTBm7UJl3DLt0y8N8FagFW47ZeG2qcGOLn fvp56qEI5PX5FmDYLutQZY0Q8e6Z28j+U8KkivN1oitDPUlVnVakW9sn1z6fXAZeRoyk8k HHMJBqJAndZRgoNL9Jrgu4pxvZQyRn05Thv1CMRuDw7DgGb6ueUCOAU1MnDtO5/oLdqR1r m/hVoXzSSMtaegyqHtqFmvaqHRXOn0XPgm8UD9/iB+UeksOHnItTLBqR6lr/4I3vAhnky4 AshuQ0Y9w/P63bKTILeaYZtRZXYg7uUAd8AzU5dOpI0I2IRz2fxOdRmWXMzBYQ== From: Gregory CLEMENT To: Paul Burton , Thomas Bogendoerfer , linux-mips@vger.kernel.org, Jiaxun Yang , Rob Herring , Krzysztof Kozlowski , devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Cc: Vladimir Kondratiev , Tawfik Bayouk , Alexandre Belloni , =?utf-8?q?Th=C3=A9o_Lebr?= =?utf-8?q?un?= , Thomas Petazzoni , Gregory CLEMENT Subject: [PATCH v8 10/14] MIPS: mobileye: Add EyeQ5 dtsi Date: Fri, 16 Feb 2024 18:42:19 +0100 Message-ID: <20240216174227.409400-11-gregory.clement@bootlin.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20240216174227.409400-1-gregory.clement@bootlin.com> References: <20240216174227.409400-1-gregory.clement@bootlin.com> Precedence: bulk X-Mailing-List: linux-mips@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-GND-Sasl: gregory.clement@bootlin.com Add a device tree include file for the Mobileye EyeQ5 SoC. Based on the work of Slava Samsonov Signed-off-by: Gregory CLEMENT --- arch/mips/boot/dts/Makefile | 1 + .../boot/dts/mobileye/eyeq5-fixed-clocks.dtsi | 292 ++++++++++++++++++ arch/mips/boot/dts/mobileye/eyeq5.dtsi | 124 ++++++++ 3 files changed, 417 insertions(+) create mode 100644 arch/mips/boot/dts/mobileye/eyeq5-fixed-clocks.dtsi create mode 100644 arch/mips/boot/dts/mobileye/eyeq5.dtsi diff --git a/arch/mips/boot/dts/Makefile b/arch/mips/boot/dts/Makefile index 928f38a79dff9..efff87cb33a9e 100644 --- a/arch/mips/boot/dts/Makefile +++ b/arch/mips/boot/dts/Makefile @@ -8,6 +8,7 @@ subdir-$(CONFIG_LANTIQ) += lantiq subdir-$(CONFIG_MACH_LOONGSON64) += loongson subdir-$(CONFIG_SOC_VCOREIII) += mscc subdir-$(CONFIG_MIPS_MALTA) += mti +subdir-$(CONFIG_MACH_EYEQ5) += mobileye subdir-$(CONFIG_LEGACY_BOARD_SEAD3) += mti subdir-$(CONFIG_FIT_IMAGE_FDT_NI169445) += ni subdir-$(CONFIG_MACH_PIC32) += pic32 diff --git a/arch/mips/boot/dts/mobileye/eyeq5-fixed-clocks.dtsi b/arch/mips/boot/dts/mobileye/eyeq5-fixed-clocks.dtsi new file mode 100644 index 0000000000000..78f5533a95c67 --- /dev/null +++ b/arch/mips/boot/dts/mobileye/eyeq5-fixed-clocks.dtsi @@ -0,0 +1,292 @@ +// SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +/* + * Copyright 2023 Mobileye Vision Technologies Ltd. + */ + +/ { + /* Fixed clock */ + pll_cpu: pll-cpu { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <1500000000>; + }; + + pll_vdi: pll-vdi { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <1280000000>; + }; + + pll_per: pll-per { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <2000000000>; + }; + + pll_ddr0: pll-ddr0 { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <1857210000>; + }; + + pll_ddr1: pll-ddr1 { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <1857210000>; + }; + +/* PLL_CPU derivatives */ + occ_cpu: occ-cpu { + compatible = "fixed-factor-clock"; + clocks = <&pll_cpu>; + #clock-cells = <0>; + clock-div = <1>; + clock-mult = <1>; + }; + si_css0_ref_clk: si-css0-ref-clk { /* gate ClkRstGen_si_css0_ref */ + compatible = "fixed-factor-clock"; + clocks = <&occ_cpu>; + #clock-cells = <0>; + clock-div = <1>; + clock-mult = <1>; + }; + cpc_clk: cpc-clk { + compatible = "fixed-factor-clock"; + clocks = <&si_css0_ref_clk>; + #clock-cells = <0>; + clock-div = <1>; + clock-mult = <1>; + }; + core0_clk: core0-clk { + compatible = "fixed-factor-clock"; + clocks = <&si_css0_ref_clk>; + #clock-cells = <0>; + clock-div = <1>; + clock-mult = <1>; + }; + core1_clk: core1-clk { + compatible = "fixed-factor-clock"; + clocks = <&si_css0_ref_clk>; + #clock-cells = <0>; + clock-div = <1>; + clock-mult = <1>; + }; + core2_clk: core2-clk { + compatible = "fixed-factor-clock"; + clocks = <&si_css0_ref_clk>; + #clock-cells = <0>; + clock-div = <1>; + clock-mult = <1>; + }; + core3_clk: core3-clk { + compatible = "fixed-factor-clock"; + clocks = <&si_css0_ref_clk>; + #clock-cells = <0>; + clock-div = <1>; + clock-mult = <1>; + }; + cm_clk: cm-clk { + compatible = "fixed-factor-clock"; + clocks = <&si_css0_ref_clk>; + #clock-cells = <0>; + clock-div = <1>; + clock-mult = <1>; + }; + mem_clk: mem-clk { + compatible = "fixed-factor-clock"; + clocks = <&si_css0_ref_clk>; + #clock-cells = <0>; + clock-div = <1>; + clock-mult = <1>; + }; + occ_isram: occ-isram { + compatible = "fixed-factor-clock"; + clocks = <&pll_cpu>; + #clock-cells = <0>; + clock-div = <2>; + clock-mult = <1>; + }; + isram_clk: isram-clk { /* gate ClkRstGen_isram */ + compatible = "fixed-factor-clock"; + clocks = <&occ_isram>; + #clock-cells = <0>; + clock-div = <1>; + clock-mult = <1>; + }; + occ_dbu: occ-dbu { + compatible = "fixed-factor-clock"; + clocks = <&pll_cpu>; + #clock-cells = <0>; + clock-div = <10>; + clock-mult = <1>; + }; + si_dbu_tp_pclk: si-dbu-tp-pclk { /* gate ClkRstGen_dbu */ + compatible = "fixed-factor-clock"; + clocks = <&occ_dbu>; + #clock-cells = <0>; + clock-div = <1>; + clock-mult = <1>; + }; +/* PLL_VDI derivatives */ + occ_vdi: occ-vdi { + compatible = "fixed-factor-clock"; + clocks = <&pll_vdi>; + #clock-cells = <0>; + clock-div = <2>; + clock-mult = <1>; + }; + vdi_clk: vdi-clk { /* gate ClkRstGen_vdi */ + compatible = "fixed-factor-clock"; + clocks = <&occ_vdi>; + #clock-cells = <0>; + clock-div = <1>; + clock-mult = <1>; + }; + occ_can_ser: occ-can-ser { + compatible = "fixed-factor-clock"; + clocks = <&pll_vdi>; + #clock-cells = <0>; + clock-div = <16>; + clock-mult = <1>; + }; + can_ser_clk: can-ser-clk { /* gate ClkRstGen_can_ser */ + compatible = "fixed-factor-clock"; + clocks = <&occ_can_ser>; + #clock-cells = <0>; + clock-div = <1>; + clock-mult = <1>; + }; + i2c_ser_clk: i2c-ser-clk { + compatible = "fixed-factor-clock"; + clocks = <&pll_vdi>; + #clock-cells = <0>; + clock-div = <20>; + clock-mult = <1>; + }; +/* PLL_PER derivatives */ + occ_periph: occ-periph { + compatible = "fixed-factor-clock"; + clocks = <&pll_per>; + #clock-cells = <0>; + clock-div = <16>; + clock-mult = <1>; + }; + periph_clk: periph-clk { + compatible = "fixed-factor-clock"; + clocks = <&occ_periph>; + #clock-cells = <0>; + clock-div = <1>; + clock-mult = <1>; + }; + can_clk: can-clk { + compatible = "fixed-factor-clock"; + clocks = <&occ_periph>; + #clock-cells = <0>; + clock-div = <1>; + clock-mult = <1>; + }; + spi_clk: spi-clk { + compatible = "fixed-factor-clock"; + clocks = <&occ_periph>; + #clock-cells = <0>; + clock-div = <1>; + clock-mult = <1>; + }; + uart_clk: uart-clk { + compatible = "fixed-factor-clock"; + clocks = <&occ_periph>; + #clock-cells = <0>; + clock-div = <1>; + clock-mult = <1>; + }; + i2c_clk: i2c-clk { + compatible = "fixed-factor-clock"; + clocks = <&occ_periph>; + #clock-cells = <0>; + clock-div = <1>; + clock-mult = <1>; + clock-output-names = "i2c_clk"; + }; + timer_clk: timer-clk { + compatible = "fixed-factor-clock"; + clocks = <&occ_periph>; + #clock-cells = <0>; + clock-div = <1>; + clock-mult = <1>; + clock-output-names = "timer_clk"; + }; + gpio_clk: gpio-clk { + compatible = "fixed-factor-clock"; + clocks = <&occ_periph>; + #clock-cells = <0>; + clock-div = <1>; + clock-mult = <1>; + clock-output-names = "gpio_clk"; + }; + emmc_sys_clk: emmc-sys-clk { + compatible = "fixed-factor-clock"; + clocks = <&pll_per>; + #clock-cells = <0>; + clock-div = <10>; + clock-mult = <1>; + clock-output-names = "emmc_sys_clk"; + }; + ccf_ctrl_clk: ccf-ctrl-clk { + compatible = "fixed-factor-clock"; + clocks = <&pll_per>; + #clock-cells = <0>; + clock-div = <4>; + clock-mult = <1>; + clock-output-names = "ccf_ctrl_clk"; + }; + occ_mjpeg_core: occ-mjpeg-core { + compatible = "fixed-factor-clock"; + clocks = <&pll_per>; + #clock-cells = <0>; + clock-div = <2>; + clock-mult = <1>; + clock-output-names = "occ_mjpeg_core"; + }; + hsm_clk: hsm-clk { /* gate ClkRstGen_hsm */ + compatible = "fixed-factor-clock"; + clocks = <&occ_mjpeg_core>; + #clock-cells = <0>; + clock-div = <1>; + clock-mult = <1>; + clock-output-names = "hsm_clk"; + }; + mjpeg_core_clk: mjpeg-core-clk { /* gate ClkRstGen_mjpeg_gen */ + compatible = "fixed-factor-clock"; + clocks = <&occ_mjpeg_core>; + #clock-cells = <0>; + clock-div = <1>; + clock-mult = <1>; + clock-output-names = "mjpeg_core_clk"; + }; + fcmu_a_clk: fcmu-a-clk { + compatible = "fixed-factor-clock"; + clocks = <&pll_per>; + #clock-cells = <0>; + clock-div = <20>; + clock-mult = <1>; + clock-output-names = "fcmu_a_clk"; + }; + occ_pci_sys: occ-pci-sys { + compatible = "fixed-factor-clock"; + clocks = <&pll_per>; + #clock-cells = <0>; + clock-div = <8>; + clock-mult = <1>; + clock-output-names = "occ_pci_sys"; + }; + pclk: pclk { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <250000000>; /* 250MHz */ + }; + tsu_clk: tsu-clk { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <125000000>; /* 125MHz */ + }; +}; diff --git a/arch/mips/boot/dts/mobileye/eyeq5.dtsi b/arch/mips/boot/dts/mobileye/eyeq5.dtsi new file mode 100644 index 0000000000000..6cc5980e2fa17 --- /dev/null +++ b/arch/mips/boot/dts/mobileye/eyeq5.dtsi @@ -0,0 +1,124 @@ +// SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause */ +/* +* Copyright 2023 Mobileye Vision Technologies Ltd. +*/ + +#include + +#include "eyeq5-fixed-clocks.dtsi" + +/ { + #address-cells = <2>; + #size-cells = <2>; + cpus { + #address-cells = <1>; + #size-cells = <0>; + cpu@0 { + device_type = "cpu"; + compatible = "img,i6500"; + reg = <0>; + clocks = <&core0_clk>; + }; + }; + + reserved-memory { + #address-cells = <2>; + #size-cells = <2>; + ranges; + + /* These reserved memory regions are also defined in bootmanager + * for configuring inbound translation for BARS, don't change + * these without syncing with bootmanager + */ + shmem0_reserved: shmem@804000000 { + reg = <0x8 0x04000000 0x0 0x1000000>; + }; + shmem1_reserved: shmem@805000000 { + reg = <0x8 0x05000000 0x0 0x1000000>; + }; + pci0_msi_reserved: pci0-msi@806000000 { + reg = <0x8 0x06000000 0x0 0x100000>; + }; + pci1_msi_reserved: pci1-msi@806100000 { + reg = <0x8 0x06100000 0x0 0x100000>; + }; + + mini_coredump0_reserved: mini-coredump0@806200000 { + reg = <0x8 0x06200000 0x0 0x100000>; + }; + mhm_reserved_0: the-mhm-reserved-0@0 { + reg = <0x8 0x00000000 0x0 0x0000800>; + }; + }; + + aliases { + serial0 = &uart0; + serial1 = &uart1; + serial2 = &uart2; + }; + + cpu_intc: interrupt-controller { + compatible = "mti,cpu-interrupt-controller"; + interrupt-controller; + #address-cells = <0>; + #interrupt-cells = <1>; + }; + + soc: soc { + #address-cells = <2>; + #size-cells = <2>; + ranges; + compatible = "simple-bus"; + + uart0: serial@800000 { + compatible = "arm,pl011", "arm,primecell"; + reg = <0 0x800000 0x0 0x1000>; + reg-io-width = <4>; + interrupt-parent = <&gic>; + interrupts = ; + clocks = <&uart_clk>, <&occ_periph>; + clock-names = "uartclk", "apb_pclk"; + }; + + uart1: serial@900000 { + compatible = "arm,pl011", "arm,primecell"; + reg = <0 0x900000 0x0 0x1000>; + reg-io-width = <4>; + interrupt-parent = <&gic>; + interrupts = ; + clocks = <&uart_clk>, <&occ_periph>; + clock-names = "uartclk", "apb_pclk"; + }; + + uart2: serial@a00000 { + compatible = "arm,pl011", "arm,primecell"; + reg = <0 0xa00000 0x0 0x1000>; + reg-io-width = <4>; + interrupt-parent = <&gic>; + interrupts = ; + clocks = <&uart_clk>, <&occ_periph>; + clock-names = "uartclk", "apb_pclk"; + }; + + gic: interrupt-controller@140000 { + compatible = "mti,gic"; + reg = <0x0 0x140000 0x0 0x20000>; + interrupt-controller; + #interrupt-cells = <3>; + + /* + * Declare the interrupt-parent even though the mti,gic + * binding doesn't require it, such that the kernel can + * figure out that cpu_intc is the root interrupt + * controller & should be probed first. + */ + interrupt-parent = <&cpu_intc>; + + timer { + compatible = "mti,gic-timer"; + interrupts = ; + clocks = <&core0_clk>; + }; + }; + }; +}; From patchwork Fri Feb 16 17:42:20 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Gregory CLEMENT X-Patchwork-Id: 13560394 Received: from relay4-d.mail.gandi.net (relay4-d.mail.gandi.net [217.70.183.196]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id DDE611350F9; Fri, 16 Feb 2024 17:42:42 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=217.70.183.196 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1708105365; cv=none; b=ndc+5oZ8vrybfohyOH8lbL8v1gN1H99bta8B8czDj2fsYGqNNkHpIIGHcqjzmND5l2eRFmpmHPzIPtNwB5P8HX6NevCvT52LT0GJQH+KMHbYcoUNSrQuWKPFvjnsbKhCUDdydVuOxXoElmcGOR0bAWbHKwJrOkJoWWVD8YjRiVc= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; 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Fri, 16 Feb 2024 17:42:40 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=bootlin.com; s=gm1; t=1708105361; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=KDGmhKsrXnlDJMy644fDIA2mW0aZ/el8TnwmSRWTTPU=; b=SclgdKHYnmvkbAj+f3uFdU2JMSrztaDZcIUtiUlyATjHqXsmyvSU1KFVbzPb3Atpbba3ey FBFQfJphAXhDPH3dePziGvY2z7pjYMw/IS4svZNmBUAlCo1tLubXk80CNCiOCjo3nARHMv K2f+6ib/fAFxSzQLZze+rkCHpisnjyuj/kEaAZiaFOLG8Da3oqgUh7PyePEPzlKJky70dJ 35Xx6nCW5h0W7UPBgk5vcrIWn64KUN2nXfF8CIzENP3iLImHArhXgggiAe4aS1T5s/4ZUw YpTE8+1zWfa0jvRePNxj83D8pzP9qpbN8YQCIi+/Ky+56BeUptWy8Xa54Yt1EA== From: Gregory CLEMENT To: Paul Burton , Thomas Bogendoerfer , linux-mips@vger.kernel.org, Jiaxun Yang , Rob Herring , Krzysztof Kozlowski , devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Cc: Vladimir Kondratiev , Tawfik Bayouk , Alexandre Belloni , =?utf-8?q?Th=C3=A9o_Lebr?= =?utf-8?q?un?= , Thomas Petazzoni , Gregory CLEMENT Subject: [PATCH v8 11/14] MIPS: mobileye: Add EPM5 device tree Date: Fri, 16 Feb 2024 18:42:20 +0100 Message-ID: <20240216174227.409400-12-gregory.clement@bootlin.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20240216174227.409400-1-gregory.clement@bootlin.com> References: <20240216174227.409400-1-gregory.clement@bootlin.com> Precedence: bulk X-Mailing-List: linux-mips@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-GND-Sasl: gregory.clement@bootlin.com Add a device tree for the Mobileye EPM5 evaluation board. Reviewed-by: Jiaxun Yang Signed-off-by: Gregory CLEMENT --- arch/mips/boot/dts/mobileye/Makefile | 4 ++++ arch/mips/boot/dts/mobileye/eyeq5-epm5.dts | 23 ++++++++++++++++++++++ 2 files changed, 27 insertions(+) create mode 100644 arch/mips/boot/dts/mobileye/Makefile create mode 100644 arch/mips/boot/dts/mobileye/eyeq5-epm5.dts diff --git a/arch/mips/boot/dts/mobileye/Makefile b/arch/mips/boot/dts/mobileye/Makefile new file mode 100644 index 0000000000000..01c01c3aad81d --- /dev/null +++ b/arch/mips/boot/dts/mobileye/Makefile @@ -0,0 +1,4 @@ +# SPDX-License-Identifier: GPL-2.0-only +# Copyright 2023 Mobileye Vision Technologies Ltd. + +dtb-$(CONFIG_MACH_EYEQ5) += eyeq5-epm5.dtb diff --git a/arch/mips/boot/dts/mobileye/eyeq5-epm5.dts b/arch/mips/boot/dts/mobileye/eyeq5-epm5.dts new file mode 100644 index 0000000000000..6898b2d8267df --- /dev/null +++ b/arch/mips/boot/dts/mobileye/eyeq5-epm5.dts @@ -0,0 +1,23 @@ +// SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +/* + * Copyright 2023 Mobileye Vision Technologies Ltd. + */ + +/dts-v1/; + +#include "eyeq5.dtsi" + +/ { + compatible = "mobileye,eyeq5-epm5", "mobileye,eyeq5"; + model = "Mobile EyeQ5 MP5 Evaluation board"; + + chosen { + stdout-path = "serial2:115200n8"; + }; + + memory@0 { + device_type = "memory"; + reg = <0x0 0x40000000 0x0 0x02000000>, + <0x8 0x02000000 0x0 0x7E000000>; + }; +}; From patchwork Fri Feb 16 17:42:21 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Gregory CLEMENT X-Patchwork-Id: 13560395 Received: from relay1-d.mail.gandi.net (relay1-d.mail.gandi.net [217.70.183.193]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 949751353E2; Fri, 16 Feb 2024 17:42:43 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=217.70.183.193 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1708105365; cv=none; b=mvyG3Q7GLv554GhLXSTdYHpqZHLv4QGaspUtQ4WjhbHclR1bxdcrjRwrwSNRHDTD3VNR2nzfVsoURx1ABWwTSPKJvRlabxooqy12jyS3Knapp/Ao4iYgHUPWt3iK107RQrs95ixuSf9xy/LlFgx3Bzsr5ibYw7fXbw/WM329tdg= ARC-Message-Signature: i=1; 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Fri, 16 Feb 2024 17:42:41 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=bootlin.com; s=gm1; t=1708105361; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=bQ4JZ6IQLu/PlyZzbHme0fXEJFmS6Qd3821XRXAYit4=; b=Bnt1BzpKaZvhFgM9qnJiViQlFu22FurjerkDxdon4W6SuFwXs25VRhtTK+JbP2FpppOjkB IZnKtBB9Dk2VvtGLig+xQpu9ZlLClxOaRX25I32URFCJZxaFex23GS/P1PmVn79w5IhHUI 67JUsglDUIQ54lqCF/csfOkXBv3lwnsfUX0smiJCL8r2MW5/Sn6mwjpdY0MHQK1lTg/PWI n6Avq63EWLfnZ5hqvBpTKZYe8J3iKW9pkIVw8ROsNgaAVW8YzDdzoe0nRIgox3glBBPenp hxnqdql32MsE+g1ukbD1EKabFVR2bwR90hqVLJmW+m6zJemr56dGS8ofjBGKxA== From: Gregory CLEMENT To: Paul Burton , Thomas Bogendoerfer , linux-mips@vger.kernel.org, Jiaxun Yang , Rob Herring , Krzysztof Kozlowski , devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Cc: Vladimir Kondratiev , Tawfik Bayouk , Alexandre Belloni , =?utf-8?q?Th=C3=A9o_Lebr?= =?utf-8?q?un?= , Thomas Petazzoni , Gregory CLEMENT Subject: [PATCH v8 12/14] MIPS: Share generic kernel code with other architecture Date: Fri, 16 Feb 2024 18:42:21 +0100 Message-ID: <20240216174227.409400-13-gregory.clement@bootlin.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20240216174227.409400-1-gregory.clement@bootlin.com> References: <20240216174227.409400-1-gregory.clement@bootlin.com> Precedence: bulk X-Mailing-List: linux-mips@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-GND-Sasl: gregory.clement@bootlin.com Some architectures might seek to utilize a significant portion of the generic kernel code while maintaining independence from the generic kernel due to specific peculiarities. This patch allows for the reuse of core code, preventing unnecessary duplication. Suggested-by: Thomas Bogendoerfer Reviewed-by: Jiaxun Yang Signed-off-by: Gregory CLEMENT --- arch/mips/Kbuild | 1 + arch/mips/Kconfig | 3 +++ arch/mips/generic/Makefile | 6 +++--- 3 files changed, 7 insertions(+), 3 deletions(-) diff --git a/arch/mips/Kbuild b/arch/mips/Kbuild index e2d623621a00e..e901bf554483b 100644 --- a/arch/mips/Kbuild +++ b/arch/mips/Kbuild @@ -11,6 +11,7 @@ obj- := $(platform-y) # mips object files # The object files are linked as core-y files would be linked +obj-y += generic/ obj-y += kernel/ obj-y += mm/ obj-y += net/ diff --git a/arch/mips/Kconfig b/arch/mips/Kconfig index 797ae590ebdba..5549d26448941 100644 --- a/arch/mips/Kconfig +++ b/arch/mips/Kconfig @@ -109,6 +109,9 @@ config MIPS_FIXUP_BIGPHYS_ADDR config MIPS_GENERIC bool +config MACH_GENERIC_CORE + bool + config MACH_INGENIC bool select SYS_SUPPORTS_32BIT_KERNEL diff --git a/arch/mips/generic/Makefile b/arch/mips/generic/Makefile index e37a59bae0a62..56011d738441f 100644 --- a/arch/mips/generic/Makefile +++ b/arch/mips/generic/Makefile @@ -4,9 +4,9 @@ # Author: Paul Burton # -obj-y += init.o -obj-y += irq.o -obj-y += proc.o +obj-$(CONFIG_MACH_GENERIC_CORE) += init.o +obj-$(CONFIG_MACH_GENERIC_CORE) += irq.o +obj-$(CONFIG_MACH_GENERIC_CORE) += proc.o obj-$(CONFIG_YAMON_DT_SHIM) += yamon-dt.o obj-$(CONFIG_LEGACY_BOARD_SEAD3) += board-sead3.o From patchwork Fri Feb 16 17:42:22 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Gregory CLEMENT X-Patchwork-Id: 13560397 Received: from relay5-d.mail.gandi.net (relay5-d.mail.gandi.net [217.70.183.197]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 038481353E6; Fri, 16 Feb 2024 17:42:43 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=217.70.183.197 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1708105366; cv=none; b=k1ZKTIt4qhSs9o4YxwuIXtrQ0HnoFVkCZU5NserfXm7N+MGnxS2x7CTlpI3mry91mKrZUtLdO0/Stj81Nvit6VmAYSQrW+RlXAJIAlH+JfsxlkMKv9iEXkLeoNlBB/ARWlImTgguAb1dHjbO4aH4NTuwFfsndgjL8bg3tJ7j6Uw= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1708105366; c=relaxed/simple; bh=PpsyNMdLxEOIEfnbTp+pBvpidipRHF9L8aBJTqmqb/w=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=tvYf6nw3Jyey8eJr3PxaDtbhor9Tqnc72WizSyImgc9BhtuWA7eO5Fai+xVQKBclDJlPyUclzXimM6O3SxVm31UTEnsgM0j8HW/uvgWA3YElYS1oeJwEGwrjUlmrp2tj/tirJCZ8/dCW5Bl+DaZWdAhCm1nWZTPXwdrAGAURFBU= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=bootlin.com; spf=pass smtp.mailfrom=bootlin.com; dkim=pass (2048-bit key) header.d=bootlin.com header.i=@bootlin.com header.b=SsuA7Nva; arc=none smtp.client-ip=217.70.183.197 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=bootlin.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=bootlin.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=bootlin.com header.i=@bootlin.com header.b="SsuA7Nva" Received: by mail.gandi.net (Postfix) with ESMTPSA id 16DA31C0006; Fri, 16 Feb 2024 17:42:42 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=bootlin.com; s=gm1; t=1708105362; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=b/xJ16yj8WxYIe9GyjcF+QVWZQeGfsPuTQ2nq8RbNuU=; b=SsuA7NvamiWZNQcZnchgBOayZIqArrvJQxQUmGOYgPQPL/SXbGEXpKSj3n3hhFQ7fFK4o2 +RZwJOnKF/9o6+XvH29c6gLl6HDcaSDCw1/IqZ5/k0WkG0ypY/oV2eCItpyDAVtQOYInZM gvlNCiL3rtSFEUSCDQaM6bq3Ygj3EPyHO+qjgkjBQYdxPBi1umWiSc3ZAnk7+gbwXb29lj eG62/HJhrsDWAIQ1VT3xajkm+9UhjGRf7kYlzzWDaJ0yi6BKi/fqRocYBCphafmlKz4nJd Wb+JUuhQZ8kCZcvsVfuBzZPU40CY22OkAw/Exef/HHQYXVpiLWXwwRfySRiEfA== From: Gregory CLEMENT To: Paul Burton , Thomas Bogendoerfer , linux-mips@vger.kernel.org, Jiaxun Yang , Rob Herring , Krzysztof Kozlowski , devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Cc: Vladimir Kondratiev , Tawfik Bayouk , Alexandre Belloni , =?utf-8?q?Th=C3=A9o_Lebr?= =?utf-8?q?un?= , Thomas Petazzoni , Gregory CLEMENT Subject: [PATCH v8 13/14] MIPS: Add support for Mobileye EyeQ5 Date: Fri, 16 Feb 2024 18:42:22 +0100 Message-ID: <20240216174227.409400-14-gregory.clement@bootlin.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20240216174227.409400-1-gregory.clement@bootlin.com> References: <20240216174227.409400-1-gregory.clement@bootlin.com> Precedence: bulk X-Mailing-List: linux-mips@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-GND-Sasl: gregory.clement@bootlin.com Introduce support for the MIPS based Mobileye EyeQ5 SoCs. Reviewed-by: Jiaxun Yang Signed-off-by: Gregory CLEMENT --- arch/mips/Kbuild.platforms | 1 + arch/mips/Kconfig | 54 ++++++++++++++ arch/mips/configs/eyeq5_defconfig | 108 ++++++++++++++++++++++++++++ arch/mips/mobileye/Makefile | 1 + arch/mips/mobileye/Platform | 16 +++++ arch/mips/mobileye/board-epm5.its.S | 24 +++++++ arch/mips/mobileye/vmlinux.its.S | 32 +++++++++ 7 files changed, 236 insertions(+) create mode 100644 arch/mips/configs/eyeq5_defconfig create mode 100644 arch/mips/mobileye/Makefile create mode 100644 arch/mips/mobileye/Platform create mode 100644 arch/mips/mobileye/board-epm5.its.S create mode 100644 arch/mips/mobileye/vmlinux.its.S diff --git a/arch/mips/Kbuild.platforms b/arch/mips/Kbuild.platforms index a2311c4bce6a6..5c145b67d3bf4 100644 --- a/arch/mips/Kbuild.platforms +++ b/arch/mips/Kbuild.platforms @@ -17,6 +17,7 @@ platform-$(CONFIG_MACH_LOONGSON2EF) += loongson2ef/ platform-$(CONFIG_MACH_LOONGSON32) += loongson32/ platform-$(CONFIG_MACH_LOONGSON64) += loongson64/ platform-$(CONFIG_MIPS_MALTA) += mti-malta/ +platform-$(CONFIG_MACH_EYEQ5) += mobileye/ platform-$(CONFIG_MACH_NINTENDO64) += n64/ platform-$(CONFIG_PIC32MZDA) += pic32/ platform-$(CONFIG_RALINK) += ralink/ diff --git a/arch/mips/Kconfig b/arch/mips/Kconfig index 5549d26448941..a40eb9ecb50d5 100644 --- a/arch/mips/Kconfig +++ b/arch/mips/Kconfig @@ -569,6 +569,60 @@ config MACH_PIC32 Microchip PIC32 is a family of general-purpose 32 bit MIPS core microcontrollers. +config MACH_EYEQ5 + bool "Mobileye EyeQ5 SoC" + select MACH_GENERIC_CORE + select ARM_AMBA + select PHYSICAL_START_BOOL + select ARCH_SPARSEMEM_DEFAULT if 64BIT + select BOOT_RAW + select BUILTIN_DTB + select CEVT_R4K + select CLKSRC_MIPS_GIC + select COMMON_CLK + select CPU_MIPSR2_IRQ_EI + select CPU_MIPSR2_IRQ_VI + select CSRC_R4K + select DMA_NONCOHERENT + select HAVE_PCI + select IRQ_MIPS_CPU + select MIPS_AUTO_PFN_OFFSET + select MIPS_CPU_SCACHE + select MIPS_GIC + select MIPS_L1_CACHE_SHIFT_7 + select PCI_DRIVERS_GENERIC + select SMP_UP if SMP + select SWAP_IO_SPACE + select SYS_HAS_CPU_MIPS64_R6 + select SYS_SUPPORTS_64BIT_KERNEL + select SYS_SUPPORTS_HIGHMEM + select SYS_SUPPORTS_LITTLE_ENDIAN + select SYS_SUPPORTS_MIPS_CPS + select SYS_SUPPORTS_RELOCATABLE + select SYS_SUPPORTS_ZBOOT + select UHI_BOOT + select USB_EHCI_BIG_ENDIAN_DESC if CPU_BIG_ENDIAN + select USB_EHCI_BIG_ENDIAN_MMIO if CPU_BIG_ENDIAN + select USB_OHCI_BIG_ENDIAN_DESC if CPU_BIG_ENDIAN + select USB_OHCI_BIG_ENDIAN_MMIO if CPU_BIG_ENDIAN + select USB_UHCI_BIG_ENDIAN_DESC if CPU_BIG_ENDIAN + select USB_UHCI_BIG_ENDIAN_MMIO if CPU_BIG_ENDIAN + select USE_OF + help + Select this to build a kernel supporting EyeQ5 SoC from Mobileye. + + bool + +config FIT_IMAGE_FDT_EPM5 + bool "Include FDT for Mobileye EyeQ5 development platforms" + depends on MACH_EYEQ5 + default n + help + Enable this to include the FDT for the EyeQ5 development platforms + from Mobileye in the FIT kernel image. + This requires u-boot on the platform. + + config MACH_NINTENDO64 bool "Nintendo 64 console" select CEVT_R4K diff --git a/arch/mips/configs/eyeq5_defconfig b/arch/mips/configs/eyeq5_defconfig new file mode 100644 index 0000000000000..c35c29a4d4795 --- /dev/null +++ b/arch/mips/configs/eyeq5_defconfig @@ -0,0 +1,108 @@ +CONFIG_SYSVIPC=y +CONFIG_NO_HZ_IDLE=y +CONFIG_HIGH_RES_TIMERS=y +CONFIG_BPF_SYSCALL=y +CONFIG_TASKSTATS=y +CONFIG_IKCONFIG=y +CONFIG_IKCONFIG_PROC=y +CONFIG_MEMCG=y +CONFIG_BLK_CGROUP=y +CONFIG_CFS_BANDWIDTH=y +CONFIG_RT_GROUP_SCHED=y +CONFIG_CGROUP_PIDS=y +CONFIG_CGROUP_FREEZER=y +CONFIG_CPUSETS=y +CONFIG_CGROUP_DEVICE=y +CONFIG_CGROUP_CPUACCT=y +CONFIG_NAMESPACES=y +CONFIG_USER_NS=y +CONFIG_SCHED_AUTOGROUP=y +CONFIG_BLK_DEV_INITRD=y +CONFIG_EXPERT=y +CONFIG_MACH_EYEQ5=y +CONFIG_FIT_IMAGE_FDT_EPM5=y +CONFIG_PAGE_SIZE_16KB=y +CONFIG_MIPS_CPS=y +CONFIG_CPU_HAS_MSA=y +CONFIG_NR_CPUS=16 +CONFIG_MIPS_RAW_APPENDED_DTB=y +CONFIG_JUMP_LABEL=y +CONFIG_COMPAT_32BIT_TIME=y +CONFIG_MODULES=y +CONFIG_MODULE_UNLOAD=y +CONFIG_TRIM_UNUSED_KSYMS=y +# CONFIG_COMPAT_BRK is not set +CONFIG_SPARSEMEM_MANUAL=y +CONFIG_USERFAULTFD=y +CONFIG_NET=y +CONFIG_PACKET=y +CONFIG_UNIX=y +CONFIG_NET_KEY=y +CONFIG_INET=y +CONFIG_IP_PNP=y +CONFIG_IP_PNP_DHCP=y +CONFIG_NETFILTER=y +CONFIG_CAN=y +CONFIG_PCI=y +CONFIG_PCI_MSI=y +CONFIG_PCI_DEBUG=y +CONFIG_PCI_ENDPOINT=y +CONFIG_DEVTMPFS=y +CONFIG_DEVTMPFS_MOUNT=y +CONFIG_CONNECTOR=y +CONFIG_MTD=y +CONFIG_MTD_UBI=y +CONFIG_MTD_UBI_BLOCK=y +CONFIG_SCSI=y +CONFIG_NETDEVICES=y +CONFIG_MACVLAN=y +CONFIG_IPVLAN=y +CONFIG_MACB=y +CONFIG_MARVELL_PHY=y +CONFIG_MICREL_PHY=y +CONFIG_CAN_M_CAN=y +CONFIG_SERIAL_AMBA_PL011=y +CONFIG_SERIAL_AMBA_PL011_CONSOLE=y +CONFIG_HW_RANDOM=y +# CONFIG_PTP_1588_CLOCK is not set +CONFIG_PINCTRL=y +CONFIG_MFD_SYSCON=y +CONFIG_HID_A4TECH=y +CONFIG_HID_BELKIN=y +CONFIG_HID_CHERRY=y +CONFIG_HID_CYPRESS=y +CONFIG_HID_EZKEY=y +CONFIG_HID_ITE=y +CONFIG_HID_KENSINGTON=y +CONFIG_HID_REDRAGON=y +CONFIG_HID_MICROSOFT=y +CONFIG_HID_MONTEREY=y +CONFIG_MMC=y +CONFIG_MMC_SDHCI=y +# CONFIG_IOMMU_SUPPORT is not set +CONFIG_RESET_CONTROLLER=y +# CONFIG_NVMEM is not set +CONFIG_EXT4_FS=y +CONFIG_EXT4_FS_POSIX_ACL=y +CONFIG_EXT4_FS_SECURITY=y +CONFIG_FS_ENCRYPTION=y +CONFIG_FUSE_FS=y +CONFIG_CUSE=y +CONFIG_MSDOS_FS=y +CONFIG_VFAT_FS=y +CONFIG_TMPFS=y +CONFIG_TMPFS_POSIX_ACL=y +CONFIG_UBIFS_FS=y +CONFIG_NFS_FS=y +CONFIG_NFS_V3_ACL=y +CONFIG_NFS_V4=y +CONFIG_NFS_V4_1=y +CONFIG_NFS_V4_2=y +CONFIG_ROOT_NFS=y +CONFIG_CRYPTO_CRC32_MIPS=y +CONFIG_FRAME_WARN=1024 +CONFIG_DEBUG_FS=y +# CONFIG_RCU_TRACE is not set +# CONFIG_FTRACE is not set +CONFIG_CMDLINE_BOOL=y +CONFIG_CMDLINE="earlycon" diff --git a/arch/mips/mobileye/Makefile b/arch/mips/mobileye/Makefile new file mode 100644 index 0000000000000..315c06b689cfb --- /dev/null +++ b/arch/mips/mobileye/Makefile @@ -0,0 +1 @@ +# SPDX-License-Identifier: GPL-2.0-or-later diff --git a/arch/mips/mobileye/Platform b/arch/mips/mobileye/Platform new file mode 100644 index 0000000000000..43b6f4644592f --- /dev/null +++ b/arch/mips/mobileye/Platform @@ -0,0 +1,16 @@ +# +# Copyright (C) 2016 Imagination Technologies +# Author: Paul Burton +# +# This program is free software; you can redistribute it and/or modify it +# under the terms of the GNU General Public License as published by the +# Free Software Foundation; either version 2 of the License, or (at your +# option) any later version. +# + +load-$(CONFIG_MACH_EYEQ5) = 0xa800000808000000 +all-$(CONFIG_MACH_EYEQ5) += vmlinux.gz.itb + +its-y := vmlinux.its.S +its-$(CONFIG_FIT_IMAGE_FDT_EPM5) += board-epm5.its.S + diff --git a/arch/mips/mobileye/board-epm5.its.S b/arch/mips/mobileye/board-epm5.its.S new file mode 100644 index 0000000000000..08e8c4f183d63 --- /dev/null +++ b/arch/mips/mobileye/board-epm5.its.S @@ -0,0 +1,24 @@ +/* SPDX-License-Identifier: (GPL-2.0 OR MIT) */ +/ { + images { + fdt-mobileye-epm5 { + description = "Mobileeye MP5 Device Tree"; + data = /incbin/("boot/dts/mobileye/eyeq5-epm5.dtb"); + type = "flat_dt"; + arch = "mips"; + compression = "none"; + hash { + algo = "sha1"; + }; + }; + }; + + configurations { + default = "conf-1"; + conf-1 { + description = "Mobileye EPM5 Linux kernel"; + kernel = "kernel"; + fdt = "fdt-mobileye-epm5"; + }; + }; +}; diff --git a/arch/mips/mobileye/vmlinux.its.S b/arch/mips/mobileye/vmlinux.its.S new file mode 100644 index 0000000000000..3e254676540f4 --- /dev/null +++ b/arch/mips/mobileye/vmlinux.its.S @@ -0,0 +1,32 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/dts-v1/; + +/ { + description = KERNEL_NAME; + #address-cells = ; + + images { + kernel { + description = KERNEL_NAME; + data = /incbin/(VMLINUX_BINARY); + type = "kernel"; + arch = "mips"; + os = "linux"; + compression = VMLINUX_COMPRESSION; + load = /bits/ ADDR_BITS ; + entry = /bits/ ADDR_BITS ; + hash { + algo = "sha1"; + }; + }; + }; + + configurations { + default = "conf-default"; + + conf-default { + description = "Generic Linux kernel"; + kernel = "kernel"; + }; + }; +}; From patchwork Fri Feb 16 17:42:23 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Gregory CLEMENT X-Patchwork-Id: 13560399 Received: from relay4-d.mail.gandi.net (relay4-d.mail.gandi.net [217.70.183.196]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 3DD0F135413; Fri, 16 Feb 2024 17:42:44 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=217.70.183.196 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1708105367; cv=none; b=QD0rhZk9m93UF5q7LUFTsb39R7hGDP89AnHbjxgiTVcHSJPn7hCkTlMddKrizGgR8kh532RXVBk+7p27qjNXAQDxw0eqJpIOytWGMP2r986lJAfWKT3w60p1UhGZQbmxg7EVSrHCb2mCgNaNffpw6cwFGb7VnzU9aWoycy6B8cM= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1708105367; c=relaxed/simple; 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Belloni , =?utf-8?q?Th=C3=A9o_Lebr?= =?utf-8?q?un?= , Thomas Petazzoni , Gregory CLEMENT Subject: [PATCH v8 14/14] MAINTAINERS: Add entry for Mobileye MIPS SoCs Date: Fri, 16 Feb 2024 18:42:23 +0100 Message-ID: <20240216174227.409400-15-gregory.clement@bootlin.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20240216174227.409400-1-gregory.clement@bootlin.com> References: <20240216174227.409400-1-gregory.clement@bootlin.com> Precedence: bulk X-Mailing-List: linux-mips@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-GND-Sasl: gregory.clement@bootlin.com Add Vlad, Théo and myself as co-maintainers for the Mobileye MIPS SoCs. Signed-off-by: Vladimir Kondratiev Signed-off-by: Théo Lebrun Signed-off-by: Gregory CLEMENT --- MAINTAINERS | 12 ++++++++++++ 1 file changed, 12 insertions(+) diff --git a/MAINTAINERS b/MAINTAINERS index 8d1052fa6a692..cb431c79c7b8e 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -14779,6 +14779,18 @@ W: https://linuxtv.org Q: http://patchwork.linuxtv.org/project/linux-media/list/ F: drivers/media/dvb-frontends/mn88473* +MOBILEYE MIPS SOCS +M: Vladimir Kondratiev +M: Gregory CLEMENT +M: Théo Lebrun +L: linux-mips@vger.kernel.org +S: Maintained +F: Documentation/devicetree/bindings/mips/mobileye.yaml +F: arch/mips/boot/dts/mobileye/ +F: arch/mips/configs/eyeq5_defconfig +F: arch/mips/mobileye/board-epm5.its.S +F: include/dt-bindings/soc/mobileye,eyeq5.h + MODULE SUPPORT M: Luis Chamberlain L: linux-modules@vger.kernel.org