From patchwork Tue Feb 27 22:04:35 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Adam Ford X-Patchwork-Id: 13574483 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 8EF34C54798 for ; Tue, 27 Feb 2024 22:05:16 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:MIME-Version:References:In-Reply-To: Message-ID:Date:Subject:Cc:To:From:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; bh=0LwrJ8OosK8YYocEjQVmYmjN7+bA7qPXzUDtUjAD2Xk=; b=13qPPzmNxABMRi esA9DAHvCtk3SrRbIfB/kz4W9SpsLlnsxvu24e2Q05RoTbtBJVjdh501rK2O3iQXgFEnzvALgrQGN HyuXHTos5kV5qmP9pvq22euTN4juuxeVXaYbfP0nMjYEOQWbTbBWhMyCR4oLDMKoS5VQ9ArPEZn0v dRwzwMXU5Kpo18sZ1G59hkOciehYzjopMPoe/oU0dLUYPJNhiKBG0bOneTa+nSJ9k3WF0oO+p2DKx GiYCxYLPB9Jqqd/TX+e2ftFcn1TDUcTivWdL4CKUppf6FiSYzIYaOgSk+0wJMWv82ki8SsJLk5Hg/ h6j9GH3fhYAu11+3ijsQ==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.97.1 #2 (Red Hat Linux)) id 1rf5Zc-000000070Wd-0SXW; Tue, 27 Feb 2024 22:05:16 +0000 Received: from mail-qv1-xf2f.google.com ([2607:f8b0:4864:20::f2f]) by bombadil.infradead.org with esmtps (Exim 4.97.1 #2 (Red Hat Linux)) id 1rf5ZN-000000070Q5-2buV; Tue, 27 Feb 2024 22:05:03 +0000 Received: by mail-qv1-xf2f.google.com with SMTP id 6a1803df08f44-6900f479e3cso19342336d6.0; Tue, 27 Feb 2024 14:05:01 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20230601; t=1709071500; x=1709676300; darn=lists.infradead.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=ENJCVwViqySP78QQC22e16vdfpVFUmVF6XiIGfyzNm8=; b=Kd+7F/OTAzDA9gjEo05A0GKHMd8OdUO+5rb7weD5zf1kUsUYHplGbDJiHyXxK7WMNE 9ADuX0CY5fPrUkQb2qYqS4EibwtVJ/ZAto6s5ZYgoGrZoV9HwFrxv3OBxg/Fc1xcmNoo vzoLGIfaUHFEztgKSqry470pXJ5PwUnVbEdDtNTEsw3C4LavvyTZDEJPM+vlcLDVp3mu CIeK8UPWq+S8+2+RjakK+o73Wa1D2cjzQ4blh36hzht9Jrqoy1qi0sxaOMWrGVChwuT6 N/T78J3WVfzJaYuS+Bgu3opPhP0H4rX/C/4tndyqyai1eFRrDUgUOSwdwuTBHPg8gkWn aNVw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1709071500; x=1709676300; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=ENJCVwViqySP78QQC22e16vdfpVFUmVF6XiIGfyzNm8=; b=h3Y/Z2wXn9mapTTBj3RDADsFqeVVViOdQqlv/CXJd5/veI1TGmT3/vfPTRS//CP73m k2NeatJ0KMiALxxfvU9dQJTxdH1BiR7vvDqSh0j0tHdJJp39JcIuzYjb4F/gaggTifhD hq8rKCvA86vWubccERL/Y3eD4qLksHOYlZ7P25KFOfCLPjmenK2I02mFO4WJyqZlpqr3 uzK5rp6OYuAdV9p92EKnEZ3pRK3yo4S5z7Dny0MG/N7h46WeYptjCO5vUpJHIljNUpY3 ykl5C4prsCgMqwto5OmZnl9CJBpgzl1jv3J+fTi2gOF3ZZeGDAXuyBk46GCOAi4v1Qtz zm5g== X-Forwarded-Encrypted: i=1; AJvYcCVlIGoCAmdpVyjbAzvSAPxn+MB85ygDjV1DM1ZDZ2gkdG5tVaFzysHBoGdJDBJkdfM3s7SdiQOoJQginO/bIqPPJfcFES+39D8E43BpyQ== X-Gm-Message-State: AOJu0YxkbLSyMUr9F+855OqVwDlayd1I0QUNIuaQyPzfjWtDaIXa0xXR CEhEslxwrSvAyo4+Ctfp2pi7W1/3LTxu9wd6S7f3jSoorM89FVNyZPYzrQAmkFZllbeu X-Google-Smtp-Source: AGHT+IEpZQhtRi5w5yIbBlDmAdFLeORFRaXPwFhoPznALYLBHwR3eVYMv/pDmm9JMFJsmDcE9UXAiA== X-Received: by 2002:a05:6214:518c:b0:68f:fe7f:abff with SMTP id kl12-20020a056214518c00b0068ffe7fabffmr3307878qvb.19.1709071500273; Tue, 27 Feb 2024 14:05:00 -0800 (PST) Received: from aford-System-Version.lan ([2601:447:d002:5be:9ee3:b2ab:6ca:180d]) by smtp.gmail.com with ESMTPSA id c12-20020a0ce14c000000b0068fc55bcf6asm4569556qvl.119.2024.02.27.14.04.58 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 27 Feb 2024 14:04:59 -0800 (PST) From: Adam Ford To: linux-arm-kernel@lists.infradead.org, linux-phy@lists.infradead.org Cc: aford@beaconembedded.com, Lucas Stach , Adam Ford , Krzysztof Kozlowski , Luca Ceresoli , Vinod Koul , Kishon Vijay Abraham I , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Shawn Guo , Sascha Hauer , Pengutronix Kernel Team , Fabio Estevam , Catalin Marinas , Will Deacon , devicetree@vger.kernel.org, imx@lists.linux.dev, linux-kernel@vger.kernel.org Subject: [PATCH V7 1/6] dt-bindings: phy: add binding for the i.MX8MP HDMI PHY Date: Tue, 27 Feb 2024 16:04:35 -0600 Message-ID: <20240227220444.77566-2-aford173@gmail.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20240227220444.77566-1-aford173@gmail.com> References: <20240227220444.77566-1-aford173@gmail.com> MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20240227_140501_668552_EC6D7221 X-CRM114-Status: GOOD ( 15.76 ) X-BeenThere: linux-phy@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: Linux Phy Mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-phy" Errors-To: linux-phy-bounces+linux-phy=archiver.kernel.org@lists.infradead.org From: Lucas Stach Add a DT binding for the HDMI PHY found on the i.MX8MP SoC. Signed-off-by: Lucas Stach Signed-off-by: Adam Ford Reviewed-by: Krzysztof Kozlowski Reviewed-by: Luca Ceresoli --- V6: No Change V5: No Change V4: No Change V3: Removed mintems at the request of Krzysztof and add his reviewed-by V2: I (Adam) tried to help move this along, so I took Lucas' patch and attempted to apply fixes based on feedback. I don't have all the history, so apologies for that. Added phy-cells to the required list and fixed an error due to the word 'binding' being in the title. --- .../bindings/phy/fsl,imx8mp-hdmi-phy.yaml | 62 +++++++++++++++++++ 1 file changed, 62 insertions(+) create mode 100644 Documentation/devicetree/bindings/phy/fsl,imx8mp-hdmi-phy.yaml diff --git a/Documentation/devicetree/bindings/phy/fsl,imx8mp-hdmi-phy.yaml b/Documentation/devicetree/bindings/phy/fsl,imx8mp-hdmi-phy.yaml new file mode 100644 index 000000000000..c43e86a8c2e0 --- /dev/null +++ b/Documentation/devicetree/bindings/phy/fsl,imx8mp-hdmi-phy.yaml @@ -0,0 +1,62 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/phy/fsl,imx8mp-hdmi-phy.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Freescale i.MX8MP HDMI PHY + +maintainers: + - Lucas Stach + +properties: + compatible: + enum: + - fsl,imx8mp-hdmi-phy + + reg: + maxItems: 1 + + "#clock-cells": + const: 0 + + clocks: + maxItems: 2 + + clock-names: + items: + - const: apb + - const: ref + + "#phy-cells": + const: 0 + + power-domains: + maxItems: 1 + +required: + - compatible + - reg + - "#clock-cells" + - clocks + - clock-names + - "#phy-cells" + - power-domains + +additionalProperties: false + +examples: + - | + #include + #include + + phy@32fdff00 { + compatible = "fsl,imx8mp-hdmi-phy"; + reg = <0x32fdff00 0x100>; + clocks = <&clk IMX8MP_CLK_HDMI_APB>, + <&clk IMX8MP_CLK_HDMI_24M>; + clock-names = "apb", "ref"; + power-domains = <&hdmi_blk_ctrl IMX8MP_HDMIBLK_PD_HDMI_TX_PHY>; + #clock-cells = <0>; + #phy-cells = <0>; + }; From patchwork Tue Feb 27 22:04:36 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Adam Ford X-Patchwork-Id: 13574485 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id A7907C5478C for ; Tue, 27 Feb 2024 22:05:19 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:MIME-Version:References:In-Reply-To: Message-ID:Date:Subject:Cc:To:From:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; bh=R6v5H03gVmNxUeSkNsUYnCoCt+R8eBqW5Sb14l7BDjk=; b=zqQ8IspICwwjJ3 C1noQ7TzBAyu2nCR4wliG0C++r/yI9cgGfcOnSr7yJQ8a+w8epEnkrOAA6Es21CuwRfUuBgqvPbNn 6DgBPuESVxfrcTb77Vk1tD9lmdqK1voIVi5KSYOk+MkHv3MtiUX2e26cN0IQ2tCeyobpoJHvOzxvh rMOrquLsd9hENNyF2vaLLFL3ZnBiSrKxRK4hJaFcqBHGr1v2JC1qoG1ohAfB/BIrsDLXVJyANkPS2 kqxk5Pu/EQpgLEVFl6UB6q+Z0QwHHoyHz/tnG2eQMrFOM2LrBxHZEmEzgDZBgaa7QLB7AhEv+5ktS IPmcqN0+1a4FrAKcgvCw==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.97.1 #2 (Red Hat Linux)) id 1rf5Zf-000000070YH-0FgH; Tue, 27 Feb 2024 22:05:19 +0000 Received: from mail-qv1-xf29.google.com ([2607:f8b0:4864:20::f29]) by bombadil.infradead.org with esmtps (Exim 4.97.1 #2 (Red Hat Linux)) id 1rf5ZR-000000070RF-0R3R; Tue, 27 Feb 2024 22:05:07 +0000 Received: by mail-qv1-xf29.google.com with SMTP id 6a1803df08f44-68facd7ea4bso15324616d6.0; Tue, 27 Feb 2024 14:05:04 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20230601; t=1709071503; x=1709676303; darn=lists.infradead.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=r8X0ujGXQtDgtpxgxvRpdwQkBEPUujPt/s5zRw7KIaM=; b=V0lJTtky/c7VKPXCRWo8Rrct+MXTzp0eGc/gP28fu5i7rMZm8iNJrplpjxi/V/rOBJ eNQIcjMvPn0kuVg4ACb2FRVfRiDY2my5v5qmZshtGrCt9O/RRCWuETDTN5LtEM+PssKI H6Ui3cayetHsV2purTploprix6vbiN+UxTMGBTjhOTa9rqwHv8CZCgAdiuS2AEHyfqG4 BRDmkbHn9hzIn66eJMtXFzr9V3B0HOvlUPPamSPeWBJq4EeHhaaxdBahWYXCGaEdLWPX Kgu3UsimpDsltfPppmp9UesiTOqQDvtN+KpBhESynkCZOp0l7B4otzXjh+NdA1p7bOuE TvWA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1709071503; x=1709676303; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=r8X0ujGXQtDgtpxgxvRpdwQkBEPUujPt/s5zRw7KIaM=; b=IiYh15b9PwOhCCCzqMMlp/f9pw7wmVx66wMeLn85fDmdVEqUZSVnTh86Dh5fukMTet 1i65nnxUQM/cbjjAVuypHePgtsbW/FXJauR296J/HKmxGIMLToEBVrmJcI2yPiHAxCyW XBlQgN8SXYUghGsPeWuhv3pUsLqUrAt9r0z1n6TVFTZ6sNq02EsyQ7C16Wd3tT6LNQDX UTkp3SHEI4XeiW3Zf37HJgFGXP18lClNG1o8Sq/gp81jJdk8XZE5xW570yzHNaDSajg7 k/D0N+NEZHgQ7rSQtKOCZfMwKFE3ZlE8iKy6IOwBYTINjgN2FfnWxz58yantH28EuJCj 6ZuA== X-Forwarded-Encrypted: i=1; AJvYcCX9hMdhKSfVKsow1ORa1dIKsb73jnUcq0KnXw3OVTBhjcx3fcZe/mVMH+PtFVLhUaPQUz1JTgJq82YsiXtoRkV4VxtSI8GvyDYdjWZOWA== X-Gm-Message-State: AOJu0YyhoheveK0hwayF/hrJEsCryVVf/HDk3InP+ACOZlnikkoU2Bas KK4U+158A+2Rrhywx0iJoYkhJIdY2XDMqpfh9jCy+BFcE5dfbw2rXDYwY45QER7xXKgH X-Google-Smtp-Source: AGHT+IHC4719qgYlOHl8JEnfK9cJI+souAJn87GtpoCOQVMSM9D5BRjsungWX8xSGjEFx+GSue4v3Q== X-Received: by 2002:a05:6214:29ca:b0:68f:3c36:1b74 with SMTP id gh10-20020a05621429ca00b0068f3c361b74mr4192543qvb.41.1709071503133; Tue, 27 Feb 2024 14:05:03 -0800 (PST) Received: from aford-System-Version.lan ([2601:447:d002:5be:9ee3:b2ab:6ca:180d]) by smtp.gmail.com with ESMTPSA id c12-20020a0ce14c000000b0068fc55bcf6asm4569556qvl.119.2024.02.27.14.05.01 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 27 Feb 2024 14:05:02 -0800 (PST) From: Adam Ford To: linux-arm-kernel@lists.infradead.org, linux-phy@lists.infradead.org Cc: aford@beaconembedded.com, Lucas Stach , Luca Ceresoli , Richard Leitner , Marco Felsch , Alexander Stein , Frieder Schrempf , Adam Ford , Marek Vasut , Vinod Koul , Kishon Vijay Abraham I , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Shawn Guo , Sascha Hauer , Pengutronix Kernel Team , Fabio Estevam , Catalin Marinas , Will Deacon , devicetree@vger.kernel.org, imx@lists.linux.dev, linux-kernel@vger.kernel.org Subject: [PATCH V7 2/6] phy: freescale: add Samsung HDMI PHY Date: Tue, 27 Feb 2024 16:04:36 -0600 Message-ID: <20240227220444.77566-3-aford173@gmail.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20240227220444.77566-1-aford173@gmail.com> References: <20240227220444.77566-1-aford173@gmail.com> MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20240227_140505_167672_43FDEB74 X-CRM114-Status: GOOD ( 20.49 ) X-BeenThere: linux-phy@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: Linux Phy Mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-phy" Errors-To: linux-phy-bounces+linux-phy=archiver.kernel.org@lists.infradead.org From: Lucas Stach This adds the driver for the Samsung HDMI PHY found on the i.MX8MP SoC. Based on downstream implementation from Sandor Yu . According to the TRM, the PHY receives parallel data from the link and serializes it. It also sets the PLL clock needed for the TX serializer. Tested-by: Luca Ceresoli (v2) Tested-by: Richard Leitner (v2) Co-developed-by: Marco Felsch Signed-off-by: Marco Felsch Signed-off-by: Lucas Stach Tested-by: Alexander Stein Tested-by: Frieder Schrempf # Kontron BL Signed-off-by: Adam Ford Tested-by: Marek Vasut Tested-by: Luca Ceresoli --- V6: Set Kconfig dependency to include COMMON_CLK due to build errors V5: Remove an unnecessary include Migrate from of_clk_add_provider to of_clk_add_hw_provider Make const structures static Fix uninitialized variables and prevent div by 0 Mark PM functions as __maybe_unused V4: - I (Adam) added a comment in the code for clarifcation based on questions from Luca concerning a difference between the code and the ref manual. - Fixed the GENMASK on REG14 - Expanded the commit message briefly describing a bit more of what this driver does. - Removed some unnecessary include files. v3: - use GENMASK/FIELD_PREP - lowercase hex values - correct coding style v2: - use DEFINE_RUNTIME_DEV_PM_OPS --- drivers/phy/freescale/Kconfig | 6 + drivers/phy/freescale/Makefile | 1 + drivers/phy/freescale/phy-fsl-samsung-hdmi.c | 720 +++++++++++++++++++ 3 files changed, 727 insertions(+) create mode 100644 drivers/phy/freescale/phy-fsl-samsung-hdmi.c diff --git a/drivers/phy/freescale/Kconfig b/drivers/phy/freescale/Kconfig index 853958fb2c06..45aaaea14fb4 100644 --- a/drivers/phy/freescale/Kconfig +++ b/drivers/phy/freescale/Kconfig @@ -35,6 +35,12 @@ config PHY_FSL_IMX8M_PCIE Enable this to add support for the PCIE PHY as found on i.MX8M family of SOCs. +config PHY_FSL_SAMSUNG_HDMI_PHY + tristate "Samsung HDMI PHY support" + depends on OF && HAS_IOMEM && COMMON_CLK + help + Enable this to add support for the Samsung HDMI PHY in i.MX8MP. + endif config PHY_FSL_LYNX_28G diff --git a/drivers/phy/freescale/Makefile b/drivers/phy/freescale/Makefile index cedb328bc4d2..c4386bfdb853 100644 --- a/drivers/phy/freescale/Makefile +++ b/drivers/phy/freescale/Makefile @@ -4,3 +4,4 @@ obj-$(CONFIG_PHY_MIXEL_LVDS_PHY) += phy-fsl-imx8qm-lvds-phy.o obj-$(CONFIG_PHY_MIXEL_MIPI_DPHY) += phy-fsl-imx8-mipi-dphy.o obj-$(CONFIG_PHY_FSL_IMX8M_PCIE) += phy-fsl-imx8m-pcie.o obj-$(CONFIG_PHY_FSL_LYNX_28G) += phy-fsl-lynx-28g.o +obj-$(CONFIG_PHY_FSL_SAMSUNG_HDMI_PHY) += phy-fsl-samsung-hdmi.o diff --git a/drivers/phy/freescale/phy-fsl-samsung-hdmi.c b/drivers/phy/freescale/phy-fsl-samsung-hdmi.c new file mode 100644 index 000000000000..89e2c01f2ccf --- /dev/null +++ b/drivers/phy/freescale/phy-fsl-samsung-hdmi.c @@ -0,0 +1,720 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright 2020 NXP + * Copyright 2022 Pengutronix, Lucas Stach + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#define PHY_REG_00 0x00 +#define PHY_REG_01 0x04 +#define PHY_REG_02 0x08 +#define PHY_REG_08 0x20 +#define PHY_REG_09 0x24 +#define PHY_REG_10 0x28 +#define PHY_REG_11 0x2c + +#define PHY_REG_12 0x30 +#define REG12_CK_DIV_MASK GENMASK(5, 4) + +#define PHY_REG_13 0x34 +#define REG13_TG_CODE_LOW_MASK GENMASK(7, 0) + +#define PHY_REG_14 0x38 +#define REG14_TOL_MASK GENMASK(7, 4) +#define REG14_RP_CODE_MASK GENMASK(3, 1) +#define REG14_TG_CODE_HIGH_MASK GENMASK(0, 0) + +#define PHY_REG_15 0x3c +#define PHY_REG_16 0x40 +#define PHY_REG_17 0x44 +#define PHY_REG_18 0x48 +#define PHY_REG_19 0x4c +#define PHY_REG_20 0x50 + +#define PHY_REG_21 0x54 +#define REG21_SEL_TX_CK_INV BIT(7) +#define REG21_PMS_S_MASK GENMASK(3, 0) + +#define PHY_REG_22 0x58 +#define PHY_REG_23 0x5c +#define PHY_REG_24 0x60 +#define PHY_REG_25 0x64 +#define PHY_REG_26 0x68 +#define PHY_REG_27 0x6c +#define PHY_REG_28 0x70 +#define PHY_REG_29 0x74 +#define PHY_REG_30 0x78 +#define PHY_REG_31 0x7c +#define PHY_REG_32 0x80 + +/* + * REG33 does not match the ref manual. According to Sandor Yu from NXP, + * "There is a doc issue on the i.MX8MP latest RM" + * REG33 is being used per guidance from Sandor + */ + +#define PHY_REG_33 0x84 +#define REG33_MODE_SET_DONE BIT(7) +#define REG33_FIX_DA BIT(1) + +#define PHY_REG_34 0x88 +#define REG34_PHY_READY BIT(7) +#define REG34_PLL_LOCK BIT(6) +#define REG34_PHY_CLK_READY BIT(5) + +#define PHY_REG_35 0x8c +#define PHY_REG_36 0x90 +#define PHY_REG_37 0x94 +#define PHY_REG_38 0x98 +#define PHY_REG_39 0x9c +#define PHY_REG_40 0xa0 +#define PHY_REG_41 0xa4 +#define PHY_REG_42 0xa8 +#define PHY_REG_43 0xac +#define PHY_REG_44 0xb0 +#define PHY_REG_45 0xb4 +#define PHY_REG_46 0xb8 +#define PHY_REG_47 0xbc + +#define PHY_PLL_DIV_REGS_NUM 6 + +struct phy_config { + u32 pixclk; + u8 pll_div_regs[PHY_PLL_DIV_REGS_NUM]; +}; + +static const struct phy_config phy_pll_cfg[] = { + { + .pixclk = 22250000, + .pll_div_regs = { 0x4b, 0xf1, 0x89, 0x88, 0x80, 0x40 }, + }, { + .pixclk = 23750000, + .pll_div_regs = { 0x50, 0xf1, 0x86, 0x85, 0x80, 0x40 }, + }, { + .pixclk = 24000000, + .pll_div_regs = { 0x50, 0xf0, 0x00, 0x00, 0x80, 0x00 }, + }, { + .pixclk = 24024000, + .pll_div_regs = { 0x50, 0xf1, 0x99, 0x02, 0x80, 0x40 }, + }, { + .pixclk = 25175000, + .pll_div_regs = { 0x54, 0xfc, 0xcc, 0x91, 0x80, 0x40 }, + }, { + .pixclk = 25200000, + .pll_div_regs = { 0x54, 0xf0, 0x00, 0x00, 0x80, 0x00 }, + }, { + .pixclk = 26750000, + .pll_div_regs = { 0x5a, 0xf2, 0x89, 0x88, 0x80, 0x40 }, + }, { + .pixclk = 27000000, + .pll_div_regs = { 0x5a, 0xf0, 0x00, 0x00, 0x80, 0x00 }, + }, { + .pixclk = 27027000, + .pll_div_regs = { 0x5a, 0xf2, 0xfd, 0x0c, 0x80, 0x40 }, + }, { + .pixclk = 29500000, + .pll_div_regs = { 0x62, 0xf4, 0x95, 0x08, 0x80, 0x40 }, + }, { + .pixclk = 30750000, + .pll_div_regs = { 0x66, 0xf4, 0x82, 0x01, 0x88, 0x45 }, + }, { + .pixclk = 30888000, + .pll_div_regs = { 0x66, 0xf4, 0x99, 0x18, 0x88, 0x45 }, + }, { + .pixclk = 33750000, + .pll_div_regs = { 0x70, 0xf4, 0x82, 0x01, 0x80, 0x40 }, + }, { + .pixclk = 35000000, + .pll_div_regs = { 0x58, 0xb8, 0x8b, 0x88, 0x80, 0x40 }, + }, { + .pixclk = 36000000, + .pll_div_regs = { 0x5a, 0xb0, 0x00, 0x00, 0x80, 0x00 }, + }, { + .pixclk = 36036000, + .pll_div_regs = { 0x5a, 0xb2, 0xfd, 0x0c, 0x80, 0x40 }, + }, { + .pixclk = 40000000, + .pll_div_regs = { 0x64, 0xb0, 0x00, 0x00, 0x80, 0x00 }, + }, { + .pixclk = 43200000, + .pll_div_regs = { 0x5a, 0x90, 0x00, 0x00, 0x80, 0x00 }, + }, { + .pixclk = 43243200, + .pll_div_regs = { 0x5a, 0x92, 0xfd, 0x0c, 0x80, 0x40 }, + }, { + .pixclk = 44500000, + .pll_div_regs = { 0x5c, 0x92, 0x98, 0x11, 0x84, 0x41 }, + }, { + .pixclk = 47000000, + .pll_div_regs = { 0x62, 0x94, 0x95, 0x82, 0x80, 0x40 }, + }, { + .pixclk = 47500000, + .pll_div_regs = { 0x63, 0x96, 0xa1, 0x82, 0x80, 0x40 }, + }, { + .pixclk = 50349650, + .pll_div_regs = { 0x54, 0x7c, 0xc3, 0x8f, 0x80, 0x40 }, + }, { + .pixclk = 50400000, + .pll_div_regs = { 0x54, 0x70, 0x00, 0x00, 0x80, 0x00 }, + }, { + .pixclk = 53250000, + .pll_div_regs = { 0x58, 0x72, 0x84, 0x03, 0x82, 0x41 }, + }, { + .pixclk = 53500000, + .pll_div_regs = { 0x5a, 0x72, 0x89, 0x88, 0x80, 0x40 }, + }, { + .pixclk = 54000000, + .pll_div_regs = { 0x5a, 0x70, 0x00, 0x00, 0x80, 0x00 }, + }, { + .pixclk = 54054000, + .pll_div_regs = { 0x5a, 0x72, 0xfd, 0x0c, 0x80, 0x40 }, + }, { + .pixclk = 59000000, + .pll_div_regs = { 0x62, 0x74, 0x95, 0x08, 0x80, 0x40 }, + }, { + .pixclk = 59340659, + .pll_div_regs = { 0x62, 0x74, 0xdb, 0x52, 0x88, 0x47 }, + }, { + .pixclk = 59400000, + .pll_div_regs = { 0x63, 0x70, 0x00, 0x00, 0x80, 0x00 }, + }, { + .pixclk = 61500000, + .pll_div_regs = { 0x66, 0x74, 0x82, 0x01, 0x88, 0x45 }, + }, { + .pixclk = 63500000, + .pll_div_regs = { 0x69, 0x74, 0x89, 0x08, 0x80, 0x40 }, + }, { + .pixclk = 67500000, + .pll_div_regs = { 0x54, 0x52, 0x87, 0x03, 0x80, 0x40 }, + }, { + .pixclk = 70000000, + .pll_div_regs = { 0x58, 0x58, 0x8b, 0x88, 0x80, 0x40 }, + }, { + .pixclk = 72000000, + .pll_div_regs = { 0x5a, 0x50, 0x00, 0x00, 0x80, 0x00 }, + }, { + .pixclk = 72072000, + .pll_div_regs = { 0x5a, 0x52, 0xfd, 0x0c, 0x80, 0x40 }, + }, { + .pixclk = 74176000, + .pll_div_regs = { 0x5d, 0x58, 0xdb, 0xA2, 0x88, 0x41 }, + }, { + .pixclk = 74250000, + .pll_div_regs = { 0x5c, 0x52, 0x90, 0x0d, 0x84, 0x41 }, + }, { + .pixclk = 78500000, + .pll_div_regs = { 0x62, 0x54, 0x87, 0x01, 0x80, 0x40 }, + }, { + .pixclk = 80000000, + .pll_div_regs = { 0x64, 0x50, 0x00, 0x00, 0x80, 0x00 }, + }, { + .pixclk = 82000000, + .pll_div_regs = { 0x66, 0x54, 0x82, 0x01, 0x88, 0x45 }, + }, { + .pixclk = 82500000, + .pll_div_regs = { 0x67, 0x54, 0x88, 0x01, 0x90, 0x49 }, + }, { + .pixclk = 89000000, + .pll_div_regs = { 0x70, 0x54, 0x84, 0x83, 0x80, 0x40 }, + }, { + .pixclk = 90000000, + .pll_div_regs = { 0x70, 0x54, 0x82, 0x01, 0x80, 0x40 }, + }, { + .pixclk = 94000000, + .pll_div_regs = { 0x4e, 0x32, 0xa7, 0x10, 0x80, 0x40 }, + }, { + .pixclk = 95000000, + .pll_div_regs = { 0x50, 0x31, 0x86, 0x85, 0x80, 0x40 }, + }, { + .pixclk = 98901099, + .pll_div_regs = { 0x52, 0x3a, 0xdb, 0x4c, 0x88, 0x47 }, + }, { + .pixclk = 99000000, + .pll_div_regs = { 0x52, 0x32, 0x82, 0x01, 0x88, 0x47 }, + }, { + .pixclk = 100699300, + .pll_div_regs = { 0x54, 0x3c, 0xc3, 0x8f, 0x80, 0x40 }, + }, { + .pixclk = 100800000, + .pll_div_regs = { 0x54, 0x30, 0x00, 0x00, 0x80, 0x00 }, + }, { + .pixclk = 102500000, + .pll_div_regs = { 0x55, 0x32, 0x8c, 0x05, 0x90, 0x4b }, + }, { + .pixclk = 104750000, + .pll_div_regs = { 0x57, 0x32, 0x98, 0x07, 0x90, 0x49 }, + }, { + .pixclk = 106500000, + .pll_div_regs = { 0x58, 0x32, 0x84, 0x03, 0x82, 0x41 }, + }, { + .pixclk = 107000000, + .pll_div_regs = { 0x5a, 0x32, 0x89, 0x88, 0x80, 0x40 }, + }, { + .pixclk = 108000000, + .pll_div_regs = { 0x5a, 0x30, 0x00, 0x00, 0x80, 0x00 }, + }, { + .pixclk = 108108000, + .pll_div_regs = { 0x5a, 0x32, 0xfd, 0x0c, 0x80, 0x40 }, + }, { + .pixclk = 118000000, + .pll_div_regs = { 0x62, 0x34, 0x95, 0x08, 0x80, 0x40 }, + }, { + .pixclk = 118800000, + .pll_div_regs = { 0x63, 0x30, 0x00, 0x00, 0x80, 0x00 }, + }, { + .pixclk = 123000000, + .pll_div_regs = { 0x66, 0x34, 0x82, 0x01, 0x88, 0x45 }, + }, { + .pixclk = 127000000, + .pll_div_regs = { 0x69, 0x34, 0x89, 0x08, 0x80, 0x40 }, + }, { + .pixclk = 135000000, + .pll_div_regs = { 0x70, 0x34, 0x82, 0x01, 0x80, 0x40 }, + }, { + .pixclk = 135580000, + .pll_div_regs = { 0x71, 0x39, 0xe9, 0x82, 0x9c, 0x5b }, + }, { + .pixclk = 137520000, + .pll_div_regs = { 0x72, 0x38, 0x99, 0x10, 0x85, 0x41 }, + }, { + .pixclk = 138750000, + .pll_div_regs = { 0x73, 0x35, 0x88, 0x05, 0x90, 0x4d }, + }, { + .pixclk = 140000000, + .pll_div_regs = { 0x75, 0x36, 0xa7, 0x90, 0x80, 0x40 }, + }, { + .pixclk = 144000000, + .pll_div_regs = { 0x78, 0x30, 0x00, 0x00, 0x80, 0x00 }, + }, { + .pixclk = 148352000, + .pll_div_regs = { 0x7b, 0x35, 0xdb, 0x39, 0x90, 0x45 }, + }, { + .pixclk = 148500000, + .pll_div_regs = { 0x7b, 0x35, 0x84, 0x03, 0x90, 0x45 }, + }, { + .pixclk = 154000000, + .pll_div_regs = { 0x40, 0x18, 0x83, 0x01, 0x00, 0x40 }, + }, { + .pixclk = 157000000, + .pll_div_regs = { 0x41, 0x11, 0xa7, 0x14, 0x80, 0x40 }, + }, { + .pixclk = 160000000, + .pll_div_regs = { 0x42, 0x12, 0xa1, 0x20, 0x80, 0x40 }, + }, { + .pixclk = 162000000, + .pll_div_regs = { 0x43, 0x18, 0x8b, 0x08, 0x96, 0x55 }, + }, { + .pixclk = 164000000, + .pll_div_regs = { 0x45, 0x11, 0x83, 0x82, 0x90, 0x4b }, + }, { + .pixclk = 165000000, + .pll_div_regs = { 0x45, 0x11, 0x84, 0x81, 0x90, 0x4b }, + }, { + .pixclk = 180000000, + .pll_div_regs = { 0x4b, 0x10, 0x00, 0x00, 0x80, 0x00 }, + }, { + .pixclk = 185625000, + .pll_div_regs = { 0x4e, 0x12, 0x9a, 0x95, 0x80, 0x40 }, + }, { + .pixclk = 188000000, + .pll_div_regs = { 0x4e, 0x12, 0xa7, 0x10, 0x80, 0x40 }, + }, { + .pixclk = 198000000, + .pll_div_regs = { 0x52, 0x12, 0x82, 0x01, 0x88, 0x47 }, + }, { + .pixclk = 205000000, + .pll_div_regs = { 0x55, 0x12, 0x8c, 0x05, 0x90, 0x4b }, + }, { + .pixclk = 209500000, + .pll_div_regs = { 0x57, 0x12, 0x98, 0x07, 0x90, 0x49 }, + }, { + .pixclk = 213000000, + .pll_div_regs = { 0x58, 0x12, 0x84, 0x03, 0x82, 0x41 }, + }, { + .pixclk = 216000000, + .pll_div_regs = { 0x5a, 0x10, 0x00, 0x00, 0x80, 0x00 }, + }, { + .pixclk = 216216000, + .pll_div_regs = { 0x5a, 0x12, 0xfd, 0x0c, 0x80, 0x40 }, + }, { + .pixclk = 237600000, + .pll_div_regs = { 0x63, 0x10, 0x00, 0x00, 0x80, 0x00 }, + }, { + .pixclk = 254000000, + .pll_div_regs = { 0x69, 0x14, 0x89, 0x08, 0x80, 0x40 }, + }, { + .pixclk = 277500000, + .pll_div_regs = { 0x73, 0x15, 0x88, 0x05, 0x90, 0x4d }, + }, { + .pixclk = 288000000, + .pll_div_regs = { 0x78, 0x10, 0x00, 0x00, 0x80, 0x00 }, + }, { + .pixclk = 297000000, + .pll_div_regs = { 0x7b, 0x15, 0x84, 0x03, 0x90, 0x45 }, + }, +}; + +struct reg_settings { + u8 reg; + u8 val; +}; + +static const struct reg_settings common_phy_cfg[] = { + { PHY_REG_00, 0x00 }, { PHY_REG_01, 0xd1 }, + { PHY_REG_08, 0x4f }, { PHY_REG_09, 0x30 }, + { PHY_REG_10, 0x33 }, { PHY_REG_11, 0x65 }, + /* REG12 pixclk specific */ + /* REG13 pixclk specific */ + /* REG14 pixclk specific */ + { PHY_REG_15, 0x80 }, { PHY_REG_16, 0x6c }, + { PHY_REG_17, 0xf2 }, { PHY_REG_18, 0x67 }, + { PHY_REG_19, 0x00 }, { PHY_REG_20, 0x10 }, + /* REG21 pixclk specific */ + { PHY_REG_22, 0x30 }, { PHY_REG_23, 0x32 }, + { PHY_REG_24, 0x60 }, { PHY_REG_25, 0x8f }, + { PHY_REG_26, 0x00 }, { PHY_REG_27, 0x00 }, + { PHY_REG_28, 0x08 }, { PHY_REG_29, 0x00 }, + { PHY_REG_30, 0x00 }, { PHY_REG_31, 0x00 }, + { PHY_REG_32, 0x00 }, { PHY_REG_33, 0x80 }, + { PHY_REG_34, 0x00 }, { PHY_REG_35, 0x00 }, + { PHY_REG_36, 0x00 }, { PHY_REG_37, 0x00 }, + { PHY_REG_38, 0x00 }, { PHY_REG_39, 0x00 }, + { PHY_REG_40, 0x00 }, { PHY_REG_41, 0xe0 }, + { PHY_REG_42, 0x83 }, { PHY_REG_43, 0x0f }, + { PHY_REG_44, 0x3E }, { PHY_REG_45, 0xf8 }, + { PHY_REG_46, 0x00 }, { PHY_REG_47, 0x00 } +}; + +struct fsl_samsung_hdmi_phy { + struct device *dev; + void __iomem *regs; + struct clk *apbclk; + struct clk *refclk; + + /* clk provider */ + struct clk_hw hw; + const struct phy_config *cur_cfg; +}; + +static inline struct fsl_samsung_hdmi_phy * +to_fsl_samsung_hdmi_phy(struct clk_hw *hw) +{ + return container_of(hw, struct fsl_samsung_hdmi_phy, hw); +} + +static void +fsl_samsung_hdmi_phy_configure_pixclk(struct fsl_samsung_hdmi_phy *phy, + const struct phy_config *cfg) +{ + u8 div = 0x1; + + switch (cfg->pixclk) { + case 22250000 ... 33750000: + div = 0xf; + break; + case 35000000 ... 40000000: + div = 0xb; + break; + case 43200000 ... 47500000: + div = 0x9; + break; + case 50349650 ... 63500000: + div = 0x7; + break; + case 67500000 ... 90000000: + div = 0x5; + break; + case 94000000 ... 148500000: + div = 0x3; + break; + case 154000000 ... 297000000: + div = 0x1; + break; + } + + writeb(REG21_SEL_TX_CK_INV | FIELD_PREP(REG21_PMS_S_MASK, div), + phy->regs + PHY_REG_21); +} + +static void +fsl_samsung_hdmi_phy_configure_pll_lock_det(struct fsl_samsung_hdmi_phy *phy, + const struct phy_config *cfg) +{ + u32 pclk = cfg->pixclk; + u32 fld_tg_code; + u32 pclk_khz; + u8 div = 1; + + switch (cfg->pixclk) { + case 22250000 ... 47500000: + div = 1; + break; + case 50349650 ... 99000000: + div = 2; + break; + case 100699300 ... 198000000: + div = 4; + break; + case 205000000 ... 297000000: + div = 8; + break; + } + + writeb(FIELD_PREP(REG12_CK_DIV_MASK, ilog2(div)), phy->regs + PHY_REG_12); + + /* + * Calculation for the frequency lock detector target code (fld_tg_code) + * is based on reference manual register description of PHY_REG13 + * (13.10.3.1.14.2): + * 1st) Calculate int_pllclk which is determinded by FLD_CK_DIV + * 2nd) Increase resolution to avoid rounding issues + * 3th) Do the div (256 / Freq. of int_pllclk) * 24 + * 4th) Reduce the resolution and always round up since the NXP + * settings rounding up always too. TODO: Check if that is + * correct. + */ + pclk /= div; + pclk_khz = pclk / 1000; + fld_tg_code = 256 * 1000 * 1000 / pclk_khz * 24; + fld_tg_code = DIV_ROUND_UP(fld_tg_code, 1000); + + /* FLD_TOL and FLD_RP_CODE taken from downstream driver */ + writeb(FIELD_PREP(REG13_TG_CODE_LOW_MASK, fld_tg_code), + phy->regs + PHY_REG_13); + writeb(FIELD_PREP(REG14_TOL_MASK, 2) | + FIELD_PREP(REG14_RP_CODE_MASK, 2) | + FIELD_PREP(REG14_TG_CODE_HIGH_MASK, fld_tg_code >> 8), + phy->regs + PHY_REG_14); +} + +static int fsl_samsung_hdmi_phy_configure(struct fsl_samsung_hdmi_phy *phy, + const struct phy_config *cfg) +{ + int i, ret; + u8 val; + + /* HDMI PHY init */ + writeb(REG33_FIX_DA, phy->regs + PHY_REG_33); + + /* common PHY registers */ + for (i = 0; i < ARRAY_SIZE(common_phy_cfg); i++) + writeb(common_phy_cfg[i].val, phy->regs + common_phy_cfg[i].reg); + + /* set individual PLL registers PHY_REG2 ... PHY_REG7 */ + for (i = 0; i < PHY_PLL_DIV_REGS_NUM; i++) + writeb(cfg->pll_div_regs[i], phy->regs + PHY_REG_02 + i * 4); + + fsl_samsung_hdmi_phy_configure_pixclk(phy, cfg); + fsl_samsung_hdmi_phy_configure_pll_lock_det(phy, cfg); + + writeb(REG33_FIX_DA | REG33_MODE_SET_DONE, phy->regs + PHY_REG_33); + + ret = readb_poll_timeout(phy->regs + PHY_REG_34, val, + val & REG34_PLL_LOCK, 50, 20000); + if (ret) + dev_err(phy->dev, "PLL failed to lock\n"); + + return ret; +} + +static unsigned long phy_clk_recalc_rate(struct clk_hw *hw, + unsigned long parent_rate) +{ + struct fsl_samsung_hdmi_phy *phy = to_fsl_samsung_hdmi_phy(hw); + + if (!phy->cur_cfg) + return 74250000; + + return phy->cur_cfg->pixclk; +} + +static long phy_clk_round_rate(struct clk_hw *hw, + unsigned long rate, unsigned long *parent_rate) +{ + int i; + + for (i = ARRAY_SIZE(phy_pll_cfg) - 1; i >= 0; i--) + if (phy_pll_cfg[i].pixclk <= rate) + return phy_pll_cfg[i].pixclk; + + return -EINVAL; +} + +static int phy_clk_set_rate(struct clk_hw *hw, + unsigned long rate, unsigned long parent_rate) +{ + struct fsl_samsung_hdmi_phy *phy = to_fsl_samsung_hdmi_phy(hw); + int i; + + for (i = ARRAY_SIZE(phy_pll_cfg) - 1; i >= 0; i--) + if (phy_pll_cfg[i].pixclk <= rate) + break; + + if (i < 0) + return -EINVAL; + + phy->cur_cfg = &phy_pll_cfg[i]; + + return fsl_samsung_hdmi_phy_configure(phy, phy->cur_cfg); +} + +static const struct clk_ops phy_clk_ops = { + .recalc_rate = phy_clk_recalc_rate, + .round_rate = phy_clk_round_rate, + .set_rate = phy_clk_set_rate, +}; + +static int phy_clk_register(struct fsl_samsung_hdmi_phy *phy) +{ + struct device *dev = phy->dev; + struct device_node *np = dev->of_node; + struct clk_init_data init; + const char *parent_name; + struct clk *phyclk; + int ret; + + parent_name = __clk_get_name(phy->refclk); + + init.parent_names = &parent_name; + init.num_parents = 1; + init.flags = 0; + init.name = "hdmi_pclk"; + init.ops = &phy_clk_ops; + + phy->hw.init = &init; + + phyclk = devm_clk_register(dev, &phy->hw); + if (IS_ERR(phyclk)) + return dev_err_probe(dev, PTR_ERR(phyclk), + "failed to register clock\n"); + + ret = of_clk_add_hw_provider(np, of_clk_hw_simple_get, phyclk); + if (ret) + return dev_err_probe(dev, ret, + "failed to register clock provider\n"); + + return 0; +} + +static int fsl_samsung_hdmi_phy_probe(struct platform_device *pdev) +{ + struct fsl_samsung_hdmi_phy *phy; + int ret; + + phy = devm_kzalloc(&pdev->dev, sizeof(*phy), GFP_KERNEL); + if (!phy) + return -ENOMEM; + + platform_set_drvdata(pdev, phy); + phy->dev = &pdev->dev; + + phy->regs = devm_platform_ioremap_resource(pdev, 0); + if (IS_ERR(phy->regs)) + return PTR_ERR(phy->regs); + + phy->apbclk = devm_clk_get(phy->dev, "apb"); + if (IS_ERR(phy->apbclk)) + return dev_err_probe(phy->dev, PTR_ERR(phy->apbclk), + "failed to get apb clk\n"); + + phy->refclk = devm_clk_get(phy->dev, "ref"); + if (IS_ERR(phy->refclk)) + return dev_err_probe(phy->dev, PTR_ERR(phy->refclk), + "failed to get ref clk\n"); + + ret = clk_prepare_enable(phy->apbclk); + if (ret) { + dev_err(phy->dev, "failed to enable apbclk\n"); + return ret; + } + + pm_runtime_get_noresume(phy->dev); + pm_runtime_set_active(phy->dev); + pm_runtime_enable(phy->dev); + + ret = phy_clk_register(phy); + if (ret) { + dev_err(&pdev->dev, "register clk failed\n"); + goto register_clk_failed; + } + + pm_runtime_put(phy->dev); + + return 0; + +register_clk_failed: + clk_disable_unprepare(phy->apbclk); + + return ret; +} + +static int fsl_samsung_hdmi_phy_remove(struct platform_device *pdev) +{ + of_clk_del_provider(pdev->dev.of_node); + + return 0; +} + +static int __maybe_unused fsl_samsung_hdmi_phy_suspend(struct device *dev) +{ + struct fsl_samsung_hdmi_phy *phy = dev_get_drvdata(dev); + + clk_disable_unprepare(phy->apbclk); + + return 0; +} + +static int __maybe_unused fsl_samsung_hdmi_phy_resume(struct device *dev) +{ + struct fsl_samsung_hdmi_phy *phy = dev_get_drvdata(dev); + int ret = 0; + + ret = clk_prepare_enable(phy->apbclk); + if (ret) { + dev_err(phy->dev, "failed to enable apbclk\n"); + return ret; + } + + if (phy->cur_cfg) + ret = fsl_samsung_hdmi_phy_configure(phy, phy->cur_cfg); + + return ret; + +} + +static DEFINE_RUNTIME_DEV_PM_OPS(fsl_samsung_hdmi_phy_pm_ops, + fsl_samsung_hdmi_phy_suspend, + fsl_samsung_hdmi_phy_resume, NULL); + +static const struct of_device_id fsl_samsung_hdmi_phy_of_match[] = { + { + .compatible = "fsl,imx8mp-hdmi-phy", + }, { + /* sentinel */ + } +}; +MODULE_DEVICE_TABLE(of, fsl_samsung_hdmi_phy_of_match); + +static struct platform_driver fsl_samsung_hdmi_phy_driver = { + .probe = fsl_samsung_hdmi_phy_probe, + .remove = fsl_samsung_hdmi_phy_remove, + .driver = { + .name = "fsl-samsung-hdmi-phy", + .of_match_table = fsl_samsung_hdmi_phy_of_match, + .pm = pm_ptr(&fsl_samsung_hdmi_phy_pm_ops), + }, +}; +module_platform_driver(fsl_samsung_hdmi_phy_driver); + +MODULE_AUTHOR("Sandor Yu "); +MODULE_DESCRIPTION("SAMSUNG HDMI 2.0 Transmitter PHY Driver"); +MODULE_LICENSE("GPL"); From patchwork Tue Feb 27 22:04:37 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Adam Ford X-Patchwork-Id: 13574484 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 458B1C54798 for ; Tue, 27 Feb 2024 22:05:21 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:MIME-Version:References:In-Reply-To: Message-ID:Date:Subject:Cc:To:From:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; bh=zJgKM5ce82ZTM9SiS9VGrSQy6Hn1AdQNuZrg1BSUeZk=; b=bPLeWNLrObg1Zd cbbSDQlPutZaYrxaZ+LZYY+sl0hQ399E4rBD6oqz0V8iyPz5ajOzN0b/MRpeeQk/dxxjxQjV5q6ix VuMOhqhnl8vOnzCIB/DkVWs4QRCMPhsfduYbD9zkxiST7NPlPzY79ImgPRJpYA0Umz37YSdX3PdrD Ft+JihmQ6TIG4g2JhEb9obci4iFDs5f5pdvUuWf71OrE5YvUYCwTWjC+9QbEvxrv3XgR1s1Jm3Z+A Zdo0I9yKHx2hhKrgYAl1MfaxsVc3Zh+6aWMYKEhaQMsqo6oY1Qipf1vKXqY1AjZqWHZ8PmYUdouI1 +LULf8pPKTYubEgYNnBw==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.97.1 #2 (Red Hat Linux)) id 1rf5Zg-000000070Zs-3WSV; Tue, 27 Feb 2024 22:05:20 +0000 Received: from mail-qv1-xf2a.google.com ([2607:f8b0:4864:20::f2a]) by bombadil.infradead.org with esmtps (Exim 4.97.1 #2 (Red Hat Linux)) id 1rf5ZT-000000070Rr-3DDV; Tue, 27 Feb 2024 22:05:09 +0000 Received: by mail-qv1-xf2a.google.com with SMTP id 6a1803df08f44-68f9e399c91so33261046d6.2; Tue, 27 Feb 2024 14:05:07 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20230601; t=1709071506; x=1709676306; darn=lists.infradead.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=zmbbJGMEJkVi0DIu9K/lMBZ7/vUErHSNsjKRRkfuNd4=; b=bEsYCuoXSGucLpSNmPIDWIkQrYuUJAd0N2YLeAn2Ee5v4we9y9Fro3SLnQKRq3TmCn toqBcrDSKAIyQbjB/wSO+y2VrBufvQYQ9F1rBaz3BEl1UeiBahQ5hoGwff9XbaRGXLwx GLly3zjgcj7RA61EqEanS1MJnZJwktBY4j35ddrwRLZKN7SjKEHmAO75VN9pqOPNLmDI 4hkNPhDUFt8gUTcycGEd8IvVdSqU3/5UzFWPGeJ7IiGHQ+bWaB1h2/3nS+9lmJUoHac3 blRh9dv9zwaWQgAp87ltxWd8dh3kSHis9/WrB6PXQ4htrzkZj0EcJKdflIsrHsYsfOUf NYAg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1709071506; x=1709676306; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=zmbbJGMEJkVi0DIu9K/lMBZ7/vUErHSNsjKRRkfuNd4=; b=AOgSrNSad1S5ig0M50U7jwJtfBinr8e1+uRCbH6TyJeHuFU0+RxyA2J+wx4uVfpfN0 ppTBf6AX607NVMt27ZV1S/Zm1CUjm0kzwlD3/sJ79u94dvE/O40EwlR/XJIDcbZ5FqfK fa6jPvT3F227wEomhIsAui8udt/sTJuZT5wENekDyLNpHMPZ0r7c2NDS+M+7JDb3a4kz VuaBD/ee51ZKrWCXGrEUbZTost/GwRgXoM09EaS38B2ts6KXHNbBx0ksij5gKuGUotZ4 G1AhXV9iYKuzGlp5w+EAH3NzOl5toV/mZi8uCkok3Pzn+5rty+KZz8ieHKGiWKx9dWtu v77A== X-Forwarded-Encrypted: i=1; AJvYcCWb8pBxvaY5MZxXFsNB0htB6mJBkw/7fR5B6TCtlKLYP3YADYQyMOua3Bk1NeUUTRLE+E2J94zLd4neXBCN2kqzYXWMOoDj8RsCo4d+jQ== X-Gm-Message-State: AOJu0YwQnOYvNqd63X/afuKDaV729ATCWd0qwIKZ9N1WYLBlfQsF7go+ E2QV1hoStpYwGI8KcDlA2gzynOKB0tJIVssCI1XmzFV6YFUXfc6Y7A6V9fbtWpxafYv+ X-Google-Smtp-Source: AGHT+IE6i0LWrYJlOlKNYdpd9Wfhikyo/roVvLACICkT0f6i3xk6KKObf+gk9jGM3IINovDqDgP+mg== X-Received: by 2002:a0c:cd07:0:b0:68f:d594:52d2 with SMTP id b7-20020a0ccd07000000b0068fd59452d2mr3267671qvm.0.1709071505915; Tue, 27 Feb 2024 14:05:05 -0800 (PST) Received: from aford-System-Version.lan ([2601:447:d002:5be:9ee3:b2ab:6ca:180d]) by smtp.gmail.com with ESMTPSA id c12-20020a0ce14c000000b0068fc55bcf6asm4569556qvl.119.2024.02.27.14.05.03 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 27 Feb 2024 14:05:05 -0800 (PST) From: Adam Ford To: linux-arm-kernel@lists.infradead.org, linux-phy@lists.infradead.org Cc: aford@beaconembedded.com, Lucas Stach , Adam Ford , Marek Vasut , Luca Ceresoli , Vinod Koul , Kishon Vijay Abraham I , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Shawn Guo , Sascha Hauer , Pengutronix Kernel Team , Fabio Estevam , Catalin Marinas , Will Deacon , devicetree@vger.kernel.org, imx@lists.linux.dev, linux-kernel@vger.kernel.org Subject: [PATCH V7 3/6] arm64: dts: imx8mp: add HDMI power-domains Date: Tue, 27 Feb 2024 16:04:37 -0600 Message-ID: <20240227220444.77566-4-aford173@gmail.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20240227220444.77566-1-aford173@gmail.com> References: <20240227220444.77566-1-aford173@gmail.com> MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20240227_140507_818947_C49848DD X-CRM114-Status: UNSURE ( 9.47 ) X-CRM114-Notice: Please train this message. X-BeenThere: linux-phy@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: Linux Phy Mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-phy" Errors-To: linux-phy-bounces+linux-phy=archiver.kernel.org@lists.infradead.org From: Lucas Stach This adds the PGC and HDMI blk-ctrl nodes providing power control for HDMI subsystem peripherals. Signed-off-by: Adam Ford Signed-off-by: Lucas Stach Tested-by: Marek Vasut Tested-by: Luca Ceresoli --- V6: No Change V5: No Change V4: No Change V3: The hdmi_blk_ctrl was in the wrong place, so move it to AIPS4. power-domains@ fixed to read power-domain@ V2: Add missing power-domains hdcp and hrv --- arch/arm64/boot/dts/freescale/imx8mp.dtsi | 38 +++++++++++++++++++++++ 1 file changed, 38 insertions(+) diff --git a/arch/arm64/boot/dts/freescale/imx8mp.dtsi b/arch/arm64/boot/dts/freescale/imx8mp.dtsi index bfc5c81a5bd4..c9bcb6641de7 100644 --- a/arch/arm64/boot/dts/freescale/imx8mp.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8mp.dtsi @@ -836,6 +836,23 @@ pgc_mediamix: power-domain@10 { <&clk IMX8MP_CLK_MEDIA_APB_ROOT>; }; + pgc_hdmimix: power-domain@14 { + #power-domain-cells = <0>; + reg = ; + clocks = <&clk IMX8MP_CLK_HDMI_ROOT>, + <&clk IMX8MP_CLK_HDMI_APB>; + assigned-clocks = <&clk IMX8MP_CLK_HDMI_AXI>, + <&clk IMX8MP_CLK_HDMI_APB>; + assigned-clock-parents = <&clk IMX8MP_SYS_PLL2_500M>, + <&clk IMX8MP_SYS_PLL1_133M>; + assigned-clock-rates = <500000000>, <133000000>; + }; + + pgc_hdmi_phy: power-domain@15 { + #power-domain-cells = <0>; + reg = ; + }; + pgc_mipi_phy2: power-domain@16 { #power-domain-cells = <0>; reg = ; @@ -1889,6 +1906,27 @@ hsio_blk_ctrl: blk-ctrl@32f10000 { #power-domain-cells = <1>; #clock-cells = <0>; }; + + hdmi_blk_ctrl: blk-ctrl@32fc0000 { + compatible = "fsl,imx8mp-hdmi-blk-ctrl", "syscon"; + reg = <0x32fc0000 0x1000>; + clocks = <&clk IMX8MP_CLK_HDMI_APB>, + <&clk IMX8MP_CLK_HDMI_ROOT>, + <&clk IMX8MP_CLK_HDMI_REF_266M>, + <&clk IMX8MP_CLK_HDMI_24M>, + <&clk IMX8MP_CLK_HDMI_FDCC_TST>; + clock-names = "apb", "axi", "ref_266m", "ref_24m", "fdcc"; + power-domains = <&pgc_hdmimix>, <&pgc_hdmimix>, + <&pgc_hdmimix>, <&pgc_hdmimix>, + <&pgc_hdmimix>, <&pgc_hdmimix>, + <&pgc_hdmimix>, <&pgc_hdmi_phy>, + <&pgc_hdmimix>, <&pgc_hdmimix>; + power-domain-names = "bus", "irqsteer", "lcdif", + "pai", "pvi", "trng", + "hdmi-tx", "hdmi-tx-phy", + "hdcp", "hrv"; + #power-domain-cells = <1>; + }; }; pcie: pcie@33800000 { From patchwork Tue Feb 27 22:04:38 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Adam Ford X-Patchwork-Id: 13574486 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 5BA97C54E4A for ; Tue, 27 Feb 2024 22:05:24 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:MIME-Version:References:In-Reply-To: Message-ID:Date:Subject:Cc:To:From:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; bh=g0hu+JTvONtqYYLnpVRRrMQIjWq3inuXgWgP/5xs7JQ=; b=QW+7c+9ibVW1Dl PQjCXCZclx36RYPLT6dS0jm0jPyTx/6dTxp+nf12uONp4tXUJ/ez+EC4cvvj5/RdOIBsw6JZOlV4v SrTxWOduCx+BgKL/ABxy4QAaubPQ48GjM/CQK3xUgCOLQGUC6ulgxtxIMNboxPAft2WH7Oh/oVL4i /B8a5Om7EVJ43cYIGIpViiuuADzocKo8dqM2q5kdv5bi82pIF37YsNip2j7YcA9khPVgBakRSVyXu dNnZJw8vyPmwz/SeJjmHBJaIzrJEsZydIrgV6iNw86L8Hmft6aBperltSm6lKbESumqNhbyk9BxaL fpM67i+xLVKqLQHHElNQ==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.97.1 #2 (Red Hat Linux)) id 1rf5Zj-000000070bg-2yey; Tue, 27 Feb 2024 22:05:23 +0000 Received: from mail-oo1-xc32.google.com ([2607:f8b0:4864:20::c32]) by bombadil.infradead.org with esmtps (Exim 4.97.1 #2 (Red Hat Linux)) id 1rf5ZW-000000070T0-0TgI; Tue, 27 Feb 2024 22:05:11 +0000 Received: by mail-oo1-xc32.google.com with SMTP id 006d021491bc7-5a0a9736535so743236eaf.3; Tue, 27 Feb 2024 14:05:09 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20230601; t=1709071508; x=1709676308; darn=lists.infradead.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=aFej3XRK1im9Jtb1YXeIJeL5LA98qLbzr4AabBMlz7o=; b=jthMvYG5OA2Zsd5cwUsRlYoiFkv8viEuuuTXaHrqi9aGWb9hftHbyKYBB+KP3s9Tzw IApAZBc9OwviAqX7DAzszpy//zs05vqg1lZyGyuwDeeKDIpk7JiOZJDsIIkY85GxLAiM lnjKP3agTyiAhQX33R7/5SFY0GJGInaVnfns1payYpukrOLGVT3Ii/Gak3OMMMKCrGFS O8G8TSUghyXD25u3HR/J9BOsGcfNve3DVxW2pUTYsAv4RAULIXh4wD76c64aMYzpeVPY pplEctZz5AearG10tS3HUdmK6U1raYVDR3mQp5UI47RK+YZGKSRHE6FIlMalDZHs7VxC YO/g== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1709071508; x=1709676308; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=aFej3XRK1im9Jtb1YXeIJeL5LA98qLbzr4AabBMlz7o=; b=hhUAift5RCNxqFZ8drBRKQqHVUix2kR2B3YNYkZCFmZ9E0SZNeVzmbi4UoH8oT4AjM j7CFxDiUCCaVz13wELzcsSsBr9tWkoUJHZ0csb8N0EeHZjP6ZF4izuigcyrdsPJxHU7a 330ERoR1+vRN5osr31DZhf+bHslQrbKNqh7xTmpPQsZ+JfNVvv1Uc0MONlSgAAKPFjAl VNXW+hqZgBDTbptPuS6rISf+M9aI6v8gzN2SfU+KmS77pwqzCY1HwNtN/bpMSoiuN15D EwKYVlt9+7OhdypprBbaPUqjp21PMhHSiJ7bat6/M756Nk1/gXBQ2snjTooij3C7NNwJ V16g== X-Forwarded-Encrypted: i=1; AJvYcCWxyNtD8tJwoZrRSkh3Qt/RM2zhKY/P+9Lk17YmgRzOUDKNuBGkggvIuK7lHjQqucFyWMXSTSX3zct2zRZIY7yj+YmF1v/o33AcGuPhZw== X-Gm-Message-State: AOJu0YwlJS/uVAG/Fo9ETQV6xm2/Vutns9IsPeoxCwCE0wgG9fN6mOW7 hFLs/T88e5Auz6JTUukhE/rYSgDPZhIH1QzayrnpNq5d89d06KhavbzshJI5P3X8ECkS X-Google-Smtp-Source: AGHT+IGWgaFRlZ2IfQsw+GCY/j+lRL8LaS2tBzQxUKTZJT76SVV2NR6kEFyuRlrSS1jgmD6sVOd+Rw== X-Received: by 2002:a05:6358:94a2:b0:17b:521f:b2ae with SMTP id i34-20020a05635894a200b0017b521fb2aemr15918125rwb.14.1709071508117; Tue, 27 Feb 2024 14:05:08 -0800 (PST) Received: from aford-System-Version.lan ([2601:447:d002:5be:9ee3:b2ab:6ca:180d]) by smtp.gmail.com with ESMTPSA id c12-20020a0ce14c000000b0068fc55bcf6asm4569556qvl.119.2024.02.27.14.05.06 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 27 Feb 2024 14:05:07 -0800 (PST) From: Adam Ford To: linux-arm-kernel@lists.infradead.org, linux-phy@lists.infradead.org Cc: aford@beaconembedded.com, Lucas Stach , Adam Ford , Marek Vasut , Luca Ceresoli , Vinod Koul , Kishon Vijay Abraham I , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Shawn Guo , Sascha Hauer , Pengutronix Kernel Team , Fabio Estevam , Catalin Marinas , Will Deacon , devicetree@vger.kernel.org, imx@lists.linux.dev, linux-kernel@vger.kernel.org Subject: [PATCH V7 4/6] arm64: dts: imx8mp: add HDMI irqsteer Date: Tue, 27 Feb 2024 16:04:38 -0600 Message-ID: <20240227220444.77566-5-aford173@gmail.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20240227220444.77566-1-aford173@gmail.com> References: <20240227220444.77566-1-aford173@gmail.com> MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20240227_140510_190096_D5E0A918 X-CRM114-Status: GOOD ( 10.01 ) X-BeenThere: linux-phy@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: Linux Phy Mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-phy" Errors-To: linux-phy-bounces+linux-phy=archiver.kernel.org@lists.infradead.org From: Lucas Stach The HDMI irqsteer is a secondary interrupt controller within the HDMI subsystem that maps all HDMI peripheral IRQs into a single upstream IRQ line. Signed-off-by: Lucas Stach Signed-off-by: Adam Ford Tested-by: Marek Vasut Tested-by: Luca Ceresoli --- V6: No Change V5: Increase size to 4KB to match the ref manual V2: Add my (Adam) s-o-b and re-order position under AIPS4 --- arch/arm64/boot/dts/freescale/imx8mp.dtsi | 13 +++++++++++++ 1 file changed, 13 insertions(+) diff --git a/arch/arm64/boot/dts/freescale/imx8mp.dtsi b/arch/arm64/boot/dts/freescale/imx8mp.dtsi index c9bcb6641de7..18bfa7d9aa7f 100644 --- a/arch/arm64/boot/dts/freescale/imx8mp.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8mp.dtsi @@ -1927,6 +1927,19 @@ hdmi_blk_ctrl: blk-ctrl@32fc0000 { "hdcp", "hrv"; #power-domain-cells = <1>; }; + + irqsteer_hdmi: interrupt-controller@32fc2000 { + compatible = "fsl,imx-irqsteer"; + reg = <0x32fc2000 0x1000>; + interrupts = ; + interrupt-controller; + #interrupt-cells = <1>; + fsl,channel = <1>; + fsl,num-irqs = <64>; + clocks = <&clk IMX8MP_CLK_HDMI_APB>; + clock-names = "ipg"; + power-domains = <&hdmi_blk_ctrl IMX8MP_HDMIBLK_PD_IRQSTEER>; + }; }; pcie: pcie@33800000 { From patchwork Tue Feb 27 22:04:39 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Adam Ford X-Patchwork-Id: 13574487 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 62AFCC5478C for ; Tue, 27 Feb 2024 22:05:28 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:MIME-Version:References:In-Reply-To: Message-ID:Date:Subject:Cc:To:From:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; bh=2HV+hYpgarjhiI26ipYlt4+Ttg+q4i+sRkD7Rxztq0Y=; b=JVLh851o+ezPdC GgBE14mYIsQi/JzIc0zg9o0ESYAK+Bk8ZkC+i3mOHQ3uOGUGkXgZjld1gun+2YYEo9k72tdJd+Gq/ qb9ram/Vx+VZ+rBCGqYz2w8RtiuegTNIYuccTDGZ83ooTYS6vBijfw2Zxw5KC0p9DDz+bwHE8NPPc dsBQld7rzMZC8VPA/9RWBV1IK5ChaJde9Zn+ttoMOxiKrHZwLKpF3oSL6hQiOTXCLl/ys5BJqnLNU jZNOo5kzG3hm4qPFLumW0bkCcQ3Udv5m+0/EToo86FM1/5HuamOzzatdwJ1nCVbgokayNCn090KQb kW2nKcZztvXhftgFHiYw==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.97.1 #2 (Red Hat Linux)) id 1rf5Zm-000000070dH-2st9; Tue, 27 Feb 2024 22:05:26 +0000 Received: from mail-qk1-x729.google.com ([2607:f8b0:4864:20::729]) by bombadil.infradead.org with esmtps (Exim 4.97.1 #2 (Red Hat Linux)) id 1rf5ZZ-000000070Ua-2G4s; Tue, 27 Feb 2024 22:05:15 +0000 Received: by mail-qk1-x729.google.com with SMTP id af79cd13be357-787bc61cb69so319662885a.1; Tue, 27 Feb 2024 14:05:12 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20230601; t=1709071510; x=1709676310; darn=lists.infradead.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=xJzAJwTasiu7hDw+tfGL3rBgM8LrL2gpliyFRMRT1lo=; b=SAh5O6phlu9/Nu9ChHut4qx4pmDlyd/IpO3J2N3U3bAd7rPiHWCTVyz6l4c+MOqqXy tqHRoqAGZNvwvH/6khKjkVXQzA2ijLeJt7DUl7IA34CabNbBoSu3P6kGgudyKsoc3gV+ AX5kZfW0R7e/nXFSVp9qQ4wwAPKFkyxiuQ2EJHcvup8GHQFVGtno6XDVnxcNe93eBSo2 4DvoVmlrPx+tv/1UuOZletxFETyMEJ4OTAUneiHDu2SwyObIrI7XPDXWRKJbvRdG0vLH nzXWBxVL+ajOGzT8BWOQ8v1SkHnoN1CXsmdJ1lekSsi1wJh9WO4M9LdMrwuKgPdKydpr DZIA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1709071510; x=1709676310; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=xJzAJwTasiu7hDw+tfGL3rBgM8LrL2gpliyFRMRT1lo=; b=Z+yNhDsQsKyJnN8ylXAzQpR0ouOK4udYx5hKN8vr7wC6N4ulMaEQDXVPBwtQNNN9L/ TaLvh+nGtSIOIM+Vmo2yilaWQzyQDNupwyx+pYTemjBlr7lNqMUQ8F/447bzXv6SnpGp 5yI1fZsY36fZ6NlKLMceF7nCQtuHVHBLGUzQB8ED+CQKVOXxFKbTxKbIirK4GKc2L9iR t4I8MWDDxX14JJVo6ZUC1Rq46Ui8aNkWdyUKQDwhCOLkno3KYXWzgaMiHH5ybzgRODN5 yIkkAz1Janek5q2EMmtzAfiS6/MP6VGY+3pudgUdNRyKh+o6WJ8LiWSptuEkgLXytZjM s9qw== X-Forwarded-Encrypted: i=1; AJvYcCUHWWQ15MTdKOzXlRXCchZYQCQST1DsUmFoa5IthhM74ew/F7m3+HIK0hIX5uhwwE4/boUn6B2TSstPDy54JykhJcMDfwJ/PHZUAsrXkQ== X-Gm-Message-State: AOJu0YymRrWkGvVMggGnNO0S04cCp/suL4qyL6kjCblO/vt1WMdnPZyp rH/WpEY00eVKaC9BGOuzVqOkJkmg5U/464efzDD+JJJcrBaylaPkYvVO9dtSMm3haAxr X-Google-Smtp-Source: AGHT+IGThGbZu2ZzIC/n4MZYA5OnZJb7hsEPXN8KiMr5hmglfpCIMmZO1Irlp/eAHem49FGv4ww+5A== X-Received: by 2002:a0c:e2c1:0:b0:68f:3126:a395 with SMTP id t1-20020a0ce2c1000000b0068f3126a395mr3046408qvl.31.1709071510382; Tue, 27 Feb 2024 14:05:10 -0800 (PST) Received: from aford-System-Version.lan ([2601:447:d002:5be:9ee3:b2ab:6ca:180d]) by smtp.gmail.com with ESMTPSA id c12-20020a0ce14c000000b0068fc55bcf6asm4569556qvl.119.2024.02.27.14.05.08 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 27 Feb 2024 14:05:10 -0800 (PST) From: Adam Ford To: linux-arm-kernel@lists.infradead.org, linux-phy@lists.infradead.org Cc: aford@beaconembedded.com, Lucas Stach , Adam Ford , Marek Vasut , Luca Ceresoli , Vinod Koul , Kishon Vijay Abraham I , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Shawn Guo , Sascha Hauer , Pengutronix Kernel Team , Fabio Estevam , Catalin Marinas , Will Deacon , devicetree@vger.kernel.org, imx@lists.linux.dev, linux-kernel@vger.kernel.org Subject: [PATCH V7 5/6] arm64: dts: imx8mp: add HDMI display pipeline Date: Tue, 27 Feb 2024 16:04:39 -0600 Message-ID: <20240227220444.77566-6-aford173@gmail.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20240227220444.77566-1-aford173@gmail.com> References: <20240227220444.77566-1-aford173@gmail.com> MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20240227_140513_628272_4F65F031 X-CRM114-Status: GOOD ( 11.73 ) X-BeenThere: linux-phy@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: Linux Phy Mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-phy" Errors-To: linux-phy-bounces+linux-phy=archiver.kernel.org@lists.infradead.org From: Lucas Stach This adds the DT nodes for all the peripherals that make up the HDMI display pipeline. Signed-off-by: Lucas Stach Signed-off-by: Adam Ford Tested-by: Marek Vasut Tested-by: Luca Ceresoli Reviewed-by: Luca Ceresoli --- V7: Make PVI node disabled by default to avoid EPROBE_DEFER V6: Make LCDIF3 disabled by default V5: No change V3: Re-ordered the HDMI parts to properly come after irqstree_hdmi inside AIPS4. Change size of LCDIF3 and PVI to match TRM sizes of 4KB. V2: I took this from Lucas' original submission with the following: Removed extra clock from HDMI-TX since it is now part of the power domain Added interrupt-parent to PVI Changed the name of the HDMI tranmitter to fsl,imx8mp-hdmi-tx Added ports to HDMI-tx --- arch/arm64/boot/dts/freescale/imx8mp.dtsi | 96 +++++++++++++++++++++++ 1 file changed, 96 insertions(+) diff --git a/arch/arm64/boot/dts/freescale/imx8mp.dtsi b/arch/arm64/boot/dts/freescale/imx8mp.dtsi index 18bfa7d9aa7f..e3510fef6030 100644 --- a/arch/arm64/boot/dts/freescale/imx8mp.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8mp.dtsi @@ -1940,6 +1940,102 @@ irqsteer_hdmi: interrupt-controller@32fc2000 { clock-names = "ipg"; power-domains = <&hdmi_blk_ctrl IMX8MP_HDMIBLK_PD_IRQSTEER>; }; + + hdmi_pvi: display-bridge@32fc4000 { + compatible = "fsl,imx8mp-hdmi-pvi"; + reg = <0x32fc4000 0x1000>; + interrupt-parent = <&irqsteer_hdmi>; + interrupts = <12>; + power-domains = <&hdmi_blk_ctrl IMX8MP_HDMIBLK_PD_PVI>; + status = "disabled"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + pvi_from_lcdif3: endpoint { + remote-endpoint = <&lcdif3_to_pvi>; + }; + }; + + port@1 { + reg = <1>; + pvi_to_hdmi_tx: endpoint { + remote-endpoint = <&hdmi_tx_from_pvi>; + }; + }; + }; + }; + + lcdif3: display-controller@32fc6000 { + compatible = "fsl,imx8mp-lcdif"; + reg = <0x32fc6000 0x1000>; + interrupt-parent = <&irqsteer_hdmi>; + interrupts = <8>; + clocks = <&hdmi_tx_phy>, + <&clk IMX8MP_CLK_HDMI_APB>, + <&clk IMX8MP_CLK_HDMI_ROOT>; + clock-names = "pix", "axi", "disp_axi"; + power-domains = <&hdmi_blk_ctrl IMX8MP_HDMIBLK_PD_LCDIF>; + status = "disabled"; + + port { + lcdif3_to_pvi: endpoint { + remote-endpoint = <&pvi_from_lcdif3>; + }; + }; + }; + + hdmi_tx: hdmi@32fd8000 { + compatible = "fsl,imx8mp-hdmi-tx"; + reg = <0x32fd8000 0x7eff>; + interrupt-parent = <&irqsteer_hdmi>; + interrupts = <0>; + clocks = <&clk IMX8MP_CLK_HDMI_APB>, + <&clk IMX8MP_CLK_HDMI_REF_266M>, + <&clk IMX8MP_CLK_32K>, + <&hdmi_tx_phy>; + clock-names = "iahb", "isfr", "cec", "pix"; + assigned-clocks = <&clk IMX8MP_CLK_HDMI_REF_266M>; + assigned-clock-parents = <&clk IMX8MP_SYS_PLL1_266M>; + power-domains = <&hdmi_blk_ctrl IMX8MP_HDMIBLK_PD_HDMI_TX>; + reg-io-width = <1>; + status = "disabled"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + hdmi_tx_from_pvi: endpoint { + remote-endpoint = <&pvi_to_hdmi_tx>; + }; + }; + + port@1 { + reg = <1>; + /* Point endpoint to the HDMI connector */ + }; + }; + }; + + hdmi_tx_phy: phy@32fdff00 { + compatible = "fsl,imx8mp-hdmi-phy"; + reg = <0x32fdff00 0x100>; + clocks = <&clk IMX8MP_CLK_HDMI_APB>, + <&clk IMX8MP_CLK_HDMI_24M>; + clock-names = "apb", "ref"; + assigned-clocks = <&clk IMX8MP_CLK_HDMI_24M>; + assigned-clock-parents = <&clk IMX8MP_CLK_24M>; + power-domains = <&hdmi_blk_ctrl IMX8MP_HDMIBLK_PD_HDMI_TX_PHY>; + #clock-cells = <0>; + #phy-cells = <0>; + status = "disabled"; + }; }; pcie: pcie@33800000 { From patchwork Tue Feb 27 22:04:40 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Adam Ford X-Patchwork-Id: 13574488 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 7B980C54798 for ; Tue, 27 Feb 2024 22:05:41 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:MIME-Version:References:In-Reply-To: Message-ID:Date:Subject:Cc:To:From:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; bh=T8Uw7uCPJNfU9Hf05/VfHe4CCuqA8LAv+Nwnr91xFpM=; b=QqQWKko/0NlQah T+CS8l45lIGx1EBLqys6qNO+1xIRzTRBLSgcj03xk5CEqWsnMSEaS4LiaDRvNuOg9gCf51WfXVjWo 9/hxx7ihBjTHruovWEc0ccaVlPCesCjwvtrEJ44yBfpW2qM7AwSZiOVtp7/dfB6UzH/cwM12HF2np RH7NrrMV2hrUDYdrCbPJJxKl5jgepClKbwUvAo47QbdC7maGb/7PQrSmlQchCTqAs8TtWGtdSb0ce AlHjdc+2ewLspFyeMwZzcb4Uh7r8ZHphNScY/Ajz5SPjQ7XXhKnsb3Y8ZDhbZ+hYQkuNvH2s3CXCg /XjKZmM2CTwRzSyKHnCQ==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.97.1 #2 (Red Hat Linux)) id 1rf5a0-000000070lw-3HTV; Tue, 27 Feb 2024 22:05:40 +0000 Received: from mail-oi1-x233.google.com ([2607:f8b0:4864:20::233]) by bombadil.infradead.org with esmtps (Exim 4.97.1 #2 (Red Hat Linux)) id 1rf5Za-000000070Uq-0xpT; Tue, 27 Feb 2024 22:05:17 +0000 Received: by mail-oi1-x233.google.com with SMTP id 5614622812f47-3c17ac08a38so2223441b6e.1; Tue, 27 Feb 2024 14:05:13 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20230601; t=1709071512; x=1709676312; darn=lists.infradead.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=Pg+umx5FUIJdMs3diOaBF+zl4OepmD7HnZ+prHeGKsA=; b=mDeaWdHAqzfNt5Wy8kA0iCYq7dpBIGGWc55k3aZdpceBmBKViHlAezgCOAqqxRnid/ E2FtCl/PuDGeyVnlFfgVrOZZB2NRmTUrPmqTZ7U6oK7lsqH8fZiTHzQa/HIS6X1dJ+/x IzUheVfmFd1n6sSlvrjHo5k82lnMmKS3/RVRpvgFxj8IOdZLJDXNG4r2key52DUhuElI rv9r93vCoq711Xm1m/BXAVVjZ00QVbvmimMuJewvYFoZxJ9nskyEXeJRGue+tp/jlKGC nvgXU2pYq+D00KabVpVyowDIYsmFzf0g9ByZ7+U+hJ1ktog8oBCjvtQy570Dm1vvnGay Z8bw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1709071512; x=1709676312; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=Pg+umx5FUIJdMs3diOaBF+zl4OepmD7HnZ+prHeGKsA=; b=CcACEfzEv5sXWTBf3V/G/S4Z5hDRt8jlQpPUXSdmv0/5lUAeQhz+4pyW6w5Idy9GlN 8FK8z2gL+eeZX8AIl/qhdxkQTNTZXFJxDZ5SQ3H1ZwO42TTvjMDQm45AKrcICUQSDu2N JFcepxcVzB/Qh011hHeEWgRFf2sQmqCkhWWYWnwZpSyBnTRoQF1iKvlvbn9JFVrtroJc W0ueKKu9CZpyypocNFS00w0dKwS1MNa1TxnuGaNV8mLOFiTqz86DB333MU6RsTTwnAWB vy2nN8mF3AKN+hiw7kzacZ8sa3aTAkgJMOGQhCCOqB5YSuXobaxJBlOer8Tssfs25hkb myow== X-Forwarded-Encrypted: i=1; AJvYcCWX8E354YjKFngVDfwn2rO+61DDV5YNGix0OIB3eYjhhtjFEbkd+DpvdVWZqVwDtSL+hHOv1uU31bOYKNn1s5mFoJOZf8ZxT/Tkq5s1CA== X-Gm-Message-State: AOJu0YzAIPvNHCx481auHDaPXGuyJ/1QJIzRq5yep2/BOr1dqz4Zk1OP 5K+8x1EMbdvGKJoodOnqJTFNOEUIVenO2V6lgRJuJkMZe7hE1XZb0Fk98OJCVXmj+Njo X-Google-Smtp-Source: AGHT+IEmWreknrcyf09k6m1PvVcfqFMnpM75hkf6hTSSVFVvDaq/6FD0SFqz9UMfV4yL5nvUNAshIA== X-Received: by 2002:a05:6358:9496:b0:17b:57c9:dddc with SMTP id i22-20020a056358949600b0017b57c9dddcmr8981848rwb.5.1709071512522; Tue, 27 Feb 2024 14:05:12 -0800 (PST) Received: from aford-System-Version.lan ([2601:447:d002:5be:9ee3:b2ab:6ca:180d]) by smtp.gmail.com with ESMTPSA id c12-20020a0ce14c000000b0068fc55bcf6asm4569556qvl.119.2024.02.27.14.05.11 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 27 Feb 2024 14:05:12 -0800 (PST) From: Adam Ford To: linux-arm-kernel@lists.infradead.org, linux-phy@lists.infradead.org Cc: aford@beaconembedded.com, Adam Ford , Luca Ceresoli , Vinod Koul , Kishon Vijay Abraham I , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Shawn Guo , Sascha Hauer , Pengutronix Kernel Team , Fabio Estevam , Catalin Marinas , Will Deacon , Lucas Stach , devicetree@vger.kernel.org, imx@lists.linux.dev, linux-kernel@vger.kernel.org Subject: [PATCH V7 6/6] arm64: defconfig: Enable DRM_IMX8MP_DW_HDMI_BRIDGE as module Date: Tue, 27 Feb 2024 16:04:40 -0600 Message-ID: <20240227220444.77566-7-aford173@gmail.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20240227220444.77566-1-aford173@gmail.com> References: <20240227220444.77566-1-aford173@gmail.com> MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20240227_140514_423963_90A348D6 X-CRM114-Status: UNSURE ( 8.29 ) X-CRM114-Notice: Please train this message. X-BeenThere: linux-phy@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: Linux Phy Mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-phy" Errors-To: linux-phy-bounces+linux-phy=archiver.kernel.org@lists.infradead.org The i.MX8M Plus has support for an HDMI transmitter. The video is genereated by lcdif3, routed to the hdmi parallel video interface, then fed to a DW HDMI bridge to support up to 4K video output. Signed-off-by: Adam Ford Reviewed-by: Luca Ceresoli Tested-by: Luca Ceresoli --- V7: No Change V6: No Change V5: Added Review and tested-by from Luca No functional change since V1 --- arch/arm64/configs/defconfig | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/arm64/configs/defconfig b/arch/arm64/configs/defconfig index 34681284043f..ee644d27652b 100644 --- a/arch/arm64/configs/defconfig +++ b/arch/arm64/configs/defconfig @@ -887,6 +887,7 @@ CONFIG_DRM_ANALOGIX_ANX7625=m CONFIG_DRM_I2C_ADV7511=m CONFIG_DRM_I2C_ADV7511_AUDIO=y CONFIG_DRM_CDNS_MHDP8546=m +CONFIG_DRM_IMX8MP_DW_HDMI_BRIDGE=m CONFIG_DRM_DW_HDMI_AHB_AUDIO=m CONFIG_DRM_DW_HDMI_CEC=m CONFIG_DRM_IMX_DCSS=m