From patchwork Fri Mar 1 15:34:58 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Romain Gantois X-Patchwork-Id: 13578616 X-Patchwork-Delegate: geert@linux-m68k.org Received: from relay8-d.mail.gandi.net (relay8-d.mail.gandi.net [217.70.183.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 7487A6EB6B; Fri, 1 Mar 2024 15:34:46 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=217.70.183.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1709307290; cv=none; b=cmqtYRjZ1cpZm65v1BJ+ZbNixYSJTR4j8h8SfDmu+1cTet25rkcoQlyA5ocHitLfqpa+szKA6qILW4uS6NjWAxN+r5Xub02NE1fVZugaSdkAqDaofe4tsiHmsf3pDuVgSEaHXu1V8hiAP689lJwnWMk6velzJhov/Md0ORM1sfE= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1709307290; c=relaxed/simple; bh=JJ7prHPsvHOxcpBUnX65Yp9J9O0AMUYus6T7dhtEC3I=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=HlFNhF3n5xKJYz3KmFAKLbNWf9BBcpMFY6k4CM12rPk05nwdJEaDIpqM7U/e3UF4TXjnMP3pIhlRjrnu7O0Lu3JY75iK7xjIWGtOdG0yVUrENp9K6h5g88LT6o+iYOknHar8IpYbT6HCkmb0l0aWtrWBLTPGQw8jheGbgnrYl1M= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=bootlin.com; spf=pass smtp.mailfrom=bootlin.com; dkim=pass (2048-bit key) header.d=bootlin.com header.i=@bootlin.com header.b=HPgIVOfY; arc=none smtp.client-ip=217.70.183.201 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=bootlin.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=bootlin.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=bootlin.com header.i=@bootlin.com header.b="HPgIVOfY" Received: by mail.gandi.net (Postfix) with ESMTPSA id 119FF1BF20C; Fri, 1 Mar 2024 15:34:38 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=bootlin.com; s=gm1; t=1709307279; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=jB0iWjGthfzsVcriozHtuEk4mZbdKYk3iEvIV12HSYs=; b=HPgIVOfYhCqJoluelOgSGaToRmX7qF7F/QLnEJK3Gd5R0LmVAUQ+weCSuCfoFLmq8si0hI VcaXTLgPp8HwVeQ/Txqmv4kvWkK716ksybCzXno+HZEwMYZntYIsZ3p5upoPUcAv6aytTs kAzzJV/960xtRNiYL+IFo6+zenkHjnGpm5f0NFj2IlwNJlQeq/zsoCYyK+jC5mBABqytF1 JZQ9Bk6LzJKsJlJrOFjxipJFgtl4N3KopixQoUjFDtCtlOuo3JuAbZZSymFpmyjqo0uSzA q89+L/IjTfHSYvtlHfhVs4rzI+QOSX6+Il3XmumY637AC6iRiJvN08FWWaOc3Q== From: Romain Gantois Date: Fri, 01 Mar 2024 16:34:58 +0100 Subject: [PATCH net-next v5 1/7] net: phylink: add PHY_F_RXC_ALWAYS_ON to PHY dev flags Precedence: bulk X-Mailing-List: linux-renesas-soc@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-Id: <20240301-rxc_bugfix-v5-1-8dac30230050@bootlin.com> References: <20240301-rxc_bugfix-v5-0-8dac30230050@bootlin.com> In-Reply-To: <20240301-rxc_bugfix-v5-0-8dac30230050@bootlin.com> To: Russell King , Andrew Lunn , Heiner Kallweit , "David S. Miller" , Eric Dumazet , Jakub Kicinski , Paolo Abeni , Alexandre Torgue , Jose Abreu , Maxime Coquelin , =?utf-8?b?Q2zDqW1lbnQgTMOp?= =?utf-8?b?Z2Vy?= Cc: Maxime Chevallier , Miquel Raynal , Thomas Petazzoni , netdev@vger.kernel.org, linux-stm32@st-md-mailman.stormreply.com, linux-arm-kernel@lists.infradead.org, linux-renesas-soc@vger.kernel.org, Romain Gantois X-Mailer: b4 0.13.0 X-GND-Sasl: romain.gantois@bootlin.com From: Russell King Some MAC controllers (e.g. stmmac) require their connected PHY to continuously provide a receive clock signal. This can cause issues in two cases: 1. The clock signal hasn't been started yet by the time the MAC driver initializes its hardware. This can make the initialization fail, as in the case of the rzn1 GMAC1 driver. 2. The clock signal is cut during a power saving event. By the time the MAC is brought back up, the clock signal is still not active since phylink_start hasn't been called yet. This brings us back to case 1. If a PHY driver reads this flag, it should ensure that the receive clock signal is started as soon as possible, and that it isn't brought down when the PHY goes into suspend. Signed-off-by: Russell King [rgantois: commit log] Signed-off-by: Romain Gantois Reviewed-by: Andrew Lunn --- drivers/net/phy/phylink.c | 10 +++++++++- include/linux/phy.h | 1 + include/linux/phylink.h | 4 ++++ 3 files changed, 14 insertions(+), 1 deletion(-) diff --git a/drivers/net/phy/phylink.c b/drivers/net/phy/phylink.c index 503fd7c40523..2bb583543dea 100644 --- a/drivers/net/phy/phylink.c +++ b/drivers/net/phy/phylink.c @@ -1923,6 +1923,8 @@ static int phylink_bringup_phy(struct phylink *pl, struct phy_device *phy, static int phylink_attach_phy(struct phylink *pl, struct phy_device *phy, phy_interface_t interface) { + u32 flags = 0; + if (WARN_ON(pl->cfg_link_an_mode == MLO_AN_FIXED || (pl->cfg_link_an_mode == MLO_AN_INBAND && phy_interface_mode_is_8023z(interface) && !pl->sfp_bus))) @@ -1931,7 +1933,10 @@ static int phylink_attach_phy(struct phylink *pl, struct phy_device *phy, if (pl->phydev) return -EBUSY; - return phy_attach_direct(pl->netdev, phy, 0, interface); + if (pl->config->mac_requires_rxc) + flags |= PHY_F_RXC_ALWAYS_ON; + + return phy_attach_direct(pl->netdev, phy, flags, interface); } /** @@ -2034,6 +2039,9 @@ int phylink_fwnode_phy_connect(struct phylink *pl, pl->link_config.interface = pl->link_interface; } + if (pl->config->mac_requires_rxc) + flags |= PHY_F_RXC_ALWAYS_ON; + ret = phy_attach_direct(pl->netdev, phy_dev, flags, pl->link_interface); phy_device_free(phy_dev); diff --git a/include/linux/phy.h b/include/linux/phy.h index e3ab2c347a59..89aff9224c4d 100644 --- a/include/linux/phy.h +++ b/include/linux/phy.h @@ -773,6 +773,7 @@ struct phy_device { /* Generic phy_device::dev_flags */ #define PHY_F_NO_IRQ 0x80000000 +#define PHY_F_RXC_ALWAYS_ON 0x40000000 static inline struct phy_device *to_phy_device(const struct device *dev) { diff --git a/include/linux/phylink.h b/include/linux/phylink.h index 6ba411732a0d..019993e5f570 100644 --- a/include/linux/phylink.h +++ b/include/linux/phylink.h @@ -138,6 +138,9 @@ enum phylink_op_type { * @poll_fixed_state: if true, starts link_poll, * if MAC link is at %MLO_AN_FIXED mode. * @mac_managed_pm: if true, indicate the MAC driver is responsible for PHY PM. + * @mac_requires_rxc: if true, the MAC always requires a receive clock from PHY. + * The PHY driver should start the clock signal as soon as + * possible and avoid stopping it during suspend events. * @ovr_an_inband: if true, override PCS to MLO_AN_INBAND * @get_fixed_state: callback to execute to determine the fixed link state, * if MAC link is at %MLO_AN_FIXED mode. @@ -150,6 +153,7 @@ struct phylink_config { enum phylink_op_type type; bool poll_fixed_state; bool mac_managed_pm; + bool mac_requires_rxc; bool ovr_an_inband; void (*get_fixed_state)(struct phylink_config *config, struct phylink_link_state *state); From patchwork Fri Mar 1 15:34:59 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Romain Gantois X-Patchwork-Id: 13578617 X-Patchwork-Delegate: geert@linux-m68k.org Received: from relay8-d.mail.gandi.net (relay8-d.mail.gandi.net [217.70.183.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id D500D6EF1F; Fri, 1 Mar 2024 15:34:47 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=217.70.183.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1709307290; cv=none; b=WqByLFfjaLwN/j2zOiOQEAZ30hoZuGkKZDITZS4NMzb1g7PtqYAwdn2bgaOUsDrhm1BaTGpY7RifrU+Sk70bGrjXA2wqd1X9ZB1JIsD6d/chTRBkmlF4rPGPujKlLH1vAvgJ3wPhp8SXxF7wTjui0Nu7AhPYu0k4A2S3GAejiL8= ARC-Message-Signature: i=1; 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Fri, 1 Mar 2024 15:34:39 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=bootlin.com; s=gm1; t=1709307280; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=BOlVZRvA1sejqI/cIvDUpaF2K3iClU462Pusbn87bfw=; b=csJgrNtVoqlvbf3CNfJVXEwObhTzr0RTiQFHy83SdxK8tSZvAv7OumXIhjc8ff+koLXsp+ wSv57z1I6iXGMBt4Z5XMfQ0FBby4uzeSxevee1Tdv2hPR0PFTyGeMgUrKOnJzlZvWDJcmB BXX04WmiZzqM5fhL2e7vc3og2qSO4B8Y6bGmCzQzwCf84PRXxPsaG8zqdBybKA/dYhpFeG UzjL7Oky6rUJVAeI/VnmzJMUmXM3HCZngGfH6sNEyiqWCZzA7Au+5CyHvnCLb2LSg/v8b9 6952j/65JwQNWvaBnR9RmFA2fvC+uuEDvTX55RgfQ9H34sYl7KHHjVbsWKO84g== From: Romain Gantois Date: Fri, 01 Mar 2024 16:34:59 +0100 Subject: [PATCH net-next v5 2/7] net: phylink: add rxc_always_on flag to phylink_pcs Precedence: bulk X-Mailing-List: linux-renesas-soc@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-Id: <20240301-rxc_bugfix-v5-2-8dac30230050@bootlin.com> References: <20240301-rxc_bugfix-v5-0-8dac30230050@bootlin.com> In-Reply-To: <20240301-rxc_bugfix-v5-0-8dac30230050@bootlin.com> To: Russell King , Andrew Lunn , Heiner Kallweit , "David S. Miller" , Eric Dumazet , Jakub Kicinski , Paolo Abeni , Alexandre Torgue , Jose Abreu , Maxime Coquelin , =?utf-8?b?Q2zDqW1lbnQgTMOp?= =?utf-8?b?Z2Vy?= Cc: Maxime Chevallier , Miquel Raynal , Thomas Petazzoni , netdev@vger.kernel.org, linux-stm32@st-md-mailman.stormreply.com, linux-arm-kernel@lists.infradead.org, linux-renesas-soc@vger.kernel.org, Romain Gantois X-Mailer: b4 0.13.0 X-GND-Sasl: romain.gantois@bootlin.com Some MAC drivers (e.g. stmmac) require a continuous receive clock signal to be generated by a PCS that is handled by a standalone PCS driver. Such a PCS driver does not have access to a PHY device, thus cannot check the PHY_F_RXC_ALWAYS_ON flag. They cannot check max_requires_rxc in the phylink config either, since it is a private member. Therefore, a new flag is needed to signal to the PCS that it should keep the RX clock signal up at all times. Suggested-by: Russell King Signed-off-by: Romain Gantois Reviewed-by: Andrew Lunn --- drivers/net/phy/phylink.c | 15 +++++++++++++++ include/linux/phylink.h | 38 ++++++++++++++++++++++++++++++++++++++ 2 files changed, 53 insertions(+) diff --git a/drivers/net/phy/phylink.c b/drivers/net/phy/phylink.c index 2bb583543dea..84a97088dfc6 100644 --- a/drivers/net/phy/phylink.c +++ b/drivers/net/phy/phylink.c @@ -1042,6 +1042,21 @@ static void phylink_pcs_poll_start(struct phylink *pl) mod_timer(&pl->link_poll, jiffies + HZ); } +int phylink_pcs_pre_init(struct phylink *pl, struct phylink_pcs *pcs) +{ + int ret = 0; + + /* Signal to PCS driver that MAC requires RX clock for init */ + if (pl->config->mac_requires_rxc) + pcs->rxc_always_on = true; + + if (pcs->ops->pcs_pre_init) + ret = pcs->ops->pcs_pre_init(pcs); + + return ret; +} +EXPORT_SYMBOL_GPL(phylink_pcs_pre_init); + static void phylink_mac_config(struct phylink *pl, const struct phylink_link_state *state) { diff --git a/include/linux/phylink.h b/include/linux/phylink.h index 019993e5f570..0bb826bf73c0 100644 --- a/include/linux/phylink.h +++ b/include/linux/phylink.h @@ -396,6 +396,10 @@ struct phylink_pcs_ops; * @phylink: pointer to &struct phylink_config * @neg_mode: provide PCS neg mode via "mode" argument * @poll: poll the PCS for link changes + * @rxc_always_on: The MAC driver requires the reference clock + * to always be on. Standalone PCS drivers which + * do not have access to a PHY device can check + * this instead of PHY_F_RXC_ALWAYS_ON. * * This structure is designed to be embedded within the PCS private data, * and will be passed between phylink and the PCS. @@ -408,6 +412,7 @@ struct phylink_pcs { struct phylink *phylink; bool neg_mode; bool poll; + bool rxc_always_on; }; /** @@ -422,6 +427,8 @@ struct phylink_pcs { * @pcs_an_restart: restart 802.3z BaseX autonegotiation. * @pcs_link_up: program the PCS for the resolved link configuration * (where necessary). + * @pcs_pre_init: configure PCS components necessary for MAC hardware + * initialization e.g. RX clock for stmmac. */ struct phylink_pcs_ops { int (*pcs_validate)(struct phylink_pcs *pcs, unsigned long *supported, @@ -441,6 +448,7 @@ struct phylink_pcs_ops { void (*pcs_an_restart)(struct phylink_pcs *pcs); void (*pcs_link_up)(struct phylink_pcs *pcs, unsigned int neg_mode, phy_interface_t interface, int speed, int duplex); + int (*pcs_pre_init)(struct phylink_pcs *pcs); }; #if 0 /* For kernel-doc purposes only. */ @@ -549,6 +557,34 @@ void pcs_an_restart(struct phylink_pcs *pcs); */ void pcs_link_up(struct phylink_pcs *pcs, unsigned int neg_mode, phy_interface_t interface, int speed, int duplex); + +/** + * pcs_pre_init() - Configure PCS components necessary for MAC initialization + * @pcs: a pointer to a &struct phylink_pcs. + * + * This function can be called by MAC drivers through the + * phylink_pcs_pre_init() wrapper, before their hardware is initialized. It + * should not be called after the link is brought up, as reconfiguring the PCS + * at this point could break the link. + * + * Some MAC devices require specific hardware initialization to be performed by + * their associated PCS device before they can properly initialize their own + * hardware. An example of this is the initialization of stmmac controllers, + * which requires an active REF_CLK signal to be provided by the PHY/PCS. + * + * By calling phylink_pcs_pre_init(), MAC drivers can ensure that the PCS is + * setup in a way that allows for successful hardware initialization. + * + * The specific configuration performed by pcs_pre_init() is dependent on the + * model of PCS and the requirements of the MAC device attached to it. PCS + * driver authors should consider whether their target device is to be used in + * conjunction with a MAC device whose driver calls phylink_pcs_pre_init(). MAC + * driver authors should document their requirements for the PCS + * pre-initialization. + * + */ +int pcs_pre_init(struct phylink_pcs *pcs); + #endif struct phylink *phylink_create(struct phylink_config *, @@ -568,6 +604,8 @@ void phylink_disconnect_phy(struct phylink *); void phylink_mac_change(struct phylink *, bool up); void phylink_pcs_change(struct phylink_pcs *, bool up); +int phylink_pcs_pre_init(struct phylink *pl, struct phylink_pcs *pcs); + void phylink_start(struct phylink *); void phylink_stop(struct phylink *); From patchwork Fri Mar 1 15:35:00 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Romain Gantois X-Patchwork-Id: 13578618 X-Patchwork-Delegate: geert@linux-m68k.org Received: from relay8-d.mail.gandi.net (relay8-d.mail.gandi.net [217.70.183.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 93F9223AD; Fri, 1 Mar 2024 15:34:48 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=217.70.183.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1709307290; cv=none; b=e9dEbo1IDS9YOQ8bbCLN6MiJcrVsjs16ir/C8xuQPDCgdThfXu3HeONh+Y9GKlpW844clKKQvo8TZ0WrrQoMRjMmkoGJy2YDQqYR0L31tL7j0SC+zNPRgEwTB/ruJoS4BJt0m3FEnjz7kYXR5jPoevGWxcVol2dNn0Ec+Iq3O04= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1709307290; c=relaxed/simple; bh=HoN9SYxlcC5LVXK7IObl4vHqULtBjTr/pRpIfm2uX+w=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=rjWJDXmAAJM4lRiODfIvLVyGn3ORFItLF98YzB79blRWqAVWbllqvOFr60HdXjJEzrQTkcgF7R5JgcY8DUDSy2PwJTkhg06RI+D4nUoDwNY8HvYPkrrVhtK1pHBIS8VCpF8OzbojcNzvkk+EXpQMpqFbGLs3UwOpyU0UTjM2xxI= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=bootlin.com; spf=pass smtp.mailfrom=bootlin.com; dkim=pass (2048-bit key) header.d=bootlin.com header.i=@bootlin.com header.b=bzCSuejX; arc=none smtp.client-ip=217.70.183.201 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=bootlin.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=bootlin.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=bootlin.com header.i=@bootlin.com header.b="bzCSuejX" Received: by mail.gandi.net (Postfix) with ESMTPSA id 2F1A31BF20F; Fri, 1 Mar 2024 15:34:40 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=bootlin.com; s=gm1; t=1709307281; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=jC25vqdZfopyzKfAOsmqFvC+QwsT1bDvBX0PBzMDySo=; b=bzCSuejXIAO/S9zxyyAOC96gP4lFkMpIV3zLML4DndWdaZjMXlW5tpK2maHeRdS3lRYSXk ADdfwpGqsEgybHoCIsrtztGqtWfeoFnF5AX9AElh1sF3zCXdkX6qVK3s6oFhkMnMUmAQ0K LpD2Ogowyd1C2Ylsxbvb7nQFXcgJjoATIyInM/bm6TnXn22PyOvq6AXQ8gLLKEVi9LlwML QKqMbyWaaOg6dGB0vX4jfXYaXRWYNZXm/6uboQfIaPJz6oFUe3qg4JVR6HSVrOfIM+ioS9 12epftB1wgMEkSPTwK+Pl35LxMarROWcns5wHm1hcQEtsTpT+ep+k/2874Qzkw== From: Romain Gantois Date: Fri, 01 Mar 2024 16:35:00 +0100 Subject: [PATCH net-next v5 3/7] net: stmmac: don't rely on lynx_pcs presence to check for a PHY Precedence: bulk X-Mailing-List: linux-renesas-soc@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-Id: <20240301-rxc_bugfix-v5-3-8dac30230050@bootlin.com> References: <20240301-rxc_bugfix-v5-0-8dac30230050@bootlin.com> In-Reply-To: <20240301-rxc_bugfix-v5-0-8dac30230050@bootlin.com> To: Russell King , Andrew Lunn , Heiner Kallweit , "David S. Miller" , Eric Dumazet , Jakub Kicinski , Paolo Abeni , Alexandre Torgue , Jose Abreu , Maxime Coquelin , =?utf-8?b?Q2zDqW1lbnQgTMOp?= =?utf-8?b?Z2Vy?= Cc: Maxime Chevallier , Miquel Raynal , Thomas Petazzoni , netdev@vger.kernel.org, linux-stm32@st-md-mailman.stormreply.com, linux-arm-kernel@lists.infradead.org, linux-renesas-soc@vger.kernel.org, Romain Gantois X-Mailer: b4 0.13.0 X-GND-Sasl: romain.gantois@bootlin.com From: Maxime Chevallier When initializing attached PHYs, there are some cases where we don't expect any PHY to be connected. The logic uses conditions based on various local PCS configuration, but also calls-in phylink_expects_phy() via stmmac_init_phy(), which is enough to ensure we don't try to initialize a PHY when using a Lynx PCS, as long as we have the phy_interface set to a 802.3z mode and are using inband negociation. Drop the lynx check, making the stmmac generic code more pcs_lynx-agnostic. Signed-off-by: Maxime Chevallier [rgantois: commit log] Signed-off-by: Romain Gantois Reviewed-by: Andrew Lunn --- drivers/net/ethernet/stmicro/stmmac/stmmac_main.c | 3 +-- 1 file changed, 1 insertion(+), 2 deletions(-) diff --git a/drivers/net/ethernet/stmicro/stmmac/stmmac_main.c b/drivers/net/ethernet/stmicro/stmmac/stmmac_main.c index 24cd80490d19..d78c625d33eb 100644 --- a/drivers/net/ethernet/stmicro/stmmac/stmmac_main.c +++ b/drivers/net/ethernet/stmicro/stmmac/stmmac_main.c @@ -3960,8 +3960,7 @@ static int __stmmac_open(struct net_device *dev, if (priv->hw->pcs != STMMAC_PCS_TBI && priv->hw->pcs != STMMAC_PCS_RTBI && (!priv->hw->xpcs || - xpcs_get_an_mode(priv->hw->xpcs, mode) != DW_AN_C73) && - !priv->hw->lynx_pcs) { + xpcs_get_an_mode(priv->hw->xpcs, mode) != DW_AN_C73)) { ret = stmmac_init_phy(dev); if (ret) { netdev_err(priv->dev, From patchwork Fri Mar 1 15:35:01 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Romain Gantois X-Patchwork-Id: 13578619 X-Patchwork-Delegate: geert@linux-m68k.org Received: from relay8-d.mail.gandi.net (relay8-d.mail.gandi.net [217.70.183.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 9D6E97004D; Fri, 1 Mar 2024 15:34:49 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=217.70.183.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1709307291; cv=none; b=YfLQHEhZn/NEtZm2/GjZcyPsW4nPccyqq1yYjn6lIl/zqJFDOSHTmxpmMFAAV/wSe+4yd190BLD9uV1qp24prVFFRnJjuaNcJpjGDKie6lHhWuN7/Mwrzn58unKR1mmWIM2R/15A4IcQRkAG+c/T/Tc+47fcF0Y+pMhO/y6GVJw= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1709307291; c=relaxed/simple; bh=QeFiuD85z6qPOKKx1mTuK/riSN+AVgPYdZAmll3Lnbc=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=YM+7njURACtEr5lhMCptCOyuMN/Ft/UZs06s+FZsVZI9kIvksHGXVmwO1Zf1RW4a/tN2wXY2RgXDMY8Mc6THvSzxmrC4eVwMaiyr4IUYGjchzwF80xNsrngU+CEOJOgzXwOuALF2Q79JltzJYllE6ky/yCbs6/998+WyxtxHaTk= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=bootlin.com; spf=pass smtp.mailfrom=bootlin.com; dkim=pass (2048-bit key) header.d=bootlin.com header.i=@bootlin.com header.b=AerBo37k; arc=none smtp.client-ip=217.70.183.201 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=bootlin.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=bootlin.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=bootlin.com header.i=@bootlin.com header.b="AerBo37k" Received: by mail.gandi.net (Postfix) with ESMTPSA id 4F4491BF211; Fri, 1 Mar 2024 15:34:41 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=bootlin.com; s=gm1; t=1709307282; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=8tGPa25k36EJxEeWQmzUhYRx/TSCnts9If8gK5aVX/8=; b=AerBo37ke4x6VVF866h2zbiFQyQ5jKbKpCPfWyo2R+uwPlTmZ1ZvLDYsp/jyXwhW1kkZGv sZB//gXWrMaY57es+DOkitbnFWWBHhBcEBwUJarPb8URDVW+IdXBMtSchXecBMqUNRyyMg 3nSyESBaZQ+LJdeX/pI0DwK7uKHlRSfIWJbS1L0iiCi92o9cVhje8WGkDltjzhHbmY0OnY +fEDuMmC7iyey/j5pMKCLVhMR9sDbVZWveHFquApHNJhiJk48RbY7Jai8psK0uM8phJSPG DFMWn/OFZPzsU5NDy+jcC6vcaQkTbP05e5PtHV9ikBDRDF4lhueyw02bzZ85dw== From: Romain Gantois Date: Fri, 01 Mar 2024 16:35:01 +0100 Subject: [PATCH net-next v5 4/7] net: stmmac: Support a generic PCS field in mac_device_info Precedence: bulk X-Mailing-List: linux-renesas-soc@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-Id: <20240301-rxc_bugfix-v5-4-8dac30230050@bootlin.com> References: <20240301-rxc_bugfix-v5-0-8dac30230050@bootlin.com> In-Reply-To: <20240301-rxc_bugfix-v5-0-8dac30230050@bootlin.com> To: Russell King , Andrew Lunn , Heiner Kallweit , "David S. Miller" , Eric Dumazet , Jakub Kicinski , Paolo Abeni , Alexandre Torgue , Jose Abreu , Maxime Coquelin , =?utf-8?b?Q2zDqW1lbnQgTMOp?= =?utf-8?b?Z2Vy?= Cc: Maxime Chevallier , Miquel Raynal , Thomas Petazzoni , netdev@vger.kernel.org, linux-stm32@st-md-mailman.stormreply.com, linux-arm-kernel@lists.infradead.org, linux-renesas-soc@vger.kernel.org, Romain Gantois X-Mailer: b4 0.13.0 X-GND-Sasl: romain.gantois@bootlin.com Global stmmac support for early initialization of PCS devices requires a generic PCS reference that can be passed to phylink_pcs_pre_init(). Currently, the mac_device_info struct contains only one PCS field, which is specific to the Lynx model. As PCS models are hardware-specific, it is more appropriate to have a generic PCS field in the mac_device_info struct. Refactor the lynx_pcs field into a generic phylink_pcs field. Signed-off-by: Romain Gantois Reviewed-by: Andrew Lunn --- drivers/net/ethernet/stmicro/stmmac/common.h | 2 +- drivers/net/ethernet/stmicro/stmmac/dwmac-socfpga.c | 8 ++++---- drivers/net/ethernet/stmicro/stmmac/stmmac_main.c | 5 +---- 3 files changed, 6 insertions(+), 9 deletions(-) diff --git a/drivers/net/ethernet/stmicro/stmmac/common.h b/drivers/net/ethernet/stmicro/stmmac/common.h index a6fefe675ef1..f55cf09f0783 100644 --- a/drivers/net/ethernet/stmicro/stmmac/common.h +++ b/drivers/net/ethernet/stmicro/stmmac/common.h @@ -593,7 +593,7 @@ struct mac_device_info { const struct stmmac_mmc_ops *mmc; const struct stmmac_est_ops *est; struct dw_xpcs *xpcs; - struct phylink_pcs *lynx_pcs; /* Lynx external PCS */ + struct phylink_pcs *phylink_pcs; struct mii_regs mii; /* MII register Addresses */ struct mac_link link; void __iomem *pcsr; /* vpointer to device CSRs */ diff --git a/drivers/net/ethernet/stmicro/stmmac/dwmac-socfpga.c b/drivers/net/ethernet/stmicro/stmmac/dwmac-socfpga.c index 68f85e4605cb..12b4a80ea3aa 100644 --- a/drivers/net/ethernet/stmicro/stmmac/dwmac-socfpga.c +++ b/drivers/net/ethernet/stmicro/stmmac/dwmac-socfpga.c @@ -479,9 +479,9 @@ static int socfpga_dwmac_probe(struct platform_device *pdev) goto err_dvr_remove; } - stpriv->hw->lynx_pcs = lynx_pcs_create_mdiodev(pcs_bus, 0); - if (IS_ERR(stpriv->hw->lynx_pcs)) { - ret = PTR_ERR(stpriv->hw->lynx_pcs); + stpriv->hw->phylink_pcs = lynx_pcs_create_mdiodev(pcs_bus, 0); + if (IS_ERR(stpriv->hw->phylink_pcs)) { + ret = PTR_ERR(stpriv->hw->phylink_pcs); goto err_dvr_remove; } } @@ -498,7 +498,7 @@ static void socfpga_dwmac_remove(struct platform_device *pdev) { struct net_device *ndev = platform_get_drvdata(pdev); struct stmmac_priv *priv = netdev_priv(ndev); - struct phylink_pcs *pcs = priv->hw->lynx_pcs; + struct phylink_pcs *pcs = priv->hw->phylink_pcs; stmmac_pltfr_remove(pdev); diff --git a/drivers/net/ethernet/stmicro/stmmac/stmmac_main.c b/drivers/net/ethernet/stmicro/stmmac/stmmac_main.c index d78c625d33eb..79844dbe4258 100644 --- a/drivers/net/ethernet/stmicro/stmmac/stmmac_main.c +++ b/drivers/net/ethernet/stmicro/stmmac/stmmac_main.c @@ -944,10 +944,7 @@ static struct phylink_pcs *stmmac_mac_select_pcs(struct phylink_config *config, if (priv->hw->xpcs) return &priv->hw->xpcs->pcs; - if (priv->hw->lynx_pcs) - return priv->hw->lynx_pcs; - - return NULL; + return priv->hw->phylink_pcs; } static void stmmac_mac_config(struct phylink_config *config, unsigned int mode, From patchwork Fri Mar 1 15:35:02 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Romain Gantois X-Patchwork-Id: 13578620 X-Patchwork-Delegate: geert@linux-m68k.org Received: from relay8-d.mail.gandi.net (relay8-d.mail.gandi.net [217.70.183.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 52B4970AEA; Fri, 1 Mar 2024 15:34:49 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=217.70.183.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1709307292; cv=none; b=UbGMIgIVOJg7ZKxXX9ljvCrnO5BypEV+FZ93zMIHoiWyr/k/jRy/yvH6V4q8nzgAF1Um7v4CO/pMqmbi1hMi6M0hQkEw5YHk6kKmqd9NeDUw11UmyOh2fpY5uwWVU/BFNlkHh3Cj2xrFkibM3HDOsf9OaPkkIatjYD7pFu9uDaU= ARC-Message-Signature: i=1; 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Fri, 1 Mar 2024 15:34:42 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=bootlin.com; s=gm1; t=1709307283; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=mPP+dx/u1QlLp7Z98ZPnW3Pcjv5oOqegMlpLj3+UIJM=; b=ndvfllSY32eEq2O0+A4kF3t7bdII2sta6fBVypj8LB92rrRUwqtSP4BVvyctivWahO+UmE gOxIc+k2/kzSo57HHYo6oqZ7vwM3vcIWCsgjXgS5SbgYrnK7x5+aypg9Ww/c5NvCq07YTX qXxfH9gjwnNjS+/Zf46uKQLKHpBsGxnQSAvGy5BsdML7q+tB+tRWTJOnHoPxA3ZivL+DMb BBmhgADBPOVigumaBI1YP51l3Nwztr9Wkk6vO7shog7g4HTiz2v644LDQP7zV9uzRcrHat xrszVivl3SW0KiAikl5KrMiUu3QQAwMtkcPcVD2aryrft7U9vkIDHdOPVpfqjw== From: Romain Gantois Date: Fri, 01 Mar 2024 16:35:02 +0100 Subject: [PATCH net-next v5 5/7] net: stmmac: Signal to PHY/PCS drivers to keep RX clock on Precedence: bulk X-Mailing-List: linux-renesas-soc@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-Id: <20240301-rxc_bugfix-v5-5-8dac30230050@bootlin.com> References: <20240301-rxc_bugfix-v5-0-8dac30230050@bootlin.com> In-Reply-To: <20240301-rxc_bugfix-v5-0-8dac30230050@bootlin.com> To: Russell King , Andrew Lunn , Heiner Kallweit , "David S. Miller" , Eric Dumazet , Jakub Kicinski , Paolo Abeni , Alexandre Torgue , Jose Abreu , Maxime Coquelin , =?utf-8?b?Q2zDqW1lbnQgTMOp?= =?utf-8?b?Z2Vy?= Cc: Maxime Chevallier , Miquel Raynal , Thomas Petazzoni , netdev@vger.kernel.org, linux-stm32@st-md-mailman.stormreply.com, linux-arm-kernel@lists.infradead.org, linux-renesas-soc@vger.kernel.org, Clark Wang , Romain Gantois X-Mailer: b4 0.13.0 X-GND-Sasl: romain.gantois@bootlin.com There is a reocurring issue with stmmac controllers where the MAC fails to initialize its hardware if an RX clock signal isn't provided on the MAC/PHY link. This causes issues when PHY or PCS devices either go into suspend while cutting the RX clock or do not bring the clock signal up early enough for the MAC to initialize successfully. Set the mac_requires_rxc flag in the stmmac phylink config so that PHY/PCS drivers know to keep the RX clock up at all times. Reported-by: Clark Wang Link: https://lore.kernel.org/all/20230202081559.3553637-1-xiaoning.wang@nxp.com/ Reported-by: Clément Léger Link: https://lore.kernel.org/linux-arm-kernel/20230116103926.276869-4-clement.leger@bootlin.com/ Suggested-by: Russell King Signed-off-by: Romain Gantois Reviewed-by: Andrew Lunn --- drivers/net/ethernet/stmicro/stmmac/stmmac_main.c | 7 +++++++ 1 file changed, 7 insertions(+) diff --git a/drivers/net/ethernet/stmicro/stmmac/stmmac_main.c b/drivers/net/ethernet/stmicro/stmmac/stmmac_main.c index 79844dbe4258..2290f4808d7e 100644 --- a/drivers/net/ethernet/stmicro/stmmac/stmmac_main.c +++ b/drivers/net/ethernet/stmicro/stmmac/stmmac_main.c @@ -1218,6 +1218,9 @@ static int stmmac_phy_setup(struct stmmac_priv *priv) priv->phylink_config.type = PHYLINK_NETDEV; priv->phylink_config.mac_managed_pm = true; + /* Stmmac always requires an RX clock for hardware initialization */ + priv->phylink_config.mac_requires_rxc = true; + mdio_bus_data = priv->plat->mdio_bus_data; if (mdio_bus_data) priv->phylink_config.ovr_an_inband = @@ -3408,6 +3411,10 @@ static int stmmac_hw_setup(struct net_device *dev, bool ptp_register) u32 chan; int ret; + /* Make sure RX clock is enabled */ + if (priv->hw->phylink_pcs) + phylink_pcs_pre_init(priv->phylink, priv->hw->phylink_pcs); + /* DMA initialization and SW reset */ ret = stmmac_init_dma_engine(priv); if (ret < 0) { From patchwork Fri Mar 1 15:35:03 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Romain Gantois X-Patchwork-Id: 13578613 X-Patchwork-Delegate: geert@linux-m68k.org Received: from relay8-d.mail.gandi.net (relay8-d.mail.gandi.net [217.70.183.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id D89CC39FCF; Fri, 1 Mar 2024 15:34:45 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=217.70.183.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1709307288; cv=none; b=Ch43BjbeWjIDKZ0XLndJI6TaGOEn0eOQXWqtspADNPWCsQ1V7ge2NSGFzaNGhiOO6kTy3Y89S5B7iAKEtDqhgyLS0Pub1YKC50gX8zII7mT2NxLzyaYcbUN6Z9q9weQqL8G3OMu73YGU/4cILr6AJgDCODxQYQOJGfiAMMd4D+4= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1709307288; c=relaxed/simple; bh=3teBvmWGv2QIb9wnN8Ug62peXilZv+opMKark4W4HdQ=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=f5YkRyOeJo1dwKmfFjOf5Q8dU++Nk3EqhVpmaPiN5TICd0zZkswAUI5XKRQ4yqKZtLS8804mABoYKLK+Isib0hk351O8uON3689Va66dwD0ag0U3NKX1K8hw2u6wnayCDVKHLoy1HrxinAAPHhhJWDq2yP7sCLfV295DGmKWXus= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=bootlin.com; spf=pass smtp.mailfrom=bootlin.com; dkim=pass (2048-bit key) header.d=bootlin.com header.i=@bootlin.com header.b=U7SDI/pC; arc=none smtp.client-ip=217.70.183.201 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=bootlin.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=bootlin.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=bootlin.com header.i=@bootlin.com header.b="U7SDI/pC" Received: by mail.gandi.net (Postfix) with ESMTPSA id 5BCB51BF209; Fri, 1 Mar 2024 15:34:43 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=bootlin.com; s=gm1; t=1709307284; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=ZIPNbDER9GD1pk643Vo4atb37f/3Xw0jKatEUes035M=; b=U7SDI/pC+amED2VmvfQeO70arxWnMp3pYtcJbFEdNkJ8BIu5ix+576uoY7iiDQKYnTkomz kLkhIDwqNDT4BWnVjaH1sDcmDgj7yujGJ+2pPKsf7ZQI7fLQ4EB6Q1cGXoCDR3V6X0t786 crrF63F/TNUxpvGB5PtxJjT/q6PZ64mBsrFcJVeKK5TpuRMVpFWLHQ94uTkgEV1Y7T3sf/ pMjuhN/PDph90SZMdK7F++VacYHKxOTyg2CLQJMeMU97pySvKMC9COvb5OnGThu/kq+Yd8 cETWHNco84MnN+Q6B+rNFruIH8n2GL6C0RUNYoNYywcPdwqH/6LSFTHZNpLjVA== From: Romain Gantois Date: Fri, 01 Mar 2024 16:35:03 +0100 Subject: [PATCH net-next v5 6/7] net: phy: qcom: at803x: Avoid hibernating if MAC requires RX clock Precedence: bulk X-Mailing-List: linux-renesas-soc@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-Id: <20240301-rxc_bugfix-v5-6-8dac30230050@bootlin.com> References: <20240301-rxc_bugfix-v5-0-8dac30230050@bootlin.com> In-Reply-To: <20240301-rxc_bugfix-v5-0-8dac30230050@bootlin.com> To: Russell King , Andrew Lunn , Heiner Kallweit , "David S. Miller" , Eric Dumazet , Jakub Kicinski , Paolo Abeni , Alexandre Torgue , Jose Abreu , Maxime Coquelin , =?utf-8?b?Q2zDqW1lbnQgTMOp?= =?utf-8?b?Z2Vy?= Cc: Maxime Chevallier , Miquel Raynal , Thomas Petazzoni , netdev@vger.kernel.org, linux-stm32@st-md-mailman.stormreply.com, linux-arm-kernel@lists.infradead.org, linux-renesas-soc@vger.kernel.org, Clark Wang , Romain Gantois X-Mailer: b4 0.13.0 X-GND-Sasl: romain.gantois@bootlin.com From: Russell King Stmmac controllers connected to an at803x PHY cannot resume properly after suspend when WoL is enabled. This happens because the MAC requires an RX clock generated by the PHY to initialize its hardware properly. But the RX clock is cut when the PHY suspends and isn't brought up until the MAC driver resumes the phylink. Prevent the at803x PHY driver from going into suspend if the attached MAC driver always requires an RX clock signal. Reported-by: Clark Wang Link: https://lore.kernel.org/all/20230202081559.3553637-1-xiaoning.wang@nxp.com/ Signed-off-by: Russell King [rgantois: commit log] Signed-off-by: Romain Gantois Reviewed-by: Andrew Lunn --- drivers/net/phy/qcom/at803x.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/drivers/net/phy/qcom/at803x.c b/drivers/net/phy/qcom/at803x.c index 4717c59d51d0..2a221b81cf37 100644 --- a/drivers/net/phy/qcom/at803x.c +++ b/drivers/net/phy/qcom/at803x.c @@ -426,7 +426,8 @@ static int at803x_hibernation_mode_config(struct phy_device *phydev) /* The default after hardware reset is hibernation mode enabled. After * software reset, the value is retained. */ - if (!(priv->flags & AT803X_DISABLE_HIBERNATION_MODE)) + if (!(priv->flags & AT803X_DISABLE_HIBERNATION_MODE) && + !(phydev->dev_flags & PHY_F_RXC_ALWAYS_ON)) return 0; return at803x_debug_reg_mask(phydev, AT803X_DEBUG_REG_HIB_CTRL, From patchwork Fri Mar 1 15:35:04 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Romain Gantois X-Patchwork-Id: 13578615 X-Patchwork-Delegate: geert@linux-m68k.org Received: from relay8-d.mail.gandi.net (relay8-d.mail.gandi.net [217.70.183.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 2B5286EF1B; Fri, 1 Mar 2024 15:34:46 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=217.70.183.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1709307289; cv=none; b=kUGG40vyip851UmY27MHyggI67COc5GZDW5n+Pd4fkEkB8iYBZcugtXd2aFwQOJG4DZmXkzmYpiVSjjFMIJGav33fIDrp0fIwxmg0hiIGMRHWCvVsyQH59PtdFtANHLSU6zB9W9TUW1Q87DqDcme3mD57QhaCdHIlgAA+Lp+dCg= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1709307289; c=relaxed/simple; bh=D49aXYPQrwkUDZmDeQoqlQjAe7+L9PHpRXAU7ZliBh0=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=ujrDfQwGJ5sqAQvOqhpggDpkmtCorN/Gd3irez6ScrOQ3M2pb0QKEtCRYuyVC7sTZKC/5LV7y5EMr8cRFaI6mtv6X2pK1kFQUGybhQ9rHSD50oyENZoWecbMIfJHTMMz9QGl8VozgWh4MxxmiN5vBs6/XEo7kJqSSgMmxejWUNs= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=bootlin.com; spf=pass smtp.mailfrom=bootlin.com; dkim=pass (2048-bit key) header.d=bootlin.com header.i=@bootlin.com header.b=BiVVlX9W; arc=none smtp.client-ip=217.70.183.201 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=bootlin.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=bootlin.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=bootlin.com header.i=@bootlin.com header.b="BiVVlX9W" Received: by mail.gandi.net (Postfix) with ESMTPSA id 7B3C51BF20E; Fri, 1 Mar 2024 15:34:44 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=bootlin.com; s=gm1; t=1709307285; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=s6LIsy4cmYZytxPJCTBqEXj+r87EQ9cGgcY4Fox5a48=; b=BiVVlX9W7Au059KYrwEXFL9D8p2hZurAT58wUJVvgByaXXhuvaCvH2/wSXvORLxvxUU4yR KoB+4+9lUtzM5wcJeXZd6DNtiTlLoXJdbbSbYFqTn2WF+P7PILutGZGIV5qERFRvkC/8vp YYx9CmA7tZ5mqzyodTzqVcxgOkh065n03B77razG2c38BYnFrNpAdy8teV/rwrqEEGFD2+ HdYf2S/lDo+FPXqm5iImOLyDGytSj59cLHq0g5xiNngDKO+a0ObNo8lKf3JJbAftciJGiz EKSeRhNoSIo/GfaYWeVgnKNGimufAiscMZAamhul8/63gOhitqW4bhxiRKHy+A== From: Romain Gantois Date: Fri, 01 Mar 2024 16:35:04 +0100 Subject: [PATCH net-next v5 7/7] net: pcs: rzn1-miic: Init RX clock early if MAC requires it Precedence: bulk X-Mailing-List: linux-renesas-soc@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-Id: <20240301-rxc_bugfix-v5-7-8dac30230050@bootlin.com> References: <20240301-rxc_bugfix-v5-0-8dac30230050@bootlin.com> In-Reply-To: <20240301-rxc_bugfix-v5-0-8dac30230050@bootlin.com> To: Russell King , Andrew Lunn , Heiner Kallweit , "David S. Miller" , Eric Dumazet , Jakub Kicinski , Paolo Abeni , Alexandre Torgue , Jose Abreu , Maxime Coquelin , =?utf-8?b?Q2zDqW1lbnQgTMOp?= =?utf-8?b?Z2Vy?= Cc: Maxime Chevallier , Miquel Raynal , Thomas Petazzoni , netdev@vger.kernel.org, linux-stm32@st-md-mailman.stormreply.com, linux-arm-kernel@lists.infradead.org, linux-renesas-soc@vger.kernel.org, Romain Gantois X-Mailer: b4 0.13.0 X-GND-Sasl: romain.gantois@bootlin.com The GMAC1 controller in the RZN1 IP requires the RX MII clock signal to be started before it initializes its own hardware, thus before it calls phylink_start. Implement the pcs_pre_init() callback so that the RX clock signal can be enabled early if necessary. Reported-by: Clément Léger Link: https://lore.kernel.org/linux-arm-kernel/20230116103926.276869-4-clement.leger@bootlin.com/ Signed-off-by: Romain Gantois Reviewed-by: Andrew Lunn --- drivers/net/pcs/pcs-rzn1-miic.c | 28 ++++++++++++++++++++++++++++ 1 file changed, 28 insertions(+) diff --git a/drivers/net/pcs/pcs-rzn1-miic.c b/drivers/net/pcs/pcs-rzn1-miic.c index d93f84fbb1fd..8a683c76a0f2 100644 --- a/drivers/net/pcs/pcs-rzn1-miic.c +++ b/drivers/net/pcs/pcs-rzn1-miic.c @@ -279,10 +279,38 @@ static int miic_validate(struct phylink_pcs *pcs, unsigned long *supported, return -EINVAL; } +static int miic_pre_init(struct phylink_pcs *pcs) +{ + struct miic_port *miic_port = phylink_pcs_to_miic_port(pcs); + struct miic *miic = miic_port->miic; + u32 val, mask; + + /* Start RX clock if required */ + if (pcs->rxc_always_on) { + /* In MII through mode, the clock signals will be driven by the + * external PHY, which might not be initialized yet. Set RMII + * as default mode to ensure that a reference clock signal is + * generated. + */ + miic_port->interface = PHY_INTERFACE_MODE_RMII; + + val = FIELD_PREP(MIIC_CONVCTRL_CONV_MODE, CONV_MODE_RMII) | + FIELD_PREP(MIIC_CONVCTRL_CONV_SPEED, CONV_MODE_100MBPS); + mask = MIIC_CONVCTRL_CONV_MODE | MIIC_CONVCTRL_CONV_SPEED; + + miic_reg_rmw(miic, MIIC_CONVCTRL(miic_port->port), mask, val); + + miic_converter_enable(miic, miic_port->port, 1); + } + + return 0; +} + static const struct phylink_pcs_ops miic_phylink_ops = { .pcs_validate = miic_validate, .pcs_config = miic_config, .pcs_link_up = miic_link_up, + .pcs_pre_init = miic_pre_init, }; struct phylink_pcs *miic_create(struct device *dev, struct device_node *np)