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[2001:1c00:20d:1300:1b1c:4449:176a:89ea]) by smtp.gmail.com with ESMTPSA id um9-20020a170906cf8900b00a44d01aff81sm1530759ejb.97.2024.03.03.02.28.54 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 03 Mar 2024 02:28:54 -0800 (PST) From: Eric Woudstra To: Andrew Lunn , Heiner Kallweit , Russell King , "David S. Miller" , Eric Dumazet , Jakub Kicinski , Paolo Abeni , =?utf-8?q?Marek_Beh=C3=BAn?= , "Frank Wunderlich" , Daniel Golle Cc: netdev@vger.kernel.org, Alexander Couzens , Eric Woudstra Subject: [PATCH v2 net-next 1/7] net: phy: realtek: configure SerDes mode for rtl822x/8251b PHYs Date: Sun, 3 Mar 2024 11:28:42 +0100 Message-ID: <20240303102848.164108-2-ericwouds@gmail.com> X-Mailer: git-send-email 2.42.1 In-Reply-To: <20240303102848.164108-1-ericwouds@gmail.com> References: <20240303102848.164108-1-ericwouds@gmail.com> Precedence: bulk X-Mailing-List: netdev@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-Patchwork-Delegate: kuba@kernel.org From: Alexander Couzens The rtl822x series and rtl8251b support switching SerDes mode between 2500base-x and sgmii based on the negotiated copper speed. Configure this switching mode according to SerDes modes supported by host. There is an additional datasheet for RTL8226B/RTL8221B called "SERDES MODE SETTING FLOW APPLICATION NOTE" where this sequence to setup interface and rate adapter mode. However, there is no documentation about the meaning of registers and bits, it's literally just magic numbers and pseudo-code. Signed-off-by: Alexander Couzens [ refactored, dropped HiSGMII mode and changed commit message ] Signed-off-by: Marek Behún [ changed rtl822x_update_interface() to use vendor register ] [ always fill in possible interfaces ] Signed-off-by: Eric Woudstra --- drivers/net/phy/realtek.c | 99 ++++++++++++++++++++++++++++++++++++++- 1 file changed, 97 insertions(+), 2 deletions(-) diff --git a/drivers/net/phy/realtek.c b/drivers/net/phy/realtek.c index 1fa70427b2a2..8a876e003774 100644 --- a/drivers/net/phy/realtek.c +++ b/drivers/net/phy/realtek.c @@ -54,6 +54,16 @@ RTL8201F_ISR_LINK) #define RTL8201F_IER 0x13 +#define RTL822X_VND1_SERDES_OPTION 0x697a +#define RTL822X_VND1_SERDES_OPTION_MODE_MASK GENMASK(5, 0) +#define RTL822X_VND1_SERDES_OPTION_MODE_2500BASEX_SGMII 0 +#define RTL822X_VND1_SERDES_OPTION_MODE_2500BASEX 2 + +#define RTL822X_VND1_SERDES_CTRL3 0x7580 +#define RTL822X_VND1_SERDES_CTRL3_MODE_MASK GENMASK(5, 0) +#define RTL822X_VND1_SERDES_CTRL3_MODE_SGMII 0x02 +#define RTL822X_VND1_SERDES_CTRL3_MODE_2500BASEX 0x16 + #define RTL8366RB_POWER_SAVE 0x15 #define RTL8366RB_POWER_SAVE_ON BIT(12) @@ -659,6 +669,60 @@ static int rtl822x_write_mmd(struct phy_device *phydev, int devnum, u16 regnum, return ret; } +static int rtl822x_config_init(struct phy_device *phydev) +{ + bool has_2500, has_sgmii; + u16 mode; + int ret; + + has_2500 = test_bit(PHY_INTERFACE_MODE_2500BASEX, + phydev->host_interfaces) || + phydev->interface == PHY_INTERFACE_MODE_2500BASEX; + + has_sgmii = test_bit(PHY_INTERFACE_MODE_SGMII, + phydev->host_interfaces) || + phydev->interface == PHY_INTERFACE_MODE_SGMII; + + /* fill in possible interfaces */ + __assign_bit(PHY_INTERFACE_MODE_2500BASEX, phydev->possible_interfaces, + has_2500); + __assign_bit(PHY_INTERFACE_MODE_SGMII, phydev->possible_interfaces, + has_sgmii); + + if (!has_2500 && !has_sgmii) + return 0; + + /* determine SerDes option mode */ + if (has_2500 && !has_sgmii) + mode = RTL822X_VND1_SERDES_OPTION_MODE_2500BASEX; + else + mode = RTL822X_VND1_SERDES_OPTION_MODE_2500BASEX_SGMII; + + /* the following sequence with magic numbers sets up the SerDes + * option mode + */ + ret = phy_write_mmd(phydev, MDIO_MMD_VEND1, 0x75f3, 0); + if (ret < 0) + return ret; + + ret = phy_modify_mmd_changed(phydev, MDIO_MMD_VEND1, + RTL822X_VND1_SERDES_OPTION, + RTL822X_VND1_SERDES_OPTION_MODE_MASK, + mode); + if (ret < 0) + return ret; + + ret = phy_write_mmd(phydev, MDIO_MMD_VEND1, 0x6a04, 0x0503); + if (ret < 0) + return ret; + + ret = phy_write_mmd(phydev, MDIO_MMD_VEND1, 0x6f10, 0xd455); + if (ret < 0) + return ret; + + return phy_write_mmd(phydev, MDIO_MMD_VEND1, 0x6f11, 0x8020); +} + static int rtl822x_get_features(struct phy_device *phydev) { int val; @@ -695,6 +759,28 @@ static int rtl822x_config_aneg(struct phy_device *phydev) return __genphy_config_aneg(phydev, ret); } +static void rtl822x_update_interface(struct phy_device *phydev) +{ + int val; + + if (!phydev->link) + return; + + /* Change interface according to serdes mode */ + val = phy_read_mmd(phydev, MDIO_MMD_VEND1, RTL822X_VND1_SERDES_CTRL3); + if (val < 0) + return; + + switch (val & RTL822X_VND1_SERDES_CTRL3_MODE_MASK) { + case RTL822X_VND1_SERDES_CTRL3_MODE_2500BASEX: + phydev->interface = PHY_INTERFACE_MODE_2500BASEX; + break; + case RTL822X_VND1_SERDES_CTRL3_MODE_SGMII: + phydev->interface = PHY_INTERFACE_MODE_SGMII; + break; + } +} + static int rtl822x_read_status(struct phy_device *phydev) { int ret; @@ -709,11 +795,13 @@ static int rtl822x_read_status(struct phy_device *phydev) lpadv); } - ret = genphy_read_status(phydev); + ret = rtlgen_read_status(phydev); if (ret < 0) return ret; - return rtlgen_get_speed(phydev); + rtl822x_update_interface(phydev); + + return 0; } static bool rtlgen_supports_2_5gbps(struct phy_device *phydev) @@ -976,6 +1064,7 @@ static struct phy_driver realtek_drvs[] = { .match_phy_device = rtl8226_match_phy_device, .get_features = rtl822x_get_features, .config_aneg = rtl822x_config_aneg, + .config_init = rtl822x_config_init, .read_status = rtl822x_read_status, .suspend = genphy_suspend, .resume = rtlgen_resume, @@ -988,6 +1077,7 @@ static struct phy_driver realtek_drvs[] = { .name = "RTL8226B_RTL8221B 2.5Gbps PHY", .get_features = rtl822x_get_features, .config_aneg = rtl822x_config_aneg, + .config_init = rtl822x_config_init, .read_status = rtl822x_read_status, .suspend = genphy_suspend, .resume = rtlgen_resume, @@ -1000,6 +1090,7 @@ static struct phy_driver realtek_drvs[] = { .name = "RTL8226-CG 2.5Gbps PHY", .get_features = rtl822x_get_features, .config_aneg = rtl822x_config_aneg, + .config_init = rtl822x_config_init, .read_status = rtl822x_read_status, .suspend = genphy_suspend, .resume = rtlgen_resume, @@ -1010,6 +1101,7 @@ static struct phy_driver realtek_drvs[] = { .name = "RTL8226B-CG_RTL8221B-CG 2.5Gbps PHY", .get_features = rtl822x_get_features, .config_aneg = rtl822x_config_aneg, + .config_init = rtl822x_config_init, .read_status = rtl822x_read_status, .suspend = genphy_suspend, .resume = rtlgen_resume, @@ -1019,6 +1111,7 @@ static struct phy_driver realtek_drvs[] = { PHY_ID_MATCH_EXACT(0x001cc849), .name = "RTL8221B-VB-CG 2.5Gbps PHY", .get_features = rtl822x_get_features, + .config_init = rtl822x_config_init, .config_aneg = rtl822x_config_aneg, .read_status = rtl822x_read_status, .suspend = genphy_suspend, @@ -1030,6 +1123,7 @@ static struct phy_driver realtek_drvs[] = { .name = "RTL8221B-VM-CG 2.5Gbps PHY", .get_features = rtl822x_get_features, .config_aneg = rtl822x_config_aneg, + .config_init = rtl822x_config_init, .read_status = rtl822x_read_status, .suspend = genphy_suspend, .resume = rtlgen_resume, @@ -1040,6 +1134,7 @@ static struct phy_driver realtek_drvs[] = { .name = "RTL8251B 5Gbps PHY", .get_features = rtl822x_get_features, .config_aneg = rtl822x_config_aneg, + .config_init = rtl822x_config_init, .read_status = rtl822x_read_status, .suspend = genphy_suspend, .resume = rtlgen_resume, From patchwork Sun Mar 3 10:28:43 2024 Content-Type: text/plain; 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[2001:1c00:20d:1300:1b1c:4449:176a:89ea]) by smtp.gmail.com with ESMTPSA id um9-20020a170906cf8900b00a44d01aff81sm1530759ejb.97.2024.03.03.02.28.55 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 03 Mar 2024 02:28:56 -0800 (PST) From: Eric Woudstra To: Andrew Lunn , Heiner Kallweit , Russell King , "David S. Miller" , Eric Dumazet , Jakub Kicinski , Paolo Abeni , =?utf-8?q?Marek_Beh=C3=BAn?= , "Frank Wunderlich" , Daniel Golle Cc: netdev@vger.kernel.org, Eric Woudstra Subject: [PATCH v2 net-next 2/7] net: phy: realtek: add get_rate_matching() for rtl822x/8251b PHYs Date: Sun, 3 Mar 2024 11:28:43 +0100 Message-ID: <20240303102848.164108-3-ericwouds@gmail.com> X-Mailer: git-send-email 2.42.1 In-Reply-To: <20240303102848.164108-1-ericwouds@gmail.com> References: <20240303102848.164108-1-ericwouds@gmail.com> Precedence: bulk X-Mailing-List: netdev@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-Patchwork-Delegate: kuba@kernel.org Uses vendor register to determine if SerDes is setup in rate-matching mode. Rate-matching only supported when SerDes is set to 2500base-x. Signed-off-by: Eric Woudstra --- drivers/net/phy/realtek.c | 29 +++++++++++++++++++++++++++++ 1 file changed, 29 insertions(+) diff --git a/drivers/net/phy/realtek.c b/drivers/net/phy/realtek.c index 8a876e003774..d7a47edd529e 100644 --- a/drivers/net/phy/realtek.c +++ b/drivers/net/phy/realtek.c @@ -723,6 +723,28 @@ static int rtl822x_config_init(struct phy_device *phydev) return phy_write_mmd(phydev, MDIO_MMD_VEND1, 0x6f11, 0x8020); } +static int rtl822x_get_rate_matching(struct phy_device *phydev, + phy_interface_t iface) +{ + int val; + + /* Only rate matching at 2500base-x */ + if (iface != PHY_INTERFACE_MODE_2500BASEX) + return RATE_MATCH_NONE; + + val = phy_read_mmd(phydev, MDIO_MMD_VEND1, RTL822X_VND1_SERDES_OPTION); + if (val < 0) + return val; + + switch (val & RTL822X_VND1_SERDES_OPTION_MODE_MASK) { + case RTL822X_VND1_SERDES_OPTION_MODE_2500BASEX: + return RATE_MATCH_PAUSE; + /* case RTL822X_VND1_SERDES_OPTION_MODE_2500BASEX_SGMII: */ + default: + return RATE_MATCH_NONE; + } +} + static int rtl822x_get_features(struct phy_device *phydev) { int val; @@ -1065,6 +1087,7 @@ static struct phy_driver realtek_drvs[] = { .get_features = rtl822x_get_features, .config_aneg = rtl822x_config_aneg, .config_init = rtl822x_config_init, + .get_rate_matching = rtl822x_get_rate_matching, .read_status = rtl822x_read_status, .suspend = genphy_suspend, .resume = rtlgen_resume, @@ -1078,6 +1101,7 @@ static struct phy_driver realtek_drvs[] = { .get_features = rtl822x_get_features, .config_aneg = rtl822x_config_aneg, .config_init = rtl822x_config_init, + .get_rate_matching = rtl822x_get_rate_matching, .read_status = rtl822x_read_status, .suspend = genphy_suspend, .resume = rtlgen_resume, @@ -1091,6 +1115,7 @@ static struct phy_driver realtek_drvs[] = { .get_features = rtl822x_get_features, .config_aneg = rtl822x_config_aneg, .config_init = rtl822x_config_init, + .get_rate_matching = rtl822x_get_rate_matching, .read_status = rtl822x_read_status, .suspend = genphy_suspend, .resume = rtlgen_resume, @@ -1102,6 +1127,7 @@ static struct phy_driver realtek_drvs[] = { .get_features = rtl822x_get_features, .config_aneg = rtl822x_config_aneg, .config_init = rtl822x_config_init, + .get_rate_matching = rtl822x_get_rate_matching, .read_status = rtl822x_read_status, .suspend = genphy_suspend, .resume = rtlgen_resume, @@ -1112,6 +1138,7 @@ static struct phy_driver realtek_drvs[] = { .name = "RTL8221B-VB-CG 2.5Gbps PHY", .get_features = rtl822x_get_features, .config_init = rtl822x_config_init, + .get_rate_matching = rtl822x_get_rate_matching, .config_aneg = rtl822x_config_aneg, .read_status = rtl822x_read_status, .suspend = genphy_suspend, @@ -1124,6 +1151,7 @@ static struct phy_driver realtek_drvs[] = { .get_features = rtl822x_get_features, .config_aneg = rtl822x_config_aneg, .config_init = rtl822x_config_init, + .get_rate_matching = rtl822x_get_rate_matching, .read_status = rtl822x_read_status, .suspend = genphy_suspend, .resume = rtlgen_resume, @@ -1135,6 +1163,7 @@ static struct phy_driver realtek_drvs[] = { .get_features = rtl822x_get_features, .config_aneg = rtl822x_config_aneg, .config_init = rtl822x_config_init, + .get_rate_matching = rtl822x_get_rate_matching, .read_status = rtl822x_read_status, .suspend = genphy_suspend, .resume = rtlgen_resume, From patchwork Sun Mar 3 10:28:44 2024 Content-Type: text/plain; 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[2001:1c00:20d:1300:1b1c:4449:176a:89ea]) by smtp.gmail.com with ESMTPSA id um9-20020a170906cf8900b00a44d01aff81sm1530759ejb.97.2024.03.03.02.28.56 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 03 Mar 2024 02:28:56 -0800 (PST) From: Eric Woudstra To: Andrew Lunn , Heiner Kallweit , Russell King , "David S. Miller" , Eric Dumazet , Jakub Kicinski , Paolo Abeni , =?utf-8?q?Marek_Beh=C3=BAn?= , "Frank Wunderlich" , Daniel Golle Cc: netdev@vger.kernel.org, Eric Woudstra Subject: [PATCH v2 net-next 3/7] net: phy: realtek: Add driver instances for rtl8221b/8251b via Clause 45 Date: Sun, 3 Mar 2024 11:28:44 +0100 Message-ID: <20240303102848.164108-4-ericwouds@gmail.com> X-Mailer: git-send-email 2.42.1 In-Reply-To: <20240303102848.164108-1-ericwouds@gmail.com> References: <20240303102848.164108-1-ericwouds@gmail.com> Precedence: bulk X-Mailing-List: netdev@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-Patchwork-Delegate: kuba@kernel.org From: Marek Behún Collected from several commits in [PATCH net-next] "Realtek RTL822x PHY rework to c45 and SerDes interface switching" The instances are used by Clause 45 only accessible PHY's on several sfp modules, which are using RollBall protocol. Signed-off-by: Marek Behún [ Added matching functions to differentiate C45 instances ] Signed-off-by: Eric Woudstra --- drivers/net/phy/realtek.c | 146 ++++++++++++++++++++++++++++++++++++-- 1 file changed, 140 insertions(+), 6 deletions(-) diff --git a/drivers/net/phy/realtek.c b/drivers/net/phy/realtek.c index d7a47edd529e..f9a67761878e 100644 --- a/drivers/net/phy/realtek.c +++ b/drivers/net/phy/realtek.c @@ -64,6 +64,13 @@ #define RTL822X_VND1_SERDES_CTRL3_MODE_SGMII 0x02 #define RTL822X_VND1_SERDES_CTRL3_MODE_2500BASEX 0x16 +/* RTL822X_VND2_XXXXX registers are only accessible when phydev->is_c45 + * is set, they cannot be accessed by C45-over-C22. + */ +#define RTL822X_VND2_GBCR 0xa412 + +#define RTL822X_VND2_GANLPAR 0xa414 + #define RTL8366RB_POWER_SAVE 0x15 #define RTL8366RB_POWER_SAVE_ON BIT(12) @@ -74,6 +81,9 @@ #define RTL_GENERIC_PHYID 0x001cc800 #define RTL_8211FVD_PHYID 0x001cc878 +#define RTL_8221B_VB_CG 0x001cc849 +#define RTL_8221B_VN_CG 0x001cc84a +#define RTL_8251B 0x001cc862 MODULE_DESCRIPTION("Realtek PHY driver"); MODULE_AUTHOR("Johnson Leung"); @@ -826,6 +836,56 @@ static int rtl822x_read_status(struct phy_device *phydev) return 0; } +static int rtl822x_c45_config_aneg(struct phy_device *phydev) +{ + bool changed = false; + int ret, val; + + if (phydev->autoneg == AUTONEG_DISABLE) + return genphy_c45_pma_setup_forced(phydev); + + ret = genphy_c45_an_config_aneg(phydev); + if (ret < 0) + return ret; + if (ret > 0) + changed = true; + + val = linkmode_adv_to_mii_ctrl1000_t(phydev->advertising); + + /* Vendor register as C45 has no standardized support for 1000BaseT */ + ret = phy_modify_mmd_changed(phydev, MDIO_MMD_VEND2, RTL822X_VND2_GBCR, + ADVERTISE_1000FULL, val); + if (ret < 0) + return ret; + if (ret > 0) + changed = true; + + return genphy_c45_check_and_restart_aneg(phydev, changed); +} + +static int rtl822x_c45_read_status(struct phy_device *phydev) +{ + int ret, val; + + ret = genphy_c45_read_status(phydev); + if (ret < 0) + return ret; + + /* Vendor register as C45 has no standardized support for 1000BaseT */ + if (phydev->autoneg == AUTONEG_ENABLE) { + val = phy_read_mmd(phydev, MDIO_MMD_VEND2, + RTL822X_VND2_GANLPAR); + if (val < 0) + return val; + + mii_stat1000_mod_linkmode_lpa_t(phydev->lp_advertising, val); + } + + rtl822x_update_interface(phydev); + + return 0; +} + static bool rtlgen_supports_2_5gbps(struct phy_device *phydev) { int val; @@ -849,6 +909,44 @@ static int rtl8226_match_phy_device(struct phy_device *phydev) rtlgen_supports_2_5gbps(phydev); } +static int rtlgen_is_c45_match(struct phy_device *phydev, unsigned int id, bool is_c45) +{ + if (phydev->is_c45) + return is_c45 && (id == phydev->c45_ids.device_ids[1]); + else + return !is_c45 && (id == phydev->phy_id); +} + +static int rtl8221b_vb_cg_c22_match_phy_device(struct phy_device *phydev) +{ + return rtlgen_is_c45_match(phydev, RTL_8221B_VB_CG, false); +} + +static int rtl8221b_vb_cg_c45_match_phy_device(struct phy_device *phydev) +{ + return rtlgen_is_c45_match(phydev, RTL_8221B_VB_CG, true); +} + +static int rtl8221b_vn_cg_c22_match_phy_device(struct phy_device *phydev) +{ + return rtlgen_is_c45_match(phydev, RTL_8221B_VN_CG, false); +} + +static int rtl8221b_vn_cg_c45_match_phy_device(struct phy_device *phydev) +{ + return rtlgen_is_c45_match(phydev, RTL_8221B_VN_CG, true); +} + +static int rtl8251b_c22_match_phy_device(struct phy_device *phydev) +{ + return rtlgen_is_c45_match(phydev, RTL_8251B, false); +} + +static int rtl8251b_c45_match_phy_device(struct phy_device *phydev) +{ + return rtlgen_is_c45_match(phydev, RTL_8251B, true); +} + static int rtlgen_resume(struct phy_device *phydev) { int ret = genphy_resume(phydev); @@ -859,6 +957,15 @@ static int rtlgen_resume(struct phy_device *phydev) return ret; } +static int rtlgen_c45_resume(struct phy_device *phydev) +{ + int ret = genphy_c45_pma_resume(phydev); + + msleep(20); + + return ret; +} + static int rtl9000a_config_init(struct phy_device *phydev) { phydev->autoneg = AUTONEG_DISABLE; @@ -1134,8 +1241,8 @@ static struct phy_driver realtek_drvs[] = { .read_page = rtl821x_read_page, .write_page = rtl821x_write_page, }, { - PHY_ID_MATCH_EXACT(0x001cc849), - .name = "RTL8221B-VB-CG 2.5Gbps PHY", + .match_phy_device = rtl8221b_vb_cg_c22_match_phy_device, + .name = "RTL8221B-VB-CG 2.5Gbps PHY (C22)", .get_features = rtl822x_get_features, .config_init = rtl822x_config_init, .get_rate_matching = rtl822x_get_rate_matching, @@ -1146,8 +1253,17 @@ static struct phy_driver realtek_drvs[] = { .read_page = rtl821x_read_page, .write_page = rtl821x_write_page, }, { - PHY_ID_MATCH_EXACT(0x001cc84a), - .name = "RTL8221B-VM-CG 2.5Gbps PHY", + .match_phy_device = rtl8221b_vb_cg_c45_match_phy_device, + .name = "RTL8221B-VB-CG 2.5Gbps PHY (C45)", + .config_init = rtl822x_config_init, + .get_rate_matching = rtl822x_get_rate_matching, + .config_aneg = rtl822x_c45_config_aneg, + .read_status = rtl822x_c45_read_status, + .suspend = genphy_c45_pma_suspend, + .resume = rtlgen_c45_resume, + }, { + .match_phy_device = rtl8221b_vn_cg_c22_match_phy_device, + .name = "RTL8221B-VM-CG 2.5Gbps PHY (C22)", .get_features = rtl822x_get_features, .config_aneg = rtl822x_config_aneg, .config_init = rtl822x_config_init, @@ -1158,8 +1274,17 @@ static struct phy_driver realtek_drvs[] = { .read_page = rtl821x_read_page, .write_page = rtl821x_write_page, }, { - PHY_ID_MATCH_EXACT(0x001cc862), - .name = "RTL8251B 5Gbps PHY", + .match_phy_device = rtl8221b_vn_cg_c45_match_phy_device, + .name = "RTL8221B-VN-CG 2.5Gbps PHY (C45)", + .config_init = rtl822x_config_init, + .get_rate_matching = rtl822x_get_rate_matching, + .config_aneg = rtl822x_c45_config_aneg, + .read_status = rtl822x_c45_read_status, + .suspend = genphy_c45_pma_suspend, + .resume = rtlgen_c45_resume, + }, { + .match_phy_device = rtl8251b_c22_match_phy_device, + .name = "RTL8251B 5Gbps PHY (C22)", .get_features = rtl822x_get_features, .config_aneg = rtl822x_config_aneg, .config_init = rtl822x_config_init, @@ -1169,6 +1294,15 @@ static struct phy_driver realtek_drvs[] = { .resume = rtlgen_resume, .read_page = rtl821x_read_page, .write_page = rtl821x_write_page, + }, { + .match_phy_device = rtl8251b_c45_match_phy_device, + .name = "RTL8251B 5Gbps PHY (C45)", + .config_init = rtl822x_config_init, + .get_rate_matching = rtl822x_get_rate_matching, + .config_aneg = rtl822x_c45_config_aneg, + .read_status = rtl822x_c45_read_status, + .suspend = genphy_c45_pma_suspend, + .resume = rtlgen_c45_resume, }, { PHY_ID_MATCH_EXACT(0x001cc961), .name = "RTL8366RB Gigabit Ethernet", From patchwork Sun Mar 3 10:28:45 2024 Content-Type: text/plain; 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[2001:1c00:20d:1300:1b1c:4449:176a:89ea]) by smtp.gmail.com with ESMTPSA id um9-20020a170906cf8900b00a44d01aff81sm1530759ejb.97.2024.03.03.02.28.57 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 03 Mar 2024 02:28:58 -0800 (PST) From: Eric Woudstra To: Andrew Lunn , Heiner Kallweit , Russell King , "David S. Miller" , Eric Dumazet , Jakub Kicinski , Paolo Abeni , =?utf-8?q?Marek_Beh=C3=BAn?= , "Frank Wunderlich" , Daniel Golle Cc: netdev@vger.kernel.org, Eric Woudstra Subject: [PATCH v2 net-next 4/7] net: phy: realtek: Change rtlgen_get_speed() to rtlgen_decode_speed() Date: Sun, 3 Mar 2024 11:28:45 +0100 Message-ID: <20240303102848.164108-5-ericwouds@gmail.com> X-Mailer: git-send-email 2.42.1 In-Reply-To: <20240303102848.164108-1-ericwouds@gmail.com> References: <20240303102848.164108-1-ericwouds@gmail.com> Precedence: bulk X-Mailing-List: netdev@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-Patchwork-Delegate: kuba@kernel.org The value of the register to determine the speed, is retrieved differently when using Clause 45 only. To use the rtlgen_get_speed() function in this case, pass the value of the register as argument to rtlgen_get_speed(). The function would then always return 0, so change it to void. A better name for this function now is rtlgen_decode_speed(). Add reading speed to rtl822x_c45_read_status(). Signed-off-by: Eric Woudstra --- drivers/net/phy/realtek.c | 38 ++++++++++++++++++++++++-------------- 1 file changed, 24 insertions(+), 14 deletions(-) diff --git a/drivers/net/phy/realtek.c b/drivers/net/phy/realtek.c index f9a67761878e..6449d8e0842c 100644 --- a/drivers/net/phy/realtek.c +++ b/drivers/net/phy/realtek.c @@ -71,6 +71,8 @@ #define RTL822X_VND2_GANLPAR 0xa414 +#define RTL822X_VND2_PHYSR 0xa434 + #define RTL8366RB_POWER_SAVE 0x15 #define RTL8366RB_POWER_SAVE_ON BIT(12) @@ -551,17 +553,8 @@ static int rtl8366rb_config_init(struct phy_device *phydev) } /* get actual speed to cover the downshift case */ -static int rtlgen_get_speed(struct phy_device *phydev) +static void rtlgen_decode_speed(struct phy_device *phydev, int val) { - int val; - - if (!phydev->link) - return 0; - - val = phy_read_paged(phydev, 0xa43, 0x12); - if (val < 0) - return val; - switch (val & RTLGEN_SPEED_MASK) { case 0x0000: phydev->speed = SPEED_10; @@ -584,19 +577,26 @@ static int rtlgen_get_speed(struct phy_device *phydev) default: break; } - - return 0; } static int rtlgen_read_status(struct phy_device *phydev) { - int ret; + int ret, val; ret = genphy_read_status(phydev); if (ret < 0) return ret; - return rtlgen_get_speed(phydev); + if (!phydev->link) + return 0; + + val = phy_read_paged(phydev, 0xa43, 0x12); + if (val < 0) + return val; + + rtlgen_decode_speed(phydev, val); + + return 0; } static int rtlgen_read_mmd(struct phy_device *phydev, int devnum, u16 regnum) @@ -881,6 +881,16 @@ static int rtl822x_c45_read_status(struct phy_device *phydev) mii_stat1000_mod_linkmode_lpa_t(phydev->lp_advertising, val); } + if (!phydev->link) + return 0; + + /* Read actual speed from vendor register. */ + val = phy_read_mmd(phydev, MDIO_MMD_VEND2, RTL822X_VND2_PHYSR); + if (val < 0) + return val; + + rtlgen_decode_speed(phydev, val); + rtl822x_update_interface(phydev); return 0; From patchwork Sun Mar 3 10:28:46 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Eric Woudstra X-Patchwork-Id: 13579709 X-Patchwork-Delegate: kuba@kernel.org Received: from mail-ej1-f48.google.com (mail-ej1-f48.google.com [209.85.218.48]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 27B0DB66C for ; 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[2001:1c00:20d:1300:1b1c:4449:176a:89ea]) by smtp.gmail.com with ESMTPSA id um9-20020a170906cf8900b00a44d01aff81sm1530759ejb.97.2024.03.03.02.28.58 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 03 Mar 2024 02:28:59 -0800 (PST) From: Eric Woudstra To: Andrew Lunn , Heiner Kallweit , Russell King , "David S. Miller" , Eric Dumazet , Jakub Kicinski , Paolo Abeni , =?utf-8?q?Marek_Beh=C3=BAn?= , "Frank Wunderlich" , Daniel Golle Cc: netdev@vger.kernel.org, Eric Woudstra Subject: [PATCH v2 net-next 5/7] net: phy: realtek: add rtl822x_c45_get_features() to set supported ports Date: Sun, 3 Mar 2024 11:28:46 +0100 Message-ID: <20240303102848.164108-6-ericwouds@gmail.com> X-Mailer: git-send-email 2.42.1 In-Reply-To: <20240303102848.164108-1-ericwouds@gmail.com> References: <20240303102848.164108-1-ericwouds@gmail.com> Precedence: bulk X-Mailing-List: netdev@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-Patchwork-Delegate: kuba@kernel.org Sets ETHTOOL_LINK_MODE_TP_BIT and ETHTOOL_LINK_MODE_MII_BIT in phydev->supported. Signed-off-by: Eric Woudstra --- drivers/net/phy/realtek.c | 13 +++++++++++++ 1 file changed, 13 insertions(+) diff --git a/drivers/net/phy/realtek.c b/drivers/net/phy/realtek.c index 6449d8e0842c..3dc27a4f2c88 100644 --- a/drivers/net/phy/realtek.c +++ b/drivers/net/phy/realtek.c @@ -836,6 +836,16 @@ static int rtl822x_read_status(struct phy_device *phydev) return 0; } +static int rtl822x_c45_get_features(struct phy_device *phydev) +{ + linkmode_set_bit(ETHTOOL_LINK_MODE_TP_BIT, + phydev->supported); + linkmode_set_bit(ETHTOOL_LINK_MODE_MII_BIT, + phydev->supported); + + return genphy_c45_pma_read_abilities(phydev); +} + static int rtl822x_c45_config_aneg(struct phy_device *phydev) { bool changed = false; @@ -1267,6 +1277,7 @@ static struct phy_driver realtek_drvs[] = { .name = "RTL8221B-VB-CG 2.5Gbps PHY (C45)", .config_init = rtl822x_config_init, .get_rate_matching = rtl822x_get_rate_matching, + .get_features = rtl822x_c45_get_features, .config_aneg = rtl822x_c45_config_aneg, .read_status = rtl822x_c45_read_status, .suspend = genphy_c45_pma_suspend, @@ -1288,6 +1299,7 @@ static struct phy_driver realtek_drvs[] = { .name = "RTL8221B-VN-CG 2.5Gbps PHY (C45)", .config_init = rtl822x_config_init, .get_rate_matching = rtl822x_get_rate_matching, + .get_features = rtl822x_c45_get_features, .config_aneg = rtl822x_c45_config_aneg, .read_status = rtl822x_c45_read_status, .suspend = genphy_c45_pma_suspend, @@ -1309,6 +1321,7 @@ static struct phy_driver realtek_drvs[] = { .name = "RTL8251B 5Gbps PHY (C45)", .config_init = rtl822x_config_init, .get_rate_matching = rtl822x_get_rate_matching, + .get_features = rtl822x_c45_get_features, .config_aneg = rtl822x_c45_config_aneg, .read_status = rtl822x_c45_read_status, .suspend = genphy_c45_pma_suspend, From patchwork Sun Mar 3 10:28:47 2024 Content-Type: text/plain; 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[2001:1c00:20d:1300:1b1c:4449:176a:89ea]) by smtp.gmail.com with ESMTPSA id um9-20020a170906cf8900b00a44d01aff81sm1530759ejb.97.2024.03.03.02.28.59 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 03 Mar 2024 02:29:00 -0800 (PST) From: Eric Woudstra To: Andrew Lunn , Heiner Kallweit , Russell King , "David S. Miller" , Eric Dumazet , Jakub Kicinski , Paolo Abeni , =?utf-8?q?Marek_Beh=C3=BAn?= , "Frank Wunderlich" , Daniel Golle Cc: netdev@vger.kernel.org, Eric Woudstra Subject: [PATCH v2 net-next 6/7] net: sfp: Fixup for OEM SFP-2.5G-T module Date: Sun, 3 Mar 2024 11:28:47 +0100 Message-ID: <20240303102848.164108-7-ericwouds@gmail.com> X-Mailer: git-send-email 2.42.1 In-Reply-To: <20240303102848.164108-1-ericwouds@gmail.com> References: <20240303102848.164108-1-ericwouds@gmail.com> Precedence: bulk X-Mailing-List: netdev@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-Patchwork-Delegate: kuba@kernel.org Change from quirk to fixup for the OEM SFP-2.5G-T module. Implementing this fixup, the rtl8221b phy is attached and the quirk is no longer used. The module is re-branded to different brands, the one I have that applies to this patch is branded LuLeey. Signed-off-by: Eric Woudstra --- drivers/net/phy/sfp.c | 9 ++++++++- 1 file changed, 8 insertions(+), 1 deletion(-) diff --git a/drivers/net/phy/sfp.c b/drivers/net/phy/sfp.c index f75c9eb3958e..191a6d5dc925 100644 --- a/drivers/net/phy/sfp.c +++ b/drivers/net/phy/sfp.c @@ -385,6 +385,13 @@ static void sfp_fixup_rollball(struct sfp *sfp) sfp->phy_t_retry = msecs_to_jiffies(1000); } +// For 2.5GBASE-T short-reach modules +static void sfp_fixup_oem_2_5gbaset(struct sfp *sfp) +{ + sfp_fixup_rollball(sfp); + sfp->id.base.extended_cc = SFF8024_ECC_2_5GBASE_T; +} + static void sfp_fixup_fs_10gt(struct sfp *sfp) { sfp_fixup_10gbaset_30m(sfp); @@ -503,7 +510,7 @@ static const struct sfp_quirk sfp_quirks[] = { SFP_QUIRK_F("Walsun", "HXSX-ATRI-1", sfp_fixup_fs_10gt), SFP_QUIRK_F("OEM", "SFP-10G-T", sfp_fixup_rollball_cc), - SFP_QUIRK_M("OEM", "SFP-2.5G-T", sfp_quirk_oem_2_5g), + SFP_QUIRK_F("OEM", "SFP-2.5G-T", sfp_fixup_oem_2_5gbaset), SFP_QUIRK_F("OEM", "RTSFP-10", sfp_fixup_rollball_cc), SFP_QUIRK_F("OEM", "RTSFP-10G", sfp_fixup_rollball_cc), SFP_QUIRK_F("Turris", "RTSFP-10", sfp_fixup_rollball), From patchwork Sun Mar 3 10:28:48 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Eric Woudstra X-Patchwork-Id: 13579711 X-Patchwork-Delegate: kuba@kernel.org Received: from mail-ej1-f50.google.com (mail-ej1-f50.google.com [209.85.218.50]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id E7EB9D533 for ; Sun, 3 Mar 2024 10:29:02 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.218.50 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1709461744; cv=none; b=ZTHqR0hKfxSVC3Z3zqCAYAQnv/fk8UuwD1XpHzke5C5s8zxsHcnT984xins48ok6vN2CmEBrOhuHBTibrZzZ11y2WE09okDyNhICycWtUQfq0S2QWBIkFMO/qMoJvaPx0ivYWlGR0m78KXX94mvH7e9tDuLNpZnCaQZBsNDQJL0= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1709461744; c=relaxed/simple; bh=/1jyHaKRxoe2gJnQbVyw3On1Pupt2uNMBdeMhD+Sm5U=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=gpuxRKyKhu3Hb+F/r7k+rrRKkWI4Lt5Qtl7eBRu5Ton6A7tf3YxMIASsT3JO8e9MHDMvVryvLodMbWyEEra99bvHfam/88BAHxmuDg1bP+7o+U0MdB738hpcVMJdsCIRj3SgI6Ie41Xb6kkmCqWdxKqhmV7PzXVWPK1uj14Xwsw= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=gmail.com; spf=pass smtp.mailfrom=gmail.com; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b=eGmz01Ff; arc=none smtp.client-ip=209.85.218.50 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=gmail.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=gmail.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b="eGmz01Ff" Received: by mail-ej1-f50.google.com with SMTP id a640c23a62f3a-a4429c556efso518129066b.0 for ; Sun, 03 Mar 2024 02:29:02 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20230601; t=1709461741; x=1710066541; darn=vger.kernel.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=tdYv15OqlzJBxWgsRDR/eNfMjbnPdFi6xhD8GveF+FA=; b=eGmz01FfqXkB45TssYgDSuDIPDiwGL0KZFL24027sFuOv9zNpJH0b7KmR7t/qtNN7q oY3HeiwRDj4Z3TOnM+90UJnybz3bu4I3hbGgNpWFgPX4zDn1tJ+KlIGYHt83E3gGNjts jHz6G4VCo/wyCrvggmU4ZeYPDQ2mAy2kmvOD83Lm28D0ePf7J8Q+JrH1rhGrwZq3+hQO Mb6bo40u7KSkcaWeeJKShVbWu10aiNW7o8u3+ZN0UC6bfJ3zbS//Ig/ht4Tfweq+70Vd 4G4iImQGX6dBBuVDNHrf1kxTVBJMwMnNyK4V0L25RHUmYRB+mXbRE8DLj5Ucx4RlgxYp M0+w== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1709461741; x=1710066541; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=tdYv15OqlzJBxWgsRDR/eNfMjbnPdFi6xhD8GveF+FA=; b=f7r0iqPW6DeZILDg/4Zqya4VeY1bhZK2ESBa//6dII8VQjuUslksklASD2+PxBWD7T PoanF2A7qfvjXzcITvrg1FaI9Zkgd1s/6HFAQBTaqXzsd4OeiAhS4/aROfzl9E9206Fg ONnF41SVD605+Q3Ww/D8uCvf7glMGIlKevYCQGxG0r7qRqLchLBd1a/rEZsh9OxG3Nmq bWP64uVcru0jlwlEzwJQ983b0i/pfiytw/EApOST2YAeVwVLKsNyl8QR8gzFnvT9lr6C 5Q2nIdmKuk45UZp2a70GRV343CXRXL1+BJaiBSjf6D56l+jOi1GcWZqsZQTiZnNIiJ3G QFnA== X-Gm-Message-State: AOJu0YzfLJZp0bG8gUdhYncLFzFbRjUQiKPfJSWMc9+yHJsNqJT1JinK tZG5bqeLtc/XlFmbkUZwsai3khubE43JMAZvNAlKbbDFcyWpz8wM X-Google-Smtp-Source: AGHT+IFcNLmNBJAqhxRjDnbeKVm4OVvH7PkCOyXgQRWHafQPCeDex5bORKS3npAWkmSZyv3czqOnig== X-Received: by 2002:a17:906:34d7:b0:a45:29f3:6cc9 with SMTP id h23-20020a17090634d700b00a4529f36cc9mr465909ejb.20.1709461741275; Sun, 03 Mar 2024 02:29:01 -0800 (PST) Received: from corebook.localdomain (2001-1c00-020d-1300-1b1c-4449-176a-89ea.cable.dynamic.v6.ziggo.nl. [2001:1c00:20d:1300:1b1c:4449:176a:89ea]) by smtp.gmail.com with ESMTPSA id um9-20020a170906cf8900b00a44d01aff81sm1530759ejb.97.2024.03.03.02.29.00 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 03 Mar 2024 02:29:00 -0800 (PST) From: Eric Woudstra To: Andrew Lunn , Heiner Kallweit , Russell King , "David S. Miller" , Eric Dumazet , Jakub Kicinski , Paolo Abeni , =?utf-8?q?Marek_Beh=C3=BAn?= , "Frank Wunderlich" , Daniel Golle Cc: netdev@vger.kernel.org, Eric Woudstra Subject: [PATCH v2 net-next 7/7] net: sfp: add quirk for another multigig RollBall transceiver Date: Sun, 3 Mar 2024 11:28:48 +0100 Message-ID: <20240303102848.164108-8-ericwouds@gmail.com> X-Mailer: git-send-email 2.42.1 In-Reply-To: <20240303102848.164108-1-ericwouds@gmail.com> References: <20240303102848.164108-1-ericwouds@gmail.com> Precedence: bulk X-Mailing-List: netdev@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-Patchwork-Delegate: kuba@kernel.org From: Marek Behún Add quirk for another RollBall copper transceiver: Turris RTSFP-2.5G, containing 2.5g capable RTL8221B PHY. Signed-off-by: Marek Behún Signed-off-by: Eric Woudstra --- drivers/net/phy/sfp.c | 1 + 1 file changed, 1 insertion(+) diff --git a/drivers/net/phy/sfp.c b/drivers/net/phy/sfp.c index 191a6d5dc925..0476624bbca6 100644 --- a/drivers/net/phy/sfp.c +++ b/drivers/net/phy/sfp.c @@ -513,6 +513,7 @@ static const struct sfp_quirk sfp_quirks[] = { SFP_QUIRK_F("OEM", "SFP-2.5G-T", sfp_fixup_oem_2_5gbaset), SFP_QUIRK_F("OEM", "RTSFP-10", sfp_fixup_rollball_cc), SFP_QUIRK_F("OEM", "RTSFP-10G", sfp_fixup_rollball_cc), + SFP_QUIRK_F("Turris", "RTSFP-2.5G", sfp_fixup_rollball), SFP_QUIRK_F("Turris", "RTSFP-10", sfp_fixup_rollball), SFP_QUIRK_F("Turris", "RTSFP-10G", sfp_fixup_rollball), };