From patchwork Tue Mar 5 18:39:18 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Biju Das X-Patchwork-Id: 13582841 X-Patchwork-Delegate: geert@linux-m68k.org Received: from relmlie5.idc.renesas.com (relmlor1.renesas.com [210.160.252.171]) by smtp.subspace.kernel.org (Postfix) with ESMTP id F27DC179AB for ; Tue, 5 Mar 2024 18:39:37 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=210.160.252.171 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1709663980; cv=none; b=h2y8/xd7e1CzU/E4J0BGqrqXNZkjdD1VQPV6VNdkTgogqG5efy+j6XS8k1Ajhbia6ADFmslvaaE65Y90hKCnoa5EUmjKHzEBx4YQZeZifVCP9PeUnkaFIWwN9jtrnqw/Rh6j2U5ztqmNEnSsSjBmN+hU/MZ1C+5Z8zb+DrlKLH8= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1709663980; c=relaxed/simple; bh=2bREaKTLqOh8r/VPFsqtGB9u04i/XY0mNtQd6Qb9ByE=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=XABWfA+FEMDRX0kqAc2LGEsJNTcHj5Muh3sZ7bipV2h4K2/Q2hPcSg+uV9T/IpRk9AbpFxhABya0vwKJDAXU+ufKDkYVL4/+wE05/FVQF5+P8Q2x1+Fp2e7wh9K7ta51Ai28IHWpC32pqNWjjdZoRG/ZsIyuX1T3jx+xyE7DbCg= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=bp.renesas.com; spf=pass smtp.mailfrom=bp.renesas.com; arc=none smtp.client-ip=210.160.252.171 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=bp.renesas.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=bp.renesas.com X-IronPort-AV: E=Sophos;i="6.06,206,1705330800"; d="scan'208";a="196498258" Received: from unknown (HELO relmlir5.idc.renesas.com) ([10.200.68.151]) by relmlie5.idc.renesas.com with ESMTP; 06 Mar 2024 03:39:31 +0900 Received: from localhost.localdomain (unknown [10.226.92.185]) by relmlir5.idc.renesas.com (Postfix) with ESMTP id 6AA4F4003ED1; Wed, 6 Mar 2024 03:39:29 +0900 (JST) From: Biju Das To: Thomas Gleixner Cc: Biju Das , Marc Zyngier , Lad Prabhakar , Geert Uytterhoeven , Biju Das , linux-renesas-soc@vger.kernel.org Subject: [PATCH v2 1/5] irqchip/renesas-rzg2l: Flush posted write Date: Tue, 5 Mar 2024 18:39:18 +0000 Message-Id: <20240305183922.138727-2-biju.das.jz@bp.renesas.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20240305183922.138727-1-biju.das.jz@bp.renesas.com> References: <20240305183922.138727-1-biju.das.jz@bp.renesas.com> Precedence: bulk X-Mailing-List: linux-renesas-soc@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 The irq_eoi() callback of the RZ/G2L interrupt chip clears the relevant interrupt cause bit in the TSCR register. This write is not sufficient because the write is posted and therefore not guaranteed to immediately clear the bit. Due to that delay the CPU can raise the just handled interrupt again. Prevent this by reading the register back which causes the posted write to be flushed to the hardware before the read completes. Fixes: 3fed09559cd8 ("irqchip: Add RZ/G2L IA55 Interrupt Controller driver") Signed-off-by: Biju Das --- v1->v2: * Updated commit header and description. * Extended the flushing of posted write to IRQ interrupt aswell. --- drivers/irqchip/irq-renesas-rzg2l.c | 16 ++++++++++++++-- 1 file changed, 14 insertions(+), 2 deletions(-) diff --git a/drivers/irqchip/irq-renesas-rzg2l.c b/drivers/irqchip/irq-renesas-rzg2l.c index 9494fc26259c..5285bc817dd0 100644 --- a/drivers/irqchip/irq-renesas-rzg2l.c +++ b/drivers/irqchip/irq-renesas-rzg2l.c @@ -99,8 +99,14 @@ static void rzg2l_irq_eoi(struct irq_data *d) * ISCR can only be cleared if the type is falling-edge, rising-edge or * falling/rising-edge. */ - if ((iscr & bit) && (iitsr & IITSR_IITSEL_MASK(hw_irq))) + if ((iscr & bit) && (iitsr & IITSR_IITSEL_MASK(hw_irq))) { writel_relaxed(iscr & ~bit, priv->base + ISCR); + /* + * Enforce that the posted write is flushed to prevent that the + * just handled interrupt is raised again. + */ + readl_relaxed(priv->base + ISCR); + } } static void rzg2l_tint_eoi(struct irq_data *d) @@ -111,8 +117,14 @@ static void rzg2l_tint_eoi(struct irq_data *d) u32 reg; reg = readl_relaxed(priv->base + TSCR); - if (reg & bit) + if (reg & bit) { writel_relaxed(reg & ~bit, priv->base + TSCR); + /* + * Enforce that the posted write is flushed to prevent that the + * just handled interrupt is raised again. + */ + readl_relaxed(priv->base + TSCR); + } } static void rzg2l_irqc_eoi(struct irq_data *d) From patchwork Tue Mar 5 18:39:19 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Biju Das X-Patchwork-Id: 13582843 X-Patchwork-Delegate: geert@linux-m68k.org Received: from relmlie5.idc.renesas.com (relmlor1.renesas.com [210.160.252.171]) by smtp.subspace.kernel.org (Postfix) with ESMTP id EE843179AB for ; Tue, 5 Mar 2024 18:39:40 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=210.160.252.171 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1709663982; cv=none; b=vFAUqQhRSrJ11q4EWeAipjXp3gDkdzXTLt6mK9JOqdultpWkhMHtB/pKbpfozL16xjmLY9wtrRsv6YoF6aiMzR7uxotOL/ln60RegosMs+UcO5fBO4yHPAe68uqUSCwZFljK/5dwsnhB/UnAh8b3EnYrWeID/AF6rZ5RZZrXDTk= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1709663982; c=relaxed/simple; bh=UEJ+bSs34iK5yxlaOnTeseC+luyjQhCS//7FhqU4dOo=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=o5wUN2sOzMxitoT33Fa/GtkbAIemWJa56qyXk/VD5M9ZQST/SK+GzJGTP2guCX7lQcisVVdLr4IeiJ7f7Wemq4HXFXhL03uHYqMVRRGtDLJ1/W6dD11Y3FJ1Brp+fn6JxzKoBAzzNye4fAQ+AOr+pzBjNMVk8nCXg0lN3iptRdc= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=bp.renesas.com; spf=pass smtp.mailfrom=bp.renesas.com; arc=none smtp.client-ip=210.160.252.171 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=bp.renesas.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=bp.renesas.com X-IronPort-AV: E=Sophos;i="6.06,206,1705330800"; d="scan'208";a="196498261" Received: from unknown (HELO relmlir5.idc.renesas.com) ([10.200.68.151]) by relmlie5.idc.renesas.com with ESMTP; 06 Mar 2024 03:39:34 +0900 Received: from localhost.localdomain (unknown [10.226.92.185]) by relmlir5.idc.renesas.com (Postfix) with ESMTP id 101B34003ED1; Wed, 6 Mar 2024 03:39:31 +0900 (JST) From: Biju Das To: Thomas Gleixner Cc: Biju Das , Marc Zyngier , Lad Prabhakar , Geert Uytterhoeven , Biju Das , linux-renesas-soc@vger.kernel.org Subject: [PATCH v2 2/5] irqchip/renesas-rzg2l: Rename rzg2l_tint_eoi() Date: Tue, 5 Mar 2024 18:39:19 +0000 Message-Id: <20240305183922.138727-3-biju.das.jz@bp.renesas.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20240305183922.138727-1-biju.das.jz@bp.renesas.com> References: <20240305183922.138727-1-biju.das.jz@bp.renesas.com> Precedence: bulk X-Mailing-List: linux-renesas-soc@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Rename rzg2l_tint_eoi()->rzg2l_clear_tint_int() and simplify the code by removing redundant priv and hw_irq local variables. Signed-off-by: Biju Das Reviewed-by: Geert Uytterhoeven --- v1->v2: * Updated commit description rzg2l_tint_eoi()->rzg2l_clear_tint_int(). * Added Rb tag from Geert. --- drivers/irqchip/irq-renesas-rzg2l.c | 8 +++----- 1 file changed, 3 insertions(+), 5 deletions(-) diff --git a/drivers/irqchip/irq-renesas-rzg2l.c b/drivers/irqchip/irq-renesas-rzg2l.c index 5285bc817dd0..599e0aba5cc0 100644 --- a/drivers/irqchip/irq-renesas-rzg2l.c +++ b/drivers/irqchip/irq-renesas-rzg2l.c @@ -109,11 +109,9 @@ static void rzg2l_irq_eoi(struct irq_data *d) } } -static void rzg2l_tint_eoi(struct irq_data *d) +static void rzg2l_clear_tint_int(struct rzg2l_irqc_priv *priv, unsigned int hwirq) { - unsigned int hw_irq = irqd_to_hwirq(d) - IRQC_TINT_START; - struct rzg2l_irqc_priv *priv = irq_data_to_priv(d); - u32 bit = BIT(hw_irq); + u32 bit = BIT(hwirq - IRQC_TINT_START); u32 reg; reg = readl_relaxed(priv->base + TSCR); @@ -136,7 +134,7 @@ static void rzg2l_irqc_eoi(struct irq_data *d) if (hw_irq >= IRQC_IRQ_START && hw_irq <= IRQC_IRQ_COUNT) rzg2l_irq_eoi(d); else if (hw_irq >= IRQC_TINT_START && hw_irq < IRQC_NUM_IRQ) - rzg2l_tint_eoi(d); + rzg2l_clear_tint_int(priv, hw_irq); raw_spin_unlock(&priv->lock); irq_chip_eoi_parent(d); } From patchwork Tue Mar 5 18:39:20 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Biju Das X-Patchwork-Id: 13582840 X-Patchwork-Delegate: geert@linux-m68k.org Received: from relmlie6.idc.renesas.com (relmlor2.renesas.com [210.160.252.172]) by smtp.subspace.kernel.org (Postfix) with ESMTP id E7BD114A8D for ; Tue, 5 Mar 2024 18:39:37 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=210.160.252.172 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1709663979; cv=none; b=DhJcoovzI1GJzi5m9QTkwomIYyMfxIxF++tp23MAvAiVxABY+jKA3/rPNqcaSGkK9eUxto6Uj4PfGdQVG0LI5FxE4v/iJIr8izMnL7xAiC+UsEdhgsoNluo+bdiwbFHq8nydykuabTGpyKDSndkoB9MvYZ4Yot1IqkWHNcqEOQM= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1709663979; c=relaxed/simple; bh=ahazKZKOviH4mPbZcEO6wWTF8NcreQPhkrWjL4vqsGY=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=skN5H5k7Dz0yJumx9q98z6XBLiqxfPZBtwCBq5wVjRaBePYrGFu1y/1aII/vnZC44A/FSlz8af7XNbFaBZwJtkJ9qSso/VwwhI+NWJSYkdQa6dg5+B+w/Jysa+QryJUOBUoDTrZM8i5J5sEH30kTbnv4QggABesFXh4t3pCyOR4= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=bp.renesas.com; spf=pass smtp.mailfrom=bp.renesas.com; arc=none smtp.client-ip=210.160.252.172 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=bp.renesas.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=bp.renesas.com X-IronPort-AV: E=Sophos;i="6.06,206,1705330800"; d="scan'208";a="200436907" Received: from unknown (HELO relmlir5.idc.renesas.com) ([10.200.68.151]) by relmlie6.idc.renesas.com with ESMTP; 06 Mar 2024 03:39:36 +0900 Received: from localhost.localdomain (unknown [10.226.92.185]) by relmlir5.idc.renesas.com (Postfix) with ESMTP id AFD894003ED1; Wed, 6 Mar 2024 03:39:34 +0900 (JST) From: Biju Das To: Thomas Gleixner Cc: Biju Das , Marc Zyngier , Lad Prabhakar , Geert Uytterhoeven , Biju Das , linux-renesas-soc@vger.kernel.org Subject: [PATCH v2 3/5] irqchip/renesas-rzg2l: Rename rzg2l_irq_eoi() Date: Tue, 5 Mar 2024 18:39:20 +0000 Message-Id: <20240305183922.138727-4-biju.das.jz@bp.renesas.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20240305183922.138727-1-biju.das.jz@bp.renesas.com> References: <20240305183922.138727-1-biju.das.jz@bp.renesas.com> Precedence: bulk X-Mailing-List: linux-renesas-soc@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Rename rzg2l_irq_eoi()->rzg2l_clear_irq_int() and simplify the code by removing redundant priv local variable. Suggested-by: Geert Uytterhoeven Signed-off-by: Biju Das --- v1->v2: * New patch. --- drivers/irqchip/irq-renesas-rzg2l.c | 7 +++---- 1 file changed, 3 insertions(+), 4 deletions(-) diff --git a/drivers/irqchip/irq-renesas-rzg2l.c b/drivers/irqchip/irq-renesas-rzg2l.c index 599e0aba5cc0..8133f05590b6 100644 --- a/drivers/irqchip/irq-renesas-rzg2l.c +++ b/drivers/irqchip/irq-renesas-rzg2l.c @@ -85,10 +85,9 @@ static struct rzg2l_irqc_priv *irq_data_to_priv(struct irq_data *data) return data->domain->host_data; } -static void rzg2l_irq_eoi(struct irq_data *d) +static void rzg2l_clear_irq_int(struct rzg2l_irqc_priv *priv, unsigned int hwirq) { - unsigned int hw_irq = irqd_to_hwirq(d) - IRQC_IRQ_START; - struct rzg2l_irqc_priv *priv = irq_data_to_priv(d); + unsigned int hw_irq = hwirq - IRQC_IRQ_START; u32 bit = BIT(hw_irq); u32 iitsr, iscr; @@ -132,7 +131,7 @@ static void rzg2l_irqc_eoi(struct irq_data *d) raw_spin_lock(&priv->lock); if (hw_irq >= IRQC_IRQ_START && hw_irq <= IRQC_IRQ_COUNT) - rzg2l_irq_eoi(d); + rzg2l_clear_irq_int(priv, hw_irq); else if (hw_irq >= IRQC_TINT_START && hw_irq < IRQC_NUM_IRQ) rzg2l_clear_tint_int(priv, hw_irq); raw_spin_unlock(&priv->lock); From patchwork Tue Mar 5 18:39:21 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Biju Das X-Patchwork-Id: 13582842 X-Patchwork-Delegate: geert@linux-m68k.org Received: from relmlie6.idc.renesas.com (relmlor2.renesas.com [210.160.252.172]) by smtp.subspace.kernel.org (Postfix) with ESMTP id B10A41426F for ; Tue, 5 Mar 2024 18:39:39 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=210.160.252.172 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1709663981; cv=none; b=qpw6nN+6U/anGwvLJGECFDkl0Adef+bvxIMK7+nJ4BjU4rKzkQHHSTbyhJPGEAeYH28RL1e2rVFRYabd5Jxudp4R/r3H7ndZtBR/CJhLQfqKHeVgsnqIfvOCUZVLk1kkWJLFwgxr5hiAaYFhjEI+Nz6Tzbp5Lcbw/ykL8uFGzy0= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1709663981; c=relaxed/simple; bh=2Pr8PMAMW8RrhjX5cQ4ZX7nTzQ+0t0yWSvhfMDCrQD8=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=a9HdThu9xjn27NZKpSaXBxEJasf0FAFT5j3xZ08OVCEeL9Toa76fOtYDpUnxtUTFcGobmIUnH5iAm7bUfyJTq1qDuskaDjO15lKs5hM/V+MyybtIHcnwUOsRXKw6I37WcF8069gm+PfWxsMtcqFolP+tJ5YsD3o/dLv2u+2an9Y= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=bp.renesas.com; spf=pass smtp.mailfrom=bp.renesas.com; arc=none smtp.client-ip=210.160.252.172 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=bp.renesas.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=bp.renesas.com X-IronPort-AV: E=Sophos;i="6.06,206,1705330800"; d="scan'208";a="200436912" Received: from unknown (HELO relmlir5.idc.renesas.com) ([10.200.68.151]) by relmlie6.idc.renesas.com with ESMTP; 06 Mar 2024 03:39:39 +0900 Received: from localhost.localdomain (unknown [10.226.92.185]) by relmlir5.idc.renesas.com (Postfix) with ESMTP id 578774003ED1; Wed, 6 Mar 2024 03:39:37 +0900 (JST) From: Biju Das To: Thomas Gleixner Cc: Biju Das , Marc Zyngier , Lad Prabhakar , Geert Uytterhoeven , Biju Das , linux-renesas-soc@vger.kernel.org Subject: [PATCH v2 4/5] irqchip/renesas-rzg2l: Fix spurious IRQ Date: Tue, 5 Mar 2024 18:39:21 +0000 Message-Id: <20240305183922.138727-5-biju.das.jz@bp.renesas.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20240305183922.138727-1-biju.das.jz@bp.renesas.com> References: <20240305183922.138727-1-biju.das.jz@bp.renesas.com> Precedence: bulk X-Mailing-List: linux-renesas-soc@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 On RZ/G2L interrupt chip, interrupt masking is required before changing the NMI, IRQ, TINT interrupt settings. Apart from this, after setting the edge type it is required to clear interrupt status register in order to avoid spurious IRQ. For IRQ edge type, use raw_spin_lock()->raw_spin_lock_irqsave() and in case of TINT edge type use TIEN for interrupt masking. Then set the interrupt detection register followed by clearing interrupt status register to fix the spurious IRQ. Fixes: 3fed09559cd8 ("irqchip: Add RZ/G2L IA55 Interrupt Controller driver") Signed-off-by: Biju Das --- v1->v2: * Updated commit header and description. * Extended spurious IRQ fix to IRQ as well. * Updated the logic for rzg2l_disable_tint_and_set_tint_source() and rzg2l_tint_set_edge(). --- drivers/irqchip/irq-renesas-rzg2l.c | 41 ++++++++++++++++++++++++----- 1 file changed, 35 insertions(+), 6 deletions(-) diff --git a/drivers/irqchip/irq-renesas-rzg2l.c b/drivers/irqchip/irq-renesas-rzg2l.c index 8133f05590b6..e793b8f07dac 100644 --- a/drivers/irqchip/irq-renesas-rzg2l.c +++ b/drivers/irqchip/irq-renesas-rzg2l.c @@ -181,8 +181,11 @@ static void rzg2l_irqc_irq_enable(struct irq_data *d) static int rzg2l_irq_set_type(struct irq_data *d, unsigned int type) { - unsigned int hw_irq = irqd_to_hwirq(d) - IRQC_IRQ_START; struct rzg2l_irqc_priv *priv = irq_data_to_priv(d); + unsigned int hwirq = irqd_to_hwirq(d); + u32 iitseln = hwirq - IRQC_IRQ_START; + bool clear_irq_int = false; + unsigned long flags; u16 sense, tmp; switch (type & IRQ_TYPE_SENSE_MASK) { @@ -192,37 +195,59 @@ static int rzg2l_irq_set_type(struct irq_data *d, unsigned int type) case IRQ_TYPE_EDGE_FALLING: sense = IITSR_IITSEL_EDGE_FALLING; + clear_irq_int = true; break; case IRQ_TYPE_EDGE_RISING: sense = IITSR_IITSEL_EDGE_RISING; + clear_irq_int = true; break; case IRQ_TYPE_EDGE_BOTH: sense = IITSR_IITSEL_EDGE_BOTH; + clear_irq_int = true; break; default: return -EINVAL; } - raw_spin_lock(&priv->lock); + raw_spin_lock_irqsave(&priv->lock, flags); tmp = readl_relaxed(priv->base + IITSR); - tmp &= ~IITSR_IITSEL_MASK(hw_irq); - tmp |= IITSR_IITSEL(hw_irq, sense); + tmp &= ~IITSR_IITSEL_MASK(iitseln); + tmp |= IITSR_IITSEL(iitseln, sense); + if (clear_irq_int) + rzg2l_clear_irq_int(priv, hwirq); writel_relaxed(tmp, priv->base + IITSR); - raw_spin_unlock(&priv->lock); + raw_spin_unlock_irqrestore(&priv->lock, flags); return 0; } +static u32 rzg2l_disable_tint_and_set_tint_source(struct irq_data *d, struct rzg2l_irqc_priv *priv, + u32 reg, u32 tssr_offset, u8 tssr_index) +{ + u32 tint = (u32)(uintptr_t)irq_data_get_irq_chip_data(d); + u32 tien = reg & (TIEN << TSSEL_SHIFT(tssr_offset)); + + /* Clear the relevant byte in reg */ + reg &= ~(TSSEL_MASK << TSSEL_SHIFT(tssr_offset)); + /* Set TINT and leave TIEN clear */ + reg |= tint << TSSEL_SHIFT(tssr_offset); + writel_relaxed(reg, priv->base + TSSR(tssr_index)); + + return reg | tien; +} + static int rzg2l_tint_set_edge(struct irq_data *d, unsigned int type) { struct rzg2l_irqc_priv *priv = irq_data_to_priv(d); unsigned int hwirq = irqd_to_hwirq(d); u32 titseln = hwirq - IRQC_TINT_START; + u32 tssr_offset = TSSR_OFFSET(titseln); + u8 tssr_index = TSSR_INDEX(titseln); u8 index, sense; - u32 reg; + u32 reg, tssr; switch (type & IRQ_TYPE_SENSE_MASK) { case IRQ_TYPE_EDGE_RISING: @@ -244,10 +269,14 @@ static int rzg2l_tint_set_edge(struct irq_data *d, unsigned int type) } raw_spin_lock(&priv->lock); + tssr = readl_relaxed(priv->base + TSSR(tssr_index)); + tssr = rzg2l_disable_tint_and_set_tint_source(d, priv, tssr, tssr_offset, tssr_index); reg = readl_relaxed(priv->base + TITSR(index)); reg &= ~(IRQ_MASK << (titseln * TITSEL_WIDTH)); reg |= sense << (titseln * TITSEL_WIDTH); writel_relaxed(reg, priv->base + TITSR(index)); + rzg2l_clear_tint_int(priv, hwirq); + writel_relaxed(tssr, priv->base + TSSR(tssr_index)); raw_spin_unlock(&priv->lock); return 0; From patchwork Tue Mar 5 18:39:22 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Biju Das X-Patchwork-Id: 13582844 X-Patchwork-Delegate: geert@linux-m68k.org Received: from relmlie5.idc.renesas.com (relmlor1.renesas.com [210.160.252.171]) by smtp.subspace.kernel.org (Postfix) with ESMTP id 2E4CF14A8D for ; Tue, 5 Mar 2024 18:39:42 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=210.160.252.171 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1709663985; cv=none; b=hPUfAXhPKzCoqvDwWNM3cm7SXJShZR7NtH1+RGXdxdQHtQFSCaixXg1uA5PE0rbcqDAL0zQ9NHGKUOb1iO9nJSG9znNxrkYMTdwoGPLe5toiwM5KzL9WVqssWWQDuJGHeRX6jRdihRbWKlcGRuYF6wSJ1V3rzFXNImEslDsWvHY= ARC-Message-Signature: i=1; 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Wed, 6 Mar 2024 03:39:39 +0900 (JST) From: Biju Das To: Thomas Gleixner Cc: Biju Das , Marc Zyngier , Lad Prabhakar , Geert Uytterhoeven , Biju Das , linux-renesas-soc@vger.kernel.org Subject: [PATCH v2 5/5] irqchip/renesas-rzg2l: Use TIEN for enable/disable Date: Tue, 5 Mar 2024 18:39:22 +0000 Message-Id: <20240305183922.138727-6-biju.das.jz@bp.renesas.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20240305183922.138727-1-biju.das.jz@bp.renesas.com> References: <20240305183922.138727-1-biju.das.jz@bp.renesas.com> Precedence: bulk X-Mailing-List: linux-renesas-soc@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Currently hardware settings for TINT detection is not in sync with TINT source as the enable/disable overrides source setting value leading to hardware inconsistent state. For eg: consider the case GPIOINT0 is used as TINT interrupt and configuring GPIOINT5 as edgetype. During disable the clearing of the entire bytes of TINT source selection for GPIOINT5 is same as GPIOINT0 with TIEN disabled. Other than this during enabling, the setting of GPIOINT5 with TIEN results in spurious IRQ as due to a HW race, it is possible that IP can use the TIEN with previous source value (GPIOINT0). So, it is better to just use TIEN for enable/disable and avoid modifying TINT source selection register.This will make the consistent hardware settings for detection method tied with TINT source and allows to simplify the code. Signed-off-by: Biju Das --- v1->v2: * Merged patch#4 and #5 and updated commit description. --- drivers/irqchip/irq-renesas-rzg2l.c | 29 +++++++++++------------------ 1 file changed, 11 insertions(+), 18 deletions(-) diff --git a/drivers/irqchip/irq-renesas-rzg2l.c b/drivers/irqchip/irq-renesas-rzg2l.c index e793b8f07dac..a7d47dbf7627 100644 --- a/drivers/irqchip/irq-renesas-rzg2l.c +++ b/drivers/irqchip/irq-renesas-rzg2l.c @@ -138,7 +138,7 @@ static void rzg2l_irqc_eoi(struct irq_data *d) irq_chip_eoi_parent(d); } -static void rzg2l_irqc_irq_disable(struct irq_data *d) +static void rzg2l_tint_irq_endisable(struct irq_data *d, bool enable) { unsigned int hw_irq = irqd_to_hwirq(d); @@ -151,31 +151,24 @@ static void rzg2l_irqc_irq_disable(struct irq_data *d) raw_spin_lock(&priv->lock); reg = readl_relaxed(priv->base + TSSR(tssr_index)); - reg &= ~(TSSEL_MASK << TSSEL_SHIFT(tssr_offset)); + if (enable) + reg |= TIEN << TSSEL_SHIFT(tssr_offset); + else + reg &= ~(TIEN << TSSEL_SHIFT(tssr_offset)); writel_relaxed(reg, priv->base + TSSR(tssr_index)); raw_spin_unlock(&priv->lock); } +} + +static void rzg2l_irqc_irq_disable(struct irq_data *d) +{ + rzg2l_tint_irq_endisable(d, false); irq_chip_disable_parent(d); } static void rzg2l_irqc_irq_enable(struct irq_data *d) { - unsigned int hw_irq = irqd_to_hwirq(d); - - if (hw_irq >= IRQC_TINT_START && hw_irq < IRQC_NUM_IRQ) { - unsigned long tint = (uintptr_t)irq_data_get_irq_chip_data(d); - struct rzg2l_irqc_priv *priv = irq_data_to_priv(d); - u32 offset = hw_irq - IRQC_TINT_START; - u32 tssr_offset = TSSR_OFFSET(offset); - u8 tssr_index = TSSR_INDEX(offset); - u32 reg; - - raw_spin_lock(&priv->lock); - reg = readl_relaxed(priv->base + TSSR(tssr_index)); - reg |= (TIEN | tint) << TSSEL_SHIFT(tssr_offset); - writel_relaxed(reg, priv->base + TSSR(tssr_index)); - raw_spin_unlock(&priv->lock); - } + rzg2l_tint_irq_endisable(d, true); irq_chip_enable_parent(d); }