From patchwork Sun Mar 10 19:20:59 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?J=2E_Neusch=C3=A4fer?= X-Patchwork-Id: 13588186 Received: from mout.gmx.net (mout.gmx.net [212.227.17.20]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 7098539FFB; Sun, 10 Mar 2024 19:22:13 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=212.227.17.20 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1710098535; cv=none; b=Dydgeb9VImAcfzgypIUx4LlkPC4N6SS4NX0LyQuU0SICzYMbYdFSlU8Q3enqmer3elYW+X8QX3Fh3wUb7ysmbZq5GtlVa1lKPby1sgaMzai0ulz4s97QCXqAdKcfmFy2xKTkKZFUeLWTv1j73FqYvofaam5DDJUENxjvVbrmQoQ= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1710098535; c=relaxed/simple; bh=6NrF/w77Op3jkfAxtCcQ+TosCvo0V+DYPJY4uCHzAtI=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=WtB2EC/sEmaMeg2plsIThgGb0+uc6o8VWl51PdUHtrhO2rtmosONBKSPaaDMM/Z+ZM9DU46iRM3i/j8O3LEcvI7r6EShYn+sfvnPIgIEoQJQGQBfz1y6GLhfC6TXLNswF+nWLf5TrRRwZnvutZMSd6Fm0Xwfcs+4YXoV5cSCBlU= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=gmx.net; spf=pass smtp.mailfrom=gmx.net; dkim=pass (2048-bit key) header.d=gmx.net header.i=j.neuschaefer@gmx.net header.b=el0RgnmE; arc=none smtp.client-ip=212.227.17.20 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=gmx.net Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=gmx.net Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=gmx.net header.i=j.neuschaefer@gmx.net header.b="el0RgnmE" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=gmx.net; s=s31663417; t=1710098501; x=1710703301; i=j.neuschaefer@gmx.net; bh=6NrF/w77Op3jkfAxtCcQ+TosCvo0V+DYPJY4uCHzAtI=; h=X-UI-Sender-Class:From:To:Cc:Subject:Date:In-Reply-To: References; b=el0RgnmEBLGVTPuV8h4c+rawNSxGTjZE3tV1RWq7zFI+zuuUxz5bPM9Resb3E7G2 1dkMmEGgXiB1r/lFASvolu0s8tKOx6uoFa8Po8NEXHNivz5vc8C1T9KdFOU+jBn6P sYEuxLJDFt8qN0XizCgtu3TNpN7lfe0PGdElxmf5zzcUhuWFAcbC+NptEAOfcm34O MucarEKG0eFmKqoEUtg3+YH069EeBAc8c0diljMMdpxREKORCCU9UZiH6C4UF2LJy f8/cNq+6iWQznCDrgeIxZtfcuBHkLgOVen4g48R5CoRsC4XDskq2fCwiQrgOo60TI e9HCtsLQQRaGO8G/Gw== X-UI-Sender-Class: 724b4f7f-cbec-4199-ad4e-598c01a50d3a Received: from probook ([78.35.216.168]) by mail.gmx.net (mrgmx104 [212.227.17.168]) with ESMTPSA (Nemesis) id 1MUXpQ-1rJ6Qf1PKi-00QPqP; Sun, 10 Mar 2024 20:21:41 +0100 From: =?utf-8?q?Jonathan_Neusch=C3=A4fer?= To: linux-clk@vger.kernel.org, openbmc@lists.ozlabs.org Cc: linux-kernel@vger.kernel.org, linux-watchdog@vger.kernel.org, devicetree@vger.kernel.org, =?utf-8?q?Jonathan_Neusch=C3=A4fer?= , Michael Turquette , Stephen Boyd , Rob Herring , Krzysztof Kozlowski , Avi Fishman , Tomer Maimon , Tali Perry , Patrick Venture , Nancy Yuen , Benjamin Fair , Daniel Lezcano , Thomas Gleixner , Philipp Zabel , Wim Van Sebroeck , Guenter Roeck , Christophe JAILLET , Conor Dooley , Krzysztof Kozlowski Subject: [PATCH v10 1/4] dt-bindings: clock: Add Nuvoton WPCM450 clock/reset controller Date: Sun, 10 Mar 2024 20:20:59 +0100 Message-ID: <20240310192108.2747084-2-j.neuschaefer@gmx.net> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20240310192108.2747084-1-j.neuschaefer@gmx.net> References: <20240310192108.2747084-1-j.neuschaefer@gmx.net> Precedence: bulk X-Mailing-List: linux-clk@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-Provags-ID: V03:K1:Fw14egUNoBom9w1dGp3wFN0nblRuKgnnItHG+gE0CBjhqzOwVYL 8rhmhsjwuFftEDklSccS7sU+B5EPg87KzmsE1L+JDFywVJ1hVra4oASOfnOwWFkAl7MXGX6 5NKVWFOKC2HI89sdOtSAX8HAh6RhYmzu+/okscjCJPy1kJjX+InDYIkVQDq1q7g0B1lNLai J/AC8ocnd7G/q31bJjHkA== X-Spam-Flag: NO UI-OutboundReport: notjunk:1;M01:P0:opuMrp+Apzg=;3lP/qhKFERKfRPkGJXwMP4HvzyC 3sZYaii7KWf+WcXuG+AYNpOAI6cdP0mz3UhHBIGdLAKph1CHAFpslAASAYXAw1D5nr0BYz5bx xHO+INPllMpKePoBd9461vMRHBcQCiRrX1mrgSN67i6mw5EuMnGnLl5dtN5bknj0Xb1o0D1hA zOhbGB3aCoDqlLQjoCBQF+KHrAqIdL+YSpfB7hxsH3b1MNRkgmxF0ElaCeefqzNMt4NFkMV2s kGO9J9VrgczZIovcMssp+QIS5GulA7ywXgO+35xDRb6+QLL22WgXP87VNQ10AzUSOlHJXO/uu VTeDFACW67xL+rpYzJw7zlLPaFCiH3xO9kITPz17Z6bkjwwFAHf2b4PpQBpS0fAIoDT615XzA mXuFH9hnvIQOA5lY2gXhY9f2kf3vUE+jsLCakFmQXKUakOfH+OgQP58H1oDEWe63cfaI0+bqJ CoVg6rCyPzZmc7GKpecn+gvJIkiZ/6AmUmgSeai+p24vf9Ffcno9kCe1n2sSPo64OciwQfYtJ RbAN4JlyAZCp9ZaYMfIUJ0XT2q/uMq9BbxgwP8EDtjr269doStCEYqdpYJFWt2khwy/cdY3cf zWYHrGcTx4WnnB5c/s1BP+b9U0iPdUBBA+kf1BID+cP/syQDyuFUEiW5afykVQ1Kq8/2nkvES vrWoNxq4c6n8PKcn/yXkHZptcHnS8kDJx8mGNpF1r7C6piK/nqN0r/at0l9MT5tYYvkw46nPJ uWzZF+D+t8+jBV+LfRLR1kTtc9pGhRLNqWxMCpzOpTXCwW9A4Aj/+vB4Zcp8KEaFcnfuUk6UT huirk3v4y98zwTUL0alwHxgymiPLOb11GpCmIn9De25HU= The Nuvoton WPCM450 SoC has a combined clock and reset controller. Add a devicetree binding for it, as well as definitions for the bit numbers used by it. Signed-off-by: Jonathan Neuschäfer Reviewed-by: Krzysztof Kozlowski --- v10: - no changes v9: - Remove clock-output-names in example, because it's now unnecessary due to driver improvements v5-v8: - no changes v4: - https://lore.kernel.org/lkml/20220610072141.347795-4-j.neuschaefer@gmx.net/ - Add R-b tag v3: - Change clock-output-names and clock-names from "refclk" to "ref", suggested by Krzysztof Kozlowski v2: - https://lore.kernel.org/lkml/20220429172030.398011-5-j.neuschaefer@gmx.net/ - Various improvements, suggested by Krzysztof Kozlowski v1: - https://lore.kernel.org/lkml/20220422183012.444674-5-j.neuschaefer@gmx.net/ --- .../bindings/clock/nuvoton,wpcm450-clk.yaml | 65 ++++++++++++++++++ .../dt-bindings/clock/nuvoton,wpcm450-clk.h | 67 +++++++++++++++++++ 2 files changed, 132 insertions(+) create mode 100644 Documentation/devicetree/bindings/clock/nuvoton,wpcm450-clk.yaml create mode 100644 include/dt-bindings/clock/nuvoton,wpcm450-clk.h -- 2.43.0 diff --git a/Documentation/devicetree/bindings/clock/nuvoton,wpcm450-clk.yaml b/Documentation/devicetree/bindings/clock/nuvoton,wpcm450-clk.yaml new file mode 100644 index 00000000000000..93521cf68a040f --- /dev/null +++ b/Documentation/devicetree/bindings/clock/nuvoton,wpcm450-clk.yaml @@ -0,0 +1,65 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/clock/nuvoton,wpcm450-clk.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Nuvoton WPCM450 clock controller + +maintainers: + - Jonathan Neuschäfer + +description: + The clock controller of the Nuvoton WPCM450 SoC supplies clocks and resets to + the rest of the chip. + +properties: + compatible: + const: nuvoton,wpcm450-clk + + reg: + maxItems: 1 + + clocks: + items: + - description: Reference clock oscillator (should be 48 MHz) + + clock-names: + items: + - const: ref + + '#clock-cells': + const: 1 + + '#reset-cells': + const: 1 + +additionalProperties: false + +required: + - compatible + - reg + - clocks + - clock-names + - '#clock-cells' + +examples: + - | + #include + #include + + refclk: clock-48mhz { + /* 48 MHz reference oscillator */ + compatible = "fixed-clock"; + clock-frequency = <48000000>; + #clock-cells = <0>; + }; + + clk: clock-controller@b0000200 { + reg = <0xb0000200 0x100>; + compatible = "nuvoton,wpcm450-clk"; + clocks = <&refclk>; + clock-names = "ref"; + #clock-cells = <1>; + #reset-cells = <1>; + }; diff --git a/include/dt-bindings/clock/nuvoton,wpcm450-clk.h b/include/dt-bindings/clock/nuvoton,wpcm450-clk.h new file mode 100644 index 00000000000000..86e1c895921b71 --- /dev/null +++ b/include/dt-bindings/clock/nuvoton,wpcm450-clk.h @@ -0,0 +1,67 @@ +/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */ + +#ifndef _DT_BINDINGS_CLOCK_NUVOTON_WPCM450_CLK_H +#define _DT_BINDINGS_CLOCK_NUVOTON_WPCM450_CLK_H + +/* Clocks based on CLKEN bits */ +#define WPCM450_CLK_FIU 0 +#define WPCM450_CLK_XBUS 1 +#define WPCM450_CLK_KCS 2 +#define WPCM450_CLK_SHM 4 +#define WPCM450_CLK_USB1 5 +#define WPCM450_CLK_EMC0 6 +#define WPCM450_CLK_EMC1 7 +#define WPCM450_CLK_USB0 8 +#define WPCM450_CLK_PECI 9 +#define WPCM450_CLK_AES 10 +#define WPCM450_CLK_UART0 11 +#define WPCM450_CLK_UART1 12 +#define WPCM450_CLK_SMB2 13 +#define WPCM450_CLK_SMB3 14 +#define WPCM450_CLK_SMB4 15 +#define WPCM450_CLK_SMB5 16 +#define WPCM450_CLK_HUART 17 +#define WPCM450_CLK_PWM 18 +#define WPCM450_CLK_TIMER0 19 +#define WPCM450_CLK_TIMER1 20 +#define WPCM450_CLK_TIMER2 21 +#define WPCM450_CLK_TIMER3 22 +#define WPCM450_CLK_TIMER4 23 +#define WPCM450_CLK_MFT0 24 +#define WPCM450_CLK_MFT1 25 +#define WPCM450_CLK_WDT 26 +#define WPCM450_CLK_ADC 27 +#define WPCM450_CLK_SDIO 28 +#define WPCM450_CLK_SSPI 29 +#define WPCM450_CLK_SMB0 30 +#define WPCM450_CLK_SMB1 31 + +/* Other clocks */ +#define WPCM450_CLK_USBPHY 32 + +#define WPCM450_NUM_CLKS 33 + +/* Resets based on IPSRST bits */ +#define WPCM450_RESET_FIU 0 +#define WPCM450_RESET_EMC0 6 +#define WPCM450_RESET_EMC1 7 +#define WPCM450_RESET_USB0 8 +#define WPCM450_RESET_USB1 9 +#define WPCM450_RESET_AES_PECI 10 +#define WPCM450_RESET_UART 11 +#define WPCM450_RESET_MC 12 +#define WPCM450_RESET_SMB2 13 +#define WPCM450_RESET_SMB3 14 +#define WPCM450_RESET_SMB4 15 +#define WPCM450_RESET_SMB5 16 +#define WPCM450_RESET_PWM 18 +#define WPCM450_RESET_TIMER 19 +#define WPCM450_RESET_ADC 27 +#define WPCM450_RESET_SDIO 28 +#define WPCM450_RESET_SSPI 29 +#define WPCM450_RESET_SMB0 30 +#define WPCM450_RESET_SMB1 31 + +#define WPCM450_NUM_RESETS 32 + +#endif /* _DT_BINDINGS_CLOCK_NUVOTON_WPCM450_CLK_H */ From patchwork Sun Mar 10 19:21:00 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?J=2E_Neusch=C3=A4fer?= X-Patchwork-Id: 13588185 Received: from mout.gmx.net (mout.gmx.net [212.227.17.21]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 2D5E139FDA; Sun, 10 Mar 2024 19:22:12 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=212.227.17.21 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1710098535; cv=none; b=qSU6cSFBjNgmp30zVYfDJRTk41UiAXMZggfPp7RiDFcms37FTyQYTlaHBzlMU3hJtBURsrIgJ1q+ekX86tjChLIAc94m+23Bbwc72IJT8092gfCvM1an3k22MMkoNcFDiZF5pXYkQ8JD1RCF3oN/g65t4FkO33SH5jCqvbxX44o= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1710098535; c=relaxed/simple; bh=xwX/n31nVi07GwxabpiM+MILqJWpXLhlRC1o1CAJ1TU=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; 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b=sl6aUEHaMe2HjYr6QOmJyK1QsGHLZhzojcObbY47BAg79bK1VrstaRZrGjE4GVvK p766bypEp/aScC5+yLwn2HSVZuB78+RUbp1fcXTVh7bpCRCAhb5u+ZltAOAuMgxeR b/8mE5rR9emmpSGiBVZ0mLiNvY0zR9mVezmhOk9YvbufSlwtibPIRPbtFKuY8/o4j jmCcgQNx+ZHfdtma8+ckf8inqnFUd/0Z9s5wCWMT+OvV56fwy+VuCt+GfJcjKuhcw 6xccW8M++fCT7eqnOWExhC5MSiM23cJmnZJkOmGmHC6OPlgcrYcKpVdoktyKODur5 k+GGtn40S1EWZNVMGw== X-UI-Sender-Class: 724b4f7f-cbec-4199-ad4e-598c01a50d3a Received: from probook ([78.35.216.168]) by mail.gmx.net (mrgmx105 [212.227.17.168]) with ESMTPSA (Nemesis) id 1MEm27-1rcZOX25HP-00GGJ0; Sun, 10 Mar 2024 20:21:42 +0100 From: =?utf-8?q?Jonathan_Neusch=C3=A4fer?= To: linux-clk@vger.kernel.org, openbmc@lists.ozlabs.org Cc: linux-kernel@vger.kernel.org, linux-watchdog@vger.kernel.org, devicetree@vger.kernel.org, =?utf-8?q?Jonathan_Neusch=C3=A4fer?= , Michael Turquette , Stephen Boyd , Rob Herring , Krzysztof Kozlowski , Avi Fishman , Tomer Maimon , Tali Perry , Patrick Venture , Nancy Yuen , Benjamin Fair , Daniel Lezcano , Thomas Gleixner , Philipp Zabel , Wim Van Sebroeck , Guenter Roeck , Christophe JAILLET , Conor Dooley Subject: [PATCH v10 2/4] ARM: dts: wpcm450: Remove clock-output-names from reference clock node Date: Sun, 10 Mar 2024 20:21:00 +0100 Message-ID: <20240310192108.2747084-3-j.neuschaefer@gmx.net> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20240310192108.2747084-1-j.neuschaefer@gmx.net> References: <20240310192108.2747084-1-j.neuschaefer@gmx.net> Precedence: bulk X-Mailing-List: linux-clk@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-Provags-ID: V03:K1:Yxv8vcS0CGRV2FQAe7UR+uwmKh8p4sYJxeQFqTQYP+MG3O7jaId NA7IC8wYRDxJy8yNxv+TZcTEmnSde5YphuZlzTDpuzM5e5rE74PC+tEvwCdM+V5JqefWDlo K11TyGY1UNv4K3xoTz4ej/8I9VumgcQnuzKKEmH2K1WdFz7aAMTnpdsDPaGkmxtt3R9g5yR pz4cCnktw9dfFSkbqDLKQ== X-Spam-Flag: NO UI-OutboundReport: notjunk:1;M01:P0:ZZGopwyhUfA=;tvpNE0Osvs/k022T2xl2BC/jc/y XNrWZyEdFWUtPhhsvlOPuEuDAvL+fPOKn1iZwyW1HHjag79DQJGyHLY3wG8KeKwEtva2CSZDx 5zeLe9phCFSbCGT4BduAOqSpIQpYLe/kCY/EHbKbpTkVejeZh0HeB/LNFG7kMmB6NA5FCGF+O hiqHtd+08UUVqMbbTSUdmT5tg9PisN9Us+WaaQErDdFp0nZ+DRlX28ZQJt/DrNl7IKSsmY5ZI SqcUanas5sUzr8B7lZdi+XEXX4WiUZmXJUHDH+ONyzMumj4PW/xlpp8y5OH+isOZe1SfBHwIm W1/NiVkxsDO9KNm+ly2R/otndqHOyNweCMSl8aFdU7aHONhjS6JihFsY2b+JSEdVKn1qPG7jG 044Ap75j80qa64a5AebhV0i5o0fn55dM7UDXk2Pppdb1w9wjrXHSHoU7wcs5K02dLpNBhYQ5b Np0CRq5D8r9AIFzAsECBHZ0HXlwUVRxM9gIYVJDGd2V/m1S+ZZlwb355hoHvEBx0Qvxti6jp1 viwYP4mXP3tkbk+y6HoIVTk6fZg/KkZ73ST2SlZi4Z94dhth5mWgh5AykR4LLswoU/IZBe7Sf 8UeagtHFs3F4tRUSQgXJ8knmHrp5yMm4qIFfwUwftsbRq9zkxUwHIT9GDmJ+Rg58Gt+sym30y 3tOIg6f1oN0hPHDuVd5251OJTR1ksz8OjllK+sJzgNUlWuxg/3UIzHiw4DSdXzt/HVSLpfTdn YW4xpjfs62HzRHHikbKynuXMcKFkCGxuDUe3FaC9T9kbOEFeQ5BGs02MsP6ghfNEf5Vn5w4Hg DfNwfoGUeanbr0oC/DQWIzx+trAUnfdtztkNQHBCmX7ns= This is not necessary anymore, because the clk-wpcm450 driver doesn't rely on global clock names anymore. Signed-off-by: Jonathan Neuschäfer --- v10: - no changes v9: - New patch --- arch/arm/boot/dts/nuvoton/nuvoton-wpcm450.dtsi | 1 - 1 file changed, 1 deletion(-) -- 2.43.0 diff --git a/arch/arm/boot/dts/nuvoton/nuvoton-wpcm450.dtsi b/arch/arm/boot/dts/nuvoton/nuvoton-wpcm450.dtsi index 6e1f0f164cb4f5..9dfdd8f67319d3 100644 --- a/arch/arm/boot/dts/nuvoton/nuvoton-wpcm450.dtsi +++ b/arch/arm/boot/dts/nuvoton/nuvoton-wpcm450.dtsi @@ -40,7 +40,6 @@ clk24m: clock-24mhz { refclk: clock-48mhz { /* 48 MHz reference oscillator */ compatible = "fixed-clock"; - clock-output-names = "ref"; clock-frequency = <48000000>; #clock-cells = <0>; }; From patchwork Sun Mar 10 19:21:01 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?J=2E_Neusch=C3=A4fer?= X-Patchwork-Id: 13588187 Received: from mout.gmx.net (mout.gmx.net [212.227.17.21]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 894693B190; 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Sun, 10 Mar 2024 20:21:53 +0100 From: =?utf-8?q?Jonathan_Neusch=C3=A4fer?= To: linux-clk@vger.kernel.org, openbmc@lists.ozlabs.org Cc: linux-kernel@vger.kernel.org, linux-watchdog@vger.kernel.org, devicetree@vger.kernel.org, =?utf-8?q?Jonathan_Neusch=C3=A4fer?= , Michael Turquette , Stephen Boyd , Rob Herring , Krzysztof Kozlowski , Avi Fishman , Tomer Maimon , Tali Perry , Patrick Venture , Nancy Yuen , Benjamin Fair , Daniel Lezcano , Thomas Gleixner , Philipp Zabel , Wim Van Sebroeck , Guenter Roeck , Christophe JAILLET , Conor Dooley , Joel Stanley , Jacky Huang , Arnd Bergmann , Krzysztof Kozlowski Subject: [PATCH v10 3/4] clk: wpcm450: Add Nuvoton WPCM450 clock/reset controller driver Date: Sun, 10 Mar 2024 20:21:01 +0100 Message-ID: <20240310192108.2747084-4-j.neuschaefer@gmx.net> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20240310192108.2747084-1-j.neuschaefer@gmx.net> References: <20240310192108.2747084-1-j.neuschaefer@gmx.net> Precedence: bulk X-Mailing-List: linux-clk@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-Provags-ID: V03:K1:VUvmWc7FGu1I3vUCrTN4TGUiRzyoTnAGI+ma982Aw7H51WgYamN lJxmL39iyQrBojPDkmm6uF2ME3WKTv8sogHtM6ObnIT1JMKXOizIm/1Of02zJbKnWA6aNoP mOEFhBZF+tQGH13kMTi+ppX7Tu9zOvkrZZMbopx1RAq8JFS2ZbphF1ZUF59tT4sXitE90ju aG25HWOyuL5WVEYYf1rsA== X-Spam-Flag: NO UI-OutboundReport: notjunk:1;M01:P0:AxNMiufJGsE=;BHUqa/Fib2c/0UdZmiyMbIC14h5 aHa1YnMR9Tzt3tGvbb54HQ9AvB74YZgTTuLMJ0KTBMn5ZhU1W/lO4bqczPdO96AI2ATPG7h1Z NHQjZdGvdxyXq4Hodjsf/iYVKWENo5uJybFpXdhfujPutontohM+MCiNVCC6+QPBCzQFgrrQr 7GnVT/+FI5oNlWPnLWAsrjY9empWic6m5HyTC9Hq8F+QPpuzapNKpVCvA86S8BrowNe2CBRud b12h8ATA0S5P71bnNjS+kfgiJHZNZxeUP1Eattry3Xp/KrevyPEq3VXT145bCLtmj2pgOA8w4 cMtYMoZYviEu9kMz4Zcgf5Kz2cdHoGSMVPVQrWsZAVj+aSZc0WXBlhlbxKYZxXT5j3gUvoTUa isMU9P7wU7fhJkoPHCr0isPmuXI7yJ0Nc8HwNRyxEND9MSV/RSE4FimHpZ1jopBXNJM0Cp0Av xatmtlFN1tMw6xy/jTagiZdY1sa572Qe8HFI7SBnNJ9jLl1Cp9SNbcmLjwtQlsNs6XTYn2bGU n3t6ZpjgzZOqY5UoQb/bbGzK7P+7S/EHYIOUSGNc1/+DkZqWTO1jEwS9yo9LDVy4+7+x/LDpO QGZIx1YapRk/OGV9QT17BOd48rEgFjDHikrrlZvK27YiQ/z99gD1jyoGoNZ2A4cjywlGrN1IG qlKE4U1O/7VqNUABZn8XqEu5gpV5xqaEAGC4+OevwKFmhJgG/aakffhCxzSpRiMEhPMUwTvXr yyKRfUjErmpQRp0Pjo1AuEHy2F7iMnBSh2lfC8MYWA813qs7HNRYk0mKr8xUPrCuCvzbgYQUK JrfE+TmuzXHubRfrRc6asFapnTwnc11HY/0pwYPyJEM68= This driver implements the following features w.r.t. the clock and reset controller in the WPCM450 SoC: - It calculates the rates for all clocks managed by the clock controller - It leaves the clock tree mostly unchanged, except that it enables/ disables clock gates based on usage. - It exposes the reset lines managed by the controller using the Generic Reset Controller subsystem NOTE: If the driver and the corresponding devicetree node are present, the driver will disable "unused" clocks. This is problem until the clock relations are properly declared in the devicetree (in a later patch). Until then, the clk_ignore_unused kernel parameter can be used as a workaround. Signed-off-by: Jonathan Neuschäfer Reviewed-by: Joel Stanley --- I have considered converting this driver to a platform driver instead of using CLK_OF_DECLARE, because platform drivers are generally the way forward. However, the timer-npcm7xx driver used on the same platform requires is initialized with TIMER_OF_DECLARE and thus requires the clocks to be available earlier than a platform driver can provide them. v10: - select RESET_{CONTROLLER,SIMPLE} from CLK_WPCM450 instead of messing with the 'default' statement v9: - Apply comments made by Stephen Boyd - Move to drivers/clk/nuvoton/ directory - Update SPDX license identifier from GPL-2.0 to GPL-2.0-only - Rename clk_np variable to np - Use of_clk_hw_register - Refer to clock parents by .fw_name v8: - https://lore.kernel.org/lkml/20230428190226.1304326-3-j.neuschaefer@gmx.net/ - Use %pe format specifier throughout the driver, as suggested by Philipp Zabel - Add Joel's R-b v7: - https://lore.kernel.org/lkml/20230422220240.322572-3-j.neuschaefer@gmx.net/ - Simplify error handling by not deallocating resources v6: - Enable RESET_SIMPLE based on ARCH_WPCM450, not ARCH_NPCM, as suggested by Tomer Maimon v5: - https://lore.kernel.org/lkml/20221104161850.2889894-6-j.neuschaefer@gmx.net/ - Switch to using clk_parent_data v4: - Fix reset controller initialization v3: - Change reference clock name from "refclk" to "ref" - Remove unused variable in return path of wpcm450_clk_register_pll - Remove unused divisor tables v2: - no changes --- drivers/clk/Makefile | 2 +- drivers/clk/nuvoton/Kconfig | 10 +- drivers/clk/nuvoton/Makefile | 1 + drivers/clk/nuvoton/clk-wpcm450.c | 372 ++++++++++++++++++++++++++++++ 4 files changed, 383 insertions(+), 2 deletions(-) create mode 100644 drivers/clk/nuvoton/clk-wpcm450.c -- 2.43.0 diff --git a/drivers/clk/Makefile b/drivers/clk/Makefile index 14fa8d4ecc1fbe..cdeb2ecf3a8e99 100644 --- a/drivers/clk/Makefile +++ b/drivers/clk/Makefile @@ -107,7 +107,7 @@ endif obj-y += mstar/ obj-y += mvebu/ obj-$(CONFIG_ARCH_MXS) += mxs/ -obj-$(CONFIG_ARCH_MA35) += nuvoton/ +obj-y += nuvoton/ obj-$(CONFIG_COMMON_CLK_NXP) += nxp/ obj-$(CONFIG_COMMON_CLK_PISTACHIO) += pistachio/ obj-$(CONFIG_COMMON_CLK_PXA) += pxa/ diff --git a/drivers/clk/nuvoton/Kconfig b/drivers/clk/nuvoton/Kconfig index fe4b7f62f46704..908881654b2e91 100644 --- a/drivers/clk/nuvoton/Kconfig +++ b/drivers/clk/nuvoton/Kconfig @@ -3,7 +3,7 @@ config COMMON_CLK_NUVOTON bool "Nuvoton clock controller common support" - depends on ARCH_MA35 || COMPILE_TEST + depends on ARCH_MA35 || ARCH_NPCM || COMPILE_TEST default y help Say y here to enable common clock controller for Nuvoton platforms. @@ -16,4 +16,12 @@ config CLK_MA35D1 help Build the clock controller driver for MA35D1 SoC. +config CLK_WPCM450 + bool "Nuvoton WPCM450 clock/reset controller support" + default y + select RESET_CONTROLLER + select RESET_SIMPLE + help + Build the clock and reset controller driver for the WPCM450 SoC. + endif diff --git a/drivers/clk/nuvoton/Makefile b/drivers/clk/nuvoton/Makefile index c3c59dd9f2aaab..b130f0d3889ca0 100644 --- a/drivers/clk/nuvoton/Makefile +++ b/drivers/clk/nuvoton/Makefile @@ -2,3 +2,4 @@ obj-$(CONFIG_CLK_MA35D1) += clk-ma35d1.o obj-$(CONFIG_CLK_MA35D1) += clk-ma35d1-divider.o obj-$(CONFIG_CLK_MA35D1) += clk-ma35d1-pll.o +obj-$(CONFIG_CLK_WPCM450) += clk-wpcm450.o diff --git a/drivers/clk/nuvoton/clk-wpcm450.c b/drivers/clk/nuvoton/clk-wpcm450.c new file mode 100644 index 00000000000000..9100c4b8a56483 --- /dev/null +++ b/drivers/clk/nuvoton/clk-wpcm450.c @@ -0,0 +1,372 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Nuvoton WPCM450 clock and reset controller driver. + * + * Copyright (C) 2022 Jonathan Neuschäfer + */ + +#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include + +struct wpcm450_clk_pll { + struct clk_hw hw; + void __iomem *pllcon; + u8 flags; +}; + +#define to_wpcm450_clk_pll(_hw) container_of(_hw, struct wpcm450_clk_pll, hw) + +#define PLLCON_FBDV GENMASK(24, 16) +#define PLLCON_PRST BIT(13) +#define PLLCON_PWDEN BIT(12) +#define PLLCON_OTDV GENMASK(10, 8) +#define PLLCON_INDV GENMASK(5, 0) + +static unsigned long wpcm450_clk_pll_recalc_rate(struct clk_hw *hw, + unsigned long parent_rate) +{ + struct wpcm450_clk_pll *pll = to_wpcm450_clk_pll(hw); + unsigned long fbdv, indv, otdv; + u64 rate; + u32 pllcon; + + if (parent_rate == 0) + return 0; + + pllcon = readl_relaxed(pll->pllcon); + + indv = FIELD_GET(PLLCON_INDV, pllcon) + 1; + fbdv = FIELD_GET(PLLCON_FBDV, pllcon) + 1; + otdv = FIELD_GET(PLLCON_OTDV, pllcon) + 1; + + rate = (u64)parent_rate * fbdv; + do_div(rate, indv * otdv); + + return rate; +} + +static int wpcm450_clk_pll_is_enabled(struct clk_hw *hw) +{ + struct wpcm450_clk_pll *pll = to_wpcm450_clk_pll(hw); + u32 pllcon; + + pllcon = readl_relaxed(pll->pllcon); + + return !(pllcon & PLLCON_PRST); +} + +static void wpcm450_clk_pll_disable(struct clk_hw *hw) +{ + struct wpcm450_clk_pll *pll = to_wpcm450_clk_pll(hw); + u32 pllcon; + + pllcon = readl_relaxed(pll->pllcon); + pllcon |= PLLCON_PRST | PLLCON_PWDEN; + writel(pllcon, pll->pllcon); +} + +static const struct clk_ops wpcm450_clk_pll_ops = { + .recalc_rate = wpcm450_clk_pll_recalc_rate, + .is_enabled = wpcm450_clk_pll_is_enabled, + .disable = wpcm450_clk_pll_disable +}; + +static struct clk_hw * +wpcm450_clk_register_pll(struct device_node *np, void __iomem *pllcon, const char *name, + const struct clk_parent_data *parent, unsigned long flags) +{ + struct wpcm450_clk_pll *pll; + struct clk_init_data init = {}; + int ret; + + pll = kzalloc(sizeof(*pll), GFP_KERNEL); + if (!pll) + return ERR_PTR(-ENOMEM); + + init.name = name; + init.ops = &wpcm450_clk_pll_ops; + init.parent_data = parent; + init.num_parents = 1; + init.flags = flags; + + pll->pllcon = pllcon; + pll->hw.init = &init; + + ret = of_clk_hw_register(np, &pll->hw); + if (ret) { + kfree(pll); + return ERR_PTR(ret); + } + + return &pll->hw; +} + +#define REG_CLKEN 0x00 +#define REG_CLKSEL 0x04 +#define REG_CLKDIV 0x08 +#define REG_PLLCON0 0x0c +#define REG_PLLCON1 0x10 +#define REG_PMCON 0x14 +#define REG_IRQWAKECON 0x18 +#define REG_IRQWAKEFLAG 0x1c +#define REG_IPSRST 0x20 + +struct wpcm450_pll_data { + const char *name; + struct clk_parent_data parent; + unsigned int reg; + unsigned long flags; +}; + +static const struct wpcm450_pll_data pll_data[] = { + { "pll0", { .fw_name = "ref" }, REG_PLLCON0, 0 }, + { "pll1", { .fw_name = "ref" }, REG_PLLCON1, 0 }, +}; + +struct wpcm450_clksel_data { + const char *name; + const struct clk_parent_data *parents; + unsigned int num_parents; + const u32 *table; + int shift; + int width; + int index; + unsigned long flags; +}; + +static const u32 parent_table[] = { 0, 1, 2 }; + +static const struct clk_parent_data default_parents[] = { + { .name = "pll0" }, + { .name = "pll1" }, + { .name = "ref" }, +}; + +static const struct clk_parent_data huart_parents[] = { + { .fw_name = "ref" }, + { .name = "refdiv2" }, +}; + +static const struct wpcm450_clksel_data clksel_data[] = { + { "cpusel", default_parents, ARRAY_SIZE(default_parents), + parent_table, 0, 2, -1, CLK_IS_CRITICAL }, + { "clkout", default_parents, ARRAY_SIZE(default_parents), + parent_table, 2, 2, -1, 0 }, + { "usbphy", default_parents, ARRAY_SIZE(default_parents), + parent_table, 6, 2, -1, 0 }, + { "uartsel", default_parents, ARRAY_SIZE(default_parents), + parent_table, 8, 2, WPCM450_CLK_USBPHY, 0 }, + { "huartsel", huart_parents, ARRAY_SIZE(huart_parents), + parent_table, 10, 1, -1, 0 }, +}; + +static const struct clk_div_table div_fixed2[] = { + { .val = 0, .div = 2 }, + { } +}; + +struct wpcm450_clkdiv_data { + const char *name; + struct clk_parent_data parent; + int div_flags; + const struct clk_div_table *table; + int shift; + int width; + unsigned long flags; +}; + +static struct wpcm450_clkdiv_data clkdiv_data_early[] = { + { "refdiv2", { .name = "ref" }, 0, div_fixed2, 0, 0 }, +}; + +static const struct wpcm450_clkdiv_data clkdiv_data[] = { + { "cpu", { .name = "cpusel" }, 0, div_fixed2, 0, 0, CLK_IS_CRITICAL }, + { "adcdiv", { .name = "ref" }, CLK_DIVIDER_POWER_OF_TWO, NULL, 28, 2, 0 }, + { "apb", { .name = "ahb" }, CLK_DIVIDER_POWER_OF_TWO, NULL, 26, 2, 0 }, + { "ahb", { .name = "cpu" }, CLK_DIVIDER_POWER_OF_TWO, NULL, 24, 2, 0 }, + { "uart", { .name = "uartsel" }, 0, NULL, 16, 4, 0 }, + { "ahb3", { .name = "ahb" }, CLK_DIVIDER_POWER_OF_TWO, NULL, 8, 2, 0 }, +}; + +struct wpcm450_clken_data { + const char *name; + struct clk_parent_data parent; + int bitnum; + unsigned long flags; +}; + +static const struct wpcm450_clken_data clken_data[] = { + { "fiu", { .name = "ahb3" }, WPCM450_CLK_FIU, 0 }, + { "xbus", { .name = "ahb3" }, WPCM450_CLK_XBUS, 0 }, + { "kcs", { .name = "apb" }, WPCM450_CLK_KCS, 0 }, + { "shm", { .name = "ahb3" }, WPCM450_CLK_SHM, 0 }, + { "usb1", { .name = "ahb" }, WPCM450_CLK_USB1, 0 }, + { "emc0", { .name = "ahb" }, WPCM450_CLK_EMC0, 0 }, + { "emc1", { .name = "ahb" }, WPCM450_CLK_EMC1, 0 }, + { "usb0", { .name = "ahb" }, WPCM450_CLK_USB0, 0 }, + { "peci", { .name = "apb" }, WPCM450_CLK_PECI, 0 }, + { "aes", { .name = "apb" }, WPCM450_CLK_AES, 0 }, + { "uart0", { .name = "uart" }, WPCM450_CLK_UART0, 0 }, + { "uart1", { .name = "uart" }, WPCM450_CLK_UART1, 0 }, + { "smb2", { .name = "apb" }, WPCM450_CLK_SMB2, 0 }, + { "smb3", { .name = "apb" }, WPCM450_CLK_SMB3, 0 }, + { "smb4", { .name = "apb" }, WPCM450_CLK_SMB4, 0 }, + { "smb5", { .name = "apb" }, WPCM450_CLK_SMB5, 0 }, + { "huart", { .name = "huartsel" }, WPCM450_CLK_HUART, 0 }, + { "pwm", { .name = "apb" }, WPCM450_CLK_PWM, 0 }, + { "timer0", { .name = "refdiv2" }, WPCM450_CLK_TIMER0, 0 }, + { "timer1", { .name = "refdiv2" }, WPCM450_CLK_TIMER1, 0 }, + { "timer2", { .name = "refdiv2" }, WPCM450_CLK_TIMER2, 0 }, + { "timer3", { .name = "refdiv2" }, WPCM450_CLK_TIMER3, 0 }, + { "timer4", { .name = "refdiv2" }, WPCM450_CLK_TIMER4, 0 }, + { "mft0", { .name = "apb" }, WPCM450_CLK_MFT0, 0 }, + { "mft1", { .name = "apb" }, WPCM450_CLK_MFT1, 0 }, + { "wdt", { .name = "refdiv2" }, WPCM450_CLK_WDT, 0 }, + { "adc", { .name = "adcdiv" }, WPCM450_CLK_ADC, 0 }, + { "sdio", { .name = "ahb" }, WPCM450_CLK_SDIO, 0 }, + { "sspi", { .name = "apb" }, WPCM450_CLK_SSPI, 0 }, + { "smb0", { .name = "apb" }, WPCM450_CLK_SMB0, 0 }, + { "smb1", { .name = "apb" }, WPCM450_CLK_SMB1, 0 }, +}; + +static DEFINE_SPINLOCK(wpcm450_clk_lock); + +/* + * NOTE: Error handling is very rudimentary here. If the clock driver initial- + * ization fails, the system is probably in bigger trouble than what is caused + * by a few leaked resources. + */ + +static void __init wpcm450_clk_init(struct device_node *np) +{ + struct clk_hw_onecell_data *clk_data; + static struct clk_hw **hws; + static struct clk_hw *hw; + void __iomem *clk_base; + int i, ret; + struct reset_simple_data *reset; + + clk_base = of_iomap(np, 0); + if (!clk_base) { + pr_err("%pOFP: failed to map registers\n", np); + of_node_put(np); + return; + } + of_node_put(np); + + clk_data = kzalloc(struct_size(clk_data, hws, WPCM450_NUM_CLKS), GFP_KERNEL); + if (!clk_data) + return; + + clk_data->num = WPCM450_NUM_CLKS; + hws = clk_data->hws; + + for (i = 0; i < WPCM450_NUM_CLKS; i++) + hws[i] = ERR_PTR(-ENOENT); + + /* PLLs */ + for (i = 0; i < ARRAY_SIZE(pll_data); i++) { + const struct wpcm450_pll_data *data = &pll_data[i]; + + hw = wpcm450_clk_register_pll(np, clk_base + data->reg, data->name, + &data->parent, data->flags); + if (IS_ERR(hw)) { + pr_info("Failed to register PLL: %pe\n", hw); + return; + } + } + + /* Early divisors (REF/2) */ + for (i = 0; i < ARRAY_SIZE(clkdiv_data_early); i++) { + const struct wpcm450_clkdiv_data *data = &clkdiv_data_early[i]; + + hw = clk_hw_register_divider_table_parent_data(NULL, data->name, &data->parent, + data->flags, clk_base + REG_CLKDIV, + data->shift, data->width, + data->div_flags, data->table, + &wpcm450_clk_lock); + if (IS_ERR(hw)) { + pr_err("Failed to register div table: %pe\n", hw); + return; + } + } + + /* Selects/muxes */ + for (i = 0; i < ARRAY_SIZE(clksel_data); i++) { + const struct wpcm450_clksel_data *data = &clksel_data[i]; + + hw = clk_hw_register_mux_parent_data(NULL, data->name, data->parents, + data->num_parents, data->flags, + clk_base + REG_CLKSEL, data->shift, + data->width, 0, + &wpcm450_clk_lock); + if (IS_ERR(hw)) { + pr_err("Failed to register mux: %pe\n", hw); + return; + } + if (data->index >= 0) + clk_data->hws[data->index] = hw; + } + + /* Divisors */ + for (i = 0; i < ARRAY_SIZE(clkdiv_data); i++) { + const struct wpcm450_clkdiv_data *data = &clkdiv_data[i]; + + hw = clk_hw_register_divider_table_parent_data(NULL, data->name, &data->parent, + data->flags, clk_base + REG_CLKDIV, + data->shift, data->width, + data->div_flags, data->table, + &wpcm450_clk_lock); + if (IS_ERR(hw)) { + pr_err("Failed to register divider: %pe\n", hw); + return; + } + } + + /* Enables/gates */ + for (i = 0; i < ARRAY_SIZE(clken_data); i++) { + const struct wpcm450_clken_data *data = &clken_data[i]; + + hw = clk_hw_register_gate_parent_data(NULL, data->name, &data->parent, data->flags, + clk_base + REG_CLKEN, data->bitnum, + data->flags, &wpcm450_clk_lock); + if (IS_ERR(hw)) { + pr_err("Failed to register gate: %pe\n", hw); + return; + } + clk_data->hws[data->bitnum] = hw; + } + + ret = of_clk_add_hw_provider(np, of_clk_hw_onecell_get, clk_data); + if (ret) + pr_err("Failed to add DT provider: %pe\n", ERR_PTR(ret)); + + /* Reset controller */ + reset = kzalloc(sizeof(*reset), GFP_KERNEL); + if (!reset) + return; + reset->rcdev.owner = THIS_MODULE; + reset->rcdev.nr_resets = WPCM450_NUM_RESETS; + reset->rcdev.ops = &reset_simple_ops; + reset->rcdev.of_node = np; + reset->membase = clk_base + REG_IPSRST; + ret = reset_controller_register(&reset->rcdev); + if (ret) + pr_err("Failed to register reset controller: %pe\n", ERR_PTR(ret)); + + of_node_put(np); +} + +CLK_OF_DECLARE(wpcm450_clk_init, "nuvoton,wpcm450-clk", wpcm450_clk_init); From patchwork Sun Mar 10 19:21:02 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?J=2E_Neusch=C3=A4fer?= X-Patchwork-Id: 13588188 Received: from mout.gmx.net (mout.gmx.net [212.227.15.19]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id B959B3B190; Sun, 10 Mar 2024 19:22:36 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=212.227.15.19 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1710098558; cv=none; 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spf=pass smtp.mailfrom=gmx.net Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=gmx.net header.i=j.neuschaefer@gmx.net header.b="Bd00Tvnk" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=gmx.net; s=s31663417; t=1710098526; x=1710703326; i=j.neuschaefer@gmx.net; bh=Lc1pMRgsV+StSf5fgFNpvmYafFqXYMKdh+E4JPDHkIM=; h=X-UI-Sender-Class:From:To:Cc:Subject:Date:In-Reply-To: References; b=Bd00TvnksM/H/dFC7U9XfpC05A/9jT7hukPQ2gkucaZ0ksg0dOFrwv+ho/g8rSS7 4MDMbtvRGrIKcfyAzGa1Tp/A+Yj6TwkzaCE6pi1SCHrUERVE9cnDbnSDofxh1al3E rkl4KhTXRv6hwezrAJ/bp/W9twYdNpH07VCqZ5TmWw9RXdzSOPnssaAuefEoDhOXW sBLR2ZC16QYBG0t/eJrzegG0mA6OFBBk4NNba2fEpHMCIB/QH0HcNNrOgDvUBW53u Vwh2K1n3ywZWxNI6WoTKcYhQD1TJTBCmeeLlgyoqoAKDsN4cDvL45LB7LzqrPm5ug My8FLUILVcDCgItSkA== X-UI-Sender-Class: 724b4f7f-cbec-4199-ad4e-598c01a50d3a Received: from probook ([78.35.216.168]) by mail.gmx.net (mrgmx004 [212.227.17.190]) with ESMTPSA (Nemesis) id 1MgNh7-1rBBBJ0KLv-00hvec; Sun, 10 Mar 2024 20:22:06 +0100 From: =?utf-8?q?Jonathan_Neusch=C3=A4fer?= To: linux-clk@vger.kernel.org, openbmc@lists.ozlabs.org Cc: linux-kernel@vger.kernel.org, linux-watchdog@vger.kernel.org, devicetree@vger.kernel.org, =?utf-8?q?Jonathan_Neusch=C3=A4fer?= , Michael Turquette , Stephen Boyd , Rob Herring , Krzysztof Kozlowski , Avi Fishman , Tomer Maimon , Tali Perry , Patrick Venture , Nancy Yuen , Benjamin Fair , Daniel Lezcano , Thomas Gleixner , Philipp Zabel , Wim Van Sebroeck , Guenter Roeck , Christophe JAILLET , Conor Dooley Subject: [PATCH v10 4/4] ARM: dts: wpcm450: Switch clocks to clock controller Date: Sun, 10 Mar 2024 20:21:02 +0100 Message-ID: <20240310192108.2747084-5-j.neuschaefer@gmx.net> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20240310192108.2747084-1-j.neuschaefer@gmx.net> References: <20240310192108.2747084-1-j.neuschaefer@gmx.net> Precedence: bulk X-Mailing-List: linux-clk@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-Provags-ID: V03:K1:CZOP/2JyhuYMjvSoJftgiK/2nFIgRon1+neVh/LZn4z7J6VfK+Y phi/XYNwa4bSKC6jy9/3KudhpuaCSWhKSnAvYt0goG/vWKXb0E9SIIDCkWj6VF420nX5Wa6 Np3/bXESt4ZTzvjlR4m8nFawznti+83B1GljuO5cYG8N+gcWJbGj0tbZN83upD3iWlEP/GK ZseouWgpoYKKzhSS+0NvQ== X-Spam-Flag: NO UI-OutboundReport: notjunk:1;M01:P0:Z1xVzBzNInU=;NDd8KIAFtG7HWYEYhvWCeKkhzkg NR4AV0H13INfVrpjhwXC58BnoZ9BO0Pd7rlvVV7zHg6e4zIaFlWNTJdA/A8f4BgdOfJ9ktPP6 QqK5ejKFY10a+I4iMJJGejcV3a+SrTO9zpsfDVQb0VIxKK86ASPEPp4fwk7/J7mSkdlH0wK9P YtHGsxbGZjEke4jWPANODol+gbw9kss6Ss8tyIHuKSZydKmflu2//O1sBnq4T9+y3Tjlio2dm jYY6FOQXaRGW9Zk/gmI09EyJibKgH/5zKrgEU8pO4Hu+8fHK6Qh10Vcps0mJb1oeKj6wFv5ZC WNJRGcISk2Eh0Ysk4M1uV7yvsarMCM5fR3n2tzoGXsX+1foHqZXS576AZsrSw5ynFAbCxkggm emkpnbcHLc+QWDHu50F3Y1oFMi69XHBxNSJCEgZd2Ir4DCFhURDKNQHKuH0WEnyH29wIxt31X X/U4/gwnhWu4tyBhu87sCfy0shO0QoZujirC2qGi8QnjTRCSDOdkB2PW61ReZnKsPIF6Dm0Bw tjje3eZeo5GugTsLZ5zwXJhYE4QnOUvd5AC/yz3PHyhQqZJsHrUMHVDJ4hlcknbJmNjEKUExq XBGIgii743CONhs6aCeaV/BWGaWzabALOrlBqKYSckZEmYMh+IGWpfmquVmgOMI0ocCybdEcJ oyr0KReDfa/BxUOmt6nQEFmWm8CAJZASMSVJJ1ihksLBmQizhCmhwQ3BPRmeZaf1EjH6V45sx Vh1dfapk8lzU01ai5YOFjUb3zugW3Kykxay3BYEPcFfTaT0TrYn2NCmIKj6ZSV41iWhdCIn8i jcqiGnSqb+Fe8nYJnkuSklRF2KYvU7DayUP18+6ecTTXA= This change is incompatible with older kernels because it requires the clock controller driver, but I think that's acceptable because WPCM450 support is generally still in an early phase. Signed-off-by: Jonathan Neuschäfer --- It's probably best to delay merging of this patch until after the driver is merged; I'm including it here for review, and in case someone want's to set up a shared branch between the clock and devicetree parts. v10: - Reintroducing this patch as part of the clock/reset controller series --- .../arm/boot/dts/nuvoton/nuvoton-wpcm450.dtsi | 22 +++++++++---------- 1 file changed, 10 insertions(+), 12 deletions(-) -- 2.43.0 diff --git a/arch/arm/boot/dts/nuvoton/nuvoton-wpcm450.dtsi b/arch/arm/boot/dts/nuvoton/nuvoton-wpcm450.dtsi index 9dfdd8f67319d3..7e3ea8b31151b3 100644 --- a/arch/arm/boot/dts/nuvoton/nuvoton-wpcm450.dtsi +++ b/arch/arm/boot/dts/nuvoton/nuvoton-wpcm450.dtsi @@ -2,6 +2,7 @@ // Copyright 2021 Jonathan Neuschäfer #include +#include / { compatible = "nuvoton,wpcm450"; @@ -30,13 +31,6 @@ cpu@0 { }; }; - clk24m: clock-24mhz { - /* 24 MHz dummy clock */ - compatible = "fixed-clock"; - clock-frequency = <24000000>; - #clock-cells = <0>; - }; - refclk: clock-48mhz { /* 48 MHz reference oscillator */ compatible = "fixed-clock"; @@ -70,7 +64,7 @@ serial0: serial@b8000000 { reg = <0xb8000000 0x20>; reg-shift = <2>; interrupts = <7 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&clk24m>; + clocks = <&clk WPCM450_CLK_UART0>; pinctrl-names = "default"; pinctrl-0 = <&bsp_pins>; status = "disabled"; @@ -81,7 +75,7 @@ serial1: serial@b8000100 { reg = <0xb8000100 0x20>; reg-shift = <2>; interrupts = <8 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&clk24m>; + clocks = <&clk WPCM450_CLK_UART1>; status = "disabled"; }; @@ -89,14 +83,18 @@ timer0: timer@b8001000 { compatible = "nuvoton,wpcm450-timer"; interrupts = <12 IRQ_TYPE_LEVEL_HIGH>; reg = <0xb8001000 0x1c>; - clocks = <&clk24m>; + clocks = <&clk WPCM450_CLK_TIMER0>, + <&clk WPCM450_CLK_TIMER1>, + <&clk WPCM450_CLK_TIMER2>, + <&clk WPCM450_CLK_TIMER3>, + <&clk WPCM450_CLK_TIMER4>; }; watchdog0: watchdog@b800101c { compatible = "nuvoton,wpcm450-wdt"; interrupts = <1 IRQ_TYPE_LEVEL_HIGH>; reg = <0xb800101c 0x4>; - clocks = <&clk24m>; + clocks = <&clk WPCM450_CLK_WDT>; }; aic: interrupt-controller@b8002000 { @@ -480,7 +478,7 @@ fiu: spi-controller@c8000000 { #size-cells = <0>; reg = <0xc8000000 0x1000>, <0xc0000000 0x4000000>; reg-names = "control", "memory"; - clocks = <&clk 0>; + clocks = <&clk WPCM450_CLK_FIU>; nuvoton,shm = <&shm>; status = "disabled"; };