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Received-SPF: Pass (protection.outlook.com: domain of amd.com designates 165.204.84.17 as permitted sender) receiver=protection.outlook.com; client-ip=165.204.84.17; helo=SATLEXMB04.amd.com; pr=C Received: from SATLEXMB04.amd.com (165.204.84.17) by CH2PEPF00000140.mail.protection.outlook.com (10.167.244.72) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.20.7386.12 via Frontend Transport; Fri, 15 Mar 2024 03:39:21 +0000 Received: from pyuan-Chachani-VN.amd.com (10.180.168.240) by SATLEXMB04.amd.com (10.181.40.145) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.35; Thu, 14 Mar 2024 22:38:43 -0500 From: Perry Yuan To: , , , , , CC: , , , , , Subject: [PATCH v5 1/8] cpufreq: acpi: move MSR_K7_HWCR_CPB_DIS_BIT into msr-index.h Date: Fri, 15 Mar 2024 11:38:02 +0800 Message-ID: X-Mailer: git-send-email 2.34.1 In-Reply-To: References: Precedence: bulk X-Mailing-List: linux-pm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-ClientProxiedBy: SATLEXMB04.amd.com (10.181.40.145) To SATLEXMB04.amd.com (10.181.40.145) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: CH2PEPF00000140:EE_|SJ1PR12MB6313:EE_ X-MS-Office365-Filtering-Correlation-Id: f4391eb5-81ad-4549-002d-08dc44a1805d X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; 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X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 15 Mar 2024 03:39:21.3144 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: f4391eb5-81ad-4549-002d-08dc44a1805d X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: CH2PEPF00000140.namprd02.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: SJ1PR12MB6313 There are some other drivers also need to use the MSR_K7_HWCR_CPB_DIS_BIT for CPB control bit, so it makes sense to move the definition to a common header file to allow other driver to use it. No intentional functional impact. Suggested-by: Gautham Ranjal Shenoy Signed-off-by: Perry Yuan --- arch/x86/include/asm/msr-index.h | 2 ++ drivers/cpufreq/acpi-cpufreq.c | 2 -- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/arch/x86/include/asm/msr-index.h b/arch/x86/include/asm/msr-index.h index 05956bd8bacf..41503647192e 100644 --- a/arch/x86/include/asm/msr-index.h +++ b/arch/x86/include/asm/msr-index.h @@ -775,6 +775,8 @@ #define MSR_K7_HWCR_IRPERF_EN BIT_ULL(MSR_K7_HWCR_IRPERF_EN_BIT) #define MSR_K7_FID_VID_CTL 0xc0010041 #define MSR_K7_FID_VID_STATUS 0xc0010042 +#define MSR_K7_HWCR_CPB_DIS_BIT 25 +#define MSR_K7_HWCR_CPB_DIS BIT_ULL(MSR_K7_HWCR_CPB_DIS_BIT) /* K6 MSRs */ #define MSR_K6_WHCR 0xc0000082 diff --git a/drivers/cpufreq/acpi-cpufreq.c b/drivers/cpufreq/acpi-cpufreq.c index 37f1cdf46d29..2fc82831bddd 100644 --- a/drivers/cpufreq/acpi-cpufreq.c +++ b/drivers/cpufreq/acpi-cpufreq.c @@ -50,8 +50,6 @@ enum { #define AMD_MSR_RANGE (0x7) #define HYGON_MSR_RANGE (0x7) -#define MSR_K7_HWCR_CPB_DIS (1ULL << 25) - struct acpi_cpufreq_data { unsigned int resume; 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If core performance boost is disabled while a core is in a boosted P-state, the core transitions to the highest performance non-boosted P-state, that is the same as the nominal frequency limit. Reported-by: Artem S. Tashkinov" Cc: Oleksandr Natalenko Closes: https://bugzilla.kernel.org/show_bug.cgi?id=217931 Signed-off-by: Perry Yuan --- drivers/cpufreq/amd-pstate.c | 50 ++++++++++++------------------------ include/linux/amd-pstate.h | 13 ++++++++++ 2 files changed, 30 insertions(+), 33 deletions(-) diff --git a/drivers/cpufreq/amd-pstate.c b/drivers/cpufreq/amd-pstate.c index 3877d4ecb5d4..e5eb09f874ba 100644 --- a/drivers/cpufreq/amd-pstate.c +++ b/drivers/cpufreq/amd-pstate.c @@ -68,6 +68,8 @@ static int cppc_state = AMD_PSTATE_UNDEFINED; static bool cppc_enabled; static bool amd_pstate_prefcore = true; static struct quirk_entry *quirks; +struct amd_pstate_global_params amd_pstate_global_params; +EXPORT_SYMBOL_GPL(amd_pstate_global_params); /* * AMD Energy Preference Performance (EPP) @@ -714,43 +716,21 @@ static int amd_get_lowest_nonlinear_freq(struct amd_cpudata *cpudata) return lowest_nonlinear_freq * 1000; } -static int amd_pstate_set_boost(struct cpufreq_policy *policy, int state) +static int amd_pstate_boost_init(struct amd_cpudata *cpudata) { - struct amd_cpudata *cpudata = policy->driver_data; + u64 boost_val; int ret; - if (!cpudata->boost_supported) { - pr_err("Boost mode is not supported by this processor or SBIOS\n"); - return -EINVAL; - } - - if (state) - policy->cpuinfo.max_freq = cpudata->max_freq; - else - policy->cpuinfo.max_freq = cpudata->nominal_freq; - - policy->max = policy->cpuinfo.max_freq; - - ret = freq_qos_update_request(&cpudata->req[1], - policy->cpuinfo.max_freq); - if (ret < 0) + ret = rdmsrl_on_cpu(cpudata->cpu, MSR_K7_HWCR, &boost_val); + if (ret) { + pr_err_once("failed to read initial CPU boost state!\n"); return ret; + } - return 0; -} - -static void amd_pstate_boost_init(struct amd_cpudata *cpudata) -{ - u32 highest_perf, nominal_perf; - - highest_perf = READ_ONCE(cpudata->highest_perf); - nominal_perf = READ_ONCE(cpudata->nominal_perf); - - if (highest_perf <= nominal_perf) - return; + amd_pstate_global_params.cpb_supported = !(boost_val & MSR_K7_HWCR_CPB_DIS); + amd_pstate_global_params.cpb_boost = amd_pstate_global_params.cpb_supported; - cpudata->boost_supported = true; - current_pstate_driver->boost_enabled = true; + return ret; } static void amd_perf_ctl_reset(unsigned int cpu) @@ -923,6 +903,9 @@ static int amd_pstate_cpu_init(struct cpufreq_policy *policy) if (ret) goto free_cpudata1; + /* initialize cpu cores boot state */ + amd_pstate_boost_init(cpudata); + min_freq = amd_get_min_freq(cpudata); nominal_freq = amd_get_nominal_freq(cpudata); cpudata->nominal_freq = nominal_freq; @@ -974,7 +957,6 @@ static int amd_pstate_cpu_init(struct cpufreq_policy *policy) policy->driver_data = cpudata; - amd_pstate_boost_init(cpudata); if (!current_pstate_driver->adjust_perf) current_pstate_driver->adjust_perf = amd_pstate_adjust_perf; @@ -1385,6 +1367,9 @@ static int amd_pstate_epp_cpu_init(struct cpufreq_policy *policy) if (ret) goto free_cpudata1; + /* initialize cpu cores boot state */ + amd_pstate_boost_init(cpudata); + min_freq = amd_get_min_freq(cpudata); nominal_freq = amd_get_nominal_freq(cpudata); cpudata->nominal_freq = nominal_freq; @@ -1435,7 +1420,6 @@ static int amd_pstate_epp_cpu_init(struct cpufreq_policy *policy) return ret; WRITE_ONCE(cpudata->cppc_cap1_cached, value); } - amd_pstate_boost_init(cpudata); return 0; diff --git a/include/linux/amd-pstate.h b/include/linux/amd-pstate.h index 1fbbe75c3dcc..383359f9cd6f 100644 --- a/include/linux/amd-pstate.h +++ b/include/linux/amd-pstate.h @@ -131,4 +131,17 @@ struct quirk_entry { u32 lowest_freq; }; +/** + * struct amd_pstate_global_params - Global parameters, mostly tunable via sysfs. + * @cpb_boost: Whether or not to use boost CPU P-states. + * @cpb_supported: Whether or not CPU boost P-states are available + * based on the MSR_K7_HWCR bit[25] state + */ +struct amd_pstate_global_params { + bool cpb_boost; + bool cpb_supported; +}; + +extern struct amd_pstate_global_params amd_pstate_global_params; + #endif /* _LINUX_AMD_PSTATE_H */ From patchwork Fri Mar 15 03:38:04 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Yuan, Perry" X-Patchwork-Id: 13593029 Received: from NAM02-SN1-obe.outbound.protection.outlook.com (mail-sn1nam02on2052.outbound.protection.outlook.com [40.107.96.52]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 2CAB2D52A; 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Thu, 14 Mar 2024 22:39:24 -0500 From: Perry Yuan To: , , , , , CC: , , , , , Subject: [PATCH v5 3/8] cpufreq: amd-pstate: implement cpb_boost sysfs entry for boost control Date: Fri, 15 Mar 2024 11:38:04 +0800 Message-ID: <44b62d7415b9c6cfa7467ff82e88566131f4bb9a.1710473712.git.perry.yuan@amd.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: References: Precedence: bulk X-Mailing-List: linux-pm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-ClientProxiedBy: SATLEXMB04.amd.com (10.181.40.145) To SATLEXMB04.amd.com (10.181.40.145) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: CH2PEPF00000142:EE_|MW4PR12MB6897:EE_ X-MS-Office365-Filtering-Correlation-Id: 7a63c1a2-44d7-4429-4c75-08dc44a18431 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: t6i8rsZOJT5uvjglUS0arcM7bzN7Iewi30CA+tigpnpc33ubg9vidU9U4ujb0PCgUXZVmfSqb4FgGh3fGPuGfDufD1S7mDFIolthZfs5PZju1PdNi+rJreTxZLTtzAdgCxIYX1Ffzm6cdmJ3y7fgEH0cZnSUmVwIr9Qu8j3j/s5GW04EpZ3fXCuPS+XH+TTbNC3JPAXA95KEuukpA6IxtIoBE6U3wd1KMl1fjkRNDa4OuYvRO+UweJTH4JUT3ddFgXr4INnTFZoaMi/zPrIMyEvm+9XyXBU7/kGRELu503UiAuF5ng9WzYB3836nEuBTTzli6dQzs5MvenI+koVaiwDA2q3x/1pxSDEQ5vz5XdCFThj6T9XfH464BhgZedhpm6CI8CqkZICNJykJOv/R5BmpFnAJt1RluOIPQ4eijf8rbCynglWkOU/n7o+gduB81nNijzs3k/7A9AJSdREul62kdCkk7Tu9dx5EGYrOMPnf+n9bctuoAfDPlr2iXOA149p4Xu5+CRUANyubCl1ZtGkZ5lh9GCVbqlq2P7WcOc/7fdt6NPTC3/FTqQl9ajsH5A7Y/1CHJJQWrf7Yv0hJ7G4sOFgUD5XB/IOsU13Ma3NVDQd+S+HOiOEZOp6HD9v6s9CzN5yDzqH44YIPDmXriq57RLhhghJouk8NEqWigLklzzXRLiWCGXnel7WDZ4RDb7d0ZoWaj0VlU7AHXNn+Qg== X-Forefront-Antispam-Report: CIP:165.204.84.17;CTRY:US;LANG:en;SCL:1;SRV:;IPV:CAL;SFV:NSPM;H:SATLEXMB04.amd.com;PTR:InfoDomainNonexistent;CAT:NONE;SFS:(13230031)(376005)(1800799015)(82310400014)(36860700004);DIR:OUT;SFP:1101; X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 15 Mar 2024 03:39:27.7390 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 7a63c1a2-44d7-4429-4c75-08dc44a18431 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: CH2PEPF00000142.namprd02.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: MW4PR12MB6897 From: Perry Yuan With this new sysfs entry `cpb_boost`created, user can change CPU boost state dynamically under `active`, `guided` and `passive` modes. And the highest perf and frequency will also be updated as the boost state changing. 0): check current boost state cat /sys/devices/system/cpu/amd_pstate/cpb_boost 1): disable CPU boost sudo bash -c "echo 0 > /sys/devices/system/cpu/amd_pstate/cpb_boost" 2): enable CPU boost sudo bash -c "echo 1 > /sys/devices/system/cpu/amd_pstate/cpb_boost" Link: https://bugzilla.kernel.org/show_bug.cgi?id=217931 Link: https://bugzilla.kernel.org/show_bug.cgi?id=217618 Signed-off-by: Perry Yuan --- drivers/cpufreq/amd-pstate.c | 97 ++++++++++++++++++++++++++++++++++++ 1 file changed, 97 insertions(+) diff --git a/drivers/cpufreq/amd-pstate.c b/drivers/cpufreq/amd-pstate.c index e5eb09f874ba..025f35bd3b01 100644 --- a/drivers/cpufreq/amd-pstate.c +++ b/drivers/cpufreq/amd-pstate.c @@ -1276,6 +1276,101 @@ static ssize_t prefcore_show(struct device *dev, return sysfs_emit(buf, "%s\n", str_enabled_disabled(amd_pstate_prefcore)); } +static int amd_cpu_boost_update(struct amd_cpudata *cpudata, u32 on) +{ + struct cpufreq_policy *policy = cpufreq_cpu_acquire(cpudata->cpu); + struct cppc_perf_ctrls perf_ctrls; + u32 highest_perf, nominal_perf; + int ret; + + if (!policy) + return -ENODATA; + + highest_perf = READ_ONCE(cpudata->highest_perf); + nominal_perf = READ_ONCE(cpudata->nominal_perf); + + if (boot_cpu_has(X86_FEATURE_CPPC)) { + u64 value = READ_ONCE(cpudata->cppc_req_cached); + + value &= ~GENMASK_ULL(7, 0); + value |= on ? highest_perf : nominal_perf; + WRITE_ONCE(cpudata->cppc_req_cached, value); + + wrmsrl_on_cpu(cpudata->cpu, MSR_AMD_CPPC_REQ, value); + + } else { + perf_ctrls.max_perf = on ? highest_perf : nominal_perf; + ret = cppc_set_epp_perf(cpudata->cpu, &perf_ctrls, 1); + if (ret) { + pr_debug("failed to set energy perf value (%d)\n", ret); + return ret; + } + } + + if (on) + policy->cpuinfo.max_freq = cpudata->max_freq; + else + policy->cpuinfo.max_freq = cpudata->nominal_freq * 1000; + + policy->max = policy->cpuinfo.max_freq; + + if (cppc_state == AMD_PSTATE_PASSIVE) { + ret = freq_qos_update_request(&cpudata->req[1], + policy->cpuinfo.max_freq); + } + + cpufreq_cpu_release(policy); + + return ret; +} + +static ssize_t cpb_boost_show(struct device *dev, + struct device_attribute *attr, char *buf) +{ + return sysfs_emit(buf, "%u\n", amd_pstate_global_params.cpb_boost); +} + +static ssize_t cpb_boost_store(struct device *dev, struct device_attribute *b, + const char *buf, size_t count) +{ + bool new_state; + ssize_t ret; + int cpu; + + mutex_lock(&amd_pstate_driver_lock); + if (!amd_pstate_global_params.cpb_supported) { + pr_err("Boost mode is not supported by this processor or SBIOS\n"); + return -EINVAL; + } + + ret = kstrtobool(buf, &new_state); + if (ret) + return -EINVAL; + + amd_pstate_global_params.cpb_boost = !!new_state; + + for_each_online_cpu(cpu) { + + struct cpufreq_policy *policy = cpufreq_cpu_get(cpu); + struct amd_cpudata *cpudata = policy->driver_data; + + if (!cpudata) { + pr_err("cpudata is NULL\n"); + ret = -ENODATA; + cpufreq_cpu_put(policy); + goto err_exit; + } + + amd_cpu_boost_update(cpudata, amd_pstate_global_params.cpb_boost); + refresh_frequency_limits(policy); + cpufreq_cpu_put(policy); + } + +err_exit: + mutex_unlock(&amd_pstate_driver_lock); + return ret < 0 ? ret : count; +} + cpufreq_freq_attr_ro(amd_pstate_max_freq); cpufreq_freq_attr_ro(amd_pstate_lowest_nonlinear_freq); @@ -1286,6 +1381,7 @@ cpufreq_freq_attr_rw(energy_performance_preference); cpufreq_freq_attr_ro(energy_performance_available_preferences); static DEVICE_ATTR_RW(status); static DEVICE_ATTR_RO(prefcore); +static DEVICE_ATTR_RW(cpb_boost); static struct freq_attr *amd_pstate_attr[] = { &amd_pstate_max_freq, @@ -1310,6 +1406,7 @@ static struct freq_attr *amd_pstate_epp_attr[] = { static struct attribute *pstate_global_attributes[] = { &dev_attr_status.attr, &dev_attr_prefcore.attr, + &dev_attr_cpb_boost.attr, NULL }; From patchwork Fri Mar 15 03:38:05 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Yuan, Perry" X-Patchwork-Id: 13593030 Received: from NAM02-BN1-obe.outbound.protection.outlook.com (mail-bn1nam02on2083.outbound.protection.outlook.com [40.107.212.83]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 34895134B0; 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Thu, 14 Mar 2024 22:39:27 -0500 From: Perry Yuan To: , , , , , CC: , , , , , Subject: [PATCH v5 4/8] cpufreq: amd-pstate: fix max_perf calculation for amd_get_max_freq() Date: Fri, 15 Mar 2024 11:38:05 +0800 Message-ID: X-Mailer: git-send-email 2.34.1 In-Reply-To: References: Precedence: bulk X-Mailing-List: linux-pm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-ClientProxiedBy: SATLEXMB04.amd.com (10.181.40.145) To SATLEXMB04.amd.com (10.181.40.145) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: CH2PEPF0000013C:EE_|MW6PR12MB8897:EE_ X-MS-Office365-Filtering-Correlation-Id: df912904-23d3-4957-7b5c-08dc44a18619 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: W5VcEBSUKiXQjzbl1v/SoYascTYY2MgnOx1vQOig4KJfxZpXHs+h3it224/sglcjJvj2V/D81HdpRpOjXot2EiHd00nD8XyM4JCGCqVPeGntmcpppnwzEVfN20SUI/4OLQxzCaTkwyPx7MiB/JeewzP5SPBF4gR5o4M0gQP0a2wf5tbRlL+dz/ppHaI6zvDRDdUxVL26a5YJAx3LrD09ixqTOy2KozB6Ourg3vvkOlNWver5N1/cf5m5uqu/Rb7YiSU8m1jtLSFmgDsBP4DjU6v/PP/u3T/TJvO6bm4E2L2ynEJWY3MtPt94dkA6I4OZ1QzkTIUQR3PekZKlMvv2oDGbs7pswloVKQUBsuJxBlJNf26mm2XMHsIMuw7JGuk2QWl/zzajenhORTBvrk+O4pia5h0vIXonz0bb9In8CUymnTURzgqASND/dk8k6OUJ5FRy07TnLFzjffgo6AEB7dZYSfxhAGrhuD0hcsfrJ6jv8KgWOsOYLSxVAwPFzHYWuPosA8YFKRT9yH1GXB0IuKSlmV6xL/VkXh0HenvDohcfYelLUmQyhVAsouhSi0jJ8uTZFRyQfWr4vANFOUvCnlalV6//V2+oZmzfO6nDawifS41RyzX51VWJoWGDvqKDnFRkHuuGFic+h66kcisFkR8Rn8KAKXF4EhumDUYGYyOcg79XgnLbpJS/u/gVsBrfZz/PofoG7VDfTvTRhq3xcB1EJ6P1UC+8beYW27zPlHiPGeOI/iKs1qyepa1p9b17 X-Forefront-Antispam-Report: CIP:165.204.84.17;CTRY:US;LANG:en;SCL:1;SRV:;IPV:CAL;SFV:NSPM;H:SATLEXMB04.amd.com;PTR:InfoDomainNonexistent;CAT:NONE;SFS:(13230031)(376005)(1800799015)(36860700004)(82310400014);DIR:OUT;SFP:1101; X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 15 Mar 2024 03:39:30.9383 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: df912904-23d3-4957-7b5c-08dc44a18619 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: CH2PEPF0000013C.namprd02.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: MW6PR12MB8897 From: Perry Yuan When CPU core Precision Boost state changed, the max frequency will also need to be updated according to the current boost state, if boost is disabled now, the max perf will be limited to nominal perf values. otherwise the max frequency will be showed wrongly. Signed-off-by: Perry Yuan Reviewed-by: Gautham R. Shenoy --- drivers/cpufreq/amd-pstate.c | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/drivers/cpufreq/amd-pstate.c b/drivers/cpufreq/amd-pstate.c index 025f35bd3b01..a4bcac673fdb 100644 --- a/drivers/cpufreq/amd-pstate.c +++ b/drivers/cpufreq/amd-pstate.c @@ -676,6 +676,10 @@ static int amd_get_max_freq(struct amd_cpudata *cpudata) nominal_perf = READ_ONCE(cpudata->nominal_perf); max_perf = READ_ONCE(cpudata->highest_perf); + /* when boost is off, the highest perf will be limited to nominal_perf */ + if (!amd_pstate_global_params.cpb_boost) + max_perf = nominal_perf; + boost_ratio = div_u64(max_perf << SCHED_CAPACITY_SHIFT, nominal_perf); From patchwork Fri Mar 15 03:38:06 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Yuan, Perry" X-Patchwork-Id: 13593031 Received: from NAM11-BN8-obe.outbound.protection.outlook.com (mail-bn8nam11on2041.outbound.protection.outlook.com [40.107.236.41]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id BD826DDB3; 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Thu, 14 Mar 2024 22:39:30 -0500 From: Perry Yuan To: , , , , , CC: , , , , , Subject: [PATCH v5 5/8] cpufreq: amd-pstate: fix the MSR highest perf will be reset issue while cpb boost off Date: Fri, 15 Mar 2024 11:38:06 +0800 Message-ID: <0a2c227ccd39c8d350289edeb46970eb394b6dd7.1710473712.git.perry.yuan@amd.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: References: Precedence: bulk X-Mailing-List: linux-pm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-ClientProxiedBy: SATLEXMB04.amd.com (10.181.40.145) To SATLEXMB04.amd.com (10.181.40.145) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: CH2PEPF0000013B:EE_|PH8PR12MB7424:EE_ X-MS-Office365-Filtering-Correlation-Id: cf60fefb-9ff1-4420-66c8-08dc44a1880f X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: kKCkf1lA0fGGVlsvQrhPSoMB2cJC09VamzK+Du+/sDqvQ+wKfxT2IOBGOfhuivVMyT3azRfuWxAl8F82A9tOh1RqL9rlQr4zGrcPnSTdt2lIQmeUnb5nodEycCEQ9eCJ5RN8rJvwaORmYI1JKj8rzcInc2PExAnaTcggKtmwgRIt8nywNq4tkaA7o7pu7BUvKBA06jcu2SU8s3RmiFCu639n1XHTvrHzIZbT3QJIFjpuoSCQcO6vc/zs4Hd1178Va9/N81YSL9kHMDte+K8PmPYXcCTCqTU59ZbKxBSJZ0+K6/ny3Z/5Sj94jz4wCsu5soqjgosshjr6F7EULmJ95QxyIVO0jbAZlW8BpWNwWnTOWq26I9vTd2ZChSkvmKoJazk2dxpAl6jDVpFNzFALbbjXYhM4xgB+W2CxtX05AtR61kUTKrFJCW62DptvolhNX/8fMEJ1dhgB8VPYyS3tG+KFisjdIVKn+3OSD5iaMLSY+GdRiMbN2zerucFufYtj2w1NmXTPS1TX6zQeE58Yg2enuUHlVd7oY5kKLhmvtxI6hxwpGIZuEQYYYXKjTIjfBrSrrYvp2ohe4HCXM2uGGALDPPXCASWgzs1Ak/Qu73hCp+MCfcXQJRApm/Ci47HjpmMm8dNMmWKFkVA4dWSI8RFVzhy6T/zb37ZdDmbIYdbeVikoTnIyrewc8PciXesAEajVElR7X9SXaJ7+rfIfmZiZi9Gyyh1uWzbiW3pED9DGIv7WDutm8t0bH7YU0y0G X-Forefront-Antispam-Report: CIP:165.204.84.17;CTRY:US;LANG:en;SCL:1;SRV:;IPV:CAL;SFV:NSPM;H:SATLEXMB04.amd.com;PTR:InfoDomainNonexistent;CAT:NONE;SFS:(13230031)(1800799015)(36860700004)(376005)(82310400014);DIR:OUT;SFP:1101; X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 15 Mar 2024 03:39:34.2276 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: cf60fefb-9ff1-4420-66c8-08dc44a1880f X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: CH2PEPF0000013B.namprd02.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: PH8PR12MB7424 From: Perry Yuan Select the min perf to fix the highest perf value while update pstate CPPC request MSR register, here we need to limit the max perf value when CPU boost is disabled in case of that highest perf value in the MSR will be reset to original highest perf value which cause the BOOST control failed. Signed-off-by: Perry Yuan --- drivers/cpufreq/amd-pstate.c | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/drivers/cpufreq/amd-pstate.c b/drivers/cpufreq/amd-pstate.c index a4bcac673fdb..1fcb35d5c3fa 100644 --- a/drivers/cpufreq/amd-pstate.c +++ b/drivers/cpufreq/amd-pstate.c @@ -488,6 +488,7 @@ static void amd_pstate_update(struct amd_cpudata *cpudata, u32 min_perf, u32 des_perf, u32 max_perf, bool fast_switch, int gov_flags) { u64 prev = READ_ONCE(cpudata->cppc_req_cached); + u32 nominal_perf = READ_ONCE(cpudata->nominal_perf); u64 value = prev; min_perf = clamp_t(unsigned long, min_perf, cpudata->min_limit_perf, @@ -507,6 +508,10 @@ static void amd_pstate_update(struct amd_cpudata *cpudata, u32 min_perf, value &= ~AMD_CPPC_DES_PERF(~0L); value |= AMD_CPPC_DES_PERF(des_perf); + /* limit the max perf when core performance boost feature is disabled */ + if (!amd_pstate_global_params.cpb_boost) + max_perf = min_t(unsigned long, nominal_perf, max_perf); + value &= ~AMD_CPPC_MAX_PERF(~0L); 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X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 15 Mar 2024 03:39:37.3604 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 0c533132-4295-49fb-6bf9-08dc44a189ed X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: CH2PEPF0000013D.namprd02.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: MW6PR12MB8914 From: Perry Yuan Introduce AMD CPU frequency boosting control sysfs entry which used for switching boost on and boost off. If core performance boost is disabled while a core is in a boosted P-state, the core automatically transitions to the highest performance non-boosted P-state The highest perf and frequency will be limited by the setting value. Signed-off-by: Perry Yuan --- Documentation/admin-guide/pm/amd-pstate.rst | 11 +++++++++++ 1 file changed, 11 insertions(+) diff --git a/Documentation/admin-guide/pm/amd-pstate.rst b/Documentation/admin-guide/pm/amd-pstate.rst index 1e0d101b020a..82fbd01da658 100644 --- a/Documentation/admin-guide/pm/amd-pstate.rst +++ b/Documentation/admin-guide/pm/amd-pstate.rst @@ -440,6 +440,17 @@ control its functionality at the system level. They are located in the This attribute is read-only to check the state of preferred core set by the kernel parameter. +``cpb_boost`` + Specifies whether core performance boost is requested to be enabled or disabled + If core performance boost is disabled while a core is in a boosted P-state, the + core automatically transitions to the highest performance non-boosted P-state. + AMD Core Performance Boost(CPB) is controlled by this new attribute file which + allow user to change all cores frequency boosting state. It supports both + ``active``, ``passive`` and ``guided`` mode control with below value write to it. + + "0" Disable Core Performance Boosting + "1" Enable Core Performance Boosting + ``cpupower`` tool support for ``amd-pstate`` =============================================== From patchwork Fri Mar 15 03:38:08 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Yuan, Perry" X-Patchwork-Id: 13593033 Received: from NAM10-MW2-obe.outbound.protection.outlook.com (mail-mw2nam10on2087.outbound.protection.outlook.com [40.107.94.87]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id C6B0A168DA; Fri, 15 Mar 2024 03:39:44 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=fail smtp.client-ip=40.107.94.87 ARC-Seal: i=2; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1710473986; cv=fail; b=B2PoTtGiDkq8uGhDJyYUD4LN5SJjntEtIb9e4fTON9otN0tsaR5f6JDhtIlnKRvxIW1Kfsz+CY8bVXJYg/DS1qcACymso/Qb/uA5FHzBn4YnyyBMLRl80VJsBH9eE0u8tR8ITzl1dPywAA2n6BvlKzg8Yz7bogHn5zGs1omjrW4= ARC-Message-Signature: i=2; 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Signed-off-by: Perry Yuan --- drivers/cpufreq/amd-pstate.c | 1 - include/linux/amd-pstate.h | 2 -- 2 files changed, 3 deletions(-) diff --git a/drivers/cpufreq/amd-pstate.c b/drivers/cpufreq/amd-pstate.c index 1fcb35d5c3fa..7c39c44be598 100644 --- a/drivers/cpufreq/amd-pstate.c +++ b/drivers/cpufreq/amd-pstate.c @@ -1757,7 +1757,6 @@ static struct cpufreq_driver amd_pstate_driver = { .exit = amd_pstate_cpu_exit, .suspend = amd_pstate_cpu_suspend, .resume = amd_pstate_cpu_resume, - .set_boost = amd_pstate_set_boost, .update_limits = amd_pstate_update_limits, .name = "amd-pstate", .attr = amd_pstate_attr, diff --git a/include/linux/amd-pstate.h b/include/linux/amd-pstate.h index 383359f9cd6f..e89cf1249715 100644 --- a/include/linux/amd-pstate.h +++ b/include/linux/amd-pstate.h @@ -56,7 +56,6 @@ struct amd_aperf_mperf { * @cur: Difference of Aperf/Mperf/tsc count between last and current sample * @prev: Last Aperf/Mperf/tsc count value read from register * @freq: current cpu frequency value - * @boost_supported: check whether the Processor or SBIOS supports boost mode * @hw_prefcore: check whether HW supports preferred core featue. * Only when hw_prefcore and early prefcore param are true, * AMD P-State driver supports preferred core featue. @@ -94,7 +93,6 @@ struct amd_cpudata { struct amd_aperf_mperf prev; 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X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 15 Mar 2024 03:39:45.1532 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: dfb98b1c-2434-49ca-2078-08dc44a18e90 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: CH2PEPF0000013E.namprd02.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: PH7PR12MB5759 As the new CPB boost control is enabled, pstate unit test needs to remove legacy `boost_supported` check and start to use new CPB boost control interface `amd_pstate_global_params.cpb_boost`. Signed-off-by: Perry Yuan --- drivers/cpufreq/amd-pstate-ut.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/cpufreq/amd-pstate-ut.c b/drivers/cpufreq/amd-pstate-ut.c index f04ae67dda37..b3601b0e6dd3 100644 --- a/drivers/cpufreq/amd-pstate-ut.c +++ b/drivers/cpufreq/amd-pstate-ut.c @@ -226,7 +226,7 @@ static void amd_pstate_ut_check_freq(u32 index) goto skip_test; } - if (cpudata->boost_supported) { + if (amd_pstate_global_params.cpb_boost) { if ((policy->max == cpudata->max_freq) || (policy->max == cpudata->nominal_freq)) amd_pstate_ut_cases[index].result = AMD_PSTATE_UT_RESULT_PASS;