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[46.102.197.201]) by smtp.gmail.com with ESMTPSA id s6-20020a5d69c6000000b0033e9f6997c7sm3631448wrw.66.2024.03.15.10.52.27 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 15 Mar 2024 10:52:27 -0700 (PDT) X-BeenThere: xen-devel@lists.xenproject.org List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , Errors-To: xen-devel-bounces@lists.xenproject.org Precedence: list Sender: "Xen-devel" X-Inumbo-ID: ca78f8af-e2f4-11ee-afdd-a90da7624cb6 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=cloud.com; s=cloud; t=1710525148; x=1711129948; darn=lists.xenproject.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=A3xo7OpI3t17GvZtWVbf/bOFO4OxNlnVn4a3LYdu7XY=; b=lD31A+PCY8pEBsu1/GrO+uUYPeTT4tztVBGCoLJZjNtgvdPF31T4F9OvXX2iSWO678 G/O/FEBjwp/IrRZWcAKiu3rXoJPg1UlEnEGVDwTiBVmcUssY9OWh4K0AxYLjq3OqnpnJ 9GLbIfMo9Rxcy2lGfQgjsld6MGeyn9Ct0XL9U= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1710525148; x=1711129948; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=A3xo7OpI3t17GvZtWVbf/bOFO4OxNlnVn4a3LYdu7XY=; b=gDoduhQTVM7bR9KVuuuG2qtlyrGOwmY/MZV/DOoeQmSxxo+rMo+LnIZY4OyzkFW4fY R+LufwxQyKwiRw81sE3v2SJv9xJhOFEpKHRgriZQDyPlwZjebin9w79PeaDZcC/bGNSM wNiWF11JeEb+Pg62BjOUAga1CKkWQIbQu2lLTJ5h6+ZuOEXqPOka1FvusTTHjnwsrUno Lt68q98qr0NFdX1z1oKz5EqOiWKk24iHUb3C9LQAKoX1t2OQojCe2Q572vkhmHxWp/SX ViZWV+R3peVwbdnqeLZfZapSc1FM5X/AQaAI4eVQKx0+/kEYihHvlSTISuxHKU0uwwXL SNFA== X-Gm-Message-State: AOJu0YwWBzviF0Aca2Cgz1MNqp3DCU/ep9//KvKuE5icpyNAaBRF6gri Sil1d8fiWzkGoBPjeBdcetS+ObfrYjdqc7iyaFJw5dRcGwZ5tHO19COWhWe2c5Q3N+FbhrgnDId V X-Google-Smtp-Source: AGHT+IFZr9DuyeXZebztwFFVMcKj7dEhu/jn+GFXCDO8LtgYFsieP3WM/Qj8hWEkm8nk9Euy5eeCzw== X-Received: by 2002:adf:ff87:0:b0:33e:6833:8fa9 with SMTP id j7-20020adfff87000000b0033e68338fa9mr3985505wrr.44.1710525148557; Fri, 15 Mar 2024 10:52:28 -0700 (PDT) From: Matthew Barnes To: Xen-devel Cc: Matthew Barnes , Jan Beulich , Andrew Cooper , =?utf-8?q?Roger_Pau_Monn=C3=A9?= , Wei Liu Subject: [XEN PATCH 1/2] x86: Enable BLD and handle #DB traps Date: Fri, 15 Mar 2024 17:52:23 +0000 Message-Id: <5c0c2fd252f425a397981546496438ebac439db2.1710524011.git.matthew.barnes@cloud.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: References: MIME-Version: 1.0 Enable Bus Lock Detect if available, and handle #DB traps to reduce effects of DoS. The value to restore MSR_DEBUGCTL to after VMExit will now depend on whether BLD is enabled or not. Restore MSR_DEBUGCTL after being cleared by storing a copy of the register value in memory, instead of hard-coding it. Signed-off-by: Matthew Barnes --- xen/arch/x86/cpu/common.c | 5 +++++ xen/arch/x86/hvm/vmx/entry.S | 2 +- xen/arch/x86/include/asm/debugreg.h | 1 + xen/arch/x86/include/asm/msr-index.h | 1 + xen/arch/x86/include/asm/msr.h | 2 ++ xen/arch/x86/msr.c | 2 ++ xen/arch/x86/traps.c | 10 ++++++++-- 7 files changed, 20 insertions(+), 3 deletions(-) diff --git a/xen/arch/x86/cpu/common.c b/xen/arch/x86/cpu/common.c index 28d7f34c4dbe..f11ac06f8292 100644 --- a/xen/arch/x86/cpu/common.c +++ b/xen/arch/x86/cpu/common.c @@ -623,6 +623,11 @@ void identify_cpu(struct cpuinfo_x86 *c) } setup_doitm(); + + if (cpu_has(c, X86_FEATURE_BLD)) { + host_msr_debugctl |= IA32_DEBUGCTLMSR_BLD; + wrmsrl(MSR_IA32_DEBUGCTLMSR, host_msr_debugctl); + } } /* leaf 0xb SMT level */ diff --git a/xen/arch/x86/hvm/vmx/entry.S b/xen/arch/x86/hvm/vmx/entry.S index 1bead826caa3..a0148f78584d 100644 --- a/xen/arch/x86/hvm/vmx/entry.S +++ b/xen/arch/x86/hvm/vmx/entry.S @@ -46,8 +46,8 @@ ENTRY(vmx_asm_vmexit_handler) /* WARNING! `ret`, `call *`, `jmp *` not safe before this point. */ /* Hardware clears MSR_DEBUGCTL on VMExit. Reinstate it if debugging Xen. */ + mov host_msr_debugctl(%rip), %eax .macro restore_lbr - mov $IA32_DEBUGCTLMSR_LBR, %eax mov $MSR_IA32_DEBUGCTLMSR, %ecx xor %edx, %edx wrmsr diff --git a/xen/arch/x86/include/asm/debugreg.h b/xen/arch/x86/include/asm/debugreg.h index 2bdaf5d9aa11..9c048ae215d6 100644 --- a/xen/arch/x86/include/asm/debugreg.h +++ b/xen/arch/x86/include/asm/debugreg.h @@ -19,6 +19,7 @@ #define DR_TRAP1 (0x2) /* db1 */ #define DR_TRAP2 (0x4) /* db2 */ #define DR_TRAP3 (0x8) /* db3 */ +#define DR_TRAP11 (0x800) /* db11 */ #define DR_STEP (0x4000) /* single-step */ #define DR_SWITCH (0x8000) /* task switch */ #define DR_NOT_RTM (0x10000) /* clear: #BP inside RTM region */ diff --git a/xen/arch/x86/include/asm/msr-index.h b/xen/arch/x86/include/asm/msr-index.h index 92dd9fa4962c..2e397bd28c77 100644 --- a/xen/arch/x86/include/asm/msr-index.h +++ b/xen/arch/x86/include/asm/msr-index.h @@ -292,6 +292,7 @@ #define MSR_IA32_DEBUGCTLMSR 0x000001d9 #define IA32_DEBUGCTLMSR_LBR (1<<0) /* Last Branch Record */ #define IA32_DEBUGCTLMSR_BTF (1<<1) /* Single Step on Branches */ +#define IA32_DEBUGCTLMSR_BLD (1<<2) /* Bus Lock Detect */ #define IA32_DEBUGCTLMSR_TR (1<<6) /* Trace Message Enable */ #define IA32_DEBUGCTLMSR_BTS (1<<7) /* Branch Trace Store */ #define IA32_DEBUGCTLMSR_BTINT (1<<8) /* Branch Trace Interrupt */ diff --git a/xen/arch/x86/include/asm/msr.h b/xen/arch/x86/include/asm/msr.h index 1d8ea9f26faa..9ff7dcc8ca8b 100644 --- a/xen/arch/x86/include/asm/msr.h +++ b/xen/arch/x86/include/asm/msr.h @@ -432,4 +432,6 @@ int init_vcpu_msr_policy(struct vcpu *v); int guest_rdmsr(struct vcpu *v, uint32_t msr, uint64_t *val); int guest_wrmsr(struct vcpu *v, uint32_t msr, uint64_t val); +extern uint32_t host_msr_debugctl; + #endif /* __ASM_MSR_H */ diff --git a/xen/arch/x86/msr.c b/xen/arch/x86/msr.c index 9babd441f9d4..7d9d162cb8b4 100644 --- a/xen/arch/x86/msr.c +++ b/xen/arch/x86/msr.c @@ -24,6 +24,8 @@ #include +uint32_t host_msr_debugctl; + DEFINE_PER_CPU(uint32_t, tsc_aux); int init_vcpu_msr_policy(struct vcpu *v) diff --git a/xen/arch/x86/traps.c b/xen/arch/x86/traps.c index d554c9d41edd..7d8eee013d00 100644 --- a/xen/arch/x86/traps.c +++ b/xen/arch/x86/traps.c @@ -1936,9 +1936,12 @@ void asmlinkage do_debug(struct cpu_user_regs *regs) */ write_debugreg(6, X86_DR6_DEFAULT); + if ( !( dr6 & DR_TRAP11 ) ) + return; + /* #DB automatically disabled LBR. Reinstate it if debugging Xen. */ if ( cpu_has_xen_lbr ) - wrmsrl(MSR_IA32_DEBUGCTLMSR, IA32_DEBUGCTLMSR_LBR); + wrmsrl(MSR_IA32_DEBUGCTLMSR, host_msr_debugctl); if ( !guest_mode(regs) ) { @@ -2130,7 +2133,10 @@ void percpu_traps_init(void) } if ( cpu_has_xen_lbr ) - wrmsrl(MSR_IA32_DEBUGCTLMSR, IA32_DEBUGCTLMSR_LBR); + { + host_msr_debugctl |= IA32_DEBUGCTLMSR_LBR; + wrmsrl(MSR_IA32_DEBUGCTLMSR, host_msr_debugctl); + } } /* Exception entries */ From patchwork Fri Mar 15 17:52:24 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Matthew Barnes X-Patchwork-Id: 13593819 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.xenproject.org (lists.xenproject.org [192.237.175.120]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 6997FC54E67 for ; Fri, 15 Mar 2024 17:52:55 +0000 (UTC) Received: from list by lists.xenproject.org with outflank-mailman.693977.1082675 (Exim 4.92) (envelope-from ) id 1rlBjN-0003Lb-3Z; Fri, 15 Mar 2024 17:52:33 +0000 X-Outflank-Mailman: Message body and most headers restored to incoming version Received: by outflank-mailman (output) from mailman id 693977.1082675; Fri, 15 Mar 2024 17:52:33 +0000 Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1rlBjM-0003LS-Ur; Fri, 15 Mar 2024 17:52:32 +0000 Received: by outflank-mailman (input) for mailman id 693977; Fri, 15 Mar 2024 17:52:31 +0000 Received: from se1-gles-sth1-in.inumbo.com ([159.253.27.254] helo=se1-gles-sth1.inumbo.com) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1rlBjL-0002sX-4Y for xen-devel@lists.xenproject.org; Fri, 15 Mar 2024 17:52:31 +0000 Received: from mail-wr1-x42e.google.com (mail-wr1-x42e.google.com [2a00:1450:4864:20::42e]) by se1-gles-sth1.inumbo.com (Halon) with ESMTPS id cb15cd4d-e2f4-11ee-afdd-a90da7624cb6; Fri, 15 Mar 2024 18:52:30 +0100 (CET) Received: by mail-wr1-x42e.google.com with SMTP id ffacd0b85a97d-33ed7ef0ae8so137624f8f.0 for ; Fri, 15 Mar 2024 10:52:30 -0700 (PDT) Received: from EMEAENGAAD91498.citrite.net (default-46-102-197-201.interdsl.co.uk. [46.102.197.201]) by smtp.gmail.com with ESMTPSA id s6-20020a5d69c6000000b0033e9f6997c7sm3631448wrw.66.2024.03.15.10.52.28 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 15 Mar 2024 10:52:29 -0700 (PDT) X-BeenThere: xen-devel@lists.xenproject.org List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , Errors-To: xen-devel-bounces@lists.xenproject.org Precedence: list Sender: "Xen-devel" X-Inumbo-ID: cb15cd4d-e2f4-11ee-afdd-a90da7624cb6 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=cloud.com; s=cloud; t=1710525149; x=1711129949; darn=lists.xenproject.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=DhANpMH0RmM2IazXWYR9pQ3eiDcQ2h+dRBwSMMkIqgk=; b=LKj7pryhWyugbzCwRfcBBbY2VW+UULNr2ePhyMDZZMsTzBqbXzIgYB/6OnSPJqH3fD lVSPwJyCQ1BjXX2ok1HiTU012xtoFgJvPZgxkvLHB6bp0UDas6Nh4iY9T94p6HpqBjUu tnLyzIV9KdfvcaA75uVIrLm6JSPfDfdYrsr0U= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1710525149; x=1711129949; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=DhANpMH0RmM2IazXWYR9pQ3eiDcQ2h+dRBwSMMkIqgk=; b=jYAz4bOMQ2aUwl5o1zOaEDXpRgR4o8kyHxIBBI4OXhb/eLWUBD01aJwUn+nq+uvbSs Zl/7mn26k3Iulnd+2RKilnpgfNfTn1LXSdEH5Eg7KVR4Wrf849EJ2bqqcM3t7/tqAfjE IZbaOLOM50FAn7Ls+LrO0l3wY+Yy4f/hZRNeplJYpV9uBiZ+BHHrIU4vNCXR8RwqTNyD CTTvIbkWXqH/q2kE5x+AYqQSlVbpVjM0YtKRI0LRJHUFTJAOjUBLGjk1Uon4bCyJaPzU vjFupNey1970RrDvoM4XY2xq9Ftgt9MUCmFHoMvvMpX+v9OxX8r1daa5elPpx+S1IkiF GMIQ== X-Gm-Message-State: AOJu0Yy0AMM33jdJVVdZBR79U4fznhtR2JFBJkIvoj/i88RMk5KN3Aqn 9MkDicltejoImwKebfP6a1WjUQxvUmFAejMKSTNsadQmol7YTBM2Fi87tjYFINMI1jyfMtXaF7T i X-Google-Smtp-Source: AGHT+IHbuMsADpmNOECnVBNngfrOhAuNJq6QcV5ZjMangmbYD50/9fKavTSvct6iL02sv/soYyNy4Q== X-Received: by 2002:a5d:58c4:0:b0:33e:d8f:3466 with SMTP id o4-20020a5d58c4000000b0033e0d8f3466mr3295974wrf.33.1710525149322; Fri, 15 Mar 2024 10:52:29 -0700 (PDT) From: Matthew Barnes To: Xen-devel Cc: Matthew Barnes , Jan Beulich , Andrew Cooper , =?utf-8?q?Roger_Pau_Monn=C3=A9?= , Wei Liu Subject: [XEN PATCH 2/2] x86: Refactor LBR feature to MSR_DEBUGCTL feature Date: Fri, 15 Mar 2024 17:52:24 +0000 Message-Id: <2f690a115fc78989bfc2e331221d7e10b5dcb196.1710524011.git.matthew.barnes@cloud.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: References: MIME-Version: 1.0 Last Branch Record and Bus Lock Detect both belong to the same MSR. The same mechanism that restores LBR also restores BLD. Therefore, the name of the feature that enables this mechanism should reflect restoring the MSR, instead of one field. No functional change. Signed-off-by: Matthew Barnes --- xen/arch/x86/hvm/vmx/entry.S | 4 ++-- xen/arch/x86/include/asm/cpufeature.h | 2 +- xen/arch/x86/include/asm/cpufeatures.h | 2 +- xen/arch/x86/traps.c | 6 +++--- 4 files changed, 7 insertions(+), 7 deletions(-) diff --git a/xen/arch/x86/hvm/vmx/entry.S b/xen/arch/x86/hvm/vmx/entry.S index a0148f78584d..acfdc370289d 100644 --- a/xen/arch/x86/hvm/vmx/entry.S +++ b/xen/arch/x86/hvm/vmx/entry.S @@ -47,12 +47,12 @@ ENTRY(vmx_asm_vmexit_handler) /* Hardware clears MSR_DEBUGCTL on VMExit. Reinstate it if debugging Xen. */ mov host_msr_debugctl(%rip), %eax - .macro restore_lbr + .macro restore_msr_debugctl mov $MSR_IA32_DEBUGCTLMSR, %ecx xor %edx, %edx wrmsr .endm - ALTERNATIVE "", restore_lbr, X86_FEATURE_XEN_LBR + ALTERNATIVE "", restore_msr_debugctl, X86_FEATURE_XEN_MSR_DEBUGCTL mov %rsp,%rdi call vmx_vmexit_handler diff --git a/xen/arch/x86/include/asm/cpufeature.h b/xen/arch/x86/include/asm/cpufeature.h index 9bc553681f4a..084501c76a03 100644 --- a/xen/arch/x86/include/asm/cpufeature.h +++ b/xen/arch/x86/include/asm/cpufeature.h @@ -223,7 +223,7 @@ static inline bool boot_cpu_has(unsigned int feat) #define cpu_has_aperfmperf boot_cpu_has(X86_FEATURE_APERFMPERF) #define cpu_has_lfence_dispatch boot_cpu_has(X86_FEATURE_LFENCE_DISPATCH) #define cpu_has_nscb boot_cpu_has(X86_FEATURE_NSCB) -#define cpu_has_xen_lbr boot_cpu_has(X86_FEATURE_XEN_LBR) +#define cpu_has_xen_msr_debugctl boot_cpu_has(X86_FEATURE_XEN_MSR_DEBUGCTL) #define cpu_has_xen_shstk (IS_ENABLED(CONFIG_XEN_SHSTK) && \ boot_cpu_has(X86_FEATURE_XEN_SHSTK)) #define cpu_has_xen_ibt (IS_ENABLED(CONFIG_XEN_IBT) && \ diff --git a/xen/arch/x86/include/asm/cpufeatures.h b/xen/arch/x86/include/asm/cpufeatures.h index 7e8221fd85dd..060d7c1d5c9e 100644 --- a/xen/arch/x86/include/asm/cpufeatures.h +++ b/xen/arch/x86/include/asm/cpufeatures.h @@ -34,7 +34,7 @@ XEN_CPUFEATURE(SC_RSB_PV, X86_SYNTH(18)) /* RSB overwrite needed for PV XEN_CPUFEATURE(SC_RSB_HVM, X86_SYNTH(19)) /* RSB overwrite needed for HVM */ XEN_CPUFEATURE(XEN_SELFSNOOP, X86_SYNTH(20)) /* SELFSNOOP gets used by Xen itself */ XEN_CPUFEATURE(SC_MSR_IDLE, X86_SYNTH(21)) /* Clear MSR_SPEC_CTRL on idle */ -XEN_CPUFEATURE(XEN_LBR, X86_SYNTH(22)) /* Xen uses MSR_DEBUGCTL.LBR */ +XEN_CPUFEATURE(XEN_MSR_DEBUGCTL, X86_SYNTH(22)) /* Xen uses MSR_DEBUGCTL */ XEN_CPUFEATURE(SC_DIV, X86_SYNTH(23)) /* DIV scrub needed */ XEN_CPUFEATURE(SC_RSB_IDLE, X86_SYNTH(24)) /* RSB overwrite needed for idle. */ XEN_CPUFEATURE(SC_VERW_IDLE, X86_SYNTH(25)) /* VERW used by Xen for idle */ diff --git a/xen/arch/x86/traps.c b/xen/arch/x86/traps.c index 7d8eee013d00..16bef5d76620 100644 --- a/xen/arch/x86/traps.c +++ b/xen/arch/x86/traps.c @@ -1940,7 +1940,7 @@ void asmlinkage do_debug(struct cpu_user_regs *regs) return; /* #DB automatically disabled LBR. Reinstate it if debugging Xen. */ - if ( cpu_has_xen_lbr ) + if ( cpu_has_xen_msr_debugctl ) wrmsrl(MSR_IA32_DEBUGCTLMSR, host_msr_debugctl); if ( !guest_mode(regs) ) @@ -2129,10 +2129,10 @@ void percpu_traps_init(void) return; } - setup_force_cpu_cap(X86_FEATURE_XEN_LBR); + setup_force_cpu_cap(X86_FEATURE_XEN_MSR_DEBUGCTL); } - if ( cpu_has_xen_lbr ) + if ( cpu_has_xen_msr_debugctl ) { host_msr_debugctl |= IA32_DEBUGCTLMSR_LBR; wrmsrl(MSR_IA32_DEBUGCTLMSR, host_msr_debugctl);