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Signed-off-by: Taniya Das --- .../devicetree/bindings/clock/qcom,sc7280-lpasscorecc.yaml | 1 + 1 file changed, 1 insertion(+) -- 2.17.1 diff --git a/Documentation/devicetree/bindings/clock/qcom,sc7280-lpasscorecc.yaml b/Documentation/devicetree/bindings/clock/qcom,sc7280-lpasscorecc.yaml index deee5423d66e..861b41933525 100644 --- a/Documentation/devicetree/bindings/clock/qcom,sc7280-lpasscorecc.yaml +++ b/Documentation/devicetree/bindings/clock/qcom,sc7280-lpasscorecc.yaml @@ -30,6 +30,7 @@ properties: - qcom,sc7280-lpassaudiocc - qcom,sc7280-lpasscorecc - qcom,sc7280-lpasshm + - qcom,qcm6490-lpassaudiocc power-domains: maxItems: 1 From patchwork Mon Mar 18 05:35:49 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Taniya Das X-Patchwork-Id: 13594990 Received: from mx0a-0031df01.pphosted.com (mx0a-0031df01.pphosted.com [205.220.168.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id B98061E4AE; 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Mon, 18 Mar 2024 05:36:55 +0000 (GMT) Received: from nalasex01b.na.qualcomm.com (nalasex01b.na.qualcomm.com [10.47.209.197]) by NALASPPMTA05.qualcomm.com (8.17.1.5/8.17.1.5) with ESMTPS id 42I5asT3014385 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Mon, 18 Mar 2024 05:36:54 GMT Received: from hu-tdas-hyd.qualcomm.com (10.80.80.8) by nalasex01b.na.qualcomm.com (10.47.209.197) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1118.40; Sun, 17 Mar 2024 22:36:50 -0700 From: Taniya Das To: Stephen Boyd , =?utf-8?q?Michael_Turquette_=C2=A0?= , Bjorn Andersson , "Konrad Dybcio" , Rob Herring , Krzysztof Kozlowski , Conor Dooley CC: Taniya Das , , , Subject: [PATCH v2 2/8] clk: qcom: lpassaudiocc-sc7280: Add support for LPASS resets for QCM6490 Date: Mon, 18 Mar 2024 11:05:49 +0530 Message-ID: <20240318053555.20405-3-quic_tdas@quicinc.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20240318053555.20405-1-quic_tdas@quicinc.com> References: <20240318053555.20405-1-quic_tdas@quicinc.com> Precedence: bulk X-Mailing-List: linux-arm-msm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-ClientProxiedBy: nasanex01b.na.qualcomm.com (10.46.141.250) To nalasex01b.na.qualcomm.com (10.47.209.197) X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-GUID: HFd3OYf-fE1BPiXuJF0RXFfQZZQ2ANnD X-Proofpoint-ORIG-GUID: HFd3OYf-fE1BPiXuJF0RXFfQZZQ2ANnD X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.272,Aquarius:18.0.1011,Hydra:6.0.619,FMLib:17.11.176.26 definitions=2024-03-17_12,2024-03-15_01,2023-05-22_02 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 mlxscore=0 bulkscore=0 clxscore=1015 priorityscore=1501 phishscore=0 suspectscore=0 lowpriorityscore=0 spamscore=0 malwarescore=0 impostorscore=0 adultscore=0 mlxlogscore=999 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.19.0-2403140001 definitions=main-2403180040 On the QCM6490 boards the LPASS firmware controls the complete clock controller functionalities. But the LPASS resets are required to be from the high level OS for the LPASS SW driver could assert/deassert the audio resets. Fixes: a9dd26639d05 ("clk: qcom: lpass: Add support for LPASS clock controller for SC7280") Signed-off-by: Taniya Das --- drivers/clk/qcom/lpassaudiocc-sc7280.c | 9 +++++++++ 1 file changed, 9 insertions(+) -- 2.17.1 diff --git a/drivers/clk/qcom/lpassaudiocc-sc7280.c b/drivers/clk/qcom/lpassaudiocc-sc7280.c index c43d0b1af7f7..d68139762a80 100644 --- a/drivers/clk/qcom/lpassaudiocc-sc7280.c +++ b/drivers/clk/qcom/lpassaudiocc-sc7280.c @@ -1,6 +1,7 @@ // SPDX-License-Identifier: GPL-2.0-only /* * Copyright (c) 2021, The Linux Foundation. All rights reserved. + * Copyright (c) 2024, Qualcomm Innovation Center, Inc. All rights reserved. */ #include @@ -721,6 +722,7 @@ static const struct qcom_cc_desc lpass_audio_cc_reset_sc7280_desc = { static const struct of_device_id lpass_audio_cc_sc7280_match_table[] = { { .compatible = "qcom,sc7280-lpassaudiocc" }, + { .compatible = "qcom,qcm6490-lpassaudiocc" }, { } }; MODULE_DEVICE_TABLE(of, lpass_audio_cc_sc7280_match_table); @@ -752,6 +754,13 @@ static int lpass_audio_cc_sc7280_probe(struct platform_device *pdev) struct regmap *regmap; int ret; + if (of_device_is_compatible(pdev->dev.of_node, "qcom,qcm6490-lpassaudiocc")) { + ret = qcom_cc_probe_by_index(pdev, 1, &lpass_audio_cc_reset_sc7280_desc); + if (ret) + dev_err(&pdev->dev, "Failed to register LPASS AUDIO CC Resets\n"); + return ret; + } + ret = lpass_audio_setup_runtime_pm(pdev); if (ret) return ret; From patchwork Mon Mar 18 05:35:50 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Taniya Das X-Patchwork-Id: 13594991 Received: from mx0a-0031df01.pphosted.com (mx0a-0031df01.pphosted.com [205.220.168.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 245BA1E4AE; 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Mon, 18 Mar 2024 05:36:58 +0000 (GMT) Received: from nalasex01b.na.qualcomm.com (nalasex01b.na.qualcomm.com [10.47.209.197]) by NALASPPMTA05.qualcomm.com (8.17.1.5/8.17.1.5) with ESMTPS id 42I5avTA014417 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Mon, 18 Mar 2024 05:36:57 GMT Received: from hu-tdas-hyd.qualcomm.com (10.80.80.8) by nalasex01b.na.qualcomm.com (10.47.209.197) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1118.40; Sun, 17 Mar 2024 22:36:53 -0700 From: Taniya Das To: Stephen Boyd , =?utf-8?q?Michael_Turquette_=C2=A0?= , Bjorn Andersson , "Konrad Dybcio" , Rob Herring , Krzysztof Kozlowski , Conor Dooley CC: Taniya Das , , , Subject: [PATCH v2 3/8] clk: qcom: lpassaudiocc-sc7280: Fix the regmap conflict warning Date: Mon, 18 Mar 2024 11:05:50 +0530 Message-ID: <20240318053555.20405-4-quic_tdas@quicinc.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20240318053555.20405-1-quic_tdas@quicinc.com> References: <20240318053555.20405-1-quic_tdas@quicinc.com> Precedence: bulk X-Mailing-List: linux-arm-msm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-ClientProxiedBy: nasanex01b.na.qualcomm.com (10.46.141.250) To nalasex01b.na.qualcomm.com (10.47.209.197) X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-GUID: k7Y7qXU6sAqssb9cNmlVwUbPQWtkNnCF X-Proofpoint-ORIG-GUID: k7Y7qXU6sAqssb9cNmlVwUbPQWtkNnCF X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.272,Aquarius:18.0.1011,Hydra:6.0.619,FMLib:17.11.176.26 definitions=2024-03-17_12,2024-03-15_01,2023-05-22_02 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 adultscore=0 lowpriorityscore=0 spamscore=0 clxscore=1015 malwarescore=0 mlxlogscore=995 bulkscore=0 priorityscore=1501 impostorscore=0 suspectscore=0 mlxscore=0 phishscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.19.0-2403140001 definitions=main-2403180040 Update the lpassaudio_cc_reset regmap name and max register details to handle the regmap conflict warning between lpassaudio_cc_reset and lpassaudio_cc. Fixes: a9dd26639d05 ("clk: qcom: lpass: Add support for LPASS clock controller for SC7280") Signed-off-by: Taniya Das --- drivers/clk/qcom/lpassaudiocc-sc7280.c | 6 ++++++ 1 file changed, 6 insertions(+) -- 2.17.1 diff --git a/drivers/clk/qcom/lpassaudiocc-sc7280.c b/drivers/clk/qcom/lpassaudiocc-sc7280.c index d68139762a80..3f1e756a6e71 100644 --- a/drivers/clk/qcom/lpassaudiocc-sc7280.c +++ b/drivers/clk/qcom/lpassaudiocc-sc7280.c @@ -755,6 +755,9 @@ static int lpass_audio_cc_sc7280_probe(struct platform_device *pdev) int ret; if (of_device_is_compatible(pdev->dev.of_node, "qcom,qcm6490-lpassaudiocc")) { + lpass_audio_cc_sc7280_regmap_config.name = "lpassaudio_cc_reset"; + lpass_audio_cc_sc7280_regmap_config.max_register = 0xc8; + ret = qcom_cc_probe_by_index(pdev, 1, &lpass_audio_cc_reset_sc7280_desc); if (ret) dev_err(&pdev->dev, "Failed to register LPASS AUDIO CC Resets\n"); @@ -787,6 +790,9 @@ static int lpass_audio_cc_sc7280_probe(struct platform_device *pdev) goto exit; } + lpass_audio_cc_sc7280_regmap_config.name = "lpassaudio_cc_reset"; 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Mon, 18 Mar 2024 05:37:01 GMT Received: from hu-tdas-hyd.qualcomm.com (10.80.80.8) by nalasex01b.na.qualcomm.com (10.47.209.197) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1118.40; Sun, 17 Mar 2024 22:36:57 -0700 From: Taniya Das To: Stephen Boyd , =?utf-8?q?Michael_Turquette_=C2=A0?= , Bjorn Andersson , "Konrad Dybcio" , Rob Herring , Krzysztof Kozlowski , Conor Dooley CC: Taniya Das , , , Subject: [PATCH v2 4/8] clk: qcom: sc7280: Update the transition delay for GDSC Date: Mon, 18 Mar 2024 11:05:51 +0530 Message-ID: <20240318053555.20405-5-quic_tdas@quicinc.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20240318053555.20405-1-quic_tdas@quicinc.com> References: <20240318053555.20405-1-quic_tdas@quicinc.com> Precedence: bulk X-Mailing-List: linux-arm-msm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-ClientProxiedBy: nasanex01b.na.qualcomm.com (10.46.141.250) To nalasex01b.na.qualcomm.com (10.47.209.197) X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-GUID: qTZ1NfWlq3RaqHcypOh-Kqr7D2i64LZw X-Proofpoint-ORIG-GUID: qTZ1NfWlq3RaqHcypOh-Kqr7D2i64LZw X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.272,Aquarius:18.0.1011,Hydra:6.0.619,FMLib:17.11.176.26 definitions=2024-03-17_12,2024-03-15_01,2023-05-22_02 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 mlxscore=0 malwarescore=0 adultscore=0 lowpriorityscore=0 clxscore=1015 phishscore=0 mlxlogscore=893 impostorscore=0 bulkscore=0 spamscore=0 suspectscore=0 priorityscore=1501 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.19.0-2403140001 definitions=main-2403180040 Update the GDSC default values of GDSC transition delay to avoid the issues in the GDSC FSM state. Fixes: fae7617bb142 ("clk: qcom: Add video clock controller driver for SC7280") Fixes: 1daec8cfebc2 ("clk: qcom: camcc: Add camera clock controller driver for SC7280") Fixes: a3cc092196ef ("clk: qcom: Add Global Clock controller (GCC) driver for SC7280") Fixes: 3e0f01d6c7e7 ("clk: qcom: Add graphics clock controller driver for SC7280") Signed-off-by: Taniya Das --- drivers/clk/qcom/camcc-sc7280.c | 19 +++++++++++++++++++ drivers/clk/qcom/gcc-sc7280.c | 10 ++++++++++ drivers/clk/qcom/gpucc-sc7280.c | 7 +++++++ drivers/clk/qcom/videocc-sc7280.c | 7 +++++++ 4 files changed, 43 insertions(+) diff --git a/drivers/clk/qcom/camcc-sc7280.c b/drivers/clk/qcom/camcc-sc7280.c index d89ddb2298e3..27bfb0f959c4 100644 --- a/drivers/clk/qcom/camcc-sc7280.c +++ b/drivers/clk/qcom/camcc-sc7280.c @@ -1,6 +1,7 @@ // SPDX-License-Identifier: GPL-2.0-only /* * Copyright (c) 2021, The Linux Foundation. All rights reserved. + * Copyright (c) 2024, Qualcomm Innovation Center, Inc. All rights reserved. */ #include @@ -2247,6 +2248,9 @@ static struct clk_branch cam_cc_sleep_clk = { static struct gdsc cam_cc_titan_top_gdsc = { .gdscr = 0xc194, + .en_rest_wait_val = 0x2, + .en_few_wait_val = 0x2, + .clk_dis_wait_val = 0xf, .pd = { .name = "cam_cc_titan_top_gdsc", }, @@ -2256,6 +2260,9 @@ static struct gdsc cam_cc_titan_top_gdsc = { static struct gdsc cam_cc_bps_gdsc = { .gdscr = 0x7004, + .en_rest_wait_val = 0x2, + .en_few_wait_val = 0x2, + .clk_dis_wait_val = 0xf, .pd = { .name = "cam_cc_bps_gdsc", }, @@ -2265,6 +2272,9 @@ static struct gdsc cam_cc_bps_gdsc = { static struct gdsc cam_cc_ife_0_gdsc = { .gdscr = 0xa004, + .en_rest_wait_val = 0x2, + .en_few_wait_val = 0x2, + .clk_dis_wait_val = 0xf, .pd = { .name = "cam_cc_ife_0_gdsc", }, @@ -2274,6 +2284,9 @@ static struct gdsc cam_cc_ife_0_gdsc = { static struct gdsc cam_cc_ife_1_gdsc = { .gdscr = 0xb004, + .en_rest_wait_val = 0x2, + .en_few_wait_val = 0x2, + .clk_dis_wait_val = 0xf, .pd = { .name = "cam_cc_ife_1_gdsc", }, @@ -2283,6 +2296,9 @@ static struct gdsc cam_cc_ife_1_gdsc = { static struct gdsc cam_cc_ife_2_gdsc = { .gdscr = 0xb070, + .en_rest_wait_val = 0x2, + .en_few_wait_val = 0x2, + .clk_dis_wait_val = 0xf, .pd = { .name = "cam_cc_ife_2_gdsc", }, @@ -2292,6 +2308,9 @@ static struct gdsc cam_cc_ife_2_gdsc = { static struct gdsc cam_cc_ipe_0_gdsc = { .gdscr = 0x8004, + .en_rest_wait_val = 0x2, + .en_few_wait_val = 0x2, + .clk_dis_wait_val = 0xf, .pd = { .name = "cam_cc_ipe_0_gdsc", }, diff --git a/drivers/clk/qcom/gcc-sc7280.c b/drivers/clk/qcom/gcc-sc7280.c index f45a8318900c..c622cd9a9d24 100644 --- a/drivers/clk/qcom/gcc-sc7280.c +++ b/drivers/clk/qcom/gcc-sc7280.c @@ -1,6 +1,7 @@ // SPDX-License-Identifier: GPL-2.0-only /* * Copyright (c) 2020-2021, The Linux Foundation. All rights reserved. + * Copyright (c) 2024, Qualcomm Innovation Center, Inc. All rights reserved. */ #include @@ -3094,6 +3095,9 @@ static struct clk_branch gcc_wpss_rscp_clk = { static struct gdsc gcc_pcie_0_gdsc = { .gdscr = 0x6b004, + .en_rest_wait_val = 0x2, + .en_few_wait_val = 0x2, + .clk_dis_wait_val = 0xf, .pd = { .name = "gcc_pcie_0_gdsc", }, @@ -3112,6 +3116,9 @@ static struct gdsc gcc_pcie_1_gdsc = { static struct gdsc gcc_ufs_phy_gdsc = { .gdscr = 0x77004, + .en_rest_wait_val = 0x2, + .en_few_wait_val = 0x2, + .clk_dis_wait_val = 0xf, .pd = { .name = "gcc_ufs_phy_gdsc", }, @@ -3121,6 +3128,9 @@ static struct gdsc gcc_ufs_phy_gdsc = { static struct gdsc gcc_usb30_prim_gdsc = { .gdscr = 0xf004, + .en_rest_wait_val = 0x2, + .en_few_wait_val = 0x2, + .clk_dis_wait_val = 0xf, .pd = { .name = "gcc_usb30_prim_gdsc", }, diff --git a/drivers/clk/qcom/gpucc-sc7280.c b/drivers/clk/qcom/gpucc-sc7280.c index 35b394feb68d..ebda57eac979 100644 --- a/drivers/clk/qcom/gpucc-sc7280.c +++ b/drivers/clk/qcom/gpucc-sc7280.c @@ -1,6 +1,7 @@ // SPDX-License-Identifier: GPL-2.0-only /* * Copyright (c) 2021, The Linux Foundation. All rights reserved. + * Copyright (c) 2024, Qualcomm Innovation Center, Inc. All rights reserved. */ #include @@ -379,6 +380,9 @@ static struct clk_branch gpu_cc_sleep_clk = { static struct gdsc cx_gdsc = { .gdscr = 0x106c, + .en_rest_wait_val = 0x2, + .en_few_wait_val = 0x2, + .clk_dis_wait_val = 0x2, .gds_hw_ctrl = 0x1540, .pd = { .name = "cx_gdsc", @@ -389,6 +393,9 @@ static struct gdsc cx_gdsc = { static struct gdsc gx_gdsc = { .gdscr = 0x100c, + .en_rest_wait_val = 0x2, + .en_few_wait_val = 0x2, + .clk_dis_wait_val = 0x2, .clamp_io_ctrl = 0x1508, .pd = { .name = "gx_gdsc", diff --git a/drivers/clk/qcom/videocc-sc7280.c b/drivers/clk/qcom/videocc-sc7280.c index cdd59c6f60df..119a3ed6eb6a 100644 --- a/drivers/clk/qcom/videocc-sc7280.c +++ b/drivers/clk/qcom/videocc-sc7280.c @@ -1,6 +1,7 @@ // SPDX-License-Identifier: GPL-2.0-only /* * Copyright (c) 2021, The Linux Foundation. All rights reserved. + * Copyright (c) 2024, Qualcomm Innovation Center, Inc. All rights reserved. */ #include @@ -232,6 +233,9 @@ static struct clk_branch video_cc_venus_ahb_clk = { static struct gdsc mvs0_gdsc = { .gdscr = 0x3004, + .en_rest_wait_val = 0x2, + .en_few_wait_val = 0x2, + .clk_dis_wait_val = 0x6, .pd = { .name = "mvs0_gdsc", }, @@ -241,6 +245,9 @@ static struct gdsc mvs0_gdsc = { static struct gdsc mvsc_gdsc = { .gdscr = 0x2004, + .en_rest_wait_val = 0x2, + .en_few_wait_val = 0x2, + .clk_dis_wait_val = 0x6, .pd = { .name = "mvsc_gdsc", }, From patchwork Mon Mar 18 05:35:52 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Taniya Das X-Patchwork-Id: 13594993 Received: from mx0a-0031df01.pphosted.com (mx0a-0031df01.pphosted.com [205.220.168.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 0D30C1E4AE; Mon, 18 Mar 2024 05:37:09 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; 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Fixes: a3cc092196ef ("clk: qcom: Add Global Clock controller (GCC) driver for SC7280") Signed-off-by: Taniya Das --- drivers/clk/qcom/gcc-sc7280.c | 3 +++ 1 file changed, 3 insertions(+) -- 2.17.1 diff --git a/drivers/clk/qcom/gcc-sc7280.c b/drivers/clk/qcom/gcc-sc7280.c index c622cd9a9d24..b937d513b814 100644 --- a/drivers/clk/qcom/gcc-sc7280.c +++ b/drivers/clk/qcom/gcc-sc7280.c @@ -3473,6 +3473,9 @@ static int gcc_sc7280_probe(struct platform_device *pdev) qcom_branch_set_clk_en(regmap, 0x71004);/* GCC_GPU_CFG_AHB_CLK */ regmap_update_bits(regmap, 0x7100C, BIT(13), BIT(13)); + /* FORCE_MEM_CORE_ON for ufs phy ice core clocks */ + qcom_branch_set_force_mem_core(regmap, gcc_ufs_phy_ice_core_clk, true); + ret = qcom_cc_register_rcg_dfs(regmap, gcc_dfs_clocks, ARRAY_SIZE(gcc_dfs_clocks)); if (ret) From patchwork Mon Mar 18 05:35:53 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Taniya Das X-Patchwork-Id: 13594994 Received: from mx0a-0031df01.pphosted.com (mx0a-0031df01.pphosted.com [205.220.168.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 4C6581EB2B; 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Mon, 18 Mar 2024 05:37:12 +0000 (GMT) Received: from nalasex01b.na.qualcomm.com (nalasex01b.na.qualcomm.com [10.47.209.197]) by NALASPPMTA03.qualcomm.com (8.17.1.5/8.17.1.5) with ESMTPS id 42I5bBe0030727 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Mon, 18 Mar 2024 05:37:12 GMT Received: from hu-tdas-hyd.qualcomm.com (10.80.80.8) by nalasex01b.na.qualcomm.com (10.47.209.197) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1118.40; Sun, 17 Mar 2024 22:37:05 -0700 From: Taniya Das To: Stephen Boyd , =?utf-8?q?Michael_Turquette_=C2=A0?= , Bjorn Andersson , "Konrad Dybcio" , Rob Herring , Krzysztof Kozlowski , Conor Dooley CC: Taniya Das , , , Subject: [PATCH v2 6/8] clk: qcom: camcc-sc7280: Add parent dependency to all camera GDSCs Date: Mon, 18 Mar 2024 11:05:53 +0530 Message-ID: <20240318053555.20405-7-quic_tdas@quicinc.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20240318053555.20405-1-quic_tdas@quicinc.com> References: <20240318053555.20405-1-quic_tdas@quicinc.com> Precedence: bulk X-Mailing-List: linux-arm-msm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-ClientProxiedBy: nasanex01b.na.qualcomm.com (10.46.141.250) To nalasex01b.na.qualcomm.com (10.47.209.197) X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-GUID: _4nzFSacQYe4by_r90PhVCDLegt8gjYc X-Proofpoint-ORIG-GUID: _4nzFSacQYe4by_r90PhVCDLegt8gjYc X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.272,Aquarius:18.0.1011,Hydra:6.0.619,FMLib:17.11.176.26 definitions=2024-03-17_12,2024-03-15_01,2023-05-22_02 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 priorityscore=1501 lowpriorityscore=0 phishscore=0 mlxlogscore=740 mlxscore=0 clxscore=1015 impostorscore=0 malwarescore=0 suspectscore=0 adultscore=0 bulkscore=0 spamscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.19.0-2403140001 definitions=main-2403180040 Camera titan top GDSC is a parent supply to all other camera GDSCs. Titan top GDSC is required to be enabled before enabling any other camera GDSCs and it should be disabled only after all other camera GDSCs are disabled. Ensure this behavior by marking titan top GDSC as parent of all other camera GDSCs. Fixes: 1daec8cfebc2 ("clk: qcom: camcc: Add camera clock controller driver for SC7280") Signed-off-by: Taniya Das Reviewed-by: Dmitry Baryshkov Reviewed-by: Konrad Dybcio --- drivers/clk/qcom/camcc-sc7280.c | 5 +++++ 1 file changed, 5 insertions(+) -- 2.17.1 diff --git a/drivers/clk/qcom/camcc-sc7280.c b/drivers/clk/qcom/camcc-sc7280.c index 27bfb0f959c4..da29d3b953ee 100644 --- a/drivers/clk/qcom/camcc-sc7280.c +++ b/drivers/clk/qcom/camcc-sc7280.c @@ -2267,6 +2267,7 @@ static struct gdsc cam_cc_bps_gdsc = { .name = "cam_cc_bps_gdsc", }, .pwrsts = PWRSTS_OFF_ON, + .parent = &cam_cc_titan_top_gdsc.pd, .flags = HW_CTRL | RETAIN_FF_ENABLE, }; @@ -2279,6 +2280,7 @@ static struct gdsc cam_cc_ife_0_gdsc = { .name = "cam_cc_ife_0_gdsc", }, .pwrsts = PWRSTS_OFF_ON, + .parent = &cam_cc_titan_top_gdsc.pd, .flags = RETAIN_FF_ENABLE, }; @@ -2291,6 +2293,7 @@ static struct gdsc cam_cc_ife_1_gdsc = { .name = "cam_cc_ife_1_gdsc", }, .pwrsts = PWRSTS_OFF_ON, + .parent = &cam_cc_titan_top_gdsc.pd, .flags = RETAIN_FF_ENABLE, }; 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Update the lpassaudio node to support the new compatible. Signed-off-by: Taniya Das --- arch/arm64/boot/dts/qcom/qcm6490-idp.dts | 28 +++++++++++++++++++++++- 1 file changed, 27 insertions(+), 1 deletion(-) -- 2.17.1 diff --git a/arch/arm64/boot/dts/qcom/qcm6490-idp.dts b/arch/arm64/boot/dts/qcom/qcm6490-idp.dts index e4bfad50a669..915f955657df 100644 --- a/arch/arm64/boot/dts/qcom/qcm6490-idp.dts +++ b/arch/arm64/boot/dts/qcom/qcm6490-idp.dts @@ -1,6 +1,6 @@ // SPDX-License-Identifier: BSD-3-Clause /* - * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. + * Copyright (c) 2023-2024 Qualcomm Innovation Center, Inc. All rights reserved. */ /dts-v1/; @@ -448,6 +448,32 @@ }; }; +&gcc { + protected-clocks = ,, + , , + , , + , , + , , + , , + ,, + , , + , + , , + , , + , , + , , + , , + , , + , , + , , + , ; +}; + +&lpass_audiocc { + compatible = "qcom,qcm6490-lpassaudiocc"; + /delete-property/ power-domains; +}; + &qupv3_id_0 { status = "okay"; }; From patchwork Mon Mar 18 05:35:55 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Taniya Das X-Patchwork-Id: 13594996 Received: from mx0b-0031df01.pphosted.com (mx0b-0031df01.pphosted.com [205.220.180.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 93DF321101; Mon, 18 Mar 2024 05:37:30 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=205.220.180.131 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1710740252; cv=none; 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Signed-off-by: Taniya Das --- arch/arm64/boot/dts/qcom/qcs6490-rb3gen2.dts | 7 ++++++- 1 file changed, 6 insertions(+), 1 deletion(-) -- 2.17.1 diff --git a/arch/arm64/boot/dts/qcom/qcs6490-rb3gen2.dts b/arch/arm64/boot/dts/qcom/qcs6490-rb3gen2.dts index 97824c769ba3..dc7edea7f7c8 100644 --- a/arch/arm64/boot/dts/qcom/qcs6490-rb3gen2.dts +++ b/arch/arm64/boot/dts/qcom/qcs6490-rb3gen2.dts @@ -1,6 +1,6 @@ // SPDX-License-Identifier: BSD-3-Clause /* - * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. + * Copyright (c) 2023-2024 Qualcomm Innovation Center, Inc. All rights reserved. */ /dts-v1/; @@ -430,6 +430,11 @@ ; }; +&lpass_audiocc { + compatible = "qcom,qcm6490-lpassaudiocc"; + /delete-property/ power-domains; +}; + &qupv3_id_0 { status = "okay"; };