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[2001:b400:e454:a466:1a3:78b9:4898:3442]) by smtp.gmail.com with ESMTPSA id j9-20020a170902da8900b001dd6c0800b4sm3975907plx.188.2024.03.17.22.52.22 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 17 Mar 2024 22:52:25 -0700 (PDT) From: Peter Yin To: patrick@stwcx.xyz, Rob Herring , Krzysztof Kozlowski , Conor Dooley , Joel Stanley , Andrew Jeffery , Wim Van Sebroeck , Guenter Roeck , devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-aspeed@lists.ozlabs.org, linux-kernel@vger.kernel.org, linux-watchdog@vger.kernel.org Subject: [PATCH v2] drivers: watchdog: ast2600 support bootstatus Date: Mon, 18 Mar 2024 13:52:19 +0800 Message-Id: <20240318055219.3460121-1-peteryin.openbmc@gmail.com> X-Mailer: git-send-email 2.25.1 MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20240317_225230_075801_80B56644 X-CRM114-Status: GOOD ( 19.05 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org Add WDIOF_EXTERN1 and WDIOF_CARDRESET bootstatus in ast2600 Regarding the AST2600 specification, the WDTn Timeout Status Register (WDT10) has bit 1 reserved. To verify the second boot source, we need to check SEC14 bit 12 and bit 13. The bits 8-23 in the WDTn Timeout Status Register are the Watchdog Event Count, which we can use to verify WDIOF_EXTERN1. Signed-off-by: Peter Yin --- Change log: v1 -> v2 - Add comment and support WDIOF_CARDRESET in ast2600 v1 - Patch 0001 - Add WDIOF_EXTERN1 bootstatus --- arch/arm/boot/dts/aspeed/aspeed-g6.dtsi | 8 ++--- drivers/watchdog/aspeed_wdt.c | 45 ++++++++++++++++++++++--- 2 files changed, 44 insertions(+), 9 deletions(-) diff --git a/arch/arm/boot/dts/aspeed/aspeed-g6.dtsi b/arch/arm/boot/dts/aspeed/aspeed-g6.dtsi index e0b44498269f..23ae7f0430e9 100644 --- a/arch/arm/boot/dts/aspeed/aspeed-g6.dtsi +++ b/arch/arm/boot/dts/aspeed/aspeed-g6.dtsi @@ -556,24 +556,24 @@ uart5: serial@1e784000 { wdt1: watchdog@1e785000 { compatible = "aspeed,ast2600-wdt"; - reg = <0x1e785000 0x40>; + reg = <0x1e785000 0x40>, <0x1e6f2000 0x20>; }; wdt2: watchdog@1e785040 { compatible = "aspeed,ast2600-wdt"; - reg = <0x1e785040 0x40>; + reg = <0x1e785040 0x40>, <0x1e6f2000 0x020>; status = "disabled"; }; wdt3: watchdog@1e785080 { compatible = "aspeed,ast2600-wdt"; - reg = <0x1e785080 0x40>; + reg = <0x1e785080 0x40>, <0x1e6f2000 0x020>; status = "disabled"; }; wdt4: watchdog@1e7850c0 { compatible = "aspeed,ast2600-wdt"; - reg = <0x1e7850C0 0x40>; + reg = <0x1e7850C0 0x40>, <0x1e6f2000 0x020>; status = "disabled"; }; diff --git a/drivers/watchdog/aspeed_wdt.c b/drivers/watchdog/aspeed_wdt.c index b4773a6aaf8c..65118e461130 100644 --- a/drivers/watchdog/aspeed_wdt.c +++ b/drivers/watchdog/aspeed_wdt.c @@ -33,6 +33,7 @@ struct aspeed_wdt { void __iomem *base; u32 ctrl; const struct aspeed_wdt_config *cfg; + void __iomem *sec_base; }; static const struct aspeed_wdt_config ast2400_config = { @@ -82,6 +83,15 @@ MODULE_DEVICE_TABLE(of, aspeed_wdt_of_table); #define WDT_RESET_MASK1 0x1c #define WDT_RESET_MASK2 0x20 +/* + * Only Ast2600 support + */ +#define WDT_EVENT_COUNTER_MASK (0xFFF << 8) +#define WDT_SECURE_ENGINE_STATUS (0x14) +#define ABR_IMAGE_SOURCE BIT(12) +#define ABR_IMAGE_SOURCE_SPI BIT(13) +#define SECOND_BOOT_ENABLE BIT(14) + /* * WDT_RESET_WIDTH controls the characteristics of the external pulse (if * enabled), specifically: @@ -313,6 +323,7 @@ static int aspeed_wdt_probe(struct platform_device *pdev) const char *reset_type; u32 duration; u32 status; + u32 sec_st; int ret; wdt = devm_kzalloc(dev, sizeof(*wdt), GFP_KERNEL); @@ -330,6 +341,12 @@ static int aspeed_wdt_probe(struct platform_device *pdev) if (IS_ERR(wdt->base)) return PTR_ERR(wdt->base); + if (of_device_is_compatible(np, "aspeed,ast2600-wdt")) { + wdt->sec_base = devm_platform_ioremap_resource(pdev, 1); + if (IS_ERR(wdt->sec_base)) + return PTR_ERR(wdt->sec_base); + } + wdt->wdd.info = &aspeed_wdt_info; if (wdt->cfg->irq_mask) { @@ -459,12 +476,30 @@ static int aspeed_wdt_probe(struct platform_device *pdev) } status = readl(wdt->base + WDT_TIMEOUT_STATUS); - if (status & WDT_TIMEOUT_STATUS_BOOT_SECONDARY) { - wdt->wdd.bootstatus = WDIOF_CARDRESET; - if (of_device_is_compatible(np, "aspeed,ast2400-wdt") || - of_device_is_compatible(np, "aspeed,ast2500-wdt")) - wdt->wdd.groups = bswitch_groups; + if (of_device_is_compatible(np, "aspeed,ast2600-wdt")) { + /* + * The WDTn Timeout Status Register bit 1 is reserved. + * To verify the second boot source, + * we need to check SEC14 bit 12 and bit 13. + */ + sec_st = readl(wdt->sec_base + WDT_SECURE_ENGINE_STATUS); + if( sec_st & SECOND_BOOT_ENABLE) + if (sec_st & ABR_IMAGE_SOURCE || + sec_st & ABR_IMAGE_SOURCE_SPI) + wdt->wdd.bootstatus |= WDIOF_CARDRESET; + + /* + * To check Watchdog Event Count for WDIOF_EXTERN1 + */ + if (status & WDT_EVENT_COUNTER_MASK) { + wdt->wdd.bootstatus |= WDIOF_EXTERN1; + } + } else { + wdt->wdd.groups = bswitch_groups; + + if (status & WDT_TIMEOUT_STATUS_BOOT_SECONDARY) + wdt->wdd.bootstatus = WDIOF_CARDRESET; } dev_set_drvdata(dev, wdt);