From patchwork Fri Mar 22 11:40:42 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Stanislav Lisovskiy X-Patchwork-Id: 13599989 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 19427C54E71 for ; Fri, 22 Mar 2024 11:40:55 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id F110010F543; Fri, 22 Mar 2024 11:40:52 +0000 (UTC) Authentication-Results: gabe.freedesktop.org; dkim=pass (2048-bit key; unprotected) header.d=intel.com header.i=@intel.com header.b="JytXF/aW"; dkim-atps=neutral Received: from mgamail.intel.com (mgamail.intel.com [198.175.65.15]) by gabe.freedesktop.org (Postfix) with ESMTPS id 445E410F398 for ; Fri, 22 Mar 2024 11:40:50 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1711107650; x=1742643650; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=jzxBxFR1RS6CAP4mPOTmL9iCpwHWZO7twSnveWw+Glg=; b=JytXF/aWWbouNDSGMGjvpOlQoD74CpG+3pWvJBPw4xOQVeUn2fLvCbVs ipjYew7b0WtkCIwzDdJiZmH/Hrt5a++0eJsvT0kd/wlkq7sfqJCtQgicf ma7dcsBNdswY1Zy3EMKmguxj6C0xRa68psAOnvl/D5+MoXKivujs/Z/GX +I1rQt/F8pFMe9VfIo1WYF11NYHYq24SShtClwkTRGR/48Jc3y0uLMdLv WGqgWbFNtWTfTW6oLpaKxBUj313fyYO36zKX/rXo90S8ap+XugWl1K2YV 7snT5uqIPYDrMQlg19Yt0Vgh8+MPfHec2WQr3kYypPDBndy4U732VURpi Q==; X-IronPort-AV: E=McAfee;i="6600,9927,11020"; a="9939207" X-IronPort-AV: E=Sophos;i="6.07,145,1708416000"; d="scan'208";a="9939207" Received: from fmviesa009.fm.intel.com ([10.60.135.149]) by orvoesa107.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 22 Mar 2024 04:40:50 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.07,145,1708416000"; d="scan'208";a="14906481" Received: from unknown (HELO slisovsk-Lenovo-ideapad-720S-13IKB.fi.intel.com) ([10.237.72.65]) by fmviesa009.fm.intel.com with ESMTP; 22 Mar 2024 04:40:48 -0700 From: Stanislav Lisovskiy To: intel-gfx@lists.freedesktop.org Cc: jani.saarinen@intel.com, Stanislav.Lisovskiy@intel.com, ville.syrjala@linux.intel.com Subject: [PATCH 1/5] drm/i915: Update mbus in intel_dbuf_mbus_update and do it properly Date: Fri, 22 Mar 2024 13:40:42 +0200 Message-Id: <20240322114046.24930-2-stanislav.lisovskiy@intel.com> X-Mailer: git-send-email 2.37.3 In-Reply-To: <20240322114046.24930-1-stanislav.lisovskiy@intel.com> References: <20240322114046.24930-1-stanislav.lisovskiy@intel.com> MIME-Version: 1.0 X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" According to BSpec we need to do correspondent MBUS updates before or after DBUF reallocation, depending on whether we are enabling or disabling mbus joining(typical scenario is swithing between multiple and single displays). Signed-off-by: Stanislav Lisovskiy --- drivers/gpu/drm/i915/display/skl_watermark.c | 9 +++++++-- 1 file changed, 7 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/i915/display/skl_watermark.c b/drivers/gpu/drm/i915/display/skl_watermark.c index bc341abcab2fe..8ff69da664807 100644 --- a/drivers/gpu/drm/i915/display/skl_watermark.c +++ b/drivers/gpu/drm/i915/display/skl_watermark.c @@ -3574,7 +3574,7 @@ void intel_dbuf_mdclk_cdclk_ratio_update(struct drm_i915_private *i915, u8 ratio * Configure MBUS_CTL and all DBUF_CTL_S of each slice to join_mbus state before * update the request state of all DBUS slices. */ -static void update_mbus_pre_enable(struct intel_atomic_state *state) +static void intel_dbuf_mbus_update(struct intel_atomic_state *state) { struct drm_i915_private *i915 = to_i915(state->base.dev); u32 mbus_ctl; @@ -3632,7 +3632,9 @@ void intel_dbuf_pre_plane_update(struct intel_atomic_state *state) WARN_ON(!new_dbuf_state->base.changed); - update_mbus_pre_enable(state); + if (!old_dbuf_state->joined_mbus && new_dbuf_state->joined_mbus) + intel_dbuf_mbus_update(state); + gen9_dbuf_slices_update(i915, old_dbuf_state->enabled_slices | new_dbuf_state->enabled_slices); @@ -3653,6 +3655,9 @@ void intel_dbuf_post_plane_update(struct intel_atomic_state *state) WARN_ON(!new_dbuf_state->base.changed); + if (old_dbuf_state->joined_mbus && !new_dbuf_state->joined_mbus) + intel_dbuf_mbus_update(state); + gen9_dbuf_slices_update(i915, new_dbuf_state->enabled_slices); } From patchwork Fri Mar 22 11:40:43 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Stanislav Lisovskiy X-Patchwork-Id: 13599990 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 8CA9BC47DD9 for ; Fri, 22 Mar 2024 11:40:56 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id D735310F4E7; Fri, 22 Mar 2024 11:40:52 +0000 (UTC) Authentication-Results: gabe.freedesktop.org; dkim=pass (2048-bit key; unprotected) header.d=intel.com header.i=@intel.com header.b="m9xQUO5p"; dkim-atps=neutral Received: from mgamail.intel.com (mgamail.intel.com [198.175.65.15]) by gabe.freedesktop.org (Postfix) with ESMTPS id 0236D10F4E7 for ; Fri, 22 Mar 2024 11:40:51 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1711107652; x=1742643652; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=2lxYUjDbmqT61E7Mf2jIA3zDoXHRpVQPLkfrm9lZHOQ=; b=m9xQUO5pIidNDaOP/lUuESxxa0tk9Eprb+dFamS+TnHid7OIXr0qvTd8 g6K7AtpNOK+LsW1j4ViZ0e8V7bIAxdIP+70lGQLKGYdyyQZHxaHhYCLGG ecoic9pCWmnSZXtlfYUf2ymm4hTwafhqY6vUNP64gcoaQp4ToEPk6+n7n Tzs3QG3cG24Yzevw0qiWUpC37g78/tbi6p1yTvEO2eFQi0MsqJ5G5xioB I4jZQXxl7N4nRuv0X8h5ULxgJ3QInbNB/yjF3kpIGBQVtxQuJFXtQ9XXM CmPINq+j2+5IR9kKjWMR1kHdTWmkYpzMrMNI3MwpiMSVu9dH5i7LqO3OJ Q==; X-IronPort-AV: E=McAfee;i="6600,9927,11020"; a="9939213" X-IronPort-AV: E=Sophos;i="6.07,145,1708416000"; d="scan'208";a="9939213" Received: from fmviesa009.fm.intel.com ([10.60.135.149]) by orvoesa107.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 22 Mar 2024 04:40:52 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.07,145,1708416000"; d="scan'208";a="14906484" Received: from unknown (HELO slisovsk-Lenovo-ideapad-720S-13IKB.fi.intel.com) ([10.237.72.65]) by fmviesa009.fm.intel.com with ESMTP; 22 Mar 2024 04:40:50 -0700 From: Stanislav Lisovskiy To: intel-gfx@lists.freedesktop.org Cc: jani.saarinen@intel.com, Stanislav.Lisovskiy@intel.com, ville.syrjala@linux.intel.com Subject: [PATCH 2/5] drm/i915: Break intel_dbuf_mbus_update into 2 separate parts Date: Fri, 22 Mar 2024 13:40:43 +0200 Message-Id: <20240322114046.24930-3-stanislav.lisovskiy@intel.com> X-Mailer: git-send-email 2.37.3 In-Reply-To: <20240322114046.24930-1-stanislav.lisovskiy@intel.com> References: <20240322114046.24930-1-stanislav.lisovskiy@intel.com> MIME-Version: 1.0 X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" We need to be able to update dbuf min tracker and mdclk ratio separately if mbus_join state didn't change, so lets add one degree of freedom and make it possible. Signed-off-by: Stanislav Lisovskiy Reviewed-by: Ville Syrjälä --- drivers/gpu/drm/i915/display/skl_watermark.c | 55 ++++++++++++-------- 1 file changed, 33 insertions(+), 22 deletions(-) diff --git a/drivers/gpu/drm/i915/display/skl_watermark.c b/drivers/gpu/drm/i915/display/skl_watermark.c index 8ff69da664807..2b947870527fc 100644 --- a/drivers/gpu/drm/i915/display/skl_watermark.c +++ b/drivers/gpu/drm/i915/display/skl_watermark.c @@ -3570,16 +3570,38 @@ void intel_dbuf_mdclk_cdclk_ratio_update(struct drm_i915_private *i915, u8 ratio DBUF_MIN_TRACKER_STATE_SERVICE(ratio - 1)); } +static void intel_dbuf_mdclk_min_tracker_update(struct intel_atomic_state *state) +{ + struct drm_i915_private *i915 = to_i915(state->base.dev); + const struct intel_dbuf_state *old_dbuf_state = + intel_atomic_get_old_dbuf_state(state); + const struct intel_dbuf_state *new_dbuf_state = + intel_atomic_get_new_dbuf_state(state); + + if (DISPLAY_VER(i915) >= 20 && + old_dbuf_state->mdclk_cdclk_ratio != new_dbuf_state->mdclk_cdclk_ratio) { + /* + * For Xe2LPD and beyond, when there is a change in the ratio + * between MDCLK and CDCLK, updates to related registers need to + * happen at a specific point in the CDCLK change sequence. In + * that case, we defer to the call to + * intel_dbuf_mdclk_cdclk_ratio_update() to the CDCLK logic. + */ + return; + } + + intel_dbuf_mdclk_cdclk_ratio_update(i915, new_dbuf_state->mdclk_cdclk_ratio, + new_dbuf_state->joined_mbus); +} + /* * Configure MBUS_CTL and all DBUF_CTL_S of each slice to join_mbus state before * update the request state of all DBUS slices. */ -static void intel_dbuf_mbus_update(struct intel_atomic_state *state) +static void intel_dbuf_mbus_join_update(struct intel_atomic_state *state) { struct drm_i915_private *i915 = to_i915(state->base.dev); u32 mbus_ctl; - const struct intel_dbuf_state *old_dbuf_state = - intel_atomic_get_old_dbuf_state(state); const struct intel_dbuf_state *new_dbuf_state = intel_atomic_get_new_dbuf_state(state); @@ -3600,21 +3622,6 @@ static void intel_dbuf_mbus_update(struct intel_atomic_state *state) intel_de_rmw(i915, MBUS_CTL, MBUS_HASHING_MODE_MASK | MBUS_JOIN | MBUS_JOIN_PIPE_SELECT_MASK, mbus_ctl); - - if (DISPLAY_VER(i915) >= 20 && - old_dbuf_state->mdclk_cdclk_ratio != new_dbuf_state->mdclk_cdclk_ratio) { - /* - * For Xe2LPD and beyond, when there is a change in the ratio - * between MDCLK and CDCLK, updates to related registers need to - * happen at a specific point in the CDCLK change sequence. In - * that case, we defer to the call to - * intel_dbuf_mdclk_cdclk_ratio_update() to the CDCLK logic. - */ - return; - } - - intel_dbuf_mdclk_cdclk_ratio_update(i915, new_dbuf_state->mdclk_cdclk_ratio, - new_dbuf_state->joined_mbus); } void intel_dbuf_pre_plane_update(struct intel_atomic_state *state) @@ -3632,8 +3639,10 @@ void intel_dbuf_pre_plane_update(struct intel_atomic_state *state) WARN_ON(!new_dbuf_state->base.changed); - if (!old_dbuf_state->joined_mbus && new_dbuf_state->joined_mbus) - intel_dbuf_mbus_update(state); + if (!old_dbuf_state->joined_mbus && new_dbuf_state->joined_mbus) { + intel_dbuf_mbus_join_update(state); + intel_dbuf_mdclk_min_tracker_update(state); + } gen9_dbuf_slices_update(i915, old_dbuf_state->enabled_slices | @@ -3655,8 +3664,10 @@ void intel_dbuf_post_plane_update(struct intel_atomic_state *state) WARN_ON(!new_dbuf_state->base.changed); - if (old_dbuf_state->joined_mbus && !new_dbuf_state->joined_mbus) - intel_dbuf_mbus_update(state); + if (old_dbuf_state->joined_mbus && !new_dbuf_state->joined_mbus) { + intel_dbuf_mbus_join_update(state); + intel_dbuf_mdclk_min_tracker_update(state); + } gen9_dbuf_slices_update(i915, new_dbuf_state->enabled_slices); From patchwork Fri Mar 22 11:40:44 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Stanislav Lisovskiy X-Patchwork-Id: 13599992 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 4BF39C54E71 for ; Fri, 22 Mar 2024 11:40:59 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 5790D10F6A3; Fri, 22 Mar 2024 11:40:58 +0000 (UTC) Authentication-Results: gabe.freedesktop.org; dkim=pass (2048-bit key; unprotected) header.d=intel.com header.i=@intel.com header.b="WfUKQLCo"; dkim-atps=neutral Received: from mgamail.intel.com (mgamail.intel.com [198.175.65.15]) by gabe.freedesktop.org (Postfix) with ESMTPS id A8D8E10F657 for ; Fri, 22 Mar 2024 11:40:53 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1711107653; x=1742643653; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=KJNAYWd5qCqe9YJSv/Pznf+ue5ZK6aTZe3com5dz7Xg=; b=WfUKQLCo6C9dJARqpSAFgWHeKmnrR+abX8HP1X8zZS9wBUSgL/tgI5rq yBt48qVXo6PMR+FQ/ZOgiXa0p+ngJZnwKnULoyyPye40lfAxcWV8xl8Qh 1x4kDalsvxsGffCDXfyjLenyQ3HRtZi5jGtuhYHSnAKwVSQ1H+48xvrqU mMb+iCOUOlgghi/LtO92QTHrO+zcc6W+xpyL7IJv832/BZbDJ9iwU+O5w uf5X6Bsze4p7VvUBo9tZdaJzoaqSOfhLXAEISQqKz2KxPsdffBvBHwLk+ V1PAhdUVS1Cop9GwFKmKON5zDPGNmFzGF6ihTArjYlLZKTJ/da9P18SuJ Q==; X-IronPort-AV: E=McAfee;i="6600,9927,11020"; a="9939215" X-IronPort-AV: E=Sophos;i="6.07,145,1708416000"; d="scan'208";a="9939215" Received: from fmviesa009.fm.intel.com ([10.60.135.149]) by orvoesa107.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 22 Mar 2024 04:40:53 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.07,145,1708416000"; d="scan'208";a="14906487" Received: from unknown (HELO slisovsk-Lenovo-ideapad-720S-13IKB.fi.intel.com) ([10.237.72.65]) by fmviesa009.fm.intel.com with ESMTP; 22 Mar 2024 04:40:51 -0700 From: Stanislav Lisovskiy To: intel-gfx@lists.freedesktop.org Cc: jani.saarinen@intel.com, Stanislav.Lisovskiy@intel.com, ville.syrjala@linux.intel.com Subject: [PATCH 3/5] drm/i915: Use old mbus_join value when increasing CDCLK Date: Fri, 22 Mar 2024 13:40:44 +0200 Message-Id: <20240322114046.24930-4-stanislav.lisovskiy@intel.com> X-Mailer: git-send-email 2.37.3 In-Reply-To: <20240322114046.24930-1-stanislav.lisovskiy@intel.com> References: <20240322114046.24930-1-stanislav.lisovskiy@intel.com> MIME-Version: 1.0 X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" In order to make sure we are not breaking the proper sequence lets to updates step by step and don't change MBUS join value during MDCLK/CDCLK programming stage. MBUS join programming would be taken care by pre/post ddb hooks. Signed-off-by: Stanislav Lisovskiy Reviewed-by: Ville Syrjälä --- drivers/gpu/drm/i915/display/intel_cdclk.c | 12 +++++++++++- 1 file changed, 11 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/i915/display/intel_cdclk.c b/drivers/gpu/drm/i915/display/intel_cdclk.c index 31aaa9780dfcf..43a9616c78260 100644 --- a/drivers/gpu/drm/i915/display/intel_cdclk.c +++ b/drivers/gpu/drm/i915/display/intel_cdclk.c @@ -2611,9 +2611,19 @@ intel_set_cdclk_pre_plane_update(struct intel_atomic_state *state) if (pipe == INVALID_PIPE || old_cdclk_state->actual.cdclk <= new_cdclk_state->actual.cdclk) { + struct intel_cdclk_config cdclk_config; + drm_WARN_ON(&i915->drm, !new_cdclk_state->base.changed); - intel_set_cdclk(i915, &new_cdclk_state->actual, pipe); + /* + * By this hack we want to prevent mbus_join to be programmed + * beforehand - we will take care of this later in pre ddb + * programming hook. + */ + cdclk_config = new_cdclk_state->actual; + cdclk_config.joined_mbus = old_cdclk_state->actual.joined_mbus; + + intel_set_cdclk(i915, &cdclk_config, pipe); } } From patchwork Fri Mar 22 11:40:45 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Stanislav Lisovskiy X-Patchwork-Id: 13599993 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 41BC6CD11DD for ; Fri, 22 Mar 2024 11:41:00 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 6D29610F6B6; Fri, 22 Mar 2024 11:40:58 +0000 (UTC) Authentication-Results: gabe.freedesktop.org; dkim=pass (2048-bit key; unprotected) header.d=intel.com header.i=@intel.com header.b="NpUTG7mP"; dkim-atps=neutral Received: from mgamail.intel.com (mgamail.intel.com [198.175.65.15]) by gabe.freedesktop.org (Postfix) with ESMTPS id 69D8C10F657 for ; Fri, 22 Mar 2024 11:40:55 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1711107655; x=1742643655; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=fIwXMhZmHKfP+KX8LwCOj1r2FugRCJOYZFUZxZrNk5Y=; b=NpUTG7mPBtVZTpVU9mNcmLcsjYjrXgwoeETSRKQkIkqvwRavBLpZmJYX 4/Hi2fN/TA62DlQJ+MP5wzIdebMBwv/1h7qU2Dpik8uGQn5jZNaSeQUCp ZYamsqncS4mOXCzT64+Z1cPI731McYu+J2Og6IGqVPPaarkT5M0Msw5Eq edCb1YeRYBFle3z9Yaxy1DtE1+PX9DYCCX5j8JpF9kkWCRdwJiFiRegHe Wrtq43rvp9maK+ptvvRLjoJona+OZscu3aFK9ukgB36Ne3E5CkTAC98xL l+zbjufOpzeb3tCZHAQZL5LFgueplR2JfO7wPAUUGHBvIg6OG09VSwkOS g==; X-IronPort-AV: E=McAfee;i="6600,9927,11020"; a="9939220" X-IronPort-AV: E=Sophos;i="6.07,145,1708416000"; d="scan'208";a="9939220" Received: from fmviesa009.fm.intel.com ([10.60.135.149]) by orvoesa107.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 22 Mar 2024 04:40:55 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.07,145,1708416000"; d="scan'208";a="14906490" Received: from unknown (HELO slisovsk-Lenovo-ideapad-720S-13IKB.fi.intel.com) ([10.237.72.65]) by fmviesa009.fm.intel.com with ESMTP; 22 Mar 2024 04:40:53 -0700 From: Stanislav Lisovskiy To: intel-gfx@lists.freedesktop.org Cc: jani.saarinen@intel.com, Stanislav.Lisovskiy@intel.com, ville.syrjala@linux.intel.com Subject: [PATCH 4/5] drm/i915: Loop over all active pipes in intel_mbus_dbox_update Date: Fri, 22 Mar 2024 13:40:45 +0200 Message-Id: <20240322114046.24930-5-stanislav.lisovskiy@intel.com> X-Mailer: git-send-email 2.37.3 In-Reply-To: <20240322114046.24930-1-stanislav.lisovskiy@intel.com> References: <20240322114046.24930-1-stanislav.lisovskiy@intel.com> MIME-Version: 1.0 X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" We need to loop through all active pipes, not just the ones, that are in current state, because disabling and enabling even a particular pipe affects credits in another one. Signed-off-by: Stanislav Lisovskiy Reviewed-by: Ville Syrjälä --- drivers/gpu/drm/i915/display/skl_watermark.c | 7 +------ 1 file changed, 1 insertion(+), 6 deletions(-) diff --git a/drivers/gpu/drm/i915/display/skl_watermark.c b/drivers/gpu/drm/i915/display/skl_watermark.c index 2b947870527fc..7eb78e0c8c8e3 100644 --- a/drivers/gpu/drm/i915/display/skl_watermark.c +++ b/drivers/gpu/drm/i915/display/skl_watermark.c @@ -3696,10 +3696,8 @@ void intel_mbus_dbox_update(struct intel_atomic_state *state) { struct drm_i915_private *i915 = to_i915(state->base.dev); const struct intel_dbuf_state *new_dbuf_state, *old_dbuf_state; - const struct intel_crtc_state *new_crtc_state; const struct intel_crtc *crtc; u32 val = 0; - int i; if (DISPLAY_VER(i915) < 11) return; @@ -3743,12 +3741,9 @@ void intel_mbus_dbox_update(struct intel_atomic_state *state) val |= MBUS_DBOX_B_CREDIT(8); } - for_each_new_intel_crtc_in_state(state, crtc, new_crtc_state, i) { + for_each_intel_crtc_in_pipe_mask(&i915->drm, crtc, new_dbuf_state->active_pipes) { u32 pipe_val = val; - if (!new_crtc_state->hw.active) - continue; - if (DISPLAY_VER(i915) >= 14) { if (xelpdp_is_only_pipe_per_dbuf_bank(crtc->pipe, new_dbuf_state->active_pipes)) From patchwork Fri Mar 22 11:40:46 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Stanislav Lisovskiy X-Patchwork-Id: 13599991 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 9CEBCC6FD1F for ; Fri, 22 Mar 2024 11:40:58 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id EA7F110F686; Fri, 22 Mar 2024 11:40:57 +0000 (UTC) Authentication-Results: gabe.freedesktop.org; dkim=pass (2048-bit key; unprotected) header.d=intel.com header.i=@intel.com header.b="MofP5lEr"; dkim-atps=neutral Received: from mgamail.intel.com (mgamail.intel.com [198.175.65.15]) by gabe.freedesktop.org (Postfix) with ESMTPS id 2BC5A10F657 for ; Fri, 22 Mar 2024 11:40:57 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1711107657; x=1742643657; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=mBoWmVySJbQlUfdYzSRxEua1gFhxdoVdMPIPTHd+aKY=; b=MofP5lErUjDqZHoBfWp2knlbGmLtgLzEQKOUfz4opUiCay4uv2uCqOHI s9SzJbPa/L1GODveadj0ra5TjfHEGNgyH/47iNpI7/iq05ZIlZD2WHeAe Cn7eRjSvo4rB3WHrUpFwxh5IoYAXF0/2UgUn7cl7TAkNHRgm5+ERIaXW2 BXzX5xZed93gHwwxUbrS55W3nQnNAr6mRH91EkKN9I9aKqUayVGMIJWLc 2/r/+zOkFU2gX7jumQ1gKFNmufuDbyfqS5h59FjW5yAVSFWe0B0f629IK qD6qXUTPZWH/by/vRcY+lBKMXuiwMnq92xZHPmD0VPzGeg95dHPycYy1L g==; X-IronPort-AV: E=McAfee;i="6600,9927,11020"; a="9939224" X-IronPort-AV: E=Sophos;i="6.07,145,1708416000"; d="scan'208";a="9939224" Received: from fmviesa009.fm.intel.com ([10.60.135.149]) by orvoesa107.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 22 Mar 2024 04:40:57 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.07,145,1708416000"; d="scan'208";a="14906493" Received: from unknown (HELO slisovsk-Lenovo-ideapad-720S-13IKB.fi.intel.com) ([10.237.72.65]) by fmviesa009.fm.intel.com with ESMTP; 22 Mar 2024 04:40:55 -0700 From: Stanislav Lisovskiy To: intel-gfx@lists.freedesktop.org Cc: jani.saarinen@intel.com, Stanislav.Lisovskiy@intel.com, ville.syrjala@linux.intel.com Subject: [PATCH 5/5] drm/i915: Implement vblank synchronized MBUS join changes Date: Fri, 22 Mar 2024 13:40:46 +0200 Message-Id: <20240322114046.24930-6-stanislav.lisovskiy@intel.com> X-Mailer: git-send-email 2.37.3 In-Reply-To: <20240322114046.24930-1-stanislav.lisovskiy@intel.com> References: <20240322114046.24930-1-stanislav.lisovskiy@intel.com> MIME-Version: 1.0 X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" Currently we can't change MBUS join status without doing a modeset, because we are lacking mechanism to synchronize those with vblank. However then this means that we can't do a fastset, if there is a need to change MBUS join state. Fix that by implementing such change. We already call correspondent check and update at pre_plane dbuf update, so the only thing left is to have a non-modeset version of that. If active pipes stay the same then fastset is possible and only MBUS join state/ddb allocation updates would be committed. Signed-off-by: Stanislav Lisovskiy --- drivers/gpu/drm/i915/display/intel_display.c | 6 +- drivers/gpu/drm/i915/display/skl_watermark.c | 108 +++++++++++++++---- drivers/gpu/drm/i915/display/skl_watermark.h | 2 + 3 files changed, 94 insertions(+), 22 deletions(-) diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c index b88f214e111ae..d5351f6fa2eb4 100644 --- a/drivers/gpu/drm/i915/display/intel_display.c +++ b/drivers/gpu/drm/i915/display/intel_display.c @@ -6895,6 +6895,8 @@ static void skl_commit_modeset_enables(struct intel_atomic_state *state) intel_pre_update_crtc(state, crtc); } + intel_dbuf_mbus_pre_ddb_update(state); + while (update_pipes) { for_each_oldnew_intel_crtc_in_state(state, crtc, old_crtc_state, new_crtc_state, i) { @@ -6925,6 +6927,8 @@ static void skl_commit_modeset_enables(struct intel_atomic_state *state) } } + intel_dbuf_mbus_post_ddb_update(state); + update_pipes = modeset_pipes; /* @@ -7169,9 +7173,7 @@ static void intel_atomic_commit_tail(struct intel_atomic_state *state) } intel_encoders_update_prepare(state); - intel_dbuf_pre_plane_update(state); - intel_mbus_dbox_update(state); for_each_new_intel_crtc_in_state(state, crtc, new_crtc_state, i) { if (new_crtc_state->do_async_flip) diff --git a/drivers/gpu/drm/i915/display/skl_watermark.c b/drivers/gpu/drm/i915/display/skl_watermark.c index 7eb78e0c8c8e3..eee13b57d4830 100644 --- a/drivers/gpu/drm/i915/display/skl_watermark.c +++ b/drivers/gpu/drm/i915/display/skl_watermark.c @@ -4,6 +4,7 @@ */ #include +#include #include "i915_drv.h" #include "i915_fixed.h" @@ -2636,13 +2637,6 @@ skl_compute_ddb(struct intel_atomic_state *state) if (ret) return ret; - if (old_dbuf_state->joined_mbus != new_dbuf_state->joined_mbus) { - /* TODO: Implement vblank synchronized MBUS joining changes */ - ret = intel_modeset_all_pipes_late(state, "MBUS joining change"); - if (ret) - return ret; - } - drm_dbg_kms(&i915->drm, "Enabled dbuf slices 0x%x -> 0x%x (total dbuf slices 0x%x), mbus joined? %s->%s\n", old_dbuf_state->enabled_slices, @@ -3594,30 +3588,57 @@ static void intel_dbuf_mdclk_min_tracker_update(struct intel_atomic_state *state new_dbuf_state->joined_mbus); } +static enum pipe intel_mbus_joined_pipe(struct intel_atomic_state *state, + const struct intel_dbuf_state *dbuf_state) +{ + struct drm_i915_private *i915 = to_i915(state->base.dev); + enum pipe sync_pipe = ffs(dbuf_state->active_pipes) - 1; + struct intel_crtc_state *new_crtc_state; + struct intel_crtc *crtc; + + drm_WARN_ON(&i915->drm, !dbuf_state->joined_mbus); + drm_WARN_ON(&i915->drm, !is_power_of_2(dbuf_state->active_pipes)); + + crtc = intel_crtc_for_pipe(i915, sync_pipe); + new_crtc_state = intel_atomic_get_new_crtc_state(state, crtc); + + if (new_crtc_state && !intel_crtc_needs_modeset(new_crtc_state)) + return sync_pipe; + else + return INVALID_PIPE; +} + /* * Configure MBUS_CTL and all DBUF_CTL_S of each slice to join_mbus state before * update the request state of all DBUS slices. */ -static void intel_dbuf_mbus_join_update(struct intel_atomic_state *state) +static void intel_dbuf_mbus_ctl_update(struct intel_atomic_state *state, + enum pipe sync_pipe) { struct drm_i915_private *i915 = to_i915(state->base.dev); u32 mbus_ctl; const struct intel_dbuf_state *new_dbuf_state = intel_atomic_get_new_dbuf_state(state); + u32 pipe_select; if (!HAS_MBUS_JOINING(i915)) return; + if (sync_pipe != INVALID_PIPE) + pipe_select = MBUS_JOIN_PIPE_SELECT(sync_pipe); + else + pipe_select = MBUS_JOIN_PIPE_SELECT_NONE; + /* * TODO: Implement vblank synchronized MBUS joining changes. * Must be properly coordinated with dbuf reprogramming. */ if (new_dbuf_state->joined_mbus) mbus_ctl = MBUS_HASHING_MODE_1x4 | MBUS_JOIN | - MBUS_JOIN_PIPE_SELECT_NONE; + pipe_select; else mbus_ctl = MBUS_HASHING_MODE_2x2 | - MBUS_JOIN_PIPE_SELECT_NONE; + pipe_select; intel_de_rmw(i915, MBUS_CTL, MBUS_HASHING_MODE_MASK | MBUS_JOIN | @@ -3632,6 +3653,42 @@ void intel_dbuf_pre_plane_update(struct intel_atomic_state *state) const struct intel_dbuf_state *old_dbuf_state = intel_atomic_get_old_dbuf_state(state); + if (!new_dbuf_state || + (new_dbuf_state->enabled_slices == old_dbuf_state->enabled_slices)) + return; + + WARN_ON(!new_dbuf_state->base.changed); + + gen9_dbuf_slices_update(i915, + old_dbuf_state->enabled_slices | + new_dbuf_state->enabled_slices); +} + +void intel_dbuf_post_plane_update(struct intel_atomic_state *state) +{ + struct drm_i915_private *i915 = to_i915(state->base.dev); + const struct intel_dbuf_state *new_dbuf_state = + intel_atomic_get_new_dbuf_state(state); + const struct intel_dbuf_state *old_dbuf_state = + intel_atomic_get_old_dbuf_state(state); + + if (!new_dbuf_state || + (new_dbuf_state->enabled_slices == old_dbuf_state->enabled_slices)) + return; + + WARN_ON(!new_dbuf_state->base.changed); + + gen9_dbuf_slices_update(i915, + new_dbuf_state->enabled_slices); +} + +void intel_dbuf_mbus_pre_ddb_update(struct intel_atomic_state *state) +{ + const struct intel_dbuf_state *new_dbuf_state = + intel_atomic_get_new_dbuf_state(state); + const struct intel_dbuf_state *old_dbuf_state = + intel_atomic_get_old_dbuf_state(state); + if (!new_dbuf_state || (new_dbuf_state->enabled_slices == old_dbuf_state->enabled_slices && new_dbuf_state->joined_mbus == old_dbuf_state->joined_mbus)) @@ -3640,16 +3697,15 @@ void intel_dbuf_pre_plane_update(struct intel_atomic_state *state) WARN_ON(!new_dbuf_state->base.changed); if (!old_dbuf_state->joined_mbus && new_dbuf_state->joined_mbus) { - intel_dbuf_mbus_join_update(state); + enum pipe sync_pipe = intel_mbus_joined_pipe(state, new_dbuf_state); + + intel_dbuf_mbus_ctl_update(state, sync_pipe); + intel_mbus_dbox_update(state); intel_dbuf_mdclk_min_tracker_update(state); } - - gen9_dbuf_slices_update(i915, - old_dbuf_state->enabled_slices | - new_dbuf_state->enabled_slices); } -void intel_dbuf_post_plane_update(struct intel_atomic_state *state) +void intel_dbuf_mbus_post_ddb_update(struct intel_atomic_state *state) { struct drm_i915_private *i915 = to_i915(state->base.dev); const struct intel_dbuf_state *new_dbuf_state = @@ -3657,6 +3713,12 @@ void intel_dbuf_post_plane_update(struct intel_atomic_state *state) const struct intel_dbuf_state *old_dbuf_state = intel_atomic_get_old_dbuf_state(state); + if (new_dbuf_state && old_dbuf_state && + new_dbuf_state->joined_mbus == old_dbuf_state->joined_mbus) { + intel_dbuf_mdclk_min_tracker_update(state); + intel_mbus_dbox_update(state); + } + if (!new_dbuf_state || (new_dbuf_state->enabled_slices == old_dbuf_state->enabled_slices && new_dbuf_state->joined_mbus == old_dbuf_state->joined_mbus)) @@ -3665,12 +3727,18 @@ void intel_dbuf_post_plane_update(struct intel_atomic_state *state) WARN_ON(!new_dbuf_state->base.changed); if (old_dbuf_state->joined_mbus && !new_dbuf_state->joined_mbus) { - intel_dbuf_mbus_join_update(state); + enum pipe sync_pipe = intel_mbus_joined_pipe(state, old_dbuf_state); + intel_dbuf_mdclk_min_tracker_update(state); - } + intel_mbus_dbox_update(state); + intel_dbuf_mbus_ctl_update(state, sync_pipe); - gen9_dbuf_slices_update(i915, - new_dbuf_state->enabled_slices); + if (sync_pipe != INVALID_PIPE) { + struct intel_crtc *crtc = intel_crtc_for_pipe(i915, sync_pipe); + + intel_crtc_wait_for_next_vblank(crtc); + } + } } static bool xelpdp_is_only_pipe_per_dbuf_bank(enum pipe pipe, u8 active_pipes) diff --git a/drivers/gpu/drm/i915/display/skl_watermark.h b/drivers/gpu/drm/i915/display/skl_watermark.h index 3a90741cab06a..f6d38b41e3a6c 100644 --- a/drivers/gpu/drm/i915/display/skl_watermark.h +++ b/drivers/gpu/drm/i915/display/skl_watermark.h @@ -77,6 +77,8 @@ int intel_dbuf_state_set_mdclk_cdclk_ratio(struct intel_atomic_state *state, u8 void intel_dbuf_pre_plane_update(struct intel_atomic_state *state); void intel_dbuf_post_plane_update(struct intel_atomic_state *state); void intel_dbuf_mdclk_cdclk_ratio_update(struct drm_i915_private *i915, u8 ratio, bool joined_mbus); +void intel_dbuf_mbus_pre_ddb_update(struct intel_atomic_state *state); +void intel_dbuf_mbus_post_ddb_update(struct intel_atomic_state *state); void intel_mbus_dbox_update(struct intel_atomic_state *state); #endif /* __SKL_WATERMARK_H__ */