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Sun, 24 Mar 2024 09:09:52 +0100 From: Sven Schnelle To: Richard Henderson Cc: qemu-devel@nongnu.org, Helge Deller , Sven Schnelle Subject: [PATCH 1/3] target/hppa: use gva_offset_mask() everywhere Date: Sun, 24 Mar 2024 09:09:43 +0100 Message-ID: <20240324080945.991100-2-svens@stackframe.org> X-Mailer: git-send-email 2.43.2 In-Reply-To: <20240324080945.991100-1-svens@stackframe.org> References: <20240324080945.991100-1-svens@stackframe.org> MIME-Version: 1.0 Received-SPF: pass client-ip=23.83.209.75; envelope-from=svens@stackframe.org; helo=gorilla.birch.relay.mailchannels.net X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_MED=-0.001, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, RCVD_IN_MSPIKE_H4=0.001, RCVD_IN_MSPIKE_WL=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org move it to cpu.h, so it can also be used in hppa_form_gva_psw() Signed-off-by: Sven Schnelle Reviewed-by: Helge Deller Reviewed-by: Richard Henderson --- target/hppa/cpu.h | 10 ++++++++-- target/hppa/translate.c | 12 +++--------- 2 files changed, 11 insertions(+), 11 deletions(-) diff --git a/target/hppa/cpu.h b/target/hppa/cpu.h index a92dc352cb..a072d0bb63 100644 --- a/target/hppa/cpu.h +++ b/target/hppa/cpu.h @@ -285,14 +285,20 @@ void hppa_translate_init(void); #define CPU_RESOLVING_TYPE TYPE_HPPA_CPU +static inline uint64_t gva_offset_mask(target_ulong psw) +{ + return (psw & PSW_W + ? MAKE_64BIT_MASK(0, 62) + : MAKE_64BIT_MASK(0, 32)); +} + static inline target_ulong hppa_form_gva_psw(target_ulong psw, uint64_t spc, target_ulong off) { #ifdef CONFIG_USER_ONLY return off; #else - off &= psw & PSW_W ? MAKE_64BIT_MASK(0, 62) : MAKE_64BIT_MASK(0, 32); - return spc | off; + return spc | (off & gva_offset_mask(psw)); #endif } diff --git a/target/hppa/translate.c b/target/hppa/translate.c index 19594f917e..0af125ed74 100644 --- a/target/hppa/translate.c +++ b/target/hppa/translate.c @@ -586,17 +586,10 @@ static bool nullify_end(DisasContext *ctx) return true; } -static uint64_t gva_offset_mask(DisasContext *ctx) -{ - return (ctx->tb_flags & PSW_W - ? MAKE_64BIT_MASK(0, 62) - : MAKE_64BIT_MASK(0, 32)); -} - static void copy_iaoq_entry(DisasContext *ctx, TCGv_i64 dest, uint64_t ival, TCGv_i64 vval) { - uint64_t mask = gva_offset_mask(ctx); + uint64_t mask = gva_offset_mask(ctx->tb_flags); if (ival != -1) { tcg_gen_movi_i64(dest, ival & mask); @@ -1403,7 +1396,8 @@ static void form_gva(DisasContext *ctx, TCGv_i64 *pgva, TCGv_i64 *pofs, *pofs = ofs; *pgva = addr = tcg_temp_new_i64(); - tcg_gen_andi_i64(addr, modify <= 0 ? ofs : base, gva_offset_mask(ctx)); + tcg_gen_andi_i64(addr, modify <= 0 ? ofs : base, + gva_offset_mask(ctx->tb_flags)); #ifndef CONFIG_USER_ONLY if (!is_phys) { tcg_gen_or_i64(addr, addr, space_select(ctx, sp, base)); From patchwork Sun Mar 24 08:09:44 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Sven Schnelle X-Patchwork-Id: 13600782 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 7A9DAC6FD1F for ; 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Sun, 24 Mar 2024 09:09:53 +0100 From: Sven Schnelle To: Richard Henderson Cc: qemu-devel@nongnu.org, Helge Deller , Sven Schnelle Subject: [PATCH 2/3] target/hppa: mask offset bits in gva Date: Sun, 24 Mar 2024 09:09:44 +0100 Message-ID: <20240324080945.991100-3-svens@stackframe.org> X-Mailer: git-send-email 2.43.2 In-Reply-To: <20240324080945.991100-1-svens@stackframe.org> References: <20240324080945.991100-1-svens@stackframe.org> MIME-Version: 1.0 Received-SPF: pass client-ip=23.83.208.37; envelope-from=svens@stackframe.org; helo=cockroach.apple.relay.mailchannels.net X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_MED=-0.001, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, RCVD_IN_MSPIKE_H4=0.001, RCVD_IN_MSPIKE_WL=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org The CPU seems to mask a few bits in the offset when running under HP-UX. ISR/IOR register contents for an address in the processor HPA (0xfffffffffffa0000) on my C8000 and J6750: running on Linux: 000000003fffffff c0000000fffa0500 running on HP-UX: 00000000301fffff c0000000fffa0500 I haven't found how this is switched (guess some diag in the firmware), but linux + seabios seems to handle that as well, so lets mask out the additional bits. Signed-off-by: Sven Schnelle Tested-by: Helge Deller --- target/hppa/cpu.h | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/target/hppa/cpu.h b/target/hppa/cpu.h index a072d0bb63..9bc4d208fa 100644 --- a/target/hppa/cpu.h +++ b/target/hppa/cpu.h @@ -283,12 +283,13 @@ static inline int HPPA_BTLB_ENTRIES(CPUHPPAState *env) void hppa_translate_init(void); +#define HPPA_GVA_OFFSET_MASK64 0x301fffffffffffff #define CPU_RESOLVING_TYPE TYPE_HPPA_CPU static inline uint64_t gva_offset_mask(target_ulong psw) { return (psw & PSW_W - ? MAKE_64BIT_MASK(0, 62) + ? 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Sun, 24 Mar 2024 09:09:53 +0100 From: Sven Schnelle To: Richard Henderson Cc: qemu-devel@nongnu.org, Helge Deller , Sven Schnelle Subject: [PATCH 3/3] target/hppa: fix building gva for wide mode Date: Sun, 24 Mar 2024 09:09:45 +0100 Message-ID: <20240324080945.991100-4-svens@stackframe.org> X-Mailer: git-send-email 2.43.2 In-Reply-To: <20240324080945.991100-1-svens@stackframe.org> References: <20240324080945.991100-1-svens@stackframe.org> MIME-Version: 1.0 Received-SPF: pass client-ip=23.83.216.33; envelope-from=svens@stackframe.org; helo=chameleon.pear.relay.mailchannels.net X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_MED=-0.001, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, RCVD_IN_MSPIKE_H4=0.001, RCVD_IN_MSPIKE_WL=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org 64 Bit hppa no longer has a fixed 32/32 bit split between space and offset. Instead it uses 42 bits for the offset. The lower 10 bits of the space are always zero, leaving 22 bits actually used. Simply or the values together to build the gva. Signed-off-by: Sven Schnelle Reviewed-by: Helge Deller Tested-by: Helge Deller Reviewed-by: Richard Henderson --- target/hppa/mem_helper.c | 13 +++++++------ 1 file changed, 7 insertions(+), 6 deletions(-) diff --git a/target/hppa/mem_helper.c b/target/hppa/mem_helper.c index 84785b5a5c..6f895fced7 100644 --- a/target/hppa/mem_helper.c +++ b/target/hppa/mem_helper.c @@ -523,13 +523,16 @@ void HELPER(itlbp_pa11)(CPUHPPAState *env, target_ulong addr, target_ulong reg) } static void itlbt_pa20(CPUHPPAState *env, target_ulong r1, - target_ulong r2, vaddr va_b) + target_ulong r2, uint64_t spc, uint64_t off) { HPPATLBEntry *ent; - vaddr va_e; + vaddr va_b, va_e; uint64_t va_size; int mask_shift; + va_b = off & gva_offset_mask(env->psw); + va_b |= spc << 32; + mask_shift = 2 * (r1 & 0xf); va_size = (uint64_t)TARGET_PAGE_SIZE << mask_shift; va_b &= -va_size; @@ -569,14 +572,12 @@ static void itlbt_pa20(CPUHPPAState *env, target_ulong r1, void HELPER(idtlbt_pa20)(CPUHPPAState *env, target_ulong r1, target_ulong r2) { - vaddr va_b = deposit64(env->cr[CR_IOR], 32, 32, env->cr[CR_ISR]); - itlbt_pa20(env, r1, r2, va_b); + itlbt_pa20(env, r1, r2, env->cr[CR_ISR], env->cr[CR_IOR]); } void HELPER(iitlbt_pa20)(CPUHPPAState *env, target_ulong r1, target_ulong r2) { - vaddr va_b = deposit64(env->cr[CR_IIAOQ], 32, 32, env->cr[CR_IIASQ]); - itlbt_pa20(env, r1, r2, va_b); + itlbt_pa20(env, r1, r2, env->cr[CR_IIASQ], env->cr[CR_IIAOQ]); } /* Purge (Insn/Data) TLB. */