From patchwork Mon Mar 25 06:40:56 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Ivan Bornyakov X-Patchwork-Id: 13601664 Received: from mail-lf1-f46.google.com (mail-lf1-f46.google.com [209.85.167.46]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id F16F815F323; Mon, 25 Mar 2024 06:41:22 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.167.46 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1711348885; cv=none; b=SsVsHyidBs4cDJQE14nLrZ0V49f7NYLctlKcocYx0xLYUIvLOg/kUuaOWB50G/W+QaC6E5dAcaQE22gg5ce0CbKZDQLmvf2YD8G9tQlSKU8VXLLXBLhmKLSq9vMOFmgpZdbIVAbrGxL7vCEW1PBzPH5tQVjHjZsHtg1B8RRuKkc= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1711348885; c=relaxed/simple; bh=qkH1n2ZJ4QVAdDXQQaJsqr3HhVev4kuqL3wJZVBjiJQ=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=L29Gt2IAL3JBUY/mO6FMGqliLLnqlxmnkf0bVeiOp+AMzeExUi1xi/9CdH4JfNJoHdOqsf5198OsjceEM6/l+zmfv1V87WAv1cNhxG0sZNBYuwaUQStDvAeOJ10Z1OUvtCrIe15c5B6Nz/ZK0kikX94aqqYY//XRFNilR4drqSI= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=gmail.com; spf=pass smtp.mailfrom=gmail.com; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b=WF9d5NSk; arc=none smtp.client-ip=209.85.167.46 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=gmail.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=gmail.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b="WF9d5NSk" Received: by mail-lf1-f46.google.com with SMTP id 2adb3069b0e04-513e89d0816so4973664e87.0; Sun, 24 Mar 2024 23:41:22 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20230601; t=1711348881; x=1711953681; darn=vger.kernel.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=N6AIAxCJz2R5rlggcf2OWr2A/Jt7N68nXNuioW63cJo=; b=WF9d5NSkpwOliSkjpgPn9m1twpCzhCbNdEVW/hSqiIKoFK+wPG41KaIDTsethpj1ob K/ZQC13trZ1P5CG+wlGnmMkpYcE/L20C3EkmKnxpfix/es30T4c4AEdZbfdj7GygZf6T PCWadpoN/S1KxbLGjT7H5WFQKOP6dULObdj6NjrW7bTiMXg9/lgb/ldB1j3dKUVNWqOs Xpm5etOji5SapWcOGUwwBcyiNhKW2XIhdVFCovEcoVZVD72z4+H9QX0+6hDBsJOR+dqT O87cdYBes8e8vLlnjph8HzK/R2MJtEvSKLD3TfYBra/b9+SLK2FFufbbgQVPA+dIO4Hm U1Pw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1711348881; x=1711953681; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=N6AIAxCJz2R5rlggcf2OWr2A/Jt7N68nXNuioW63cJo=; b=RyqXZZXXcM3CrD4JICAl7K/+qwSH9p1xZoNEYz+q8N3f5NAxE68hhSHL39QkIKjGXz 78stMNnwaoLU3H/kavmuT2LpyqShxlXk6bEcprc4by0qa2500ZMCMzhtvZS3bVW/dePN rMOv3+xjBG35Lu5dw+8k+/yhfseQbxB0ivV0nSXhJ2Lv8w1fJb3YDPH0FFMGGNl+lxfK Y3Kj9YbaWho0J4QB9Dw3U5msMYck+zDybpYc2M9jLB08sF0f6AzrNhkuyv+wYAkRKB9g TPYc2Px6sgfNqsm1hnHMneUcP0+GqHbYx53Oaj3XOMKcbFblS7nGWEhCFONN1lhVtf+5 yohQ== X-Forwarded-Encrypted: i=1; AJvYcCVTuTCiJpJTp3gxISf/b2hxtWF+zfRtCJeqw1w+sC/Zc4aCMNMCmFGKYZwpNGwVpooH9OZ4nduZR/VzVj9oF8rDrIdJx+ecIkAhH/XAf1QiH8LJ9bhU5VBZA2RSZoY5YoDPy4gxMBrXwqs= X-Gm-Message-State: AOJu0YxSFZathlCYP8qBf8k8WkvN4N1WyMf3F6wPmepDQyS57By5OzVo q3i70z72mHugUCBICyTAsKFoO6vZl+8nTu54+IzhrVTElINf4476HmM1S09td5U= X-Google-Smtp-Source: AGHT+IHjY6jEU2tUXWbuyMoSaswlaUukw1uj+p5qAz9JveoI6u6Y8TnVuzQi/pZsWTT3oA4L1wKcfw== X-Received: by 2002:a05:6512:3b12:b0:515:a670:3a6c with SMTP id f18-20020a0565123b1200b00515a6703a6cmr3648059lfv.23.1711348879078; Sun, 24 Mar 2024 23:41:19 -0700 (PDT) Received: from localhost.localdomain ([178.70.43.28]) by smtp.gmail.com with ESMTPSA id h12-20020a0565123c8c00b00515a411fd20sm828229lfv.105.2024.03.24.23.41.18 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 24 Mar 2024 23:41:18 -0700 (PDT) From: Ivan Bornyakov To: Nas Chung , Jackson Lee , Mauro Carvalho Chehab , Philipp Zabel Cc: Ivan Bornyakov , linux-media@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH v2 1/5] media: chips-media: wave5: support decoding HEVC Main10 profile Date: Mon, 25 Mar 2024 09:40:56 +0300 Message-ID: <20240325064102.9278-2-brnkv.i1@gmail.com> X-Mailer: git-send-email 2.44.0 In-Reply-To: <20240325064102.9278-1-brnkv.i1@gmail.com> References: <20240325064102.9278-1-brnkv.i1@gmail.com> Precedence: bulk X-Mailing-List: linux-media@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Add support for decoding HEVC Main10 profile by scaling FBC buffer stride and size by the factor of (bitdepth / 8). Signed-off-by: Ivan Bornyakov --- .../chips-media/wave5/wave5-vpu-dec.c | 30 +++++++++++-------- .../platform/chips-media/wave5/wave5-vpuapi.h | 1 + 2 files changed, 18 insertions(+), 13 deletions(-) diff --git a/drivers/media/platform/chips-media/wave5/wave5-vpu-dec.c b/drivers/media/platform/chips-media/wave5/wave5-vpu-dec.c index ef227af72348..5a71a711f2e8 100644 --- a/drivers/media/platform/chips-media/wave5/wave5-vpu-dec.c +++ b/drivers/media/platform/chips-media/wave5/wave5-vpu-dec.c @@ -1055,6 +1055,22 @@ static int wave5_prepare_fb(struct vpu_instance *inst) int ret, i; struct v4l2_m2m_buffer *buf, *n; struct v4l2_m2m_ctx *m2m_ctx = inst->v4l2_fh.m2m_ctx; + u32 bitdepth = inst->codec_info->dec_info.initial_info.luma_bitdepth; + + switch (bitdepth) { + case 8: + break; + case 10: + if (inst->std == W_HEVC_DEC && + inst->dev->attr.support_hevc10bit_dec) + break; + + fallthrough; + default: + dev_err(inst->dev->dev, "no support for %d bit depth\n", bitdepth); + + return -EINVAL; + } linear_num = v4l2_m2m_num_dst_bufs_ready(m2m_ctx); non_linear_num = inst->fbc_buf_count; @@ -1063,7 +1079,7 @@ static int wave5_prepare_fb(struct vpu_instance *inst) struct frame_buffer *frame = &inst->frame_buf[i]; struct vpu_buf *vframe = &inst->frame_vbuf[i]; - fb_stride = inst->dst_fmt.width; + fb_stride = ALIGN(inst->dst_fmt.width * bitdepth / 8, 32); fb_height = ALIGN(inst->dst_fmt.height, 32); luma_size = fb_stride * fb_height; @@ -1408,22 +1424,10 @@ static int wave5_vpu_dec_start_streaming(struct vb2_queue *q, unsigned int count if (ret) goto free_bitstream_vbuf; } else if (q->type == V4L2_BUF_TYPE_VIDEO_CAPTURE_MPLANE) { - struct dec_initial_info *initial_info = - &inst->codec_info->dec_info.initial_info; - if (inst->state == VPU_INST_STATE_STOP) ret = switch_state(inst, VPU_INST_STATE_INIT_SEQ); if (ret) goto return_buffers; - - if (inst->state == VPU_INST_STATE_INIT_SEQ) { - if (initial_info->luma_bitdepth != 8) { - dev_info(inst->dev->dev, "%s: no support for %d bit depth", - __func__, initial_info->luma_bitdepth); - ret = -EINVAL; - goto return_buffers; - } - } } return ret; diff --git a/drivers/media/platform/chips-media/wave5/wave5-vpuapi.h b/drivers/media/platform/chips-media/wave5/wave5-vpuapi.h index 352f6e904e50..465ff9dfe8b1 100644 --- a/drivers/media/platform/chips-media/wave5/wave5-vpuapi.h +++ b/drivers/media/platform/chips-media/wave5/wave5-vpuapi.h @@ -327,6 +327,7 @@ struct vpu_attr { u32 support_backbone: 1; u32 support_avc10bit_enc: 1; u32 support_hevc10bit_enc: 1; + u32 support_hevc10bit_dec: 1; u32 support_vcore_backbone: 1; u32 support_vcpu_backbone: 1; }; From patchwork Mon Mar 25 06:40:57 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Ivan Bornyakov X-Patchwork-Id: 13601665 Received: from mail-lf1-f43.google.com (mail-lf1-f43.google.com [209.85.167.43]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id DAFDE15F32E; Mon, 25 Mar 2024 06:41:24 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.167.43 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1711348888; cv=none; b=KBpK2zAMAuqvcaQREXRCCl69dBV2giHEvdhF0sU/thtHjbZg/wisBvjCYb55N5M1iUvEj8H1juiatoH4OYZJAUk++RVIKN5HHW7tnzyrE6KuRNj3TMmVYJUxyozseNt4oz3NzlvFDo77Y/JDMEPbO+94OJ/0z94npKTbh/CAJ2I= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1711348888; c=relaxed/simple; bh=CNyZv7F7MM6DJREsMjJWxzU9kMvkiJmWI7Qjwel8lhk=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=Uc6WPZbao5E29GOxAu4rJ0Jwr8bGF5zl1onCZ+k/qlRNUo5f6/3JjCuLLCPcf+3b/qVj0A7/uBZnoHr/Mvt8XwF02A59ZA/G6T8lrF9kXVwURfrzCqMUztlO/BHMM8jLA0Oap9ytq+pbfeDQ1bK5P5y7sn2Z5PgSNMgC2p2Xtbs= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=gmail.com; spf=pass smtp.mailfrom=gmail.com; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b=SYuvxDRJ; arc=none smtp.client-ip=209.85.167.43 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=gmail.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=gmail.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b="SYuvxDRJ" Received: by mail-lf1-f43.google.com with SMTP id 2adb3069b0e04-512e4f4e463so4185781e87.1; Sun, 24 Mar 2024 23:41:24 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20230601; t=1711348883; x=1711953683; darn=vger.kernel.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=oushmNgLEoSiFSU+fvxV91NyvXwpQw1n1UeXr157a84=; b=SYuvxDRJG2GMwDVgtxkq2u17Tl5oVvcbnHSoV1Ako0bw1uQr2Hn8qAqisAhZ6etkWw FQBAmcGYGc7ryHqWRqq2kcYzDWut95X8LrpIOcvT9o5G8HR9oTTamgAqgD7tXV62+Ipa HKRVTd0NAf1QOPy8KfjX+zSl3pDPeik1SPNftLaCYuH368sdwhlHGM7eq4XET4lGpQ2f Hf/J++FMeO+VyFXfT5NNfEmccPE4l6a3UzfCJAlmO2AekeTTnEzqLvey537sm9IdH7zX Rg4KMp8ZCqFYrcsVApm9MlWQFVrEl6sjTERPPc1SXbrXvQq/YXO/F8I9XN17zQbSYSS/ OY2A== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1711348883; x=1711953683; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=oushmNgLEoSiFSU+fvxV91NyvXwpQw1n1UeXr157a84=; b=SmCgiqhIGOplPos9rgtI9qX5DMLepZVupdVY0uiRduLDir442/tK3P+NDfOILkunb6 p9GGTSrxZkHY/h2I7LYoJURhFMsppPFmAc8IeKVf1maLbsR4DIqzIOtZESo8VP34z6NN n5bmJvnsVZd4s+NlUI62zADMgzq8V7psc3HlDg9njt7FRq5PL06nirSHFV5UIYAn3zuG B2dgSollYDiv7Wk9fy4zhcgOXvvl01zd02jxUHRM1t7swzgtfH3Cu72Cc4xFSxqadCeF 2vtXGLv8WHMcUL7dsd3QIvHtm1BivJoSMiE0S1tEEdMVe8MSjRe18ENu419gPLmkEkF8 j+dw== X-Forwarded-Encrypted: i=1; AJvYcCVJ3/+GJXygmCFPDnyEsnbgzOLmI036qgg3JAuR08OIz3Na3xy0ZDPNy6n4Vt7MBckPrbUa32J2aWuJmwxcrszNqIZe4jl+tgIqtDPcWvrRRH6METpRTvhwWcdz5xkQ6R7LQ0q4LdB+wT4= X-Gm-Message-State: AOJu0YysYhmeSVvkezHUXdivyCSd5L8GEKzZXes4gE7qQzQrEpk3WVBf QluGhoqs4TzQ6sSxyGveVinDthTGEWQdp+cWa8suS9oJ4Zqvh8li X-Google-Smtp-Source: AGHT+IEHz8wglR5bVMyA+cP5TCwFZTUL3ntj2kxAM1vtL9dUsR1o9AoXt44qB7zzSAqCBI64BzoyOw== X-Received: by 2002:a19:ca05:0:b0:513:ed0f:36c9 with SMTP id a5-20020a19ca05000000b00513ed0f36c9mr3620740lfg.45.1711348882734; Sun, 24 Mar 2024 23:41:22 -0700 (PDT) Received: from localhost.localdomain ([178.70.43.28]) by smtp.gmail.com with ESMTPSA id h12-20020a0565123c8c00b00515a411fd20sm828229lfv.105.2024.03.24.23.41.22 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 24 Mar 2024 23:41:22 -0700 (PDT) From: Ivan Bornyakov To: Nas Chung , Jackson Lee , Mauro Carvalho Chehab , Philipp Zabel Cc: Ivan Bornyakov , linux-media@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH v2 2/5] media: chips-media: wave5: support reset lines Date: Mon, 25 Mar 2024 09:40:57 +0300 Message-ID: <20240325064102.9278-3-brnkv.i1@gmail.com> X-Mailer: git-send-email 2.44.0 In-Reply-To: <20240325064102.9278-1-brnkv.i1@gmail.com> References: <20240325064102.9278-1-brnkv.i1@gmail.com> Precedence: bulk X-Mailing-List: linux-media@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Add initial support for optional reset lines. For now, simply deassert resets on driver probe and assert them back on driver remove. Signed-off-by: Ivan Bornyakov --- .../media/platform/chips-media/wave5/wave5-vpu.c | 16 +++++++++++++++- .../platform/chips-media/wave5/wave5-vpuapi.h | 1 + 2 files changed, 16 insertions(+), 1 deletion(-) diff --git a/drivers/media/platform/chips-media/wave5/wave5-vpu.c b/drivers/media/platform/chips-media/wave5/wave5-vpu.c index 1b3df5b04249..1e631da58e15 100644 --- a/drivers/media/platform/chips-media/wave5/wave5-vpu.c +++ b/drivers/media/platform/chips-media/wave5/wave5-vpu.c @@ -10,6 +10,7 @@ #include #include #include +#include #include "wave5-vpu.h" #include "wave5-regdefine.h" #include "wave5-vpuconfig.h" @@ -151,6 +152,16 @@ static int wave5_vpu_probe(struct platform_device *pdev) dev_set_drvdata(&pdev->dev, dev); dev->dev = &pdev->dev; + dev->resets = devm_reset_control_array_get_optional_exclusive(&pdev->dev); + if (IS_ERR(dev->resets)) { + return dev_err_probe(&pdev->dev, PTR_ERR(dev->resets), + "Failed to get reset control\n"); + } + + ret = reset_control_deassert(dev->resets); + if (ret) + return dev_err_probe(&pdev->dev, ret, "Failed to deassert resets\n"); + ret = devm_clk_bulk_get_all(&pdev->dev, &dev->clks); /* continue without clock, assume externally managed */ @@ -163,7 +174,7 @@ static int wave5_vpu_probe(struct platform_device *pdev) ret = clk_bulk_prepare_enable(dev->num_clks, dev->clks); if (ret) { dev_err(&pdev->dev, "Enabling clocks, fail: %d\n", ret); - return ret; + goto err_reset_assert; } ret = of_property_read_u32(pdev->dev.of_node, "sram-size", @@ -246,6 +257,8 @@ static int wave5_vpu_probe(struct platform_device *pdev) wave5_vdi_release(&pdev->dev); err_clk_dis: clk_bulk_disable_unprepare(dev->num_clks, dev->clks); +err_reset_assert: + reset_control_assert(dev->resets); return ret; } @@ -256,6 +269,7 @@ static void wave5_vpu_remove(struct platform_device *pdev) mutex_destroy(&dev->dev_lock); mutex_destroy(&dev->hw_lock); + reset_control_assert(dev->resets); clk_bulk_disable_unprepare(dev->num_clks, dev->clks); wave5_vpu_enc_unregister_device(dev); wave5_vpu_dec_unregister_device(dev); diff --git a/drivers/media/platform/chips-media/wave5/wave5-vpuapi.h b/drivers/media/platform/chips-media/wave5/wave5-vpuapi.h index 465ff9dfe8b1..da530fd98964 100644 --- a/drivers/media/platform/chips-media/wave5/wave5-vpuapi.h +++ b/drivers/media/platform/chips-media/wave5/wave5-vpuapi.h @@ -758,6 +758,7 @@ struct vpu_device { struct ida inst_ida; struct clk_bulk_data *clks; int num_clks; + struct reset_control *resets; }; struct vpu_instance; From patchwork Mon Mar 25 06:40:58 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Ivan Bornyakov X-Patchwork-Id: 13601666 Received: from mail-lf1-f49.google.com (mail-lf1-f49.google.com [209.85.167.49]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 6036515F316; Mon, 25 Mar 2024 06:41:26 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.167.49 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1711348888; cv=none; b=GNTxkefk/BFmUC8Sw8FijX7nBmy7Pmb8cGB2dnMmouSeQDUa5Ep9558Sb+keTv+NNAxTgTafTnPppi4VWR7KdC8RbVaOb1CWQSf90EBBhaMlzp5IQ9+8JziqGFDiQsvE9Mi1Zoup6ia8n9tA3hyWDwbap3fKv61Ez76PQ52FLwg= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1711348888; c=relaxed/simple; bh=qd9OurlGMiM81BMao1aJ4SpekOda8rLsQ9rKx4C/g1Q=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=bLM0VZJvsV0YulS247LQeXRf+f+2y34A72Vellms1mrUNXlj5ekhMQ2iNudVTvBHbX++rGz/+KcfocLYJDbiiC/ipCc6zhZC/ngurifImKger2I4B5aMOTd7OjpGkUVQ9Dj+vGvNIHvuKBJwJA45ywBjd/lEvxUtYRo11T45jcQ= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=gmail.com; spf=pass smtp.mailfrom=gmail.com; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b=iitRAe5e; arc=none smtp.client-ip=209.85.167.49 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=gmail.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=gmail.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b="iitRAe5e" Received: by mail-lf1-f49.google.com with SMTP id 2adb3069b0e04-515a68d45faso1223984e87.3; Sun, 24 Mar 2024 23:41:25 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20230601; t=1711348884; x=1711953684; darn=vger.kernel.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=gBcn1nMAdTSCT3A+/DCOtS0XSUKaFGHkFwng8LbwhbQ=; b=iitRAe5epbWwo+3LUaUIf6fAusQZb/o4pbfDymaDhwGL1yN9eD2quwjbNzUW/HhmUM K0vSc/xsDeHdMXRtKdAZl5P0t0G3hzsfyG9Gq8EBX8kYDqOBMnDNa5HD7qtFt5nJ744v MWpkral+DGEuHn53KAyOTT9I8Z2nN/LNsbm7bzgf6m+dyfZ0/NHgdJe4Xz43nCkK4SBs +cY8D/BGjIxppZlLkkZwu+P/zSWmqjaPv1WeHaraDfcAP8OlnrkY5wkL6xvYDK5StVJ1 Tid8ixec0T32+z4oQzSQucSicsF8rbtqKAJKbBtIyDpnj/QzE4lkx7K4qD4q6FhwaPe/ gE3g== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1711348884; x=1711953684; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=gBcn1nMAdTSCT3A+/DCOtS0XSUKaFGHkFwng8LbwhbQ=; b=X+H+pVuD6ayR3zq7HKG0eyXMNVFQb8yPCtevILO+1rdpRvfpMU4OhMNDO1BC67w5si 3KWkL+SmqurX8SUzQhqcONVCZ6JJAqtOWjT2NQo3TbLW+herelvQI6N92E3cEQfbNgk7 PJuujR9DKXwBO+yvvHKoFDRPB3/af/LZpM+KvhhZfBhZ+sNGKWh2YEBjx8faSmnW2NJw qEzD0Q479OazerJmswH6AunVDMul2aR+uyu2+0+66dBgOo/B5YNzaUtLz8wASBb6Y9D1 Y8BMSOCFGKT076lM0fXLuhHZYx5iFWo4Y5x2fkV/FDZUj2QTeXOsHt3OdQumGg/FsXL5 yTjg== X-Forwarded-Encrypted: i=1; AJvYcCUTvhpUVgI8DiBd1f4QAg71BgMD9E3D7gVZ9YgO3TzFKWbQlRbgGRV3iMNWzdPCowGSNW3SZBOvryOXLnKKUqkBp/hZ7K7VtDA5XzOkZB7Bzh3Y5bqinwLS8V2ceQePSDSQZapwPl88SyU= X-Gm-Message-State: AOJu0YwCoGZ7b68sY0dM9cjMw0r1DKYIKVLec1U93oAdahOmj2JKAF8j /ftj/vw27izFd9yBzOrWTvWvew45SNNdOoR8IngfsiAEBYQ64XZz X-Google-Smtp-Source: AGHT+IEbp9BSSIYvBpgQ5OzZMtwrAE7JxYZUhvNxNOIUJU8eReaml8Hi3C/KUmT9d90QR2EjR65JAw== X-Received: by 2002:a19:ca07:0:b0:512:fabd:8075 with SMTP id a7-20020a19ca07000000b00512fabd8075mr3636661lfg.48.1711348884375; Sun, 24 Mar 2024 23:41:24 -0700 (PDT) Received: from localhost.localdomain ([178.70.43.28]) by smtp.gmail.com with ESMTPSA id h12-20020a0565123c8c00b00515a411fd20sm828229lfv.105.2024.03.24.23.41.23 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 24 Mar 2024 23:41:23 -0700 (PDT) From: Ivan Bornyakov To: Nas Chung , Jackson Lee , Mauro Carvalho Chehab , Philipp Zabel Cc: Ivan Bornyakov , linux-media@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH v2 3/5] media: chips-media: wave5: separate irq setup routine Date: Mon, 25 Mar 2024 09:40:58 +0300 Message-ID: <20240325064102.9278-4-brnkv.i1@gmail.com> X-Mailer: git-send-email 2.44.0 In-Reply-To: <20240325064102.9278-1-brnkv.i1@gmail.com> References: <20240325064102.9278-1-brnkv.i1@gmail.com> Precedence: bulk X-Mailing-List: linux-media@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Separate interrupts setup routine to reduce code duplication. Also enable interrupts based on vpu_attr->support_encoders and vpu_attr->support_decoders fields to facilitate other Wave5xx IPs support, because not all of them are both encoders and decoders. Signed-off-by: Ivan Bornyakov --- .../platform/chips-media/wave5/wave5-hw.c | 53 +++++++++---------- 1 file changed, 24 insertions(+), 29 deletions(-) diff --git a/drivers/media/platform/chips-media/wave5/wave5-hw.c b/drivers/media/platform/chips-media/wave5/wave5-hw.c index 2d82791f575e..cdd0a0948a94 100644 --- a/drivers/media/platform/chips-media/wave5/wave5-hw.c +++ b/drivers/media/platform/chips-media/wave5/wave5-hw.c @@ -299,6 +299,27 @@ static int wave5_send_query(struct vpu_device *vpu_dev, struct vpu_instance *ins return wave5_vpu_firmware_command_queue_error_check(vpu_dev, NULL); } +static void setup_wave5_interrupts(struct vpu_device *vpu_dev) +{ + u32 reg_val = 0; + + if (vpu_dev->attr.support_encoders) { + /* Encoder interrupt */ + reg_val |= BIT(INT_WAVE5_ENC_SET_PARAM); + reg_val |= BIT(INT_WAVE5_ENC_PIC); + reg_val |= BIT(INT_WAVE5_BSBUF_FULL); + } + + if (vpu_dev->attr.support_decoders) { + /* Decoder interrupt */ + reg_val |= BIT(INT_WAVE5_INIT_SEQ); + reg_val |= BIT(INT_WAVE5_DEC_PIC); + reg_val |= BIT(INT_WAVE5_BSBUF_EMPTY); + } + + return vpu_write_reg(vpu_dev, W5_VPU_VINT_ENABLE, reg_val); +} + static int setup_wave5_properties(struct device *dev) { struct vpu_device *vpu_dev = dev_get_drvdata(dev); @@ -340,6 +361,8 @@ static int setup_wave5_properties(struct device *dev) p_attr->support_vcpu_backbone = FIELD_GET(FEATURE_VCPU_BACKBONE, hw_config_def0); p_attr->support_vcore_backbone = FIELD_GET(FEATURE_VCORE_BACKBONE, hw_config_def0); + setup_wave5_interrupts(vpu_dev); + return 0; } @@ -417,16 +440,6 @@ int wave5_vpu_init(struct device *dev, u8 *fw, size_t size) wave5_fio_writel(vpu_dev, W5_BACKBONE_AXI_PARAM, 0); vpu_write_reg(vpu_dev, W5_SEC_AXI_PARAM, 0); - /* Encoder interrupt */ - reg_val = BIT(INT_WAVE5_ENC_SET_PARAM); - reg_val |= BIT(INT_WAVE5_ENC_PIC); - reg_val |= BIT(INT_WAVE5_BSBUF_FULL); - /* Decoder interrupt */ - reg_val |= BIT(INT_WAVE5_INIT_SEQ); - reg_val |= BIT(INT_WAVE5_DEC_PIC); - reg_val |= BIT(INT_WAVE5_BSBUF_EMPTY); - vpu_write_reg(vpu_dev, W5_VPU_VINT_ENABLE, reg_val); - reg_val = vpu_read_reg(vpu_dev, W5_VPU_RET_VPU_CONFIG0); if (FIELD_GET(FEATURE_BACKBONE, reg_val)) { reg_val = ((WAVE5_PROC_AXI_ID << 28) | @@ -1034,16 +1047,6 @@ int wave5_vpu_re_init(struct device *dev, u8 *fw, size_t size) wave5_fio_writel(vpu_dev, W5_BACKBONE_AXI_PARAM, 0); vpu_write_reg(vpu_dev, W5_SEC_AXI_PARAM, 0); - /* Encoder interrupt */ - reg_val = BIT(INT_WAVE5_ENC_SET_PARAM); - reg_val |= BIT(INT_WAVE5_ENC_PIC); - reg_val |= BIT(INT_WAVE5_BSBUF_FULL); - /* Decoder interrupt */ - reg_val |= BIT(INT_WAVE5_INIT_SEQ); - reg_val |= BIT(INT_WAVE5_DEC_PIC); - reg_val |= BIT(INT_WAVE5_BSBUF_EMPTY); - vpu_write_reg(vpu_dev, W5_VPU_VINT_ENABLE, reg_val); - reg_val = vpu_read_reg(vpu_dev, W5_VPU_RET_VPU_CONFIG0); if (FIELD_GET(FEATURE_BACKBONE, reg_val)) { reg_val = ((WAVE5_PROC_AXI_ID << 28) | @@ -1134,15 +1137,7 @@ static int wave5_vpu_sleep_wake(struct device *dev, bool i_sleep_wake, const uin wave5_fio_writel(vpu_dev, W5_BACKBONE_AXI_PARAM, 0); vpu_write_reg(vpu_dev, W5_SEC_AXI_PARAM, 0); - /* Encoder interrupt */ - reg_val = BIT(INT_WAVE5_ENC_SET_PARAM); - reg_val |= BIT(INT_WAVE5_ENC_PIC); - reg_val |= BIT(INT_WAVE5_BSBUF_FULL); - /* Decoder interrupt */ - reg_val |= BIT(INT_WAVE5_INIT_SEQ); - reg_val |= BIT(INT_WAVE5_DEC_PIC); - reg_val |= BIT(INT_WAVE5_BSBUF_EMPTY); - vpu_write_reg(vpu_dev, W5_VPU_VINT_ENABLE, reg_val); + setup_wave5_interrupts(vpu_dev); reg_val = vpu_read_reg(vpu_dev, W5_VPU_RET_VPU_CONFIG0); if (FIELD_GET(FEATURE_BACKBONE, reg_val)) { From patchwork Mon Mar 25 06:40:59 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Ivan Bornyakov X-Patchwork-Id: 13601667 Received: from mail-lf1-f49.google.com (mail-lf1-f49.google.com [209.85.167.49]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id BECA415F3F3; Mon, 25 Mar 2024 06:41:27 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.167.49 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1711348889; cv=none; b=Vo5qMXrOAGg08cfxhDEaM7tImZ1ZRj1P5e7hz5fcWapZanQjoi3a8MPXTzOh8uYMNAb0nDauDe6urw/yRySRAxKseYBkO7AE2OyguslBNcNx6q55z8u61suf3MbvYAkIS4Sm35Wf1cEUBKyjCDWtur8KQJmRkX3Bdip326kop2E= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1711348889; c=relaxed/simple; bh=WCUsd9wRlKcgYIo1YAVt/aabTPpoE7JMRDqoJPTiBMI=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=arlaQA9Y8JEp46gL7G+56x/yYusd6mOHec/BiDNRD29hdr7/ANvcxTt/tcwXPiJDvkcC+WhJmvS9hxhEs+yTg+kU7fre5F2x8Y14AyAJLIgSTOkpS06F2b/tN8GIM68bSl8281nAcY/wVm9Xx2TkTob7z6p/I8ygAYFclCiV1MU= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=gmail.com; spf=pass smtp.mailfrom=gmail.com; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b=UkF35Z8g; arc=none smtp.client-ip=209.85.167.49 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=gmail.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=gmail.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b="UkF35Z8g" Received: by mail-lf1-f49.google.com with SMTP id 2adb3069b0e04-515a86daf09so1282863e87.3; Sun, 24 Mar 2024 23:41:27 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20230601; t=1711348886; x=1711953686; darn=vger.kernel.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=USH6Nfz0NCBGWMX/IQB4cQ8iG0IHQkGBXucHa0AClMU=; b=UkF35Z8gDFuDpTRGIVaeNX/S2WTkhPMBKP8+pQBselwSGQJg9hgOWoEqk8R7V9Sgk/ 8xmZ0iZn1I+J902tv96qGIWOtv9PDBUFie4OBrYz+86DxaPx2559rpKhX95jbLbziiFl jrhH0qC/HzAVYOgeCqHLL1dnWBEOseQfRxkiif39EkFlM+HkWpkfKb3CUN1mizqVFaR2 jXDiVFrE+n95WqOE/4IvogqnoDwWNfqfZ0xPnH3XxPORNE/GLimYu7NdWuCPVPnVhMnN Dw03wiaWwubqTV3q4FaHUdrMdElFA8sOS5iTs5UfyDda/VD1C6T+C6sncRRmj5w6zAIq byCQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1711348886; x=1711953686; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=USH6Nfz0NCBGWMX/IQB4cQ8iG0IHQkGBXucHa0AClMU=; b=s4rZeNehlXztKJRL4t3DPPcHHeiXDBlec2bpqRlSk8I92pv+jg5+3zNeidzGHvNf6e B/ehCCIwzr95r5h+vzXNgS9g4drIXaW1hal9+CE5AyIX7SJbmaFf5IuOremJaU0Jf9Sr zh7h8/cOQmv9ondPNQ210n2I/71Viu+rXDmBwc/enQrt8R5bn2/ikemWO87tUeKtQUV4 cCEH22VTWH8zsKI9XxgzCGqliHHqeXM4PDfUk7q9Bztf7DEUn/Op2VmSb11zi25ulB2a HarKdQ8p/xCFUDLCNdwW4wUj0wev68pVvCAKutCt4famQ83dv4zmvqsktdHbrTWEML9G ULOQ== X-Forwarded-Encrypted: i=1; AJvYcCUcuhIkqH3ZZHUQCeSBNX7KJqzhOLPUDLE6XvyE8sfvtnrZj5faVdjsnQzH5MzqWuTUNpXja7Vi5e6GTceazwlCUQ8iyfbonkgizLU3j5OF3khvO1uaF9Y8Tn+FKtdFVjNJo/tofARcv5Y= X-Gm-Message-State: AOJu0YzA+W9rAeGn2jk002aNr+Zq3wT76I/tIVCz6p0sW8z4mwlBvIZ+ 3kg2FYOJ0s5h6eqhoEJfWmbSdi98Iuwdspx9STyT4X591+2Bx+VQ X-Google-Smtp-Source: AGHT+IGXGxkFkZFLm6+hr+Mw1cisKEtfNT6CUbf967HH0uF75IKvYnDI9/+81I8CyPM/Kh9fsojA9g== X-Received: by 2002:a05:6512:1c7:b0:513:5c10:309c with SMTP id f7-20020a05651201c700b005135c10309cmr4522562lfp.3.1711348885777; Sun, 24 Mar 2024 23:41:25 -0700 (PDT) Received: from localhost.localdomain ([178.70.43.28]) by smtp.gmail.com with ESMTPSA id h12-20020a0565123c8c00b00515a411fd20sm828229lfv.105.2024.03.24.23.41.25 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 24 Mar 2024 23:41:25 -0700 (PDT) From: Ivan Bornyakov To: Nas Chung , Jackson Lee , Mauro Carvalho Chehab , Philipp Zabel Cc: Ivan Bornyakov , linux-media@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH v2 4/5] media: chips-media: wave5: drop "sram-size" DT prop Date: Mon, 25 Mar 2024 09:40:59 +0300 Message-ID: <20240325064102.9278-5-brnkv.i1@gmail.com> X-Mailer: git-send-email 2.44.0 In-Reply-To: <20240325064102.9278-1-brnkv.i1@gmail.com> References: <20240325064102.9278-1-brnkv.i1@gmail.com> Precedence: bulk X-Mailing-List: linux-media@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Use all available SRAM memory up to WAVE5_MAX_SRAM_SIZE. Remove excessive "sram-size" device-tree property as genalloc is already able to determine available memory. Signed-off-by: Ivan Bornyakov --- .../platform/chips-media/wave5/wave5-vdi.c | 21 ++++++++++--------- .../platform/chips-media/wave5/wave5-vpu.c | 7 ------- .../platform/chips-media/wave5/wave5-vpuapi.h | 1 - .../chips-media/wave5/wave5-vpuconfig.h | 2 ++ 4 files changed, 13 insertions(+), 18 deletions(-) diff --git a/drivers/media/platform/chips-media/wave5/wave5-vdi.c b/drivers/media/platform/chips-media/wave5/wave5-vdi.c index 3809f70bc0b4..a63fffed55e9 100644 --- a/drivers/media/platform/chips-media/wave5/wave5-vdi.c +++ b/drivers/media/platform/chips-media/wave5/wave5-vdi.c @@ -174,16 +174,19 @@ int wave5_vdi_allocate_array(struct vpu_device *vpu_dev, struct vpu_buf *array, void wave5_vdi_allocate_sram(struct vpu_device *vpu_dev) { struct vpu_buf *vb = &vpu_dev->sram_buf; + dma_addr_t daddr; + void *vaddr; + size_t size; - if (!vpu_dev->sram_pool || !vpu_dev->sram_size) + if (!vpu_dev->sram_pool || vb->vaddr) return; - if (!vb->vaddr) { - vb->size = vpu_dev->sram_size; - vb->vaddr = gen_pool_dma_alloc(vpu_dev->sram_pool, vb->size, - &vb->daddr); - if (!vb->vaddr) - vb->size = 0; + size = min_t(size_t, WAVE5_MAX_SRAM_SIZE, gen_pool_avail(vpu_dev->sram_pool)); + vaddr = gen_pool_dma_alloc(vpu_dev->sram_pool, size, &daddr); + if (vaddr) { + vb->vaddr = vaddr; + vb->daddr = daddr; + vb->size = size; } dev_dbg(vpu_dev->dev, "%s: sram daddr: %pad, size: %zu, vaddr: 0x%p\n", @@ -197,9 +200,7 @@ void wave5_vdi_free_sram(struct vpu_device *vpu_dev) if (!vb->size || !vb->vaddr) return; - if (vb->vaddr) - gen_pool_free(vpu_dev->sram_pool, (unsigned long)vb->vaddr, - vb->size); + gen_pool_free(vpu_dev->sram_pool, (unsigned long)vb->vaddr, vb->size); memset(vb, 0, sizeof(*vb)); } diff --git a/drivers/media/platform/chips-media/wave5/wave5-vpu.c b/drivers/media/platform/chips-media/wave5/wave5-vpu.c index 1e631da58e15..2a972cddf4a6 100644 --- a/drivers/media/platform/chips-media/wave5/wave5-vpu.c +++ b/drivers/media/platform/chips-media/wave5/wave5-vpu.c @@ -177,13 +177,6 @@ static int wave5_vpu_probe(struct platform_device *pdev) goto err_reset_assert; } - ret = of_property_read_u32(pdev->dev.of_node, "sram-size", - &dev->sram_size); - if (ret) { - dev_warn(&pdev->dev, "sram-size not found\n"); - dev->sram_size = 0; - } - dev->sram_pool = of_gen_pool_get(pdev->dev.of_node, "sram", 0); if (!dev->sram_pool) dev_warn(&pdev->dev, "sram node not found\n"); diff --git a/drivers/media/platform/chips-media/wave5/wave5-vpuapi.h b/drivers/media/platform/chips-media/wave5/wave5-vpuapi.h index da530fd98964..975d96b22191 100644 --- a/drivers/media/platform/chips-media/wave5/wave5-vpuapi.h +++ b/drivers/media/platform/chips-media/wave5/wave5-vpuapi.h @@ -750,7 +750,6 @@ struct vpu_device { struct vpu_attr attr; struct vpu_buf common_mem; u32 last_performance_cycles; - u32 sram_size; struct gen_pool *sram_pool; struct vpu_buf sram_buf; void __iomem *vdb_register; diff --git a/drivers/media/platform/chips-media/wave5/wave5-vpuconfig.h b/drivers/media/platform/chips-media/wave5/wave5-vpuconfig.h index d9751eedb0f9..9d99afb78c89 100644 --- a/drivers/media/platform/chips-media/wave5/wave5-vpuconfig.h +++ b/drivers/media/platform/chips-media/wave5/wave5-vpuconfig.h @@ -28,6 +28,8 @@ #define WAVE521ENC_WORKBUF_SIZE (128 * 1024) //HEVC 128K, AVC 40K #define WAVE521DEC_WORKBUF_SIZE (1784 * 1024) +#define WAVE5_MAX_SRAM_SIZE (64 * 1024) + #define MAX_NUM_INSTANCE 32 #define W5_MIN_ENC_PIC_WIDTH 256 From patchwork Mon Mar 25 06:41:00 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Ivan Bornyakov X-Patchwork-Id: 13601668 Received: from mail-lf1-f50.google.com (mail-lf1-f50.google.com [209.85.167.50]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 97DEB15F3E9; Mon, 25 Mar 2024 06:41:29 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.167.50 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1711348892; cv=none; b=Nb4WhNlgBr8BV+rCkkUinY7jcuAAbPAoU/xFXMfF7yTrmDdW/Ec+aKtGHcgvWMij5o12WUw5dWbUm5UfIn0Hd71W/aq/dDIfJfpI5yENrO7hqNSDT3VcPGud/IRyrKLM3oPwP5/gHn8MLl7I00FZK7mtgNjuADCLy5yoQNK7WC0= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1711348892; c=relaxed/simple; bh=OU0tIm9dlpe4iwlvPb4X4be/AMKQdMK/VPbN3eK/RWI=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=NvjDZTUOr9qz8Q0nDDR7KCjL2OLwQ6wTA+6Yil4Z1RzeKCBjxOHYzOtRFEfwtnDbXdE9Vdl6Q9rBlmBa9ouOUlq8FPV6uEiLvuDjQosCqdBWHB9fOD9HRAG4oC5UjY4e0bNN+FHDtL15LzVFkyvFpzH0sDO7ST95y2ty+pMNLYk= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=gmail.com; spf=pass smtp.mailfrom=gmail.com; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b=CtlpAQel; arc=none smtp.client-ip=209.85.167.50 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=gmail.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=gmail.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b="CtlpAQel" Received: by mail-lf1-f50.google.com with SMTP id 2adb3069b0e04-5157af37806so4684953e87.0; Sun, 24 Mar 2024 23:41:29 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20230601; t=1711348888; x=1711953688; darn=vger.kernel.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=DALG5MAaAsL2QRefNz5eLRRNCRNGGHL2QfxPXVFHLeU=; b=CtlpAQel47fHFluPTuOUO777ePvX891+6pdhxOxE/cpVy8V5fR8pxhTb4efDx73vxA L1MHb08LHu94D/TjR+wPeAetVdWiAyAgq2txvoksXoi15qUGST+blWvaLYspWlnucA6E mnb9XOygHo/0MqIOdevCw+QxtNRFinGKdR0uKtJI+pOW5INR5tu5nzOd9nxa7aeyWRpJ kZUaHt7noayfbK/sy8eASy8+JnLTldlmQbWliickjCFp51AeIBFoNBgOCcqCmRKAsTRH im9swcjpwUx9ypf6dIpTbSDyPGzsYquZ65CiEyq64WDYSAeNXCmREuaWBM8C0AMhJJmI caUA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1711348888; x=1711953688; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=DALG5MAaAsL2QRefNz5eLRRNCRNGGHL2QfxPXVFHLeU=; b=KuFbvn7V8XxHafamZC0Gomhfr3HE739mu9BLHZxLU25pYLeTfYy1JX+MWjhM+cRugD IbmAVW38PBSQ2qsUQ63dwZNo/IOx/izM9guUWOjS1XAi7f5cFcOR2PqMw7jR7Rplie0X 0I7638z84YZIhYhRB9P6lM89EF01Sl9vFnjZR8NsSUVhy9vogbdSzxjcjERxUhIVdJ5j z6lzuIidqL+Hz4fTOAa87KuPxvHYE/dFJ5qiv6iOtWYu9G4wTOXZ4YhBgQusLCu6aMA4 GuuxiHgBnzuV3TQh/wt6StuifsWjcCG8znqfctjAm/5l1zkpRiyrpXX0zbtBn9pP5yCp CTfQ== X-Forwarded-Encrypted: i=1; AJvYcCXYbk9XL1GP6QFzjKAkLn+7W9/Brroo5OkCC2xBQYNKFHczA3cbsoMtL+2AwCEtB8AtuEkTZuldQArziShC8JCbxo6IIK7CcPA9q+Jn9YTGfKNMyXN9uWEdo2O57qkHusD9PYmkVjRz1P4= X-Gm-Message-State: AOJu0YzmvczmwKdnv3bM00kS9DTLyOZd5Ous6oCxd3aDHnGWTxg19ZWv vEPbNsnBPlHwpn5AJQwebTisDEeIoExJi2M+A8nG93H62Ruwb+to X-Google-Smtp-Source: AGHT+IEzwMUNiMPHZezXfTughyeG7hA2SQ2Blx3nDWbRNKTb2AvZPTdZ/TQwfV1DhVP3uw7lszJ0Jg== X-Received: by 2002:a05:6512:3119:b0:513:cebb:cf19 with SMTP id n25-20020a056512311900b00513cebbcf19mr3944836lfb.53.1711348887491; Sun, 24 Mar 2024 23:41:27 -0700 (PDT) Received: from localhost.localdomain ([178.70.43.28]) by smtp.gmail.com with ESMTPSA id h12-20020a0565123c8c00b00515a411fd20sm828229lfv.105.2024.03.24.23.41.26 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 24 Mar 2024 23:41:27 -0700 (PDT) From: Ivan Bornyakov To: Nas Chung , Jackson Lee , Mauro Carvalho Chehab , Philipp Zabel Cc: Ivan Bornyakov , linux-media@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH v2 5/5] media: chips-media: wave5: support Wave515 decoder Date: Mon, 25 Mar 2024 09:41:00 +0300 Message-ID: <20240325064102.9278-6-brnkv.i1@gmail.com> X-Mailer: git-send-email 2.44.0 In-Reply-To: <20240325064102.9278-1-brnkv.i1@gmail.com> References: <20240325064102.9278-1-brnkv.i1@gmail.com> Precedence: bulk X-Mailing-List: linux-media@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Add initial support for Wave515 multi-decoder IP. For now it is only able to decode HEVC Main/Main10 profile videos. This was tested on FPGA prototype, so wave5_dt_ids[] was not expanded. Users of the real hardware with Wave515 IP will have to * provide firmware specific to their SoC * add struct wave5_match_data like this: static const struct wave5_match_data platform_name_wave515_data = { .flags = WAVE5_IS_DEC, .fw_name = "cnm/wave515_platform_name_fw.bin", }; * add item to wave5_dt_ids[] like this: { .compatible = "vendor,soc-wave515", .data = &platform_name_wave515_data, }, * describe new compatible in Documentation/devicetree/bindings/media/cnm,wave521c.yaml Signed-off-by: Ivan Bornyakov --- .../platform/chips-media/wave5/wave5-helper.c | 3 +- .../platform/chips-media/wave5/wave5-hw.c | 245 ++++++++++++++---- .../chips-media/wave5/wave5-regdefine.h | 5 + .../platform/chips-media/wave5/wave5-vdi.c | 6 +- .../chips-media/wave5/wave5-vpu-dec.c | 14 +- .../platform/chips-media/wave5/wave5-vpu.c | 8 +- .../platform/chips-media/wave5/wave5-vpuapi.h | 1 + .../chips-media/wave5/wave5-vpuconfig.h | 9 +- .../media/platform/chips-media/wave5/wave5.h | 1 + 9 files changed, 233 insertions(+), 59 deletions(-) diff --git a/drivers/media/platform/chips-media/wave5/wave5-helper.c b/drivers/media/platform/chips-media/wave5/wave5-helper.c index 8433ecab230c..c68f1e110ed9 100644 --- a/drivers/media/platform/chips-media/wave5/wave5-helper.c +++ b/drivers/media/platform/chips-media/wave5/wave5-helper.c @@ -29,7 +29,8 @@ void wave5_cleanup_instance(struct vpu_instance *inst) { int i; - if (list_is_singular(&inst->list)) + if (list_is_singular(&inst->list) && + inst->dev->product_code != WAVE515_CODE) wave5_vdi_free_sram(inst->dev); for (i = 0; i < inst->fbc_buf_count; i++) diff --git a/drivers/media/platform/chips-media/wave5/wave5-hw.c b/drivers/media/platform/chips-media/wave5/wave5-hw.c index cdd0a0948a94..e38995de6870 100644 --- a/drivers/media/platform/chips-media/wave5/wave5-hw.c +++ b/drivers/media/platform/chips-media/wave5/wave5-hw.c @@ -24,8 +24,10 @@ #define FEATURE_HEVC_ENCODER BIT(0) /* Decoder support fields */ +#define W515_FEATURE_HEVC10BIT_DEC BIT(1) #define FEATURE_AVC_DECODER BIT(3) #define FEATURE_HEVC_DECODER BIT(2) +#define W515_FEATURE_HEVC_DECODER BIT(0) #define FEATURE_BACKBONE BIT(16) #define FEATURE_VCORE_BACKBONE BIT(22) @@ -155,6 +157,8 @@ static int wave5_wait_bus_busy(struct vpu_device *vpu_dev, unsigned int addr) { u32 gdi_status_check_value = 0x3f; + if (vpu_dev->product_code == WAVE515_CODE) + gdi_status_check_value = 0x0738; if (vpu_dev->product_code == WAVE521C_CODE || vpu_dev->product_code == WAVE521_CODE || vpu_dev->product_code == WAVE521E1_CODE) @@ -186,6 +190,8 @@ unsigned int wave5_vpu_get_product_id(struct vpu_device *vpu_dev) u32 val = vpu_read_reg(vpu_dev, W5_PRODUCT_NUMBER); switch (val) { + case WAVE515_CODE: + return PRODUCT_ID_515; case WAVE521C_CODE: return PRODUCT_ID_521; case WAVE521_CODE: @@ -349,17 +355,33 @@ static int setup_wave5_properties(struct device *dev) hw_config_def1 = vpu_read_reg(vpu_dev, W5_RET_STD_DEF1); hw_config_feature = vpu_read_reg(vpu_dev, W5_RET_CONF_FEATURE); - p_attr->support_hevc10bit_enc = FIELD_GET(FEATURE_HEVC10BIT_ENC, hw_config_feature); - p_attr->support_avc10bit_enc = FIELD_GET(FEATURE_AVC10BIT_ENC, hw_config_feature); - - p_attr->support_decoders = FIELD_GET(FEATURE_AVC_DECODER, hw_config_def1) << STD_AVC; - p_attr->support_decoders |= FIELD_GET(FEATURE_HEVC_DECODER, hw_config_def1) << STD_HEVC; - p_attr->support_encoders = FIELD_GET(FEATURE_AVC_ENCODER, hw_config_def1) << STD_AVC; - p_attr->support_encoders |= FIELD_GET(FEATURE_HEVC_ENCODER, hw_config_def1) << STD_HEVC; - - p_attr->support_backbone = FIELD_GET(FEATURE_BACKBONE, hw_config_def0); - p_attr->support_vcpu_backbone = FIELD_GET(FEATURE_VCPU_BACKBONE, hw_config_def0); - p_attr->support_vcore_backbone = FIELD_GET(FEATURE_VCORE_BACKBONE, hw_config_def0); + if (vpu_dev->product_code == WAVE515_CODE) { + p_attr->support_hevc10bit_dec = FIELD_GET(W515_FEATURE_HEVC10BIT_DEC, + hw_config_feature); + p_attr->support_decoders = FIELD_GET(W515_FEATURE_HEVC_DECODER, + hw_config_def1) << STD_HEVC; + } else { + p_attr->support_hevc10bit_enc = FIELD_GET(FEATURE_HEVC10BIT_ENC, + hw_config_feature); + p_attr->support_avc10bit_enc = FIELD_GET(FEATURE_AVC10BIT_ENC, + hw_config_feature); + + p_attr->support_decoders = FIELD_GET(FEATURE_AVC_DECODER, + hw_config_def1) << STD_AVC; + p_attr->support_decoders |= FIELD_GET(FEATURE_HEVC_DECODER, + hw_config_def1) << STD_HEVC; + p_attr->support_encoders = FIELD_GET(FEATURE_AVC_ENCODER, + hw_config_def1) << STD_AVC; + p_attr->support_encoders |= FIELD_GET(FEATURE_HEVC_ENCODER, + hw_config_def1) << STD_HEVC; + + p_attr->support_backbone = FIELD_GET(FEATURE_BACKBONE, + hw_config_def0); + p_attr->support_vcpu_backbone = FIELD_GET(FEATURE_VCPU_BACKBONE, + hw_config_def0); + p_attr->support_vcore_backbone = FIELD_GET(FEATURE_VCORE_BACKBONE, + hw_config_def0); + } setup_wave5_interrupts(vpu_dev); @@ -403,12 +425,18 @@ int wave5_vpu_init(struct device *dev, u8 *fw, size_t size) common_vb = &vpu_dev->common_mem; code_base = common_vb->daddr; + + if (vpu_dev->product_code == WAVE515_CODE) + code_size = WAVE515_MAX_CODE_BUF_SIZE; + else + code_size = WAVE5_MAX_CODE_BUF_SIZE; + /* ALIGN TO 4KB */ - code_size = (WAVE5_MAX_CODE_BUF_SIZE & ~0xfff); + code_size &= ~0xfff; if (code_size < size * 2) return -EINVAL; - temp_base = common_vb->daddr + WAVE5_TEMPBUF_OFFSET; + temp_base = code_base + code_size; temp_size = WAVE5_TEMPBUF_SIZE; ret = wave5_vdi_write_memory(vpu_dev, common_vb, 0, fw, size); @@ -436,9 +464,12 @@ int wave5_vpu_init(struct device *dev, u8 *fw, size_t size) /* These register must be reset explicitly */ vpu_write_reg(vpu_dev, W5_HW_OPTION, 0); - wave5_fio_writel(vpu_dev, W5_BACKBONE_PROC_EXT_ADDR, 0); - wave5_fio_writel(vpu_dev, W5_BACKBONE_AXI_PARAM, 0); - vpu_write_reg(vpu_dev, W5_SEC_AXI_PARAM, 0); + + if (vpu_dev->product_code != WAVE515_CODE) { + wave5_fio_writel(vpu_dev, W5_BACKBONE_PROC_EXT_ADDR, 0); + wave5_fio_writel(vpu_dev, W5_BACKBONE_AXI_PARAM, 0); + vpu_write_reg(vpu_dev, W5_SEC_AXI_PARAM, 0); + } reg_val = vpu_read_reg(vpu_dev, W5_VPU_RET_VPU_CONFIG0); if (FIELD_GET(FEATURE_BACKBONE, reg_val)) { @@ -453,6 +484,24 @@ int wave5_vpu_init(struct device *dev, u8 *fw, size_t size) wave5_fio_writel(vpu_dev, W5_BACKBONE_PROG_AXI_ID, reg_val); } + if (vpu_dev->product_code == WAVE515_CODE) { + dma_addr_t task_buf_base; + + vpu_write_reg(vpu_dev, W5_CMD_INIT_NUM_TASK_BUF, WAVE515_COMMAND_QUEUE_DEPTH); + vpu_write_reg(vpu_dev, W5_CMD_INIT_TASK_BUF_SIZE, WAVE515_ONE_TASKBUF_SIZE); + + for (i = 0; i < WAVE515_COMMAND_QUEUE_DEPTH; i++) { + task_buf_base = temp_base + temp_size + + (i * WAVE515_ONE_TASKBUF_SIZE); + vpu_write_reg(vpu_dev, + W5_CMD_INIT_ADDR_TASK_BUF0 + (i * 4), + task_buf_base); + } + + vpu_write_reg(vpu_dev, W515_CMD_ADDR_SEC_AXI, vpu_dev->sram_buf.daddr); + vpu_write_reg(vpu_dev, W515_CMD_SEC_AXI_SIZE, vpu_dev->sram_buf.size); + } + vpu_write_reg(vpu_dev, W5_VPU_BUSY_STATUS, 1); vpu_write_reg(vpu_dev, W5_COMMAND, W5_INIT_VPU); vpu_write_reg(vpu_dev, W5_VPU_REMAP_CORE_START, 1); @@ -493,29 +542,39 @@ int wave5_vpu_build_up_dec_param(struct vpu_instance *inst, return -EINVAL; } - p_dec_info->vb_work.size = WAVE521DEC_WORKBUF_SIZE; + if (vpu_dev->product == PRODUCT_ID_515) + p_dec_info->vb_work.size = WAVE515DEC_WORKBUF_SIZE; + else + p_dec_info->vb_work.size = WAVE521DEC_WORKBUF_SIZE; + ret = wave5_vdi_allocate_dma_memory(inst->dev, &p_dec_info->vb_work); if (ret) return ret; - vpu_write_reg(inst->dev, W5_CMD_DEC_VCORE_INFO, 1); + if (inst->dev->product_code != WAVE515_CODE) + vpu_write_reg(inst->dev, W5_CMD_DEC_VCORE_INFO, 1); wave5_vdi_clear_memory(inst->dev, &p_dec_info->vb_work); vpu_write_reg(inst->dev, W5_ADDR_WORK_BASE, p_dec_info->vb_work.daddr); vpu_write_reg(inst->dev, W5_WORK_SIZE, p_dec_info->vb_work.size); - vpu_write_reg(inst->dev, W5_CMD_ADDR_SEC_AXI, vpu_dev->sram_buf.daddr); - vpu_write_reg(inst->dev, W5_CMD_SEC_AXI_SIZE, vpu_dev->sram_buf.size); + if (inst->dev->product_code != WAVE515_CODE) { + vpu_write_reg(inst->dev, W5_CMD_ADDR_SEC_AXI, vpu_dev->sram_buf.daddr); + vpu_write_reg(inst->dev, W5_CMD_SEC_AXI_SIZE, vpu_dev->sram_buf.size); + } vpu_write_reg(inst->dev, W5_CMD_DEC_BS_START_ADDR, p_dec_info->stream_buf_start_addr); vpu_write_reg(inst->dev, W5_CMD_DEC_BS_SIZE, p_dec_info->stream_buf_size); /* NOTE: SDMA reads MSB first */ vpu_write_reg(inst->dev, W5_CMD_BS_PARAM, BITSTREAM_ENDIANNESS_BIG_ENDIAN); - /* This register must be reset explicitly */ - vpu_write_reg(inst->dev, W5_CMD_EXT_ADDR, 0); - vpu_write_reg(inst->dev, W5_CMD_NUM_CQ_DEPTH_M1, (COMMAND_QUEUE_DEPTH - 1)); + + if (inst->dev->product_code != WAVE515_CODE) { + /* This register must be reset explicitly */ + vpu_write_reg(inst->dev, W5_CMD_EXT_ADDR, 0); + vpu_write_reg(inst->dev, W5_CMD_NUM_CQ_DEPTH_M1, (COMMAND_QUEUE_DEPTH - 1)); + } ret = send_firmware_command(inst, W5_CREATE_INSTANCE, true, NULL, NULL); if (ret) { @@ -566,7 +625,7 @@ static u32 get_bitstream_options(struct dec_info *info) int wave5_vpu_dec_init_seq(struct vpu_instance *inst) { struct dec_info *p_dec_info = &inst->codec_info->dec_info; - u32 cmd_option = INIT_SEQ_NORMAL; + u32 bs_option, cmd_option = INIT_SEQ_NORMAL; u32 reg_val, fail_res; int ret; @@ -576,7 +635,12 @@ int wave5_vpu_dec_init_seq(struct vpu_instance *inst) vpu_write_reg(inst->dev, W5_BS_RD_PTR, p_dec_info->stream_rd_ptr); vpu_write_reg(inst->dev, W5_BS_WR_PTR, p_dec_info->stream_wr_ptr); - vpu_write_reg(inst->dev, W5_BS_OPTION, get_bitstream_options(p_dec_info)); + bs_option = get_bitstream_options(p_dec_info); + + if (inst->dev->product_code == WAVE515_CODE) + bs_option |= BSOPTION_RD_PTR_VALID_FLAG; + + vpu_write_reg(inst->dev, W5_BS_OPTION, bs_option); vpu_write_reg(inst->dev, W5_COMMAND_OPTION, cmd_option); vpu_write_reg(inst->dev, W5_CMD_DEC_USER_MASK, p_dec_info->user_data_enable); @@ -642,10 +706,12 @@ static void wave5_get_dec_seq_result(struct vpu_instance *inst, struct dec_initi info->profile = FIELD_GET(SEQ_PARAM_PROFILE_MASK, reg_val); } - info->vlc_buf_size = vpu_read_reg(inst->dev, W5_RET_VLC_BUF_SIZE); - info->param_buf_size = vpu_read_reg(inst->dev, W5_RET_PARAM_BUF_SIZE); - p_dec_info->vlc_buf_size = info->vlc_buf_size; - p_dec_info->param_buf_size = info->param_buf_size; + if (inst->dev->product_code != WAVE515_CODE) { + info->vlc_buf_size = vpu_read_reg(inst->dev, W5_RET_VLC_BUF_SIZE); + info->param_buf_size = vpu_read_reg(inst->dev, W5_RET_PARAM_BUF_SIZE); + p_dec_info->vlc_buf_size = info->vlc_buf_size; + p_dec_info->param_buf_size = info->param_buf_size; + } } int wave5_vpu_dec_get_seq_info(struct vpu_instance *inst, struct dec_initial_info *info) @@ -747,22 +813,27 @@ int wave5_vpu_dec_register_framebuffer(struct vpu_instance *inst, struct frame_b pic_size = (init_info->pic_width << 16) | (init_info->pic_height); - vb_buf.size = (p_dec_info->vlc_buf_size * VLC_BUF_NUM) + + if (inst->dev->product_code != WAVE515_CODE) { + vb_buf.size = (p_dec_info->vlc_buf_size * VLC_BUF_NUM) + (p_dec_info->param_buf_size * COMMAND_QUEUE_DEPTH); - vb_buf.daddr = 0; + vb_buf.daddr = 0; - if (vb_buf.size != p_dec_info->vb_task.size) { - wave5_vdi_free_dma_memory(inst->dev, &p_dec_info->vb_task); - ret = wave5_vdi_allocate_dma_memory(inst->dev, &vb_buf); - if (ret) - goto free_fbc_c_tbl_buffers; + if (vb_buf.size != p_dec_info->vb_task.size) { + wave5_vdi_free_dma_memory(inst->dev, + &p_dec_info->vb_task); + ret = wave5_vdi_allocate_dma_memory(inst->dev, + &vb_buf); + if (ret) + goto free_fbc_c_tbl_buffers; - p_dec_info->vb_task = vb_buf; - } + p_dec_info->vb_task = vb_buf; + } - vpu_write_reg(inst->dev, W5_CMD_SET_FB_ADDR_TASK_BUF, - p_dec_info->vb_task.daddr); - vpu_write_reg(inst->dev, W5_CMD_SET_FB_TASK_BUF_SIZE, vb_buf.size); + vpu_write_reg(inst->dev, W5_CMD_SET_FB_ADDR_TASK_BUF, + p_dec_info->vb_task.daddr); + vpu_write_reg(inst->dev, W5_CMD_SET_FB_TASK_BUF_SIZE, + vb_buf.size); + } } else { pic_size = (init_info->pic_width << 16) | (init_info->pic_height); @@ -999,17 +1070,24 @@ int wave5_vpu_re_init(struct device *dev, u8 *fw, size_t size) dma_addr_t code_base, temp_base; dma_addr_t old_code_base, temp_size; u32 code_size, reason_code; - u32 reg_val; + u32 i, reg_val; struct vpu_device *vpu_dev = dev_get_drvdata(dev); common_vb = &vpu_dev->common_mem; code_base = common_vb->daddr; + + if (vpu_dev->product_code == WAVE515_CODE) + code_size = WAVE515_MAX_CODE_BUF_SIZE; + else + code_size = WAVE5_MAX_CODE_BUF_SIZE; + /* ALIGN TO 4KB */ - code_size = (WAVE5_MAX_CODE_BUF_SIZE & ~0xfff); + code_size &= ~0xfff; if (code_size < size * 2) return -EINVAL; - temp_base = common_vb->daddr + WAVE5_TEMPBUF_OFFSET; + + temp_base = code_base + code_size; temp_size = WAVE5_TEMPBUF_SIZE; old_code_base = vpu_read_reg(vpu_dev, W5_VPU_REMAP_PADDR); @@ -1043,9 +1121,12 @@ int wave5_vpu_re_init(struct device *dev, u8 *fw, size_t size) /* These register must be reset explicitly */ vpu_write_reg(vpu_dev, W5_HW_OPTION, 0); - wave5_fio_writel(vpu_dev, W5_BACKBONE_PROC_EXT_ADDR, 0); - wave5_fio_writel(vpu_dev, W5_BACKBONE_AXI_PARAM, 0); - vpu_write_reg(vpu_dev, W5_SEC_AXI_PARAM, 0); + + if (vpu_dev->product_code != WAVE515_CODE) { + wave5_fio_writel(vpu_dev, W5_BACKBONE_PROC_EXT_ADDR, 0); + wave5_fio_writel(vpu_dev, W5_BACKBONE_AXI_PARAM, 0); + vpu_write_reg(vpu_dev, W5_SEC_AXI_PARAM, 0); + } reg_val = vpu_read_reg(vpu_dev, W5_VPU_RET_VPU_CONFIG0); if (FIELD_GET(FEATURE_BACKBONE, reg_val)) { @@ -1060,6 +1141,28 @@ int wave5_vpu_re_init(struct device *dev, u8 *fw, size_t size) wave5_fio_writel(vpu_dev, W5_BACKBONE_PROG_AXI_ID, reg_val); } + if (vpu_dev->product_code == WAVE515_CODE) { + dma_addr_t task_buf_base; + + vpu_write_reg(vpu_dev, W5_CMD_INIT_NUM_TASK_BUF, + WAVE515_COMMAND_QUEUE_DEPTH); + vpu_write_reg(vpu_dev, W5_CMD_INIT_TASK_BUF_SIZE, + WAVE515_ONE_TASKBUF_SIZE); + + for (i = 0; i < WAVE515_COMMAND_QUEUE_DEPTH; i++) { + task_buf_base = temp_base + temp_size + + (i * WAVE515_ONE_TASKBUF_SIZE); + vpu_write_reg(vpu_dev, + W5_CMD_INIT_ADDR_TASK_BUF0 + (i * 4), + task_buf_base); + } + + vpu_write_reg(vpu_dev, W515_CMD_ADDR_SEC_AXI, + vpu_dev->sram_buf.daddr); + vpu_write_reg(vpu_dev, W515_CMD_SEC_AXI_SIZE, + vpu_dev->sram_buf.size); + } + vpu_write_reg(vpu_dev, W5_VPU_BUSY_STATUS, 1); vpu_write_reg(vpu_dev, W5_COMMAND, W5_INIT_VPU); vpu_write_reg(vpu_dev, W5_VPU_REMAP_CORE_START, 1); @@ -1081,10 +1184,10 @@ int wave5_vpu_re_init(struct device *dev, u8 *fw, size_t size) static int wave5_vpu_sleep_wake(struct device *dev, bool i_sleep_wake, const uint16_t *code, size_t size) { - u32 reg_val; + u32 i, reg_val; struct vpu_buf *common_vb; - dma_addr_t code_base; - u32 code_size, reason_code; + dma_addr_t code_base, temp_base; + u32 code_size, temp_size, reason_code; struct vpu_device *vpu_dev = dev_get_drvdata(dev); int ret; @@ -1114,13 +1217,22 @@ static int wave5_vpu_sleep_wake(struct device *dev, bool i_sleep_wake, const uin common_vb = &vpu_dev->common_mem; code_base = common_vb->daddr; + + if (vpu_dev->product_code == WAVE515_CODE) + code_size = WAVE515_MAX_CODE_BUF_SIZE; + else + code_size = WAVE5_MAX_CODE_BUF_SIZE; + /* ALIGN TO 4KB */ - code_size = (WAVE5_MAX_CODE_BUF_SIZE & ~0xfff); + code_size &= ~0xfff; if (code_size < size * 2) { dev_err(dev, "size too small\n"); return -EINVAL; } + temp_base = code_base + code_size; + temp_size = WAVE5_TEMPBUF_SIZE; + /* Power on without DEBUG mode */ vpu_write_reg(vpu_dev, W5_PO_CONF, 0); @@ -1133,9 +1245,12 @@ static int wave5_vpu_sleep_wake(struct device *dev, bool i_sleep_wake, const uin /* These register must be reset explicitly */ vpu_write_reg(vpu_dev, W5_HW_OPTION, 0); - wave5_fio_writel(vpu_dev, W5_BACKBONE_PROC_EXT_ADDR, 0); - wave5_fio_writel(vpu_dev, W5_BACKBONE_AXI_PARAM, 0); - vpu_write_reg(vpu_dev, W5_SEC_AXI_PARAM, 0); + + if (vpu_dev->product_code != WAVE515_CODE) { + wave5_fio_writel(vpu_dev, W5_BACKBONE_PROC_EXT_ADDR, 0); + wave5_fio_writel(vpu_dev, W5_BACKBONE_AXI_PARAM, 0); + vpu_write_reg(vpu_dev, W5_SEC_AXI_PARAM, 0); + } setup_wave5_interrupts(vpu_dev); @@ -1152,6 +1267,28 @@ static int wave5_vpu_sleep_wake(struct device *dev, bool i_sleep_wake, const uin wave5_fio_writel(vpu_dev, W5_BACKBONE_PROG_AXI_ID, reg_val); } + if (vpu_dev->product_code == WAVE515_CODE) { + dma_addr_t task_buf_base; + + vpu_write_reg(vpu_dev, W5_CMD_INIT_NUM_TASK_BUF, + WAVE515_COMMAND_QUEUE_DEPTH); + vpu_write_reg(vpu_dev, W5_CMD_INIT_TASK_BUF_SIZE, + WAVE515_ONE_TASKBUF_SIZE); + + for (i = 0; i < WAVE515_COMMAND_QUEUE_DEPTH; i++) { + task_buf_base = temp_base + temp_size + + (i * WAVE515_ONE_TASKBUF_SIZE); + vpu_write_reg(vpu_dev, + W5_CMD_INIT_ADDR_TASK_BUF0 + (i * 4), + task_buf_base); + } + + vpu_write_reg(vpu_dev, W515_CMD_ADDR_SEC_AXI, + vpu_dev->sram_buf.daddr); + vpu_write_reg(vpu_dev, W515_CMD_SEC_AXI_SIZE, + vpu_dev->sram_buf.size); + } + vpu_write_reg(vpu_dev, W5_VPU_BUSY_STATUS, 1); vpu_write_reg(vpu_dev, W5_COMMAND, W5_WAKEUP_VPU); /* Start VPU after settings */ diff --git a/drivers/media/platform/chips-media/wave5/wave5-regdefine.h b/drivers/media/platform/chips-media/wave5/wave5-regdefine.h index a15c6b2c3d8b..557344754c4c 100644 --- a/drivers/media/platform/chips-media/wave5/wave5-regdefine.h +++ b/drivers/media/platform/chips-media/wave5/wave5-regdefine.h @@ -205,6 +205,9 @@ enum query_opt { #define W5_ADDR_TEMP_BASE (W5_REG_BASE + 0x011C) #define W5_TEMP_SIZE (W5_REG_BASE + 0x0120) #define W5_HW_OPTION (W5_REG_BASE + 0x012C) +#define W5_CMD_INIT_NUM_TASK_BUF (W5_REG_BASE + 0x0134) +#define W5_CMD_INIT_ADDR_TASK_BUF0 (W5_REG_BASE + 0x0138) +#define W5_CMD_INIT_TASK_BUF_SIZE (W5_REG_BASE + 0x0178) #define W5_SEC_AXI_PARAM (W5_REG_BASE + 0x0180) /************************************************************************/ @@ -216,7 +219,9 @@ enum query_opt { #define W5_CMD_DEC_BS_SIZE (W5_REG_BASE + 0x0120) #define W5_CMD_BS_PARAM (W5_REG_BASE + 0x0124) #define W5_CMD_ADDR_SEC_AXI (W5_REG_BASE + 0x0130) +#define W515_CMD_ADDR_SEC_AXI (W5_REG_BASE + 0x0124) #define W5_CMD_SEC_AXI_SIZE (W5_REG_BASE + 0x0134) +#define W515_CMD_SEC_AXI_SIZE (W5_REG_BASE + 0x0128) #define W5_CMD_EXT_ADDR (W5_REG_BASE + 0x0138) #define W5_CMD_NUM_CQ_DEPTH_M1 (W5_REG_BASE + 0x013C) #define W5_CMD_ERR_CONCEAL (W5_REG_BASE + 0x0140) diff --git a/drivers/media/platform/chips-media/wave5/wave5-vdi.c b/drivers/media/platform/chips-media/wave5/wave5-vdi.c index a63fffed55e9..78888c57b6da 100644 --- a/drivers/media/platform/chips-media/wave5/wave5-vdi.c +++ b/drivers/media/platform/chips-media/wave5/wave5-vdi.c @@ -18,7 +18,11 @@ static int wave5_vdi_allocate_common_memory(struct device *dev) if (!vpu_dev->common_mem.vaddr) { int ret; - vpu_dev->common_mem.size = SIZE_COMMON; + if (vpu_dev->product_code == WAVE515_CODE) + vpu_dev->common_mem.size = WAVE515_SIZE_COMMON; + else + vpu_dev->common_mem.size = SIZE_COMMON; + ret = wave5_vdi_allocate_dma_memory(vpu_dev, &vpu_dev->common_mem); if (ret) { dev_err(dev, "unable to allocate common buffer\n"); diff --git a/drivers/media/platform/chips-media/wave5/wave5-vpu-dec.c b/drivers/media/platform/chips-media/wave5/wave5-vpu-dec.c index 5a71a711f2e8..65a99053c5e8 100644 --- a/drivers/media/platform/chips-media/wave5/wave5-vpu-dec.c +++ b/drivers/media/platform/chips-media/wave5/wave5-vpu-dec.c @@ -1869,7 +1869,8 @@ static int wave5_vpu_open_dec(struct file *filp) goto cleanup_inst; } - wave5_vdi_allocate_sram(inst->dev); + if (inst->dev->product_code != WAVE515_CODE) + wave5_vdi_allocate_sram(inst->dev); return 0; @@ -1897,6 +1898,14 @@ int wave5_vpu_dec_register_device(struct vpu_device *dev) struct video_device *vdev_dec; int ret; + /* + * secondary AXI setup for Wave515 is done by INIT_VPU command, + * that's why SRAM memory is allocated at VPU device register + * rather than at device open. + */ + if (dev->product_code == WAVE515_CODE) + wave5_vdi_allocate_sram(dev); + vdev_dec = devm_kzalloc(dev->v4l2_dev.dev, sizeof(*vdev_dec), GFP_KERNEL); if (!vdev_dec) return -ENOMEM; @@ -1930,6 +1939,9 @@ int wave5_vpu_dec_register_device(struct vpu_device *dev) void wave5_vpu_dec_unregister_device(struct vpu_device *dev) { + if (dev->product_code == WAVE515_CODE) + wave5_vdi_free_sram(dev); + video_unregister_device(dev->video_dev_dec); if (dev->v4l2_m2m_dec_dev) v4l2_m2m_release(dev->v4l2_m2m_dec_dev); diff --git a/drivers/media/platform/chips-media/wave5/wave5-vpu.c b/drivers/media/platform/chips-media/wave5/wave5-vpu.c index 2a972cddf4a6..fc267348399e 100644 --- a/drivers/media/platform/chips-media/wave5/wave5-vpu.c +++ b/drivers/media/platform/chips-media/wave5/wave5-vpu.c @@ -60,7 +60,13 @@ static irqreturn_t wave5_vpu_irq_thread(int irq, void *dev_id) if (irq_reason & BIT(INT_WAVE5_INIT_SEQ) || irq_reason & BIT(INT_WAVE5_ENC_SET_PARAM)) { - if (seq_done & BIT(inst->id)) { + if ((dev->product_code == WAVE515_CODE) && + (cmd_done & BIT(inst->id))) { + cmd_done &= ~BIT(inst->id); + wave5_vdi_write_register(dev, W5_RET_QUEUE_CMD_DONE_INST, + cmd_done); + complete(&inst->irq_done); + } else if (seq_done & BIT(inst->id)) { seq_done &= ~BIT(inst->id); wave5_vdi_write_register(dev, W5_RET_SEQ_DONE_INSTANCE_INFO, seq_done); diff --git a/drivers/media/platform/chips-media/wave5/wave5-vpuapi.h b/drivers/media/platform/chips-media/wave5/wave5-vpuapi.h index 975d96b22191..601205df4433 100644 --- a/drivers/media/platform/chips-media/wave5/wave5-vpuapi.h +++ b/drivers/media/platform/chips-media/wave5/wave5-vpuapi.h @@ -18,6 +18,7 @@ #include "wave5-vdi.h" enum product_id { + PRODUCT_ID_515, PRODUCT_ID_521, PRODUCT_ID_511, PRODUCT_ID_517, diff --git a/drivers/media/platform/chips-media/wave5/wave5-vpuconfig.h b/drivers/media/platform/chips-media/wave5/wave5-vpuconfig.h index 9d99afb78c89..b4128524fcfd 100644 --- a/drivers/media/platform/chips-media/wave5/wave5-vpuconfig.h +++ b/drivers/media/platform/chips-media/wave5/wave5-vpuconfig.h @@ -8,6 +8,7 @@ #ifndef _VPU_CONFIG_H_ #define _VPU_CONFIG_H_ +#define WAVE515_CODE 0x5150 #define WAVE517_CODE 0x5170 #define WAVE537_CODE 0x5370 #define WAVE511_CODE 0x5110 @@ -21,12 +22,13 @@ ((c) == WAVE517_CODE || (c) == WAVE537_CODE || \ (c) == WAVE511_CODE || (c) == WAVE521_CODE || \ (c) == WAVE521E1_CODE || (c) == WAVE521C_CODE || \ - (c) == WAVE521C_DUAL_CODE); \ + (c) == WAVE521C_DUAL_CODE) || (c) == WAVE515_CODE; \ }) #define WAVE517_WORKBUF_SIZE (2 * 1024 * 1024) #define WAVE521ENC_WORKBUF_SIZE (128 * 1024) //HEVC 128K, AVC 40K #define WAVE521DEC_WORKBUF_SIZE (1784 * 1024) +#define WAVE515DEC_WORKBUF_SIZE (2 * 1024 * 1024) #define WAVE5_MAX_SRAM_SIZE (64 * 1024) @@ -52,16 +54,21 @@ #define VLC_BUF_NUM (2) #define COMMAND_QUEUE_DEPTH (2) +#define WAVE515_COMMAND_QUEUE_DEPTH (4) #define W5_REMAP_INDEX0 0 #define W5_REMAP_INDEX1 1 #define W5_REMAP_MAX_SIZE (1024 * 1024) #define WAVE5_MAX_CODE_BUF_SIZE (2 * 1024 * 1024) +#define WAVE515_MAX_CODE_BUF_SIZE (1024 * 1024) #define WAVE5_TEMPBUF_OFFSET WAVE5_MAX_CODE_BUF_SIZE #define WAVE5_TEMPBUF_SIZE (1024 * 1024) +#define WAVE515_TASKBUF_OFFSET (WAVE515_MAX_CODE_BUF_SIZE + WAVE5_TEMPBUF_SIZE) #define SIZE_COMMON (WAVE5_MAX_CODE_BUF_SIZE + WAVE5_TEMPBUF_SIZE) +#define WAVE515_ONE_TASKBUF_SIZE (8 * 1024 * 1024) +#define WAVE515_SIZE_COMMON (WAVE515_TASKBUF_OFFSET + WAVE515_COMMAND_QUEUE_DEPTH * WAVE515_ONE_TASKBUF_SIZE) //=====4. VPU REPORT MEMORY ======================// diff --git a/drivers/media/platform/chips-media/wave5/wave5.h b/drivers/media/platform/chips-media/wave5/wave5.h index 063028eccd3b..57b00e182b6e 100644 --- a/drivers/media/platform/chips-media/wave5/wave5.h +++ b/drivers/media/platform/chips-media/wave5/wave5.h @@ -22,6 +22,7 @@ */ #define BSOPTION_ENABLE_EXPLICIT_END BIT(0) #define BSOPTION_HIGHLIGHT_STREAM_END BIT(1) +#define BSOPTION_RD_PTR_VALID_FLAG BIT(31) /* * Currently the driver only supports hardware with little endian but for source