From patchwork Mon Mar 25 16:40:17 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jisheng Zhang X-Patchwork-Id: 13602511 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 79E85C6FD1F for ; Mon, 25 Mar 2024 16:53:47 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:MIME-Version:References:In-Reply-To: Message-ID:Date:Subject:Cc:To:From:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; bh=nTeSpB+Kz8PP9VpJq2j1d6TbTHKuyRMgD+ed3CjMCwc=; b=MwghEELLoPygBG aPTWcga9GhpiFbBu9PmSve+E9YUFKsZpE0FX0HDbNIaKFLcpq1OBr5XzLrssCEr9PK23y1tdI4V6m dtXWvfVsGy+3PuopFnfh5AwYGA80Zf6L2Ri53lBzXTR1p+vZmhKxRKP0z1sJVU1wG5G2A2ratnGzi f2yYQk9shReUntVsigfjhQL0lCwTynadHaCnBzxljEtQynH6HcCkPnD2OHJ0I6Et+26UsXqMkoykF GJJ7B3e838keJHzM/MK0wB5L1l4RbekPYN2bm7yK2tsrPwjSpPk+NPfuNYhQ+4E4wRFN2pYWKShnT hJzsFU6hLVGWVyRF5UTA==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.97.1 #2 (Red Hat Linux)) id 1ronZv-00000000skM-09zj; Mon, 25 Mar 2024 16:53:43 +0000 Received: from dfw.source.kernel.org ([139.178.84.217]) by bombadil.infradead.org with esmtps (Exim 4.97.1 #2 (Red Hat Linux)) id 1ronZr-00000000shq-3E0O for linux-riscv@lists.infradead.org; Mon, 25 Mar 2024 16:53:41 +0000 Received: from smtp.kernel.org (transwarp.subspace.kernel.org [100.75.92.58]) by dfw.source.kernel.org (Postfix) with ESMTP id 0200C6118C; Mon, 25 Mar 2024 16:53:39 +0000 (UTC) Received: by smtp.kernel.org (Postfix) with ESMTPSA id 1A506C43390; Mon, 25 Mar 2024 16:53:36 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1711385618; bh=vNJUUGgBYsqzd1U+c0XNtNNwoWAwHgq0i6v5JcQYy7Y=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=D1xjklQ9T3CUCWED7yfG2ZMg+v7PSjM3W4B+DkuMr25oQbcUGTDaIrKYJdh3ggagm /xhQgXW0roNkItDioF6LE49k7MEfmjwU+knmOqmuoh4VKTFM5T68nKzKidhNR1oxNK Jy340vIkQYcantibiT87kBrAZhlsSq6dI/Ch8NywMF5SUtB2Ywz8P/SliUSjpNz9TM JYuvx7BYR1UikX4XBeXLuMArHIgUOs+WzYLygvAYlpjBZz/lPo9L0efBqBHh3IFWr4 WmFIC4zK/kEZ/KsIUTbtFcWrBTKU9t+/V8KG0BJ73eoKMPnAh1LqWL0nKfZtKujtxN oQUreGyV/GmxQ== From: Jisheng Zhang To: Paul Walmsley , Palmer Dabbelt , Albert Ou , Daniel Lezcano , Thomas Gleixner Cc: linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org Subject: [PATCH 1/5] riscv: nommu: remove PAGE_OFFSET hardcoding Date: Tue, 26 Mar 2024 00:40:17 +0800 Message-ID: <20240325164021.3229-2-jszhang@kernel.org> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20240325164021.3229-1-jszhang@kernel.org> References: <20240325164021.3229-1-jszhang@kernel.org> MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20240325_095339_917715_CBD84A3D X-CRM114-Status: UNSURE ( 9.63 ) X-CRM114-Notice: Please train this message. X-BeenThere: linux-riscv@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-riscv" Errors-To: linux-riscv-bounces+linux-riscv=archiver.kernel.org@lists.infradead.org Currently, PAGE_OFFSET is hardcoded as 0x8000_0000, it works fine since there's only one nommu platform in the mainline. However, there are many cases where the (S)DRAM base address isn't 0x8000_0000, so remove the hardcoding value, and introduce DRAM_BASE which will be set by users during configuring. DRAM_BASE is 0x8000_0000 by default. Signed-off-by: Jisheng Zhang --- arch/riscv/Kconfig | 8 +++++++- 1 file changed, 7 insertions(+), 1 deletion(-) diff --git a/arch/riscv/Kconfig b/arch/riscv/Kconfig index 7895c77545f1..afd51dbdc253 100644 --- a/arch/riscv/Kconfig +++ b/arch/riscv/Kconfig @@ -247,10 +247,16 @@ config MMU Select if you want MMU-based virtualised addressing space support by paged memory management. If unsure, say 'Y'. +if !MMU +config DRAM_BASE + hex '(S)DRAM Base Address' + default 0x80000000 +endif + config PAGE_OFFSET hex default 0xC0000000 if 32BIT && MMU - default 0x80000000 if !MMU + default DRAM_BASE if !MMU default 0xff60000000000000 if 64BIT config KASAN_SHADOW_OFFSET From patchwork Mon Mar 25 16:40:18 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jisheng Zhang X-Patchwork-Id: 13602512 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id A200EC54E58 for ; Mon, 25 Mar 2024 16:53:49 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:MIME-Version:References:In-Reply-To: Message-ID:Date:Subject:Cc:To:From:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; bh=Z+o6GilBLOxzDZOoGXLFPlh9Tipq0zaOilQdWJViFH4=; b=hXScbbR0diMsUz 0xJoE+fi/RueIYB+OwqiBNma3D2jcyzmHZzQRLUqt9FljQzK/jdmBzhJq3+xxI0SRBEbAyYHMgHZl 939uLmUw+Atb8tWxCQmnNhES6JzQp+v5QqUjKFALSfrGFj0Iko1IfXz8VffF7Ep/AaPQIb6BgrYqE jIZWA52ppWieL5+BRhk9ctcgl0grY0JkI/fe/ffaqeef016B986dqdwUYYksud7yCUjdJb30pXd/Q eWj/UAi8+6CXF6UcRGzsfogkmCSHazKNvrrkG8A9Qf7lsEHUnHOxMgPMTLOL63rycLyjBn+iZqsPL 0UbdJPoiLwy11EE93A+A==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.97.1 #2 (Red Hat Linux)) id 1ronZy-00000000slL-0al4; Mon, 25 Mar 2024 16:53:46 +0000 Received: from dfw.source.kernel.org ([2604:1380:4641:c500::1]) by bombadil.infradead.org with esmtps (Exim 4.97.1 #2 (Red Hat Linux)) id 1ronZt-00000000sih-39BA for linux-riscv@lists.infradead.org; Mon, 25 Mar 2024 16:53:44 +0000 Received: from smtp.kernel.org (transwarp.subspace.kernel.org [100.75.92.58]) by dfw.source.kernel.org (Postfix) with ESMTP id 104BD611AE; Mon, 25 Mar 2024 16:53:41 +0000 (UTC) Received: by smtp.kernel.org (Postfix) with ESMTPSA id 1ECE4C433F1; Mon, 25 Mar 2024 16:53:38 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1711385620; bh=w6ZM0qzs2PGzaQXvUXmLy9gFSChzi3ytqtQ7RsJPkIE=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=TqpK//uSQEaK2p8j5RufU/zoTdsqlJw9JaorQ6kkKPd4MTQwJgbjlLTxTI6S3nS7K BPva1d2LxjAXvyR93epam3JmVqaLdtPWjtZmwPBIZmuAL44cT/GoxvwiBj7/WCLkvT 45zGIyPMbG1FaCOV0OraeQKppFqC7Ml2wQABrVv2U8eNs5iYuDmu26OWqQcPFxovTj JRly5wAASJkRRvtBGFMjoZ3EoTPYm7867mTqnJXydye4VSabI3bZGTw/OtVj5AlzAH bogv6Zx9BSin3R+FSuPeXGrDU+epew4dyKbKvQHqNQZ8kxPoePqh5NkQdFrg4OY++g lKd7Mtvm7a2TA== From: Jisheng Zhang To: Paul Walmsley , Palmer Dabbelt , Albert Ou , Daniel Lezcano , Thomas Gleixner Cc: linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org Subject: [PATCH 2/5] riscv: nommu: use CSR_TIME* for get_cycles* implementation Date: Tue, 26 Mar 2024 00:40:18 +0800 Message-ID: <20240325164021.3229-3-jszhang@kernel.org> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20240325164021.3229-1-jszhang@kernel.org> References: <20240325164021.3229-1-jszhang@kernel.org> MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20240325_095341_874032_141BEC1C X-CRM114-Status: GOOD ( 11.42 ) X-BeenThere: linux-riscv@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-riscv" Errors-To: linux-riscv-bounces+linux-riscv=archiver.kernel.org@lists.infradead.org Per riscv privileged spec, "The time CSR is a read-only shadow of the memory-mapped mtime register", "On RV32I the timeh CSR is a read-only shadow of the upper 32 bits of the memory-mapped mtime register, while time shadows only the lower 32 bits of mtime." Since get_cycles() only reads the timer, it's fine to use CSR_TIME to implement get_cycles(). Signed-off-by: Jisheng Zhang --- arch/riscv/include/asm/timex.h | 40 ---------------------------------- 1 file changed, 40 deletions(-) diff --git a/arch/riscv/include/asm/timex.h b/arch/riscv/include/asm/timex.h index a06697846e69..a3fb85d505d4 100644 --- a/arch/riscv/include/asm/timex.h +++ b/arch/riscv/include/asm/timex.h @@ -10,44 +10,6 @@ typedef unsigned long cycles_t; -#ifdef CONFIG_RISCV_M_MODE - -#include - -#ifdef CONFIG_64BIT -static inline cycles_t get_cycles(void) -{ - return readq_relaxed(clint_time_val); -} -#else /* !CONFIG_64BIT */ -static inline u32 get_cycles(void) -{ - return readl_relaxed(((u32 *)clint_time_val)); -} -#define get_cycles get_cycles - -static inline u32 get_cycles_hi(void) -{ - return readl_relaxed(((u32 *)clint_time_val) + 1); -} -#define get_cycles_hi get_cycles_hi -#endif /* CONFIG_64BIT */ - -/* - * Much like MIPS, we may not have a viable counter to use at an early point - * in the boot process. Unfortunately we don't have a fallback, so instead - * we just return 0. - */ -static inline unsigned long random_get_entropy(void) -{ - if (unlikely(clint_time_val == NULL)) - return random_get_entropy_fallback(); - return get_cycles(); -} -#define random_get_entropy() random_get_entropy() - -#else /* CONFIG_RISCV_M_MODE */ - static inline cycles_t get_cycles(void) { return csr_read(CSR_TIME); @@ -60,8 +22,6 @@ static inline u32 get_cycles_hi(void) } #define get_cycles_hi get_cycles_hi -#endif /* !CONFIG_RISCV_M_MODE */ - #ifdef CONFIG_64BIT static inline u64 get_cycles64(void) { From patchwork Mon Mar 25 16:40:19 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jisheng Zhang X-Patchwork-Id: 13602513 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id C402BC54E58 for ; Mon, 25 Mar 2024 16:53:52 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:MIME-Version:References:In-Reply-To: Message-ID:Date:Subject:Cc:To:From:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; bh=52fINBEHtdilr3pihHRmcw6vB1Tp9a+7/FU2XFFQOIU=; b=4HWNydXkjaCmiC 8I4slpE/i3jV9BVabQlIlyKZEP0zzn+dbhR63MBxUrJH0cMEpGWFkNRo6Ak7wQxoaFL8CBNc7DPm3 NP6EnOl/iBuoWdoNSHzSYHlmUeZW/wsEBGdxtCU/fnR/8WYc3qXjLrc8wWQPL9zmH75N9DjQY6upC hD1dz5duozzZJ+eZ606BEYQ0c7L3nHVahTbT2fM9CIyyT8vrKEZfkS7RuwRZbl1MbNK7VngDyBSMN j5aIBpesHHjRBflFT2+Le5tW3ZmJUH4PQS4Urdd8Wa1GZm1Oix79LJcD9kHsM5xTvR0ZGK11dScsB DU69CQSJka4BrilTtGTA==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.97.1 #2 (Red Hat Linux)) id 1rona1-00000000sng-0aYg; Mon, 25 Mar 2024 16:53:49 +0000 Received: from sin.source.kernel.org ([145.40.73.55]) by bombadil.infradead.org with esmtps (Exim 4.97.1 #2 (Red Hat Linux)) id 1ronZx-00000000skn-2wdD for linux-riscv@lists.infradead.org; Mon, 25 Mar 2024 16:53:47 +0000 Received: from smtp.kernel.org (transwarp.subspace.kernel.org [100.75.92.58]) by sin.source.kernel.org (Postfix) with ESMTP id 72EA8CE1B9C; Mon, 25 Mar 2024 16:53:43 +0000 (UTC) Received: by smtp.kernel.org (Postfix) with ESMTPSA id 23E98C433C7; Mon, 25 Mar 2024 16:53:40 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1711385622; bh=NrGlxqgZh3B1ZksAfxarZEX2wTrdfyxjcZNnuUN0fWY=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=sbe2U8cHcKbsb3NjqeI+VDc1Bq5b3EylZM6uqyiPyKXZ3EuJuhgYjfp6Tf1WyBsNa dP4VEkfxtxGFCZqC8jHHbhJQ/1+MxsNMSLxTMGQ1HsQb2YvGSFCKTgWuWwUmUHPb2V /ByEg7Vas3QPjTBvMMPzmQpyoluP9C3KnGMwgCeOn/2Cod4L7saQFCa/FI5JJfiQXx DLeSGwQKaumx1Aqo+ho0dZjVC18qWDt4LzXuCzrPLOAgviB8jMQrdK5Do/O+2yl8Jr MCo+Dc69iwxnjqQiwCG5+Ftiebcub+WIp6whR7p2BMc9kYBMSFAcemQ91LgPNgZ/cJ RikMAyfdIif3g== From: Jisheng Zhang To: Paul Walmsley , Palmer Dabbelt , Albert Ou , Daniel Lezcano , Thomas Gleixner Cc: linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org Subject: [PATCH 3/5] clocksource/drivers/timer-clint: Remove clint_time_val Date: Tue, 26 Mar 2024 00:40:19 +0800 Message-ID: <20240325164021.3229-4-jszhang@kernel.org> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20240325164021.3229-1-jszhang@kernel.org> References: <20240325164021.3229-1-jszhang@kernel.org> MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20240325_095346_177798_B92DE85E X-CRM114-Status: GOOD ( 13.78 ) X-BeenThere: linux-riscv@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-riscv" Errors-To: linux-riscv-bounces+linux-riscv=archiver.kernel.org@lists.infradead.org The usage have been removed, so it's time to remove clint_time_val. Signed-off-by: Jisheng Zhang --- arch/riscv/include/asm/clint.h | 26 -------------------------- drivers/clocksource/timer-clint.c | 17 ----------------- 2 files changed, 43 deletions(-) delete mode 100644 arch/riscv/include/asm/clint.h diff --git a/arch/riscv/include/asm/clint.h b/arch/riscv/include/asm/clint.h deleted file mode 100644 index 0789fd37b40a..000000000000 --- a/arch/riscv/include/asm/clint.h +++ /dev/null @@ -1,26 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ -/* - * Copyright (C) 2020 Google, Inc - */ - -#ifndef _ASM_RISCV_CLINT_H -#define _ASM_RISCV_CLINT_H - -#include -#include - -#ifdef CONFIG_RISCV_M_MODE -/* - * This lives in the CLINT driver, but is accessed directly by timex.h to avoid - * any overhead when accessing the MMIO timer. - * - * The ISA defines mtime as a 64-bit memory-mapped register that increments at - * a constant frequency, but it doesn't define some other constraints we depend - * on (most notably ordering constraints, but also some simpler stuff like the - * memory layout). Thus, this is called "clint_time_val" instead of something - * like "riscv_mtime", to signify that these non-ISA assumptions must hold. - */ -extern u64 __iomem *clint_time_val; -#endif - -#endif diff --git a/drivers/clocksource/timer-clint.c b/drivers/clocksource/timer-clint.c index 09fd292eb83d..56acaa93b6c3 100644 --- a/drivers/clocksource/timer-clint.c +++ b/drivers/clocksource/timer-clint.c @@ -24,10 +24,6 @@ #include #include -#ifndef CONFIG_RISCV_M_MODE -#include -#endif - #define CLINT_IPI_OFF 0 #define CLINT_TIMER_CMP_OFF 0x4000 #define CLINT_TIMER_VAL_OFF 0xbff8 @@ -40,11 +36,6 @@ static u64 __iomem *clint_timer_val; static unsigned long clint_timer_freq; static unsigned int clint_timer_irq; -#ifdef CONFIG_RISCV_M_MODE -u64 __iomem *clint_time_val; -EXPORT_SYMBOL(clint_time_val); -#endif - #ifdef CONFIG_SMP static void clint_send_ipi(unsigned int cpu) { @@ -217,14 +208,6 @@ static int __init clint_timer_init_dt(struct device_node *np) clint_timer_val = base + CLINT_TIMER_VAL_OFF; clint_timer_freq = riscv_timebase; -#ifdef CONFIG_RISCV_M_MODE - /* - * Yes, that's an odd naming scheme. time_val is public, but hopefully - * will die in favor of something cleaner. - */ - clint_time_val = clint_timer_val; -#endif - pr_info("%pOFP: timer running at %ld Hz\n", np, clint_timer_freq); rc = clocksource_register_hz(&clint_clocksource, clint_timer_freq); From patchwork Mon Mar 25 16:40:20 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jisheng Zhang X-Patchwork-Id: 13602514 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id D82F2C54E58 for ; Mon, 25 Mar 2024 16:53:55 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; 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Mon, 25 Mar 2024 16:53:49 +0000 Received: from smtp.kernel.org (transwarp.subspace.kernel.org [100.75.92.58]) by sin.source.kernel.org (Postfix) with ESMTP id A457ACE1BAA; Mon, 25 Mar 2024 16:53:45 +0000 (UTC) Received: by smtp.kernel.org (Postfix) with ESMTPSA id 285A8C433F1; Mon, 25 Mar 2024 16:53:42 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1711385624; bh=JxFNqk1udzBJf0wb9hzCshesMQ7wj/gJiBIIdlgKlnQ=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=BBUCPAz08ws6G27uwdiYhJaiZaAMK7cNJLpZ3myQHlDdWdUAFQob1dxDd7GbxJDXC k6naSdjnDeynjjzTHXDxmX/sg5j/MpwZUwme4C+kkQdZb05BeggwrFCrA3cMQRhTye V6FcJfKXPjEN46BvjPOqWyJG6J+gnBNpyDXxIU0pmN2bmMy7or9UKvEwU4aGYV76+H UI88J060emfq8sn9e7+H8iy+rsYI4/JaSAqgtL3YmWp2xs3a6phKS5b7cZBNlZDRE8 fd/IKf4ULYTZzOIzybOI4+UBb8g+ZSZ4DGIhi4fhhJMfwgxtk+ROyxU0+2qJ+y/bLe XZi9O/tukUQrg== From: Jisheng Zhang To: Paul Walmsley , Palmer Dabbelt , Albert Ou , Daniel Lezcano , Thomas Gleixner Cc: linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org Subject: [PATCH 4/5] clocksource/drivers/timer-clint: Use get_cycles() Date: Tue, 26 Mar 2024 00:40:20 +0800 Message-ID: <20240325164021.3229-5-jszhang@kernel.org> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20240325164021.3229-1-jszhang@kernel.org> References: <20240325164021.3229-1-jszhang@kernel.org> MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20240325_095347_618322_49D106F8 X-CRM114-Status: GOOD ( 11.48 ) X-BeenThere: linux-riscv@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-riscv" Errors-To: linux-riscv-bounces+linux-riscv=archiver.kernel.org@lists.infradead.org Per riscv privileged spec, "The time CSR is a read-only shadow of the memory-mapped mtime register", "On RV32I the timeh CSR is a read-only shadow of the upper 32 bits of the memory-mapped mtime register, while time shadows only the lower 32 bits of mtime.", so it's fine to use time CSR to implement sched_clock and clint clockevent/clocksource. Signed-off-by: Jisheng Zhang --- drivers/clocksource/timer-clint.c | 25 +------------------------ 1 file changed, 1 insertion(+), 24 deletions(-) diff --git a/drivers/clocksource/timer-clint.c b/drivers/clocksource/timer-clint.c index 56acaa93b6c3..4537c77e623c 100644 --- a/drivers/clocksource/timer-clint.c +++ b/drivers/clocksource/timer-clint.c @@ -32,7 +32,6 @@ static u32 __iomem *clint_ipi_base; static unsigned int clint_ipi_irq; static u64 __iomem *clint_timer_cmp; -static u64 __iomem *clint_timer_val; static unsigned long clint_timer_freq; static unsigned int clint_timer_irq; @@ -60,31 +59,10 @@ static void clint_ipi_interrupt(struct irq_desc *desc) } #endif -#ifdef CONFIG_64BIT -#define clint_get_cycles() readq_relaxed(clint_timer_val) -#else -#define clint_get_cycles() readl_relaxed(clint_timer_val) -#define clint_get_cycles_hi() readl_relaxed(((u32 *)clint_timer_val) + 1) -#endif - -#ifdef CONFIG_64BIT static u64 notrace clint_get_cycles64(void) { - return clint_get_cycles(); -} -#else /* CONFIG_64BIT */ -static u64 notrace clint_get_cycles64(void) -{ - u32 hi, lo; - - do { - hi = clint_get_cycles_hi(); - lo = clint_get_cycles(); - } while (hi != clint_get_cycles_hi()); - - return ((u64)hi << 32) | lo; + return get_cycles64(); } -#endif /* CONFIG_64BIT */ static u64 clint_rdtime(struct clocksource *cs) { @@ -205,7 +183,6 @@ static int __init clint_timer_init_dt(struct device_node *np) clint_ipi_base = base + CLINT_IPI_OFF; clint_timer_cmp = base + CLINT_TIMER_CMP_OFF; - clint_timer_val = base + CLINT_TIMER_VAL_OFF; clint_timer_freq = riscv_timebase; pr_info("%pOFP: timer running at %ld Hz\n", np, clint_timer_freq); From patchwork Mon Mar 25 16:40:21 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jisheng Zhang X-Patchwork-Id: 13602515 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id A615DC6FD1F for ; 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Mon, 25 Mar 2024 16:53:54 +0000 Received: from dfw.source.kernel.org ([139.178.84.217]) by bombadil.infradead.org with esmtps (Exim 4.97.1 #2 (Red Hat Linux)) id 1ronZz-00000000smC-3TGo for linux-riscv@lists.infradead.org; Mon, 25 Mar 2024 16:53:49 +0000 Received: from smtp.kernel.org (transwarp.subspace.kernel.org [100.75.92.58]) by dfw.source.kernel.org (Postfix) with ESMTP id 1AFBD60EB2; Mon, 25 Mar 2024 16:53:47 +0000 (UTC) Received: by smtp.kernel.org (Postfix) with ESMTPSA id 2FF7FC43399; Mon, 25 Mar 2024 16:53:45 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1711385626; bh=USjwiJfYFCW4AFS9tztvFTk4Lr/QV8A+qsGGTHmlU9g=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=aQw3HWi2KumzvUq+QquuTX8sj1Ig+lvifx/LxjM0xOX73RKrN2zBTC1N6EUqN0M8I G7xEyRIaPeb9H3u8Jkox4cQ9xCrthzl1Q/mZ+InXlYwaN9bLqdyscnmnjBzaBdGKPQ kEpHbE+85Yo9a5HfHkdeRMem8ECfQ4McQlJPRS6wgnc+oT8kmgtodWVeHp6PQan8Mn i87UfCVVPyUMJs2+5hIQ9cZKcX8aXZHItnkOKxhZFObkKc/8whsC3vxYU3Jv+F1QqV Sw7PYJNMpiNreRIRDFpBAQRHbgu309evfKT4rbLA5qY8JoM0jmrkajj+qPwN3Dn4i2 QOuyLrlxiFh8Q== From: Jisheng Zhang To: Paul Walmsley , Palmer Dabbelt , Albert Ou , Daniel Lezcano , Thomas Gleixner Cc: linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org Subject: [PATCH 5/5] clocksource/drivers/timer-clint: Add T-Head C9xx clint support Date: Tue, 26 Mar 2024 00:40:21 +0800 Message-ID: <20240325164021.3229-6-jszhang@kernel.org> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20240325164021.3229-1-jszhang@kernel.org> References: <20240325164021.3229-1-jszhang@kernel.org> MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20240325_095348_035374_2BEC3299 X-CRM114-Status: GOOD ( 10.84 ) X-BeenThere: linux-riscv@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-riscv" Errors-To: linux-riscv-bounces+linux-riscv=archiver.kernel.org@lists.infradead.org The mtimecmp in T-Head C9xx clint only supports 32bit read/write, implement such support. Signed-off-by: Jisheng Zhang --- drivers/clocksource/timer-clint.c | 24 ++++++++++++++++++++++++ 1 file changed, 24 insertions(+) diff --git a/drivers/clocksource/timer-clint.c b/drivers/clocksource/timer-clint.c index 4537c77e623c..71188732e8a3 100644 --- a/drivers/clocksource/timer-clint.c +++ b/drivers/clocksource/timer-clint.c @@ -34,6 +34,7 @@ static unsigned int clint_ipi_irq; static u64 __iomem *clint_timer_cmp; static unsigned long clint_timer_freq; static unsigned int clint_timer_irq; +static bool is_c900_clint; #ifdef CONFIG_SMP static void clint_send_ipi(unsigned int cpu) @@ -88,6 +89,19 @@ static int clint_clock_next_event(unsigned long delta, return 0; } +static int c900_clint_clock_next_event(unsigned long delta, + struct clock_event_device *ce) +{ + void __iomem *r = clint_timer_cmp + + cpuid_to_hartid_map(smp_processor_id()); + u64 val = clint_get_cycles64() + delta; + + csr_set(CSR_IE, IE_TIE); + writel_relaxed(val, r); + writel_relaxed(val >> 32, r + 4); + return 0; +} + static DEFINE_PER_CPU(struct clock_event_device, clint_clock_event) = { .name = "clint_clockevent", .features = CLOCK_EVT_FEAT_ONESHOT, @@ -99,6 +113,9 @@ static int clint_timer_starting_cpu(unsigned int cpu) { struct clock_event_device *ce = per_cpu_ptr(&clint_clock_event, cpu); + if (is_c900_clint) + ce->set_next_event = c900_clint_clock_next_event; + ce->cpumask = cpumask_of(cpu); clockevents_config_and_register(ce, clint_timer_freq, 100, ULONG_MAX); @@ -233,5 +250,12 @@ static int __init clint_timer_init_dt(struct device_node *np) return rc; } +static int __init c900_clint_timer_init_dt(struct device_node *np) +{ + is_c900_clint = true; + return clint_timer_init_dt(np); +} + TIMER_OF_DECLARE(clint_timer, "riscv,clint0", clint_timer_init_dt); TIMER_OF_DECLARE(clint_timer1, "sifive,clint0", clint_timer_init_dt); +TIMER_OF_DECLARE(clint_timer2, "thead,c900-clint", clint_timer_init_dt);