From patchwork Mon Mar 25 17:26:17 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Andrew Davis X-Patchwork-Id: 13602566 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 46A98C54E64 for ; Mon, 25 Mar 2024 17:27:07 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:MIME-Version:Message-ID:Date:Subject:CC :To:From:Reply-To:Content-ID:Content-Description:Resent-Date:Resent-From: Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID:In-Reply-To:References: List-Owner; bh=Fv0k6LHWT3YOT5JHtjvLNuXxyCTOobpuIO+1iC0qd5I=; b=TYxxlU0GCg+Ipl 8OrJEaWN57k5VeU7EN6KpjgK8c58paUuiienL8BmTdpkRGd6c6Fs82r12JqC7H4ejtweU69JzVmh9 cwuKVl99VcTBNr2w/5HBMZVMKdA2SJIRPoM4GgNoN5CA+HLTrotw7/OrcLRdeKQ/EXj8/GsiwUGOu iPwJ4Ux3tYKCtDR7bPquey7hGzZkhcpg5u5Yp4875hb9GG+UBVshX+GT8pqofh/rw87kGrpYk1O0g 9+wieGckH8i4wZBXeuHlO7mh5O6nC/mainjIhQFY/Jzzllt8DzgTUum+nO6Cb3mgxRolWpc9fI5Nq auy8tl+adIKzT3SJBywA==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.97.1 #2 (Red Hat Linux)) id 1roo5s-000000012BS-28Z3; Mon, 25 Mar 2024 17:26:44 +0000 Received: from lelv0143.ext.ti.com ([198.47.23.248]) by bombadil.infradead.org with esmtps (Exim 4.97.1 #2 (Red Hat Linux)) id 1roo5o-00000001298-0lli for linux-arm-kernel@lists.infradead.org; Mon, 25 Mar 2024 17:26:42 +0000 Received: from fllv0034.itg.ti.com ([10.64.40.246]) by lelv0143.ext.ti.com (8.15.2/8.15.2) with ESMTP id 42PHQKx1061960; Mon, 25 Mar 2024 12:26:20 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ti.com; s=ti-com-17Q1; t=1711387580; bh=LQCWHfRfk2zps5GrMrRcYXVrZU5MK69gK8L47AXSiH0=; h=From:To:CC:Subject:Date; b=h79AbBty/k3XWIx7j5bAYQme8+nwnGAvU/Zv76EL69LTnMk8aCJC7J3P2eJhKtSbF Kee5EvtZyzcWKj1SWjzpxkgL5jlIAH/uqa1FlvEpMfz7wSuHDu6TksExGPos9EJ9lB ghjEcNe9ScIRcPaBtZXU22v9gUXzg5rh5mIUNuVg= Received: from DFLE115.ent.ti.com (dfle115.ent.ti.com [10.64.6.36]) by fllv0034.itg.ti.com (8.15.2/8.15.2) with ESMTPS id 42PHQKBZ109596 (version=TLSv1.2 cipher=AES256-GCM-SHA384 bits=256 verify=FAIL); Mon, 25 Mar 2024 12:26:20 -0500 Received: from DFLE106.ent.ti.com (10.64.6.27) by DFLE115.ent.ti.com (10.64.6.36) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2507.23; Mon, 25 Mar 2024 12:26:20 -0500 Received: from lelvsmtp5.itg.ti.com (10.180.75.250) by DFLE106.ent.ti.com (10.64.6.27) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2507.23 via Frontend Transport; Mon, 25 Mar 2024 12:26:20 -0500 Received: from lelvsmtp6.itg.ti.com ([10.249.42.149]) by lelvsmtp5.itg.ti.com (8.15.2/8.15.2) with ESMTP id 42PHQK80042985; Mon, 25 Mar 2024 12:26:20 -0500 From: Andrew Davis To: Russell King , Baruch Siach , Vladimir Zapolskiy , Masami Hiramatsu , Arnd Bergmann , Geert Uytterhoeven CC: , , Andrew Davis Subject: [PATCH v2 1/3] ARM: mach-hpe: Rework support and directory structure Date: Mon, 25 Mar 2024 12:26:17 -0500 Message-ID: <20240325172619.113661-1-afd@ti.com> X-Mailer: git-send-email 2.39.2 MIME-Version: 1.0 X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20240325_102640_396813_E9B7B7D6 X-CRM114-Status: GOOD ( 23.05 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org Having a platform need a mach-* directory should be seen as a negative, it means the platform needs special non-standard handling. ARM64 support does not allow mach-* directories at all. While we may not get to that given all the non-standard architectures we support, we should still try to get as close as we can and reduce the number of mach directories. The mach-hpe/ directory and files, provides just one "feature": having the kernel print the machine name if the DTB does not also contain a "model" string (which they always do). To reduce the number of mach-* directories let's do without that feature and remove this directory. Note, we drop the l2c_aux_mask = ~0 line, but this is safe as the fallback GENERIC_DT machine has that as the default. Signed-off-by: Andrew Davis --- Changes from v1: - Updated commit desc with l2c_aux_mask info - Rebased on v6.9-rc1 MAINTAINERS | 1 - arch/arm/Kconfig | 2 -- arch/arm/Kconfig.platforms | 25 +++++++++++++++++++++++++ arch/arm/Makefile | 1 - arch/arm/mach-hpe/Kconfig | 23 ----------------------- arch/arm/mach-hpe/Makefile | 1 - arch/arm/mach-hpe/gxp.c | 15 --------------- 7 files changed, 25 insertions(+), 43 deletions(-) delete mode 100644 arch/arm/mach-hpe/Kconfig delete mode 100644 arch/arm/mach-hpe/Makefile delete mode 100644 arch/arm/mach-hpe/gxp.c diff --git a/MAINTAINERS b/MAINTAINERS index aa3b947fb0801..947186f0b0c64 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -2244,7 +2244,6 @@ F: Documentation/devicetree/bindings/spi/hpe,gxp-spifi.yaml F: Documentation/devicetree/bindings/timer/hpe,gxp-timer.yaml F: Documentation/hwmon/gxp-fan-ctrl.rst F: arch/arm/boot/dts/hpe/ -F: arch/arm/mach-hpe/ F: drivers/clocksource/timer-gxp.c F: drivers/hwmon/gxp-fan-ctrl.c F: drivers/i2c/busses/i2c-gxp.c diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig index b14aed3a17abb..9f55fd24c163a 100644 --- a/arch/arm/Kconfig +++ b/arch/arm/Kconfig @@ -386,8 +386,6 @@ source "arch/arm/mach-highbank/Kconfig" source "arch/arm/mach-hisi/Kconfig" -source "arch/arm/mach-hpe/Kconfig" - source "arch/arm/mach-imx/Kconfig" source "arch/arm/mach-ixp4xx/Kconfig" diff --git a/arch/arm/Kconfig.platforms b/arch/arm/Kconfig.platforms index 845ab08e20a4b..5c19c1f2cff61 100644 --- a/arch/arm/Kconfig.platforms +++ b/arch/arm/Kconfig.platforms @@ -87,6 +87,31 @@ config MACH_ASM9260 help Support for Alphascale ASM9260 based platform. +menuconfig ARCH_HPE + bool "HPE SoC support" + depends on ARCH_MULTI_V7 + help + This enables support for HPE ARM based BMC chips. + +if ARCH_HPE + +config ARCH_HPE_GXP + bool "HPE GXP SoC" + depends on ARCH_MULTI_V7 + select ARM_VIC + select GENERIC_IRQ_CHIP + select CLKSRC_MMIO + help + HPE GXP is the name of the HPE Soc. This SoC is used to implement many + BMC features at HPE. It supports ARMv7 architecture based on the Cortex + A9 core. It is capable of using an AXI bus to which a memory controller + is attached. It has multiple SPI interfaces to connect boot flash and + BIOS flash. It uses a 10/100/1000 MAC for network connectivity. It + has multiple i2c engines to drive connectivity with a host + infrastructure. + +endif + menuconfig ARCH_MOXART bool "MOXA ART SoC" depends on ARCH_MULTI_V4 diff --git a/arch/arm/Makefile b/arch/arm/Makefile index d82908b1b1bb4..131778fbc6827 100644 --- a/arch/arm/Makefile +++ b/arch/arm/Makefile @@ -182,7 +182,6 @@ machine-$(CONFIG_ARCH_FOOTBRIDGE) += footbridge machine-$(CONFIG_ARCH_GEMINI) += gemini machine-$(CONFIG_ARCH_HIGHBANK) += highbank machine-$(CONFIG_ARCH_HISI) += hisi -machine-$(CONFIG_ARCH_HPE) += hpe machine-$(CONFIG_ARCH_IXP4XX) += ixp4xx machine-$(CONFIG_ARCH_KEYSTONE) += keystone machine-$(CONFIG_ARCH_LPC18XX) += lpc18xx diff --git a/arch/arm/mach-hpe/Kconfig b/arch/arm/mach-hpe/Kconfig deleted file mode 100644 index 3372bbf38d383..0000000000000 --- a/arch/arm/mach-hpe/Kconfig +++ /dev/null @@ -1,23 +0,0 @@ -menuconfig ARCH_HPE - bool "HPE SoC support" - depends on ARCH_MULTI_V7 - help - This enables support for HPE ARM based BMC chips. -if ARCH_HPE - -config ARCH_HPE_GXP - bool "HPE GXP SoC" - depends on ARCH_MULTI_V7 - select ARM_VIC - select GENERIC_IRQ_CHIP - select CLKSRC_MMIO - help - HPE GXP is the name of the HPE Soc. This SoC is used to implement many - BMC features at HPE. It supports ARMv7 architecture based on the Cortex - A9 core. It is capable of using an AXI bus to which a memory controller - is attached. It has multiple SPI interfaces to connect boot flash and - BIOS flash. It uses a 10/100/1000 MAC for network connectivity. It - has multiple i2c engines to drive connectivity with a host - infrastructure. - -endif diff --git a/arch/arm/mach-hpe/Makefile b/arch/arm/mach-hpe/Makefile deleted file mode 100644 index 8b0a91234df4e..0000000000000 --- a/arch/arm/mach-hpe/Makefile +++ /dev/null @@ -1 +0,0 @@ -obj-$(CONFIG_ARCH_HPE_GXP) += gxp.o diff --git a/arch/arm/mach-hpe/gxp.c b/arch/arm/mach-hpe/gxp.c deleted file mode 100644 index 581c8da517b86..0000000000000 --- a/arch/arm/mach-hpe/gxp.c +++ /dev/null @@ -1,15 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* Copyright (C) 2022 Hewlett-Packard Enterprise Development Company, L.P. */ - -#include - -static const char * const gxp_board_dt_compat[] = { - "hpe,gxp", - NULL, -}; - -DT_MACHINE_START(GXP_DT, "HPE GXP") - .dt_compat = gxp_board_dt_compat, - .l2c_aux_val = 0, - .l2c_aux_mask = ~0, -MACHINE_END From patchwork Mon Mar 25 17:26:18 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Andrew Davis X-Patchwork-Id: 13602565 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 03EC4C54E64 for ; Mon, 25 Mar 2024 17:27:02 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:MIME-Version:References:In-Reply-To: Message-ID:Date:Subject:CC:To:From:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; bh=SWffErFSCpFALS9AZhA+9lCu5vydkASbP4gl4RUsvxc=; b=qTiLFWmr+MkkWx JjumKxvKe8K3h7njVCquYRIa67X/On89mZeQTodS3v002EWwLVjOHoUvYLTiP26OpNx7fmCsa/+cY rEYkwGyBuS/Fn11mmaZC+LJOK+LRCkyxuPDByEgp2KH0PkM2WPU/BIMpaOW+uXPcfQqdrEbbYFWhS /PPGlSPtzhDOJTNe6WIWiULngRPQfmXniWTYSy6xR56WLfMMcPRX38ZddGFx0aRvf2a2ZCZ8Xrtnn 2Pe5defxeLETs4+n71Sd3rqB7+v5xHaiGWC1QYSftEv8wJsHFyR5ybqgLpqyL24FONICZDBF3aGyA wp+S280LKT50KFSW3YKw==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.97.1 #2 (Red Hat Linux)) id 1roo5t-000000012Bw-26qc; Mon, 25 Mar 2024 17:26:45 +0000 Received: from lelv0143.ext.ti.com ([198.47.23.248]) by bombadil.infradead.org with esmtps (Exim 4.97.1 #2 (Red Hat Linux)) id 1roo5o-00000001299-0ldC for linux-arm-kernel@lists.infradead.org; Mon, 25 Mar 2024 17:26:42 +0000 Received: from fllv0035.itg.ti.com ([10.64.41.0]) by lelv0143.ext.ti.com (8.15.2/8.15.2) with ESMTP id 42PHQL12061966; Mon, 25 Mar 2024 12:26:21 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ti.com; s=ti-com-17Q1; t=1711387581; bh=u2R75byDJ62cMgKm2V1bDaB3tq9bjRG3tOWnOwtsXzc=; h=From:To:CC:Subject:Date:In-Reply-To:References; b=aBNLEp5Wzf03RkEY1T66D4gpVGTtK8LdgGzBe9h8yOx18a92ruvv+30kgia40L0rT v+9/9VLpMJvh8+J1b0pdUSlxseUrsqy5Nvw9mwqXqTHaF46tdU+PWP1NJlDI6Yc2/D flZek70rkE0G27NBspllT+jOs/9IujN5P1m8vmLU= Received: from DLEE114.ent.ti.com (dlee114.ent.ti.com [157.170.170.25]) by fllv0035.itg.ti.com (8.15.2/8.15.2) with ESMTPS id 42PHQL8K094182 (version=TLSv1.2 cipher=AES256-GCM-SHA384 bits=256 verify=FAIL); Mon, 25 Mar 2024 12:26:21 -0500 Received: from DLEE112.ent.ti.com (157.170.170.23) by DLEE114.ent.ti.com (157.170.170.25) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2507.23; Mon, 25 Mar 2024 12:26:20 -0500 Received: from lelvsmtp5.itg.ti.com (10.180.75.250) by DLEE112.ent.ti.com (157.170.170.23) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2507.23 via Frontend Transport; Mon, 25 Mar 2024 12:26:21 -0500 Received: from lelvsmtp6.itg.ti.com ([10.249.42.149]) by lelvsmtp5.itg.ti.com (8.15.2/8.15.2) with ESMTP id 42PHQK81042985; Mon, 25 Mar 2024 12:26:20 -0500 From: Andrew Davis To: Russell King , Baruch Siach , Vladimir Zapolskiy , Masami Hiramatsu , Arnd Bergmann , Geert Uytterhoeven CC: , , Andrew Davis Subject: [PATCH v2 2/3] ARM: mach-lpc18xx: Rework support and directory structure Date: Mon, 25 Mar 2024 12:26:18 -0500 Message-ID: <20240325172619.113661-2-afd@ti.com> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20240325172619.113661-1-afd@ti.com> References: <20240325172619.113661-1-afd@ti.com> MIME-Version: 1.0 X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20240325_102640_403544_60070595 X-CRM114-Status: GOOD ( 20.91 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org Having a platform need a mach-* directory should be seen as a negative, it means the platform needs special non-standard handling. ARM64 support does not allow mach-* directories at all. While we may not get to that given all the non-standard architectures we support, we should still try to get as close as we can and reduce the number of mach directories. The mach-lpc18xx/ directory and files, provides just one "feature": having the kernel print the machine name if the DTB does not also contain a "model" string (which they always do). To reduce the number of mach-* directories let's do without that feature and remove this directory. Note the fallback machine has a default l2c_aux_mask value set to ~0, which is different than the value of 0 used when none is provided. This is safe here as this platform does not use an l2x0 cache controller. Signed-off-by: Andrew Davis --- Changes from v1: - Updated commit desc with l2c_aux_mask info - Rebased on v6.9-rc1 arch/arm/Kconfig | 11 ----------- arch/arm/Kconfig.platforms | 11 +++++++++++ arch/arm/Makefile | 1 - arch/arm/mach-lpc18xx/Makefile | 2 -- arch/arm/mach-lpc18xx/board-dt.c | 19 ------------------- 5 files changed, 11 insertions(+), 33 deletions(-) delete mode 100644 arch/arm/mach-lpc18xx/Makefile delete mode 100644 arch/arm/mach-lpc18xx/board-dt.c diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig index 9f55fd24c163a..66a16ee1ed8f1 100644 --- a/arch/arm/Kconfig +++ b/arch/arm/Kconfig @@ -459,17 +459,6 @@ source "arch/arm/mach-vt8500/Kconfig" source "arch/arm/mach-zynq/Kconfig" # ARMv7-M architecture -config ARCH_LPC18XX - bool "NXP LPC18xx/LPC43xx" - depends on ARM_SINGLE_ARMV7M - select ARCH_HAS_RESET_CONTROLLER - select ARM_AMBA - select CLKSRC_LPC32XX - select PINCTRL - help - Support for NXP's LPC18xx Cortex-M3 and LPC43xx Cortex-M4 - high performance microcontrollers. - config ARCH_MPS2 bool "ARM MPS2 platform" depends on ARM_SINGLE_ARMV7M diff --git a/arch/arm/Kconfig.platforms b/arch/arm/Kconfig.platforms index 5c19c1f2cff61..29fbed968d361 100644 --- a/arch/arm/Kconfig.platforms +++ b/arch/arm/Kconfig.platforms @@ -112,6 +112,17 @@ config ARCH_HPE_GXP endif +config ARCH_LPC18XX + bool "NXP LPC18xx/LPC43xx" + depends on ARM_SINGLE_ARMV7M + select ARCH_HAS_RESET_CONTROLLER + select ARM_AMBA + select CLKSRC_LPC32XX + select PINCTRL + help + Support for NXP's LPC18xx Cortex-M3 and LPC43xx Cortex-M4 + high performance microcontrollers. + menuconfig ARCH_MOXART bool "MOXA ART SoC" depends on ARCH_MULTI_V4 diff --git a/arch/arm/Makefile b/arch/arm/Makefile index 131778fbc6827..8da36594c2f3f 100644 --- a/arch/arm/Makefile +++ b/arch/arm/Makefile @@ -184,7 +184,6 @@ machine-$(CONFIG_ARCH_HIGHBANK) += highbank machine-$(CONFIG_ARCH_HISI) += hisi machine-$(CONFIG_ARCH_IXP4XX) += ixp4xx machine-$(CONFIG_ARCH_KEYSTONE) += keystone -machine-$(CONFIG_ARCH_LPC18XX) += lpc18xx machine-$(CONFIG_ARCH_LPC32XX) += lpc32xx machine-$(CONFIG_ARCH_MESON) += meson machine-$(CONFIG_ARCH_MMP) += mmp diff --git a/arch/arm/mach-lpc18xx/Makefile b/arch/arm/mach-lpc18xx/Makefile deleted file mode 100644 index c80d80c199d37..0000000000000 --- a/arch/arm/mach-lpc18xx/Makefile +++ /dev/null @@ -1,2 +0,0 @@ -# SPDX-License-Identifier: GPL-2.0-only -obj-y += board-dt.o diff --git a/arch/arm/mach-lpc18xx/board-dt.c b/arch/arm/mach-lpc18xx/board-dt.c deleted file mode 100644 index 4729eb83401ae..0000000000000 --- a/arch/arm/mach-lpc18xx/board-dt.c +++ /dev/null @@ -1,19 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-only -/* - * Device Tree board file for NXP LPC18xx/43xx - * - * Copyright (C) 2015 Joachim Eastwood - */ - -#include - -static const char *const lpc18xx_43xx_compat[] __initconst = { - "nxp,lpc1850", - "nxp,lpc4350", - "nxp,lpc4370", - NULL -}; - -DT_MACHINE_START(LPC18XXDT, "NXP LPC18xx/43xx (Device Tree)") - .dt_compat = lpc18xx_43xx_compat, -MACHINE_END From patchwork Mon Mar 25 17:26:19 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Andrew Davis X-Patchwork-Id: 13602567 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id EE57EC54E58 for ; Mon, 25 Mar 2024 17:27:09 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:MIME-Version:References:In-Reply-To: Message-ID:Date:Subject:CC:To:From:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; bh=H0waNK8dSaQy7TXPybkFSA2jW6wNdZnLyPKrYUM1Iyc=; b=WnGBdK40Wp+RkE mcLQYX07va2suEoMaClNgCwEKTSjf6KaPfVSgVNyd41WUE8z4u0vJx+wPE9TqUD5QTeDDiIF4PGQY DKOo2azRYYbs3yD+XopvBl9gA9qpL0KlyVIZ/W3iAW9vSFYTTilFXNtYrfM4Zgap9TPUkaY0ZVwMV wVmnulgd9adWufVDK7epVoanHdvND/xmmVmF5Kk9L2HqspgUR+we2Zhn6er1pWbs2F9IIgJPK/7ze q216tTaHfv4ElSkXMjaAQSafeayseKXaFp+Qg4JR3V+j/CLTxUfaF4T3Xm6rPkXaDMPlHJzc3v6VG gPvd9QtsocXTUh/7rMUw==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.97.1 #2 (Red Hat Linux)) id 1roo64-000000012FF-30O0; Mon, 25 Mar 2024 17:26:56 +0000 Received: from fllv0015.ext.ti.com ([198.47.19.141]) by bombadil.infradead.org with esmtps (Exim 4.97.1 #2 (Red Hat Linux)) id 1roo5q-0000000129S-0bQS for linux-arm-kernel@lists.infradead.org; Mon, 25 Mar 2024 17:26:44 +0000 Received: from fllv0034.itg.ti.com ([10.64.40.246]) by fllv0015.ext.ti.com (8.15.2/8.15.2) with ESMTP id 42PHQL5h041264; Mon, 25 Mar 2024 12:26:21 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ti.com; s=ti-com-17Q1; t=1711387581; bh=3OMPh6dmxdlpe6Hnodj4089wI8A2TXp1Am7XOmBFFKE=; h=From:To:CC:Subject:Date:In-Reply-To:References; b=ZU6vH8dCXu0KqVU/jyl+PzajEEULJVHtp4Fvi981ZH3mFZ6Gp5UbL6wEe0r7lajIf jHASJxUPdAB9WpQU7/JjWzDPBhBjqHVBk8uQ4smUBvALRZMaVfgo/SK/uO/seHeN/u xx4gTMi3g0valJUce5hhKN/HjUhkst8Te6JCR1l4= Received: from DLEE109.ent.ti.com (dlee109.ent.ti.com [157.170.170.41]) by fllv0034.itg.ti.com (8.15.2/8.15.2) with ESMTPS id 42PHQLdX109602 (version=TLSv1.2 cipher=AES256-GCM-SHA384 bits=256 verify=FAIL); Mon, 25 Mar 2024 12:26:21 -0500 Received: from DLEE115.ent.ti.com (157.170.170.26) by DLEE109.ent.ti.com (157.170.170.41) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2507.23; Mon, 25 Mar 2024 12:26:21 -0500 Received: from lelvsmtp5.itg.ti.com (10.180.75.250) by DLEE115.ent.ti.com (157.170.170.26) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2507.23 via Frontend Transport; Mon, 25 Mar 2024 12:26:21 -0500 Received: from lelvsmtp6.itg.ti.com ([10.249.42.149]) by lelvsmtp5.itg.ti.com (8.15.2/8.15.2) with ESMTP id 42PHQK82042985; Mon, 25 Mar 2024 12:26:21 -0500 From: Andrew Davis To: Russell King , Baruch Siach , Vladimir Zapolskiy , Masami Hiramatsu , Arnd Bergmann , Geert Uytterhoeven CC: , , Andrew Davis Subject: [PATCH v2 3/3] ARM: mach-ixp4xx: Rework support and directory structure Date: Mon, 25 Mar 2024 12:26:19 -0500 Message-ID: <20240325172619.113661-3-afd@ti.com> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20240325172619.113661-1-afd@ti.com> References: <20240325172619.113661-1-afd@ti.com> MIME-Version: 1.0 X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20240325_102642_623006_20030206 X-CRM114-Status: GOOD ( 21.59 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org Having a platform need a mach-* directory should be seen as a negative, it means the platform needs special non-standard handling. ARM64 support does not allow mach-* directories at all. While we may not get to that given all the non-standard architectures we support, we should still try to get as close as we can and reduce the number of mach directories. The mach-ixp4xx/ directory and files, provides just one "feature": having the kernel print the machine name if the DTB does not also contain a "model" string (which they always do). To reduce the number of mach-* directories let's do without that feature and remove this directory. Note the fallback machine has a default l2c_aux_mask value set to ~0, which is different than the value of 0 used when none is provided. This is safe here as this platform does not use an l2x0 cache controller. Signed-off-by: Andrew Davis --- Changes from v1: - Updated commit desc with l2c_aux_mask info - Rebased on v6.9-rc1 MAINTAINERS | 1 - arch/arm/Kconfig.platforms | 19 +++++++++++++++++++ arch/arm/mach-ixp4xx/Kconfig | 19 ------------------- arch/arm/mach-ixp4xx/Makefile | 2 -- arch/arm/mach-ixp4xx/ixp4xx-of.c | 22 ---------------------- 5 files changed, 19 insertions(+), 44 deletions(-) delete mode 100644 arch/arm/mach-ixp4xx/Kconfig delete mode 100644 arch/arm/mach-ixp4xx/Makefile delete mode 100644 arch/arm/mach-ixp4xx/ixp4xx-of.c diff --git a/MAINTAINERS b/MAINTAINERS index 947186f0b0c64..a0fcb6d27c0e3 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -2270,7 +2270,6 @@ F: Documentation/devicetree/bindings/memory-controllers/intel,ixp4xx-expansion* F: Documentation/devicetree/bindings/rng/intel,ixp46x-rng.yaml F: Documentation/devicetree/bindings/timer/intel,ixp4xx-timer.yaml F: arch/arm/boot/dts/intel/ixp/ -F: arch/arm/mach-ixp4xx/ F: drivers/bus/intel-ixp4xx-eb.c F: drivers/char/hw_random/ixp4xx-rng.c F: drivers/clocksource/timer-ixp4xx.c diff --git a/arch/arm/Kconfig.platforms b/arch/arm/Kconfig.platforms index 29fbed968d361..bf2185f87180c 100644 --- a/arch/arm/Kconfig.platforms +++ b/arch/arm/Kconfig.platforms @@ -112,6 +112,25 @@ config ARCH_HPE_GXP endif +config ARCH_IXP4XX + bool "IXP4xx-based platforms" + depends on ARCH_MULTI_V5 + depends on CPU_BIG_ENDIAN + select ARM_APPENDED_DTB # Old Redboot bootloaders deployed + select CPU_XSCALE + select GPIO_IXP4XX + select GPIOLIB + select FORCE_PCI + select I2C + select I2C_IOP3XX + select IXP4XX_IRQ + select IXP4XX_TIMER + select USB_EHCI_BIG_ENDIAN_DESC + select USB_EHCI_BIG_ENDIAN_MMIO + select USE_OF + help + Support for Intel's IXP4XX (XScale) family of processors. + config ARCH_LPC18XX bool "NXP LPC18xx/LPC43xx" depends on ARM_SINGLE_ARMV7M diff --git a/arch/arm/mach-ixp4xx/Kconfig b/arch/arm/mach-ixp4xx/Kconfig deleted file mode 100644 index cb46802f5ce52..0000000000000 --- a/arch/arm/mach-ixp4xx/Kconfig +++ /dev/null @@ -1,19 +0,0 @@ -# SPDX-License-Identifier: GPL-2.0-only -menuconfig ARCH_IXP4XX - bool "IXP4xx-based platforms" - depends on ARCH_MULTI_V5 - depends on CPU_BIG_ENDIAN - select ARM_APPENDED_DTB # Old Redboot bootloaders deployed - select CPU_XSCALE - select GPIO_IXP4XX - select GPIOLIB - select FORCE_PCI - select I2C - select I2C_IOP3XX - select IXP4XX_IRQ - select IXP4XX_TIMER - select USB_EHCI_BIG_ENDIAN_DESC - select USB_EHCI_BIG_ENDIAN_MMIO - select USE_OF - help - Support for Intel's IXP4XX (XScale) family of processors. diff --git a/arch/arm/mach-ixp4xx/Makefile b/arch/arm/mach-ixp4xx/Makefile deleted file mode 100644 index 3d1c9d854c7f3..0000000000000 --- a/arch/arm/mach-ixp4xx/Makefile +++ /dev/null @@ -1,2 +0,0 @@ -# SPDX-License-Identifier: GPL-2.0 -obj-y += ixp4xx-of.o diff --git a/arch/arm/mach-ixp4xx/ixp4xx-of.c b/arch/arm/mach-ixp4xx/ixp4xx-of.c deleted file mode 100644 index 1b4d84a5b02f6..0000000000000 --- a/arch/arm/mach-ixp4xx/ixp4xx-of.c +++ /dev/null @@ -1,22 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* - * IXP4xx Device Tree boot support - */ -#include - -/* - * We handle 4 different SoC families. These compatible strings are enough - * to provide the core so that different boards can add their more detailed - * specifics. - */ -static const char *ixp4xx_of_board_compat[] = { - "intel,ixp42x", - "intel,ixp43x", - "intel,ixp45x", - "intel,ixp46x", - NULL, -}; - -DT_MACHINE_START(IXP4XX_DT, "IXP4xx (Device Tree)") - .dt_compat = ixp4xx_of_board_compat, -MACHINE_END