From patchwork Tue Mar 26 14:01:04 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Johan Hovold X-Patchwork-Id: 13604238 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 101FE74C0B; Tue, 26 Mar 2024 14:01:32 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1711461693; cv=none; b=ObGC9Siezth9Z/iTu+qrWY2yWhq46/Brl1f9aA4XR/NFE7VsHWK/vXsAql0kGdjdZRMnrW7YlyMPlt5H6vg02hP5CZl00wjmEcv27ADtj0YV7T73A9iQkCmj0pyGk8oeCCLWLq7szNZx4o5IMvCquUy/I1FjXLTYLbD5nkqpV/U= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1711461693; c=relaxed/simple; bh=mSAR/ds6sNoK+caG9qPwIX3WHSQBTErTxeDXv/sxkCY=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=rz/IviagompFJOPP/+kfN4AL3BIslvwMnwjlgMdneWsCd1EdRGO8svQ2BrG/XfitOUjD2aiTaq/fw4LZr0psr/sXtK6y5L4E//pZ43IYkBv9XZxwUolV/iQB32Zzu7BGNn+CgaVtb9StLMhmVbdnVRzBLARq9aqMI0WqgRRLej4= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=pyWCR6rB; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="pyWCR6rB" Received: by smtp.kernel.org (Postfix) with ESMTPSA id 95F84C433F1; Tue, 26 Mar 2024 14:01:32 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1711461692; bh=mSAR/ds6sNoK+caG9qPwIX3WHSQBTErTxeDXv/sxkCY=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=pyWCR6rBVaxhyy3gtY2q/5fsuIadAnK7pf/x0bZfKqvCGfKwq+jbgeURiklGKsSWP MGwa31t2xVfbOiDESji2/FZhKhSys8WDdCopOCWJPWW/Ae9XxCFPnPGHsK0TCmsld9 /cKMMJZFdVg/DJfw3C9sGkYFASlW4Bq0HvuxBLUT5p86AzHbZhlBS5D52ZQc+WITXH fwRRb9uRejd5BKsuBF1jMr7KeHkzzRdes2aWMHn4aWMBdYjfHowWx4MLjdZlFrIT+7 rK08Ll/nRqB7yEHCxWpM9ia+kqUSPg+8ujiK0LjhC8kTo0qkoKMBrEUq4fJP8qpITY rbH1TGqg/sLYg== Received: from johan by xi.lan with local (Exim 4.97.1) (envelope-from ) id 1rp7My-000000005Yp-37IP; Tue, 26 Mar 2024 15:01:40 +0100 From: Johan Hovold To: Bjorn Andersson Cc: Konrad Dybcio , Michael Turquette , Stephen Boyd , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Mark Brown , Dmitry Baryshkov , linux-arm-msm@vger.kernel.org, linux-clk@vger.kernel.org, linux-kernel@vger.kernel.org, Johan Hovold Subject: [PATCH 1/5] dt-bindings: clock: qcom: add SA8540P gpucc Date: Tue, 26 Mar 2024 15:01:04 +0100 Message-ID: <20240326140108.21307-2-johan+linaro@kernel.org> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20240326140108.21307-1-johan+linaro@kernel.org> References: <20240326140108.21307-1-johan+linaro@kernel.org> Precedence: bulk X-Mailing-List: linux-arm-msm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 The SA8540P platform is closely related to SC8280XP but differs in that it uses an external supply for the GX power domain. Add a new compatible string for the SA8540P GPU clock controller so that the OS can determine which resources to look for. Fixes: e60b95d2b687 ("dt-bindings: clock: qcom: Allow VDD_GFX supply to GX") Signed-off-by: Johan Hovold --- Documentation/devicetree/bindings/clock/qcom,gpucc.yaml | 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/clock/qcom,gpucc.yaml b/Documentation/devicetree/bindings/clock/qcom,gpucc.yaml index f57aceddac6b..5b385e4976b6 100644 --- a/Documentation/devicetree/bindings/clock/qcom,gpucc.yaml +++ b/Documentation/devicetree/bindings/clock/qcom,gpucc.yaml @@ -28,6 +28,7 @@ properties: compatible: enum: - qcom,sdm845-gpucc + - qcom,sa8540p-gpucc - qcom,sa8775p-gpucc - qcom,sc7180-gpucc - qcom,sc7280-gpucc From patchwork Tue Mar 26 14:01:05 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Johan Hovold X-Patchwork-Id: 13604241 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 102B375806; Tue, 26 Mar 2024 14:01:32 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1711461693; cv=none; b=mTZrJ6ZbVpbVBdKzEKyTTILtamxArQrHXYtlSyxaTFopkGNHode0ugBuW5q+S/XAKupPm7P+t3k/7/9ZGjnFJySvgF5vcVNfkKjCwBNFheCt55l4sCo0TfnPjl1v4Jr9AajgdkF2R539hUPrPUqUsdqkzk83oDneUpgEBwZY0Zs= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1711461693; c=relaxed/simple; bh=yz4Tw4H/56nETqXKR1UOj4GtHTZDq3JA8OzpkBRqe+c=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=UCxbKWNm/0s1icjmlnSPAxygojWbPyt+YfIxpRtLYspzlLjgRgkgmSHJTLvAMk8GDpsG91tinCMcr6WCWGrljNQEcG60TtphYkI4M7OjU6ajRjskh5Cg6274TGtRg3pWSXUHpsLK4wAu2zAMsa5Oh4zPkI/pc0BM/6aFnV62ISA= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=HEAw18pT; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="HEAw18pT" Received: by smtp.kernel.org (Postfix) with ESMTPSA id A4673C43399; Tue, 26 Mar 2024 14:01:32 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1711461692; bh=yz4Tw4H/56nETqXKR1UOj4GtHTZDq3JA8OzpkBRqe+c=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=HEAw18pTYLJaYmZyq5gRSq+pnu16Uc6Bt6e+P0nEyiQTXO2qzcq0LG+eLR2gd9Sls 0RUA2Np3QPYdEGdlfW4zwxwEmGe1VLGpAB51cYxW0TWkGdY11tcHfLV5eR3ozeqNLd euGgktPEcr8Uq6+a195UF54987YoPj9OKI9gdJEow11I5w+op8DczisLxhSIffWXct W5vMzZTzhg45bjR4sfy71xiYmyCsO7mXr0xRXcR+auJBT9QnDQoAhAgCqySoqBz1id XchLCb4YUb+A8kJ1joOoXS6RvWMxMJckMygWvtnvCOwAwNVORu3d42/9T2+v98+5RF tEewqYiJkS/ug== Received: from johan by xi.lan with local (Exim 4.97.1) (envelope-from ) id 1rp7My-000000005Yr-3Rkg; Tue, 26 Mar 2024 15:01:40 +0100 From: Johan Hovold To: Bjorn Andersson Cc: Konrad Dybcio , Michael Turquette , Stephen Boyd , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Mark Brown , Dmitry Baryshkov , linux-arm-msm@vger.kernel.org, linux-clk@vger.kernel.org, linux-kernel@vger.kernel.org, Johan Hovold Subject: [PATCH 2/5] arm64: dts: qcom: sa8540p: use sa8540p gpucc compatible Date: Tue, 26 Mar 2024 15:01:05 +0100 Message-ID: <20240326140108.21307-3-johan+linaro@kernel.org> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20240326140108.21307-1-johan+linaro@kernel.org> References: <20240326140108.21307-1-johan+linaro@kernel.org> Precedence: bulk X-Mailing-List: linux-arm-msm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 The SA8540P platform is closely related to SC8280XP but differs in that it uses an external supply for the GX power domain. Use the new SA8540P compatible string for the GPU clock controller so that the OS can determine which resources to look for. Note that a fallback SC8280XP compatible is added temporarily to avoid any temporary regressions for sa8295p-adp. Fixes: fd5821a1a83c ("arm64: dts: qcom: sa8540p: Drop gfx.lvl as power-domain for gpucc") Signed-off-by: Johan Hovold --- arch/arm64/boot/dts/qcom/sa8540p.dtsi | 2 ++ 1 file changed, 2 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sa8540p.dtsi b/arch/arm64/boot/dts/qcom/sa8540p.dtsi index 23888029cc11..3b31a9ea3492 100644 --- a/arch/arm64/boot/dts/qcom/sa8540p.dtsi +++ b/arch/arm64/boot/dts/qcom/sa8540p.dtsi @@ -168,6 +168,8 @@ opp-2592000000 { }; &gpucc { + compatible = "qcom,sa8540p-gpucc", "qcom,sc8280xp-gpucc"; + /* SA8295P and SA8540P doesn't provide gfx.lvl */ /delete-property/ power-domains; From patchwork Tue Mar 26 14:01:06 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Johan Hovold X-Patchwork-Id: 13604240 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 1027C757FD; Tue, 26 Mar 2024 14:01:32 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1711461693; cv=none; b=bHs1hWYhhHF9C39TlcPTN2Unht1JKH50SS688jwXp2dtllEj9eIY4Fvo3CzJH4NTpOSUtd7MZmN6BiqbZsejBhDBkmumVsbdR8tpYk5lVK7HAh/GRaib+XH3NGpNwcqpbV9hfFDx80tEy/GoHHKKOb6MZhBeHGf5hVeW8iykOzM= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1711461693; c=relaxed/simple; bh=sshlJawg659jSJfqUQ6B4XGmjcjFXGGOIn2jUhaVb9U=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=WRUJX+BegCfF1lcxXDbx5jloShuszyi9gbB6Dw3zUNzwuIWooDacBqQb+UKauIrtea7uxVXAr1UiiceBPtZQ+mdNcES4rOaFg6r0MsE7p7ZlB+VM1fadlSKPsSyJBoDYQ/+w8qdsem6G69Y6PfroRJWwdm7/NjScKZsyMIC/DPw= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=rKVoACsQ; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="rKVoACsQ" Received: by smtp.kernel.org (Postfix) with ESMTPSA id A7B8BC433A6; Tue, 26 Mar 2024 14:01:32 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1711461692; bh=sshlJawg659jSJfqUQ6B4XGmjcjFXGGOIn2jUhaVb9U=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=rKVoACsQNc8saXiMROuxFyNJiPoe+4lapP5s6rohMVryogcSykeied/MZMn4lTjAy xGmUFXVigXSJwQoLZPR+7NLHcJ0Y2IVdEiUGt4tnrSSqdTi/kgarFjpIxjnHOkt6NP m3q5Xmq0sGpbr+ljYdR0bzUSrrWSgFEYPtndnKooQmHAj9EbfqjNuppmHgvvNZugGj vjCA+R+OJkgj0IpKMGmAtv09fcYaUds9Phi6ttscTbN2AFCYnAazff54S/Q+dDgcbY gunLiHCOaWHABdrAGB3gw0zc/ZJFyHl98X1B+XDAkcJkOGw5SAtKgGSlHPIUc6f8id iXlK71+UD2jDA== Received: from johan by xi.lan with local (Exim 4.97.1) (envelope-from ) id 1rp7My-000000005Yt-3rXx; Tue, 26 Mar 2024 15:01:40 +0100 From: Johan Hovold To: Bjorn Andersson Cc: Konrad Dybcio , Michael Turquette , Stephen Boyd , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Mark Brown , Dmitry Baryshkov , linux-arm-msm@vger.kernel.org, linux-clk@vger.kernel.org, linux-kernel@vger.kernel.org, Johan Hovold Subject: [PATCH 3/5] clk: qcom: gpucc-sc8280xp: make cc descriptor const Date: Tue, 26 Mar 2024 15:01:06 +0100 Message-ID: <20240326140108.21307-4-johan+linaro@kernel.org> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20240326140108.21307-1-johan+linaro@kernel.org> References: <20240326140108.21307-1-johan+linaro@kernel.org> Precedence: bulk X-Mailing-List: linux-arm-msm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Add the missing 'const' keyword to mark the Qualcomm clock controller descriptor data as constant. Signed-off-by: Johan Hovold Reviewed-by: Konrad Dybcio --- drivers/clk/qcom/gpucc-sc8280xp.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/clk/qcom/gpucc-sc8280xp.c b/drivers/clk/qcom/gpucc-sc8280xp.c index 3611d2d1823d..df6b01768767 100644 --- a/drivers/clk/qcom/gpucc-sc8280xp.c +++ b/drivers/clk/qcom/gpucc-sc8280xp.c @@ -415,7 +415,7 @@ static const struct regmap_config gpu_cc_sc8280xp_regmap_config = { .fast_io = true, }; -static struct qcom_cc_desc gpu_cc_sc8280xp_desc = { +static const struct qcom_cc_desc gpu_cc_sc8280xp_desc = { .config = &gpu_cc_sc8280xp_regmap_config, .clks = gpu_cc_sc8280xp_clocks, .num_clks = ARRAY_SIZE(gpu_cc_sc8280xp_clocks), From patchwork Tue Mar 26 14:01:07 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Johan Hovold X-Patchwork-Id: 13604237 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 101B374BF7; Tue, 26 Mar 2024 14:01:32 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1711461693; cv=none; b=lwbbspPXZ9Y6e491b36Nxx0nGgBSmJdPkOiW4a4siMLJiqTkotSUTxzYl6y9uBABXDx9ICCGjwGOjsi9PU7qRKO2L78ND9QV+f4sKF0k4+IlfP61nVoC3ZIL+gi+SP9n/iYWT/55cRLVzLhfYxlMfTvaIs5rM+AzWi4hjN3L2HM= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1711461693; c=relaxed/simple; bh=YduINrvbMOueuJqN2WQd7cwXtw1eGBZDNUU5mHMNzIY=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=fEPxj8XIz4+7lGSXUbs/0jHSVLZ1pQo7qyFNXtSRhkJdYb30owsqy8YJANUJ+lndsBBGyvQ2R3eHAN5O+KrBJvV/zCSUNwnqXJ6M5yhaxZn90DC+wTap1ezIoQbKODZH6OUXUp8wTSImFRu5qeXeGe+YlhYKFYdltNSaBJrjR3s= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=NQagXrOk; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="NQagXrOk" Received: by smtp.kernel.org (Postfix) with ESMTPSA id A11A5C433C7; Tue, 26 Mar 2024 14:01:32 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1711461692; bh=YduINrvbMOueuJqN2WQd7cwXtw1eGBZDNUU5mHMNzIY=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=NQagXrOkDJ2nzKNDuwk6S4AAezeSSR8JOpJLcaLy8rgL47JDF4P8jAZY3nCet63x9 zU0jkCBKKXH6jWvEmYpycxC0Z/NVwVADNCoQDQxdjOibYv4Neamv1rwVUfAzoDYzhj fKgr+wqgcE5mbXP4sn4xkdjUZdzioZib1KiASBiVDGHWlAT1Ke41nnSpMHYJfQpCgr W7e3h7Tqsg0LsKGsWrWy4HBmI3JplnsITQm0NK98D5+k2+X2B462hg/IdETJxzRdnK wJthC9ChHQ9v3VwZ7MkbZ0RENxGDW4Aual8D2O0DMLWbTbZ8tdDXucUkHEode64xyM 5KTsBeKu1XaWg== Received: from johan by xi.lan with local (Exim 4.97.1) (envelope-from ) id 1rp7Mz-000000005Yv-00Jt; Tue, 26 Mar 2024 15:01:41 +0100 From: Johan Hovold To: Bjorn Andersson Cc: Konrad Dybcio , Michael Turquette , Stephen Boyd , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Mark Brown , Dmitry Baryshkov , linux-arm-msm@vger.kernel.org, linux-clk@vger.kernel.org, linux-kernel@vger.kernel.org, Johan Hovold Subject: [PATCH 4/5] clk: qcom: gpucc-sc8280xp: fix GX external supply lookup Date: Tue, 26 Mar 2024 15:01:07 +0100 Message-ID: <20240326140108.21307-5-johan+linaro@kernel.org> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20240326140108.21307-1-johan+linaro@kernel.org> References: <20240326140108.21307-1-johan+linaro@kernel.org> Precedence: bulk X-Mailing-List: linux-arm-msm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 The SA8540P platform is closely related to SC8280XP but differs in that it uses an external supply for the GX power domain. Use the new SA8540P compatible to determine whether to look up the external supply. This specifically avoids warnings such as: gpu_cc-sc8280xp 3d90000.clock-controller: supply vdd-gfx not found, using dummy regulator on SC8280XP. Note that this also avoids triggering a potential deadlock on SC8280XP even if the underlying issue still remains for the derivative platforms like SA8540P and SA8295P that actually use the supply. Fixes: deebc79b28d6 ("clk: qcom: gpucc-sc8280xp: Add external supply for GX gdsc") Link: https://lore.kernel.org/lkml/Zf25Sv2x9WaCFuIH@hovoldconsulting.com/ Signed-off-by: Johan Hovold --- drivers/clk/qcom/gpucc-sc8280xp.c | 40 +++++++++++++++++++++++++++---- 1 file changed, 35 insertions(+), 5 deletions(-) diff --git a/drivers/clk/qcom/gpucc-sc8280xp.c b/drivers/clk/qcom/gpucc-sc8280xp.c index df6b01768767..48a2e8df14f2 100644 --- a/drivers/clk/qcom/gpucc-sc8280xp.c +++ b/drivers/clk/qcom/gpucc-sc8280xp.c @@ -390,7 +390,7 @@ static struct gdsc cx_gdsc = { .flags = VOTABLE | RETAIN_FF_ENABLE, }; -static struct gdsc gx_gdsc = { +static struct gdsc sa8540p_gx_gdsc = { .gdscr = 0x100c, .clamp_io_ctrl = 0x1508, .pd = { @@ -402,9 +402,25 @@ static struct gdsc gx_gdsc = { .supply = "vdd-gfx", }; +static struct gdsc sc8280xp_gx_gdsc = { + .gdscr = 0x100c, + .clamp_io_ctrl = 0x1508, + .pd = { + .name = "gx_gdsc", + .power_on = gdsc_gx_do_nothing_enable, + }, + .pwrsts = PWRSTS_OFF_ON, + .flags = CLAMP_IO | RETAIN_FF_ENABLE, +}; + +static struct gdsc *gpu_cc_sa8540p_gdscs[] = { + [GPU_CC_CX_GDSC] = &cx_gdsc, + [GPU_CC_GX_GDSC] = &sa8540p_gx_gdsc, +}; + static struct gdsc *gpu_cc_sc8280xp_gdscs[] = { [GPU_CC_CX_GDSC] = &cx_gdsc, - [GPU_CC_GX_GDSC] = &gx_gdsc, + [GPU_CC_GX_GDSC] = &sc8280xp_gx_gdsc, }; static const struct regmap_config gpu_cc_sc8280xp_regmap_config = { @@ -415,6 +431,14 @@ static const struct regmap_config gpu_cc_sc8280xp_regmap_config = { .fast_io = true, }; +static const struct qcom_cc_desc gpu_cc_sa8540p_desc = { + .config = &gpu_cc_sc8280xp_regmap_config, + .clks = gpu_cc_sc8280xp_clocks, + .num_clks = ARRAY_SIZE(gpu_cc_sc8280xp_clocks), + .gdscs = gpu_cc_sa8540p_gdscs, + .num_gdscs = ARRAY_SIZE(gpu_cc_sa8540p_gdscs), +}; + static const struct qcom_cc_desc gpu_cc_sc8280xp_desc = { .config = &gpu_cc_sc8280xp_regmap_config, .clks = gpu_cc_sc8280xp_clocks, @@ -425,9 +449,14 @@ static const struct qcom_cc_desc gpu_cc_sc8280xp_desc = { static int gpu_cc_sc8280xp_probe(struct platform_device *pdev) { + const struct qcom_cc_desc *desc; struct regmap *regmap; int ret; + desc = of_device_get_match_data(&pdev->dev); + if (!desc) + return -EINVAL; + ret = devm_pm_runtime_enable(&pdev->dev); if (ret) return ret; @@ -436,7 +465,7 @@ static int gpu_cc_sc8280xp_probe(struct platform_device *pdev) if (ret) return ret; - regmap = qcom_cc_map(pdev, &gpu_cc_sc8280xp_desc); + regmap = qcom_cc_map(pdev, desc); if (IS_ERR(regmap)) { pm_runtime_put(&pdev->dev); return PTR_ERR(regmap); @@ -449,14 +478,15 @@ static int gpu_cc_sc8280xp_probe(struct platform_device *pdev) qcom_branch_set_clk_en(regmap, 0x1170); /* GPU_CC_CB_CLK */ qcom_branch_set_clk_en(regmap, 0x109c); /* GPU_CC_CXO_CLK */ - ret = qcom_cc_really_probe(pdev, &gpu_cc_sc8280xp_desc, regmap); + ret = qcom_cc_really_probe(pdev, desc, regmap); pm_runtime_put(&pdev->dev); return ret; } static const struct of_device_id gpu_cc_sc8280xp_match_table[] = { - { .compatible = "qcom,sc8280xp-gpucc" }, + { .compatible = "qcom,sa8540p-gpucc", &gpu_cc_sa8540p_desc }, + { .compatible = "qcom,sc8280xp-gpucc", &gpu_cc_sc8280xp_desc }, { } }; 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Tue, 26 Mar 2024 15:01:41 +0100 From: Johan Hovold To: Bjorn Andersson Cc: Konrad Dybcio , Michael Turquette , Stephen Boyd , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Mark Brown , Dmitry Baryshkov , linux-arm-msm@vger.kernel.org, linux-clk@vger.kernel.org, linux-kernel@vger.kernel.org, Johan Hovold Subject: [PATCH 5/5] arm64: dts: qcom: sa8540p: drop fallback gpucc compatible Date: Tue, 26 Mar 2024 15:01:08 +0100 Message-ID: <20240326140108.21307-6-johan+linaro@kernel.org> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20240326140108.21307-1-johan+linaro@kernel.org> References: <20240326140108.21307-1-johan+linaro@kernel.org> Precedence: bulk X-Mailing-List: linux-arm-msm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Drop the fallback SC8280XP GPU clock controller compatible that was added temporarily to handle the transition to the new SA8540P compatible. Signed-off-by: Johan Hovold --- arch/arm64/boot/dts/qcom/sa8540p.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/qcom/sa8540p.dtsi b/arch/arm64/boot/dts/qcom/sa8540p.dtsi index 3b31a9ea3492..9c2e99d30d08 100644 --- a/arch/arm64/boot/dts/qcom/sa8540p.dtsi +++ b/arch/arm64/boot/dts/qcom/sa8540p.dtsi @@ -168,7 +168,7 @@ opp-2592000000 { }; &gpucc { - compatible = "qcom,sa8540p-gpucc", "qcom,sc8280xp-gpucc"; + compatible = "qcom,sa8540p-gpucc"; /* SA8295P and SA8540P doesn't provide gfx.lvl */ /delete-property/ power-domains;