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[2001:b400:e383:3566:13c:5a87:9abc:381e]) by smtp.gmail.com with ESMTPSA id h12-20020a170902eecc00b001e0501d3058sm8356848plb.63.2024.03.27.01.53.37 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 27 Mar 2024 01:53:40 -0700 (PDT) From: Peter Yin To: patrick@stwcx.xyz, Wim Van Sebroeck , Guenter Roeck , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Joel Stanley , Andrew Jeffery , linux-watchdog@vger.kernel.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-aspeed@lists.ozlabs.org, linux-kernel@vger.kernel.org Subject: [PATCH v4 1/4] ARM: dts: aspeed: Add the AST2500 WDT with SCU register Date: Wed, 27 Mar 2024 16:53:27 +0800 Message-Id: <20240327085330.3281697-2-peteryin.openbmc@gmail.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20240327085330.3281697-1-peteryin.openbmc@gmail.com> References: <20240327085330.3281697-1-peteryin.openbmc@gmail.com> Precedence: bulk X-Mailing-List: linux-watchdog@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 The AST2500 WDT references the System Control Unit register for its operation. Signed-off-by: Peter Yin --- arch/arm/boot/dts/aspeed/aspeed-g5.dtsi | 3 +++ 1 file changed, 3 insertions(+) diff --git a/arch/arm/boot/dts/aspeed/aspeed-g5.dtsi b/arch/arm/boot/dts/aspeed/aspeed-g5.dtsi index 04f98d1dbb97..5fd12c057c31 100644 --- a/arch/arm/boot/dts/aspeed/aspeed-g5.dtsi +++ b/arch/arm/boot/dts/aspeed/aspeed-g5.dtsi @@ -410,12 +410,14 @@ wdt1: watchdog@1e785000 { compatible = "aspeed,ast2500-wdt"; reg = <0x1e785000 0x20>; clocks = <&syscon ASPEED_CLK_APB>; + aspeed,scu = <&syscon>; }; wdt2: watchdog@1e785020 { compatible = "aspeed,ast2500-wdt"; reg = <0x1e785020 0x20>; clocks = <&syscon ASPEED_CLK_APB>; + aspeed,scu = <&syscon>; }; wdt3: watchdog@1e785040 { @@ -423,6 +425,7 @@ wdt3: watchdog@1e785040 { reg = <0x1e785040 0x20>; clocks = <&syscon ASPEED_CLK_APB>; status = "disabled"; + aspeed,scu = <&syscon>; }; pwm_tacho: pwm-tacho-controller@1e786000 { From patchwork Wed Mar 27 08:53:28 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: PeterYin X-Patchwork-Id: 13605970 Received: from mail-pl1-f180.google.com (mail-pl1-f180.google.com [209.85.214.180]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 8B12B381C7; Wed, 27 Mar 2024 08:53:45 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.214.180 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1711529626; cv=none; b=EjOCTBCKuX2PB42lDj+TQIVFnPjEf8Sj69ERITfJ7Mewqpv4zxIk/vRBO105qGVe+9OnBomFl9ZQkvN4QUulSiNP+jLWItTJP53RAFAtLeQoNYMmeGrLbEhowgXJvihGtTpoAyhMdJ0gG5tzhTaJKt9sQ1mEA91Oq92a7ww7aSA= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1711529626; c=relaxed/simple; bh=OmbQeEpYAXewoGuDq+EgMFX3vG7k0YYOmneTwe9coEE=; h=From:To:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=AQ9Vi1jX8grtZ0E0X0RZdga3I9IO7gYYJE2xYV7ulzABPodkKQE/rll1HZ20BqU9D0wwwO/6ga3nDOPeDFOUVPXfol/+uZaIaoUsk4ATdEiHeSDODE0T+zKl5TQonFvN2DcPAR9KgnN3EGcuwWkCPJw2aiKEBWAuioqZiVquo60= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=gmail.com; spf=pass smtp.mailfrom=gmail.com; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b=Q8kVElcV; arc=none smtp.client-ip=209.85.214.180 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=gmail.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=gmail.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b="Q8kVElcV" Received: by mail-pl1-f180.google.com with SMTP id d9443c01a7336-1e0d6356ce9so21811645ad.3; Wed, 27 Mar 2024 01:53:45 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20230601; t=1711529625; x=1712134425; darn=vger.kernel.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:from:to:cc:subject:date:message-id :reply-to; bh=dNSpu6YM8BptgR2qjrv8QihJHcI+7VsMuE3/EFlGmdw=; b=Q8kVElcV/XFrGp0HVllKUnRVNST6F1VeaOh1n7YQPd1rQbS1REqUycbRlikR8A9Taq FWNsikCTsaALOQM/z+wyi3cAQWhCEfaRJeEVrrwNCD6nXRj1YVR5LBZt6ZpEVzOsEhUO HH7hy/4x4FcrRIUe+9faNxP42thMZIB2uhJPHVlC1t7pZ7zdojPZW3Wj3pe+ywzrJgF4 TSeWzqTsLMwuhXqD0xWivwWL0reJk6ML7JBZ2Yvo6ac7hAkDMLbdqpfTmoCgvCzFqvKo 7BCfs4OZHO6rHBztE1yMSs6W6FVuMLIPNm8paD9nFf+UJP59lkFEn4a+2LuLe9sDOMaC irBA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1711529625; x=1712134425; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=dNSpu6YM8BptgR2qjrv8QihJHcI+7VsMuE3/EFlGmdw=; b=vL/VdMG+JRhbLLuwbWZZhVuchSSEREz0onYDrKgj+NzaxWV3emB+IiPx5ogfaMRomV z2hJkEjLWlCSAuFORS4RXLWBAZs/vIEy9aQOUoqEMFEwmudPckZwE7tTGXxrLSKebCO1 2WfASppYzFPqZStiRLRJVgFczkNenfTU37mMBQIOj8Tj1hw8Fmf2ZmjjqkgToyA9Q6nY aC9Nn6sWMjoHh7SEKA4S57mNQiLPPn7thwGkWBjM8eDWzbPu7Jh41vDWhHPccQrMz+Ef d6k3ZH2rtL6/RtEI3JsD7kVbgmvrt10D3oktsIFttqIsyzJavVsv7Oqcfn0ubT6f8Bkx bxLQ== X-Forwarded-Encrypted: i=1; AJvYcCWsrCmXrL2EaTPZf1e6Me/HyIq/ZanV/VQ1wSzpZ/mkSZ8/ALPK3QcW3fCkf3ZX9Py9LFEFd2U3VLFjWtPZY9RQxsroLcPTs6jMYQzOjxfo+sRoYSmh+iWxB6j9G2ZUGehWwmfVqRb8j7joflX2wYLx/xX+HaEvHZ17ZYeysOnmtqtvwF/dwkud X-Gm-Message-State: AOJu0Yzxc0ps/DK6zK6KHyZAW2EFTs34J/G5IWA8MsUPrETEWHFsGv61 DZFE+R6OqTW5M7iqGKHhWMgpr1RXpgKW6TwnqtL3I64DDCDFCgsF X-Google-Smtp-Source: AGHT+IHn+z3k+py4UVKTT73n+eHw2Es3sDNz128MEDJ3zzb3n/dn1oWz8gRzbMhU0oCuzm6/uIBFXg== X-Received: by 2002:a17:903:2a8e:b0:1e0:294f:17d3 with SMTP id lv14-20020a1709032a8e00b001e0294f17d3mr660549plb.5.1711529624925; Wed, 27 Mar 2024 01:53:44 -0700 (PDT) Received: from peter-bmc.dhcpserver.bu9bmc.local (2001-b400-e383-3566-013c-5a87-9abc-381e.emome-ip6.hinet.net. [2001:b400:e383:3566:13c:5a87:9abc:381e]) by smtp.gmail.com with ESMTPSA id h12-20020a170902eecc00b001e0501d3058sm8356848plb.63.2024.03.27.01.53.41 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 27 Mar 2024 01:53:44 -0700 (PDT) From: Peter Yin To: patrick@stwcx.xyz, Wim Van Sebroeck , Guenter Roeck , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Joel Stanley , Andrew Jeffery , linux-watchdog@vger.kernel.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-aspeed@lists.ozlabs.org, linux-kernel@vger.kernel.org Subject: [PATCH v4 2/4] ARM: dts: aspeed: Add the AST2600 WDT with SCU register Date: Wed, 27 Mar 2024 16:53:28 +0800 Message-Id: <20240327085330.3281697-3-peteryin.openbmc@gmail.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20240327085330.3281697-1-peteryin.openbmc@gmail.com> References: <20240327085330.3281697-1-peteryin.openbmc@gmail.com> Precedence: bulk X-Mailing-List: linux-watchdog@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 The AST2600 Watchdog Timer (WDT) references the System Control Unit (SCU) register for its operation. Signed-off-by: Peter Yin --- arch/arm/boot/dts/aspeed/aspeed-g6.dtsi | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/arch/arm/boot/dts/aspeed/aspeed-g6.dtsi b/arch/arm/boot/dts/aspeed/aspeed-g6.dtsi index 5f640b7d6b6d..2f7788f2f153 100644 --- a/arch/arm/boot/dts/aspeed/aspeed-g6.dtsi +++ b/arch/arm/boot/dts/aspeed/aspeed-g6.dtsi @@ -558,23 +558,27 @@ uart5: serial@1e784000 { wdt1: watchdog@1e785000 { compatible = "aspeed,ast2600-wdt"; reg = <0x1e785000 0x40>; + aspeed,scu = <&syscon>; }; wdt2: watchdog@1e785040 { compatible = "aspeed,ast2600-wdt"; reg = <0x1e785040 0x40>; + aspeed,scu = <&syscon>; status = "disabled"; }; wdt3: watchdog@1e785080 { compatible = "aspeed,ast2600-wdt"; reg = <0x1e785080 0x40>; + aspeed,scu = <&syscon>; status = "disabled"; }; wdt4: watchdog@1e7850c0 { compatible = "aspeed,ast2600-wdt"; reg = <0x1e7850C0 0x40>; + aspeed,scu = <&syscon>; status = "disabled"; }; From patchwork Wed Mar 27 08:53:29 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: PeterYin X-Patchwork-Id: 13605971 Received: from mail-pl1-f177.google.com (mail-pl1-f177.google.com [209.85.214.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id DD6E138F91; Wed, 27 Mar 2024 08:53:49 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.214.177 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1711529631; cv=none; b=I62Kp53+rQvnO4tbxHDZZF8ewoAQjSxd+lIlQaYvUItES33ORJ+uPBigh0tcyeqItqDant8Soy2wXMZeQR4CzhsWwTu1gKAGbWegNqikdeHNZH99dfy71orzHiir51wJqmfen0SiVOEDEpZWVFq8OTm6od8mYSomXw8PvN4eJ1M= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1711529631; c=relaxed/simple; bh=uZfnDGW6R8YxxzhmPXNOoQ4C6Vi6QB/c1rE2mdl1BHU=; h=From:To:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=dkZT7Cbq95K4X2w1UAK/5NoMSSMzwU86c9Gkt9EeLWYmzwiJDxjBeK8s4Ww0Ayr8ndLrZlguHB+N9CXc2ViqqR9dCzy+Cr+XzdLlTuWsExhG2VwpsUxSUop3SUMfiP/MhHL9QYEHV3IioZQibkSH0yqfBcBSLsNjrN5oftMtCQw= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=gmail.com; spf=pass smtp.mailfrom=gmail.com; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b=g+JwgNcr; arc=none smtp.client-ip=209.85.214.177 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=gmail.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=gmail.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b="g+JwgNcr" Received: by mail-pl1-f177.google.com with SMTP id d9443c01a7336-1e0189323b4so50458795ad.1; Wed, 27 Mar 2024 01:53:49 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20230601; t=1711529629; x=1712134429; darn=vger.kernel.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:from:to:cc:subject:date:message-id :reply-to; bh=b9G+01fnYmsgdrsm4iyF3y0ufJf0ihC4vR7iu7tY8Oc=; b=g+JwgNcrp1VEMApevgQF3DomfW5mmrx6DmKYn/UCuf6Q90bHKjfQ6CC9s85AOuhxPw bgh0KO9asDOHJHU72KhKnOAhBhC7uC3jhS0Wn2iE1ubHOtVJ4uRT+bkfDNTmXAXMjbew XtCeLVc5lRENVR297RZ+AtIYfdsbHb+nl9vlXaOfnasyUd+bPdr1f3e/7+N4mNdCgHLl TcR17rpe5Gla8Pyb9Hls5IMJ4FpVKU527Iljctycj50Q0eNQYF8fXNA8mitl2MAfnXL3 GObHSG1NNsHwU07PM9h3MrYEOdHVPrQrE6KYJ2NpFuYRbfZpZlA+FliA66BSS2KgfTyx W9dA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1711529629; x=1712134429; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=b9G+01fnYmsgdrsm4iyF3y0ufJf0ihC4vR7iu7tY8Oc=; b=ozuNaZrZRF1iJwqW0jbZadzA1aG4L3PdnrJJZFzr3zjFvtXBNAOlpX1T9szhZjKFCo g2ztrejudocrWcD+czYFayRxXA0w9qWIFlcY8UsIH24L+ZO4FU52u9UB7f8qdfxl5AoO ET6K8ctNbQzJqZtd0qjez0HrdEtzfn1ZV56NM0joZ+27sbdxoMmKkhCxwLg3qtA9Ve70 3meOZYBSrDJQJgQbhIg2OZ81XNREbv7rW9yjEQNyJmbjxk7jscfJQxVctESAHG+Oi00S U8ij9uRJCRjMS9ILDrXo7+b0HEqA7ofu/+/+D+jxFRkcEb6TKOTnDFK3K39gfegx/I6v 9/UA== X-Forwarded-Encrypted: i=1; AJvYcCUyhY9ss2Oh0epFAXiBdY15bgFGMwTsJtJFfsoQR6tqPVWrxA9I4/fHB3muLuJOU8PqaKPr2QTkfO24Z4ZZ6WL3sLiv7QJdeK2KpxhLpe+O/pnqIQQFuzS+o8bQ4Wu5zWbvDuoNpMNNcZVAMwD/GM91lYfcqjllqGODcuP+59SFUi+4qvKvdEgf X-Gm-Message-State: AOJu0YzwluFAdBRRUoJegbWV/8715/7j/d/t51iZySseHytmmigYj++F JxkrYis4grEowsPRo2YF0KgvP8PqMghJnIXNpBrbSRvS5+8vDwjR X-Google-Smtp-Source: AGHT+IHMtf+g4HCFGxUFbq7vGIja15S+RN2FfG532r/JlKdvx3ne3MqOCeZu8bYoa6cKVVkgxKSGoQ== X-Received: by 2002:a17:902:a3c6:b0:1de:e5aa:5ce with SMTP id q6-20020a170902a3c600b001dee5aa05cemr1931176plb.41.1711529629258; Wed, 27 Mar 2024 01:53:49 -0700 (PDT) Received: from peter-bmc.dhcpserver.bu9bmc.local (2001-b400-e383-3566-013c-5a87-9abc-381e.emome-ip6.hinet.net. [2001:b400:e383:3566:13c:5a87:9abc:381e]) by smtp.gmail.com with ESMTPSA id h12-20020a170902eecc00b001e0501d3058sm8356848plb.63.2024.03.27.01.53.45 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 27 Mar 2024 01:53:48 -0700 (PDT) From: Peter Yin To: patrick@stwcx.xyz, Wim Van Sebroeck , Guenter Roeck , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Joel Stanley , Andrew Jeffery , linux-watchdog@vger.kernel.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-aspeed@lists.ozlabs.org, linux-kernel@vger.kernel.org Subject: [PATCH v4 3/4] dt-bindings: watchdog: aspeed-wdt: Add aspeed,scu Date: Wed, 27 Mar 2024 16:53:29 +0800 Message-Id: <20240327085330.3281697-4-peteryin.openbmc@gmail.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20240327085330.3281697-1-peteryin.openbmc@gmail.com> References: <20240327085330.3281697-1-peteryin.openbmc@gmail.com> Precedence: bulk X-Mailing-List: linux-watchdog@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 To use the SCU register to obtain reset flags for supporting bootstatus. Signed-off-by: Peter Yin --- Documentation/devicetree/bindings/watchdog/aspeed-wdt.txt | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/Documentation/devicetree/bindings/watchdog/aspeed-wdt.txt b/Documentation/devicetree/bindings/watchdog/aspeed-wdt.txt index 3208adb3e52e..80a1f58b5a2e 100644 --- a/Documentation/devicetree/bindings/watchdog/aspeed-wdt.txt +++ b/Documentation/devicetree/bindings/watchdog/aspeed-wdt.txt @@ -8,6 +8,8 @@ Required properties: - reg: physical base address of the controller and length of memory mapped region + - aspeed,scu: a reference to the System Control Unit node of the Aspeed + SOC. Optional properties: @@ -62,6 +64,7 @@ Examples: reg = <0x1e785000 0x1c>; aspeed,reset-type = "system"; aspeed,external-signal; + aspeed,scu = <&syscon>; }; #include @@ -70,4 +73,5 @@ Examples: reg = <0x1e785040 0x40>; aspeed,reset-mask = ; + aspeed,scu = <&syscon>; }; From patchwork Wed Mar 27 08:53:30 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: PeterYin X-Patchwork-Id: 13605972 Received: from mail-pl1-f179.google.com (mail-pl1-f179.google.com [209.85.214.179]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id C899D40849; Wed, 27 Mar 2024 08:53:53 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.214.179 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1711529635; cv=none; b=R4UgTZ3lcwzS6Bw5s7wwcXdpJCtUNTx4CFgyyZrJZLEbC4Wqv43BSvcZg9hBC1Qbmzu3nz6nA0e61AOZ4dLLaPSUdKiRTFd2ky/3VlqHhMCDHc2Y8qo8w2GbNY5taNzYxF8unWhVJRQk/GIhpS632o0G6GZKWE5OizOfOAD7cLM= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1711529635; c=relaxed/simple; bh=mEMpsvf/Lu9Dlvkkk/Qka3rYdQiTY2A48dn0KD6WLwI=; h=From:To:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=d1fvikrLkQLJ/WbuoHi5raTQvhiVnjPdbH7Pzb+bSCx9LPTwzL8qMMZr8Ma/NDyUUOFw1pVcpCOzqSESDAkij6RputY7iIF/4o2vksqzLVWsmTMZkTCFYZI6Zb9w0WgXfNHKMLzgQ34DgV7MIMVk+8AetzV4qiPqzH5SUVHWLIQ= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=gmail.com; spf=pass smtp.mailfrom=gmail.com; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b=Tl2/c4cz; arc=none smtp.client-ip=209.85.214.179 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=gmail.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=gmail.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b="Tl2/c4cz" Received: by mail-pl1-f179.google.com with SMTP id d9443c01a7336-1e0f0398553so14861615ad.3; Wed, 27 Mar 2024 01:53:53 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20230601; t=1711529633; x=1712134433; darn=vger.kernel.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:from:to:cc:subject:date:message-id :reply-to; bh=QZEbTSOw9EjuXuuOhzMwhOK0HhVADXjRmiePaMQf/CY=; b=Tl2/c4czTvOoLPfdZIzFxIQ1bi11G3C7p7fv+Vv7AnXVjXr5opULz/A1e8g3TDnoV5 K1iooePHEwRugKpFkwsdRn+PN1qgnK9voZxlXZd32q2+iV0p6wOJrVQYux+q1jqff1qx /qL36//STvQKPjnmdoVHtDRwoItqX8fkZdKtyEIORxMH8CqQy0B/XfKOvkT6XKtsM22A e/5m85dv2ICzDoYaqBrWVgPrFcvZKIx4+DYogb19cZZrUIOedgmNdgnVE+h1NGwybxFs oF4HLgoLggsUBky4QT+Lv4MXfMRHzQLJicNrkbt2LlvBQrUkV+jZYXVIRd50jKTG3t+0 rVDg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1711529633; x=1712134433; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=QZEbTSOw9EjuXuuOhzMwhOK0HhVADXjRmiePaMQf/CY=; b=d0Xai2EF0QjKCC8osRwVQLjKkjHrQ4+l/0qjxXLIPKBGhNkXvk7S6apqhk+kalVnPt V8z0FH15Hw1QG1SBJORut/sPhyNHXlDsbMnIN2iVzVETjsw4AHUTepo52AkOK4IL3cmh f+Qu/cG/eaDhZIkD67J1HvM5NMzCZkQ820kiDOitosBocpMrCTL+z/0PSQ3/A6U4fHO8 uAh6s5Ge99ph+EZIQFJNSXSWpo0S/Ewt6oYSwSG3fzGeMw//MoPP49Bl+AEThMsGo37J qaezi1tACqfPokvwEjdPg4PGpIFQPdAl8WIjC0nHlse5q5QLs76KN6n1vvukwaa1NGlL U/CQ== X-Forwarded-Encrypted: i=1; AJvYcCWLGubckVlm+g6C/OXvEDXMgRSmV7BbhcUpU4jCSfNkaJUfynAy51ubMT4LNRDVYBGllrqUdddhH/QxrzkQbcvGsWm2IovWNF/M79LZWQzni1uJ3ftw6apLID077No53Pef1s226do1gdG/5kR2oDeDdBDEh3zO/RGo6ctZwc0EE3Gs0M1NWqek X-Gm-Message-State: AOJu0YxVR+z1nWWgMHTSp7E2fEmaFOpBv298V6Cx0oulXfDWKHA2VTmk hIQ5rULOAMRDpvIm0+QGJNxUH8kBM825GTNwQMHrcp05meqmU5bh X-Google-Smtp-Source: AGHT+IFlw6rOiGuhTJ4vNythc7vqhRqSyiMQo9PeosfY33Phf1K75pTfq+88EaBWSjn9tJXb1tX3pQ== X-Received: by 2002:a17:902:c94a:b0:1e0:acb1:7977 with SMTP id i10-20020a170902c94a00b001e0acb17977mr785333pla.49.1711529633261; Wed, 27 Mar 2024 01:53:53 -0700 (PDT) Received: from peter-bmc.dhcpserver.bu9bmc.local (2001-b400-e383-3566-013c-5a87-9abc-381e.emome-ip6.hinet.net. [2001:b400:e383:3566:13c:5a87:9abc:381e]) by smtp.gmail.com with ESMTPSA id h12-20020a170902eecc00b001e0501d3058sm8356848plb.63.2024.03.27.01.53.50 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 27 Mar 2024 01:53:52 -0700 (PDT) From: Peter Yin To: patrick@stwcx.xyz, Wim Van Sebroeck , Guenter Roeck , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Joel Stanley , Andrew Jeffery , linux-watchdog@vger.kernel.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-aspeed@lists.ozlabs.org, linux-kernel@vger.kernel.org Subject: [PATCH v4 4/4] drivers: watchdog: ast2500 and ast2600 support bootstatus Date: Wed, 27 Mar 2024 16:53:30 +0800 Message-Id: <20240327085330.3281697-5-peteryin.openbmc@gmail.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20240327085330.3281697-1-peteryin.openbmc@gmail.com> References: <20240327085330.3281697-1-peteryin.openbmc@gmail.com> Precedence: bulk X-Mailing-List: linux-watchdog@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Add WDIOF_EXTERN1 and WDIOF_CARDRESET bootstatus in ast2600 Regarding the AST2600 specification, the WDTn Timeout Status Register (WDT10) has bit 1 reserved. Bit 1 of the status register indicates on ast2500 if the boot was from the second boot source. It does not indicate that the most recent reset was triggered by the watchdog. The code should just be changed to set WDIOF_CARDRESET if bit 0 of the status register is set. Include SCU register to veriy WDIOF_EXTERN1 in ast2600 SCU74 or ast2500 SCU3C when bit1 is set. Signed-off-by: Peter Yin --- drivers/watchdog/aspeed_wdt.c | 60 +++++++++++++++++++++++++---------- 1 file changed, 44 insertions(+), 16 deletions(-) diff --git a/drivers/watchdog/aspeed_wdt.c b/drivers/watchdog/aspeed_wdt.c index b4773a6aaf8c..29e9afdee619 100644 --- a/drivers/watchdog/aspeed_wdt.c +++ b/drivers/watchdog/aspeed_wdt.c @@ -11,10 +11,12 @@ #include #include #include +#include #include #include #include #include +#include #include static bool nowayout = WATCHDOG_NOWAYOUT; @@ -65,23 +67,32 @@ MODULE_DEVICE_TABLE(of, aspeed_wdt_of_table); #define WDT_RELOAD_VALUE 0x04 #define WDT_RESTART 0x08 #define WDT_CTRL 0x0C -#define WDT_CTRL_BOOT_SECONDARY BIT(7) -#define WDT_CTRL_RESET_MODE_SOC (0x00 << 5) -#define WDT_CTRL_RESET_MODE_FULL_CHIP (0x01 << 5) -#define WDT_CTRL_RESET_MODE_ARM_CPU (0x10 << 5) -#define WDT_CTRL_1MHZ_CLK BIT(4) -#define WDT_CTRL_WDT_EXT BIT(3) -#define WDT_CTRL_WDT_INTR BIT(2) -#define WDT_CTRL_RESET_SYSTEM BIT(1) -#define WDT_CTRL_ENABLE BIT(0) +#define WDT_CTRL_BOOT_SECONDARY BIT(7) +#define WDT_CTRL_RESET_MODE_SOC (0x00 << 5) +#define WDT_CTRL_RESET_MODE_FULL_CHIP (0x01 << 5) +#define WDT_CTRL_RESET_MODE_ARM_CPU (0x10 << 5) +#define WDT_CTRL_1MHZ_CLK BIT(4) +#define WDT_CTRL_WDT_EXT BIT(3) +#define WDT_CTRL_WDT_INTR BIT(2) +#define WDT_CTRL_RESET_SYSTEM BIT(1) +#define WDT_CTRL_ENABLE BIT(0) #define WDT_TIMEOUT_STATUS 0x10 -#define WDT_TIMEOUT_STATUS_IRQ BIT(2) -#define WDT_TIMEOUT_STATUS_BOOT_SECONDARY BIT(1) +#define WDT_TIMEOUT_STATUS_IRQ BIT(2) +#define WDT_TIMEOUT_STATUS_BOOT_SECONDARY BIT(1) +#define WDT_TIMEOUT_STATUS_EVENT BIT(0) #define WDT_CLEAR_TIMEOUT_STATUS 0x14 -#define WDT_CLEAR_TIMEOUT_AND_BOOT_CODE_SELECTION BIT(0) +#define WDT_CLEAR_TIMEOUT_AND_BOOT_CODE_SELECTION BIT(0) #define WDT_RESET_MASK1 0x1c #define WDT_RESET_MASK2 0x20 +/* + * Ast2600 SCU74 bit1 is External reset flag + * Ast2500 SCU3C bit1 is External reset flag + */ +#define EXTERN_RESET_FLAG BIT(1) +#define AST2500_SYSTEM_RESET_EVENT 0x3C +#define AST2600_SYSTEM_RESET_EVENT 0x74 + /* * WDT_RESET_WIDTH controls the characteristics of the external pulse (if * enabled), specifically: @@ -330,6 +341,11 @@ static int aspeed_wdt_probe(struct platform_device *pdev) if (IS_ERR(wdt->base)) return PTR_ERR(wdt->base); + struct regmap *scu_base = syscon_regmap_lookup_by_phandle(dev->of_node, + "aspeed,scu"); + if (IS_ERR(scu_base)) + return PTR_ERR(scu_base); + wdt->wdd.info = &aspeed_wdt_info; if (wdt->cfg->irq_mask) { @@ -459,14 +475,26 @@ static int aspeed_wdt_probe(struct platform_device *pdev) } status = readl(wdt->base + WDT_TIMEOUT_STATUS); - if (status & WDT_TIMEOUT_STATUS_BOOT_SECONDARY) { + if (status & WDT_TIMEOUT_STATUS_EVENT) wdt->wdd.bootstatus = WDIOF_CARDRESET; - if (of_device_is_compatible(np, "aspeed,ast2400-wdt") || - of_device_is_compatible(np, "aspeed,ast2500-wdt")) - wdt->wdd.groups = bswitch_groups; + if (of_device_is_compatible(np, "aspeed,ast2600-wdt")) { + ret = regmap_read(scu_base, + AST2600_SYSTEM_RESET_EVENT, + &status); + } else { + ret = regmap_read(scu_base, + AST2500_SYSTEM_RESET_EVENT, + &status); + wdt->wdd.groups = bswitch_groups; } + /* + * Reset cause by Extern Reset + */ + if (status & EXTERN_RESET_FLAG && !ret) + wdt->wdd.bootstatus |= WDIOF_EXTERN1; + dev_set_drvdata(dev, wdt); return devm_watchdog_register_device(dev, &wdt->wdd);