From patchwork Wed Mar 27 09:13:30 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Manivannan Sadhasivam X-Patchwork-Id: 13606036 Received: from mail-pg1-f179.google.com (mail-pg1-f179.google.com [209.85.215.179]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id CDCE436AFC for ; Wed, 27 Mar 2024 09:14:10 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.215.179 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1711530852; cv=none; b=DglDL0yzuX3RZqoDjikgYRwJY6+hcFVUPkYxXpjJx4jOH9tlaufDZZKGSwD/D/b6a0hfVdJLhAFmMCeGHkoGO+sCsNF+AunWdiuWcWGPf84h2vR2OeCNEnK9lPmiikQuls+vznxpWKMlDpxZ/4Bhz6pYmPtYxEMlDfNWUKgo/Dc= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1711530852; c=relaxed/simple; bh=C9itwwrFPiwdNm8Zd8w7cqdwK6rVpgcx54kNU3MQW98=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=t70OWbsuwmIUPGezK3AlfBUAiFZovHUhHQQTZL3UaEhoe6AaXjjpqTSju+5uWTtY185WIt+ka7/8tvm6m/a4G81Uk7roKdbaDOJWQs2WrasUwLBSyCTLfR80lsR7wA6IbvhjyVAzMtG9AUpF9avl0q9oiBYE/KmKW5Pm3yMc1XE= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linaro.org; spf=pass smtp.mailfrom=linaro.org; dkim=pass (2048-bit key) header.d=linaro.org header.i=@linaro.org header.b=ucsCVpns; arc=none smtp.client-ip=209.85.215.179 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linaro.org Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=linaro.org Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=linaro.org header.i=@linaro.org header.b="ucsCVpns" Received: by mail-pg1-f179.google.com with SMTP id 41be03b00d2f7-5ce2aada130so4617402a12.1 for ; Wed, 27 Mar 2024 02:14:10 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1711530850; x=1712135650; darn=vger.kernel.org; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:from:to:cc:subject:date:message-id :reply-to; bh=n+x0WiOVlEoxEWj6JmzpWEM32pTOAvBFw/2lqI7CQ3Y=; b=ucsCVpnsUGhjrywQhz6t7mVi0L22t6KzHgofmYLvUhje5KS8JLa2y1bv3f+MLoVfMB KWsqHXc+/8g71Bj/fenIcU80XiQATaY8tDwIIsvBec38nDndLdAACVq2RCD0RfEIdIlG o5v6gIooAz+QojLYOo1KoNoE/NTDxt2Q9QoYTjdnyRqPgP1xg+JSgh+Cq0byOirsUN9c PVdQJd8TOuc/bKcsJmGgXaF+8FbYUTN/9WTq3Y8Tm+WQ3jEDiyWJ/uOtbG+J46b+Y0uD 1G2IngqC5jE0x56dHzhRpayUaI++topFQQ/v1LOro5gFrznvGEMesnlqMOUPhTawk2We eQjA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1711530850; x=1712135650; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=n+x0WiOVlEoxEWj6JmzpWEM32pTOAvBFw/2lqI7CQ3Y=; b=OTMvr5qJM2QjObddx2SdsrwlGFWikC2Z0XrA/4EPfyq2HE9+rAGJ23Cd23zRvCeYqV chDfA29bgJt2eMlh/iI2bhKOO6U86DuufQEwiXB8+3WY3oRI54mbPrnEjXVfkzz6KqTV 9e0f/WYKweG2m7sBgmZq+MWsVYEwrp9VIqfr9mIPjoa8uQUdxYxp/oR1Le+EDZm+Svii rUrpeJLKKAIwj+Z/1N7QH3a8HQlOTe6CeBqrPMssjsBZCHEtqdYmI3c1qXN2IU9pCg+o 7H+xyZMT91mNO520/VkTwsU5ej3/A695itVfApsgi1fx3FEfvQGBcBLLI0FRU11A3ohv 9S4Q== X-Forwarded-Encrypted: i=1; AJvYcCX+mYjnc375HS53weF93aeL/V9qSnEM7ejDxDyF0yLGyVNf4ht4vnyJ02YXNZb7k6XDXUaMPyiwUE+/uqg9gi+BB0L9/DWd4nT/C4wE3A== X-Gm-Message-State: AOJu0YyEqO2zZGvWMOKUQtZF2ytjUAcjufjpPMCUYfCwIGMtIQRlAgsT L2CaJo4qgiU0796bvWCnrbzo+AZHZxxeP2EFhfJMNmDT3Q4nIzXOxWwrpACeKQ== X-Google-Smtp-Source: AGHT+IGgoOBDdamY0w9pmOqmWVWOcqQuZDgDIWGyjcZElUTVYGxdc7EmsdQmE4x6o3Q48n8wUoM2tg== X-Received: by 2002:a17:90a:ba8b:b0:29b:961a:29c3 with SMTP id t11-20020a17090aba8b00b0029b961a29c3mr4336581pjr.49.1711530849946; Wed, 27 Mar 2024 02:14:09 -0700 (PDT) Received: from [127.0.1.1] ([120.60.52.77]) by smtp.gmail.com with ESMTPSA id h190-20020a6383c7000000b005dc4fc80b21sm8673871pge.70.2024.03.27.02.13.59 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 27 Mar 2024 02:14:09 -0700 (PDT) From: Manivannan Sadhasivam Date: Wed, 27 Mar 2024 14:43:30 +0530 Subject: [PATCH v12 1/8] PCI: dwc: ep: Fix DBI access failure for drivers requiring refclk from host Precedence: bulk X-Mailing-List: linux-arm-msm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-Id: <20240327-pci-dbi-rework-v12-1-082625472414@linaro.org> References: <20240327-pci-dbi-rework-v12-0-082625472414@linaro.org> In-Reply-To: <20240327-pci-dbi-rework-v12-0-082625472414@linaro.org> To: Jingoo Han , Lorenzo Pieralisi , =?utf-8?q?Krzysztof_Wilczy?= =?utf-8?q?=C5=84ski?= , Rob Herring , Bjorn Helgaas , Marek Vasut , Yoshihiro Shimoda , Thierry Reding , Jonathan Hunter , Vidya Sagar , Vignesh Raghavendra , Richard Zhu , Lucas Stach , Shawn Guo , Sascha Hauer , Pengutronix Kernel Team , Fabio Estevam , NXP Linux Team , Minghuan Lian , Mingkai Hu , Roy Zang , Kunihiko Hayashi , Masami Hiramatsu , Kishon Vijay Abraham I , Jesper Nilsson , Srikanth Thokala , Shawn Lin , Heiko Stuebner , Kishon Vijay Abraham I Cc: linux-pci@vger.kernel.org, linux-kernel@vger.kernel.org, linux-renesas-soc@vger.kernel.org, linux-arm-msm@vger.kernel.org, linux-tegra@vger.kernel.org, linux-omap@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linuxppc-dev@lists.ozlabs.org, Niklas Cassel , linux-arm-kernel@axis.com, linux-rockchip@lists.infradead.org, Manivannan Sadhasivam , Frank Li X-Mailer: b4 0.12.4 X-Developer-Signature: v=1; a=openpgp-sha256; l=7480; i=manivannan.sadhasivam@linaro.org; h=from:subject:message-id; bh=C9itwwrFPiwdNm8Zd8w7cqdwK6rVpgcx54kNU3MQW98=; b=owEBbQGS/pANAwAKAVWfEeb+kc71AcsmYgBmA+NIJnfXD7LMZio8W0A249GNJA5H9smQ0/YIV 2Mbshx2fmCJATMEAAEKAB0WIQRnpUMqgUjL2KRYJ5dVnxHm/pHO9QUCZgPjSAAKCRBVnxHm/pHO 9SFSCACcl92q4s6I4nZd3WCcfhQumw0iLwZ/wn0ylz4u11oziIW8gOj04TPmEFpvKK4yUo2H2gV emRIqlv3a2MowhrvoJ/FySPsqbtDFadni6vd5WA+H1hK0Cc5vAmsMuverqXHYM37THcdHfKjGVf dnUP8okf0Y594v6qqTsidArO8n/hzakaqI++awJiG9/LH8RFIR5CvkdtH0gnsksv9fhZJsmXJLv HHU5iUqaNDOnOKsBxS/m+1G5GP12FiFevRHj3ySuW/KGbiQ7rAc7qe76wzQXksTMbMWHBG7llAa aZWRSGu6qekGHKePMBoUsGEAOFcBvwCqKD8NKC0q7hQEWBg2 X-Developer-Key: i=manivannan.sadhasivam@linaro.org; a=openpgp; fpr=C668AEC3C3188E4C611465E7488550E901166008 The DWC glue drivers requiring an active reference clock from the PCIe host for initializing their PCIe EP core, set a flag called 'core_init_notifier' to let DWC driver know that these drivers need a special attention during initialization. In these drivers, access to the hw registers (like DBI) before receiving the active refclk from host will result in access failure and also could cause a whole system hang. But the current DWC EP driver doesn't honor the requirements of the drivers setting 'core_init_notifier' flag and tries to access the DBI registers during dw_pcie_ep_init(). This causes the system hang for glue drivers such as Tegra194 and Qcom EP as they depend on refclk from host and have set the above mentioned flag. To workaround this issue, users of the affected platforms have to maintain the dependency with the PCIe host by booting the PCIe EP after host boot. But this won't provide a good user experience, since PCIe EP is _one_ of the features of those platforms and it doesn't make sense to delay the whole platform booting due to PCIe requiring active refclk. So to fix this issue, let's move all the DBI access from dw_pcie_ep_init() in the DWC EP driver to the dw_pcie_ep_init_complete() API. This API will only be called by the drivers setting 'core_init_notifier' flag once refclk is received from host. For the rest of the drivers that gets the refclk locally, this API will be called within dw_pcie_ep_init(). Fixes: e966f7390da9 ("PCI: dwc: Refactor core initialization code for EP mode") Co-developed-by: Vidya Sagar Signed-off-by: Vidya Sagar Reviewed-by: Frank Li Reviewed-by: Niklas Cassel Signed-off-by: Manivannan Sadhasivam --- drivers/pci/controller/dwc/pcie-designware-ep.c | 120 ++++++++++++++---------- 1 file changed, 71 insertions(+), 49 deletions(-) diff --git a/drivers/pci/controller/dwc/pcie-designware-ep.c b/drivers/pci/controller/dwc/pcie-designware-ep.c index 746a11dcb67f..c43a1479de2c 100644 --- a/drivers/pci/controller/dwc/pcie-designware-ep.c +++ b/drivers/pci/controller/dwc/pcie-designware-ep.c @@ -604,11 +604,16 @@ static unsigned int dw_pcie_ep_find_ext_capability(struct dw_pcie *pci, int cap) int dw_pcie_ep_init_complete(struct dw_pcie_ep *ep) { struct dw_pcie *pci = to_dw_pcie_from_ep(ep); + struct dw_pcie_ep_func *ep_func; + struct device *dev = pci->dev; + struct pci_epc *epc = ep->epc; unsigned int offset, ptm_cap_base; unsigned int nbars; u8 hdr_type; + u8 func_no; + int i, ret; + void *addr; u32 reg; - int i; hdr_type = dw_pcie_readb_dbi(pci, PCI_HEADER_TYPE) & PCI_HEADER_TYPE_MASK; @@ -619,6 +624,58 @@ int dw_pcie_ep_init_complete(struct dw_pcie_ep *ep) return -EIO; } + dw_pcie_version_detect(pci); + + dw_pcie_iatu_detect(pci); + + ret = dw_pcie_edma_detect(pci); + if (ret) + return ret; + + if (!ep->ib_window_map) { + ep->ib_window_map = devm_bitmap_zalloc(dev, pci->num_ib_windows, + GFP_KERNEL); + if (!ep->ib_window_map) + goto err_remove_edma; + } + + if (!ep->ob_window_map) { + ep->ob_window_map = devm_bitmap_zalloc(dev, pci->num_ob_windows, + GFP_KERNEL); + if (!ep->ob_window_map) + goto err_remove_edma; + } + + if (!ep->outbound_addr) { + addr = devm_kcalloc(dev, pci->num_ob_windows, sizeof(phys_addr_t), + GFP_KERNEL); + if (!addr) + goto err_remove_edma; + ep->outbound_addr = addr; + } + + for (func_no = 0; func_no < epc->max_functions; func_no++) { + + ep_func = dw_pcie_ep_get_func_from_ep(ep, func_no); + if (ep_func) + continue; + + ep_func = devm_kzalloc(dev, sizeof(*ep_func), GFP_KERNEL); + if (!ep_func) + goto err_remove_edma; + + ep_func->func_no = func_no; + ep_func->msi_cap = dw_pcie_ep_find_capability(ep, func_no, + PCI_CAP_ID_MSI); + ep_func->msix_cap = dw_pcie_ep_find_capability(ep, func_no, + PCI_CAP_ID_MSIX); + + list_add_tail(&ep_func->list, &ep->func_list); + } + + if (ep->ops->init) + ep->ops->init(ep); + offset = dw_pcie_ep_find_ext_capability(pci, PCI_EXT_CAP_ID_REBAR); ptm_cap_base = dw_pcie_ep_find_ext_capability(pci, PCI_EXT_CAP_ID_PTM); @@ -658,14 +715,17 @@ int dw_pcie_ep_init_complete(struct dw_pcie_ep *ep) dw_pcie_dbi_ro_wr_dis(pci); return 0; + +err_remove_edma: + dw_pcie_edma_remove(pci); + + return ret; } EXPORT_SYMBOL_GPL(dw_pcie_ep_init_complete); int dw_pcie_ep_init(struct dw_pcie_ep *ep) { int ret; - void *addr; - u8 func_no; struct resource *res; struct pci_epc *epc; struct dw_pcie *pci = to_dw_pcie_from_ep(ep); @@ -673,7 +733,6 @@ int dw_pcie_ep_init(struct dw_pcie_ep *ep) struct platform_device *pdev = to_platform_device(dev); struct device_node *np = dev->of_node; const struct pci_epc_features *epc_features; - struct dw_pcie_ep_func *ep_func; INIT_LIST_HEAD(&ep->func_list); @@ -691,26 +750,6 @@ int dw_pcie_ep_init(struct dw_pcie_ep *ep) if (ep->ops->pre_init) ep->ops->pre_init(ep); - dw_pcie_version_detect(pci); - - dw_pcie_iatu_detect(pci); - - ep->ib_window_map = devm_bitmap_zalloc(dev, pci->num_ib_windows, - GFP_KERNEL); - if (!ep->ib_window_map) - return -ENOMEM; - - ep->ob_window_map = devm_bitmap_zalloc(dev, pci->num_ob_windows, - GFP_KERNEL); - if (!ep->ob_window_map) - return -ENOMEM; - - addr = devm_kcalloc(dev, pci->num_ob_windows, sizeof(phys_addr_t), - GFP_KERNEL); - if (!addr) - return -ENOMEM; - ep->outbound_addr = addr; - epc = devm_pci_epc_create(dev, &epc_ops); if (IS_ERR(epc)) { dev_err(dev, "Failed to create epc device\n"); @@ -724,23 +763,6 @@ int dw_pcie_ep_init(struct dw_pcie_ep *ep) if (ret < 0) epc->max_functions = 1; - for (func_no = 0; func_no < epc->max_functions; func_no++) { - ep_func = devm_kzalloc(dev, sizeof(*ep_func), GFP_KERNEL); - if (!ep_func) - return -ENOMEM; - - ep_func->func_no = func_no; - ep_func->msi_cap = dw_pcie_ep_find_capability(ep, func_no, - PCI_CAP_ID_MSI); - ep_func->msix_cap = dw_pcie_ep_find_capability(ep, func_no, - PCI_CAP_ID_MSIX); - - list_add_tail(&ep_func->list, &ep->func_list); - } - - if (ep->ops->init) - ep->ops->init(ep); - ret = pci_epc_mem_init(epc, ep->phys_base, ep->addr_size, ep->page_size); if (ret < 0) { @@ -756,25 +778,25 @@ int dw_pcie_ep_init(struct dw_pcie_ep *ep) goto err_exit_epc_mem; } - ret = dw_pcie_edma_detect(pci); - if (ret) - goto err_free_epc_mem; - if (ep->ops->get_features) { epc_features = ep->ops->get_features(ep); if (epc_features->core_init_notifier) return 0; } + /* + * NOTE:- Avoid accessing the hardware (Ex:- DBI space) before this + * step as platforms that implement 'core_init_notifier' feature may + * not have the hardware ready (i.e. core initialized) for access + * (Ex: tegra194). Any hardware access on such platforms result + * in system hang. + */ ret = dw_pcie_ep_init_complete(ep); if (ret) - goto err_remove_edma; + goto err_free_epc_mem; return 0; -err_remove_edma: - dw_pcie_edma_remove(pci); - err_free_epc_mem: pci_epc_mem_free_addr(epc, ep->msi_mem_phys, ep->msi_mem, epc->mem->window.page_size); From patchwork Wed Mar 27 09:13:31 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Manivannan Sadhasivam X-Patchwork-Id: 13606037 Received: from mail-oo1-f47.google.com (mail-oo1-f47.google.com [209.85.161.47]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id D6961381BE for ; Wed, 27 Mar 2024 09:14:20 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.161.47 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1711530862; cv=none; b=SYjMO+4z/GIbwmMXNavHMHi0rTecwbdceoq+fFGGQ5gqUgy5HK4gQLl882e335mM6LB8k4GVXnRX9EvAwgjza11tngnj5/5j2eDmSVwhTqh/wv8ounCzlNpZ4QF0hSf9tLI/bKFGaDcijx04WZNJPS7dJEEJDp6s9/Ck9W65pFQ= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1711530862; c=relaxed/simple; bh=pNo18qkD8Pxin1ExwVA6sv//n2b0xE66vsBA+jskrBo=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=H40M947rFwytHABTD4n/k0Z2/QbXw5mWLCQEd68bRH23kU0lUuWA/DaUqgtYie+VlaL7fnBDEn18vKOc58BxYbAwZhHaySmILBX+Y6Sf8cYc2rgI3Lhv3EC2HaC9SNSVmLM6bYHdzoL1P3acJFnT+ixZ8XOFbCIrGwl0PitVkhQ= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linaro.org; spf=pass smtp.mailfrom=linaro.org; dkim=pass (2048-bit key) header.d=linaro.org header.i=@linaro.org header.b=EG8bvRRM; arc=none smtp.client-ip=209.85.161.47 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linaro.org Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=linaro.org Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=linaro.org header.i=@linaro.org header.b="EG8bvRRM" Received: by mail-oo1-f47.google.com with SMTP id 006d021491bc7-5a4817189c8so3810987eaf.1 for ; Wed, 27 Mar 2024 02:14:20 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1711530860; x=1712135660; darn=vger.kernel.org; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:from:to:cc:subject:date:message-id :reply-to; bh=YqASZM91XPcXELguAroAsfznz8SI/TV8wGGgEbcPSCg=; b=EG8bvRRM7uD707uoc9VjTbvQIcXJ639OA7he0nYXcsSv56A43LV56om/tEB8Yzk8Le Kf16CTu9RmGaCenkl76b52s4O/9b88r5DOV7YIbMl47Dk3WCmweenGX5IG5FTt9GBaFs 8O17+aisI3DsAFBjAqVDimk7RPfjj6KNto1v62NBCE1wIgR3VxfEWWJZtV4yrYrN0Abp DkVJcjmuivLbppxqOPfXM9ZtRCLPVGbVDD/DRQ03gzh1llNMQTWVqEz3Z/PmPCvIySRQ vEPhSziNc3Hrq7VOKdGMIGUhrwP0MOUGswsNIT20MhKeOJrmgzPZxMXbD7+k5Tn31m5c fAEA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1711530860; x=1712135660; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=YqASZM91XPcXELguAroAsfznz8SI/TV8wGGgEbcPSCg=; b=wEe6rL2ECH7+irCP30KvG/OTG4DV0CIZqY6H4c4wOldZFLkBdaOdMaSM2fKh28/G1V eKJR6psijQHjnOLWSqydyqnQaUFpq8H+nS15T6v4Rj5CBh7JWnnZ/TrEG1oLVNenEJ3L 1Dy7WlKKVmMOqYpRibwhQKBkerUCGgIarQ/8lmcnSrSug49IgyUkO7rivuyYZcZr26t6 cjCccfGJvGorzTxO417gtWQfngdNTrMm0RZtf9kyPezYmnuTLnrZ92/8x2KJ+cYEORS+ gaq3DSyTCbzy8pV1Aq3VoXuqVybZDY0gDfmOmgQAQYPG/GPs7RDbm9DXIuhGQR2JXzVG /CQQ== X-Forwarded-Encrypted: i=1; AJvYcCUawx2RaBT6TJxpxPn6FoWJ+HXlKbZoUvlqEHbToxw/EgNi/9Z/HG3UPOC0GQezQEykZeMUzOTSkZ2kpPXBDT00EnTC1dcS91HUaV0bNw== X-Gm-Message-State: AOJu0Ywv+IiSUZNvPIxMUuD0XzJ7O9Qy8doiLlqzNz3UGbXQ+2uGAHL/ otjE1gzWs0zVTki7J+o0dxGy2m8MxO1LeZNykS0Fz2Y7ggFQiA49C+rmACyA5Q== X-Google-Smtp-Source: AGHT+IGkxnrnXnBY3c/aP7t7drqoD/wVEvlWzS8FQLVs973449FDjsXS7XP6PnjZ8yU1SgAX6Fby7A== X-Received: by 2002:a05:6358:42aa:b0:17e:de1f:290 with SMTP id s42-20020a05635842aa00b0017ede1f0290mr5630348rwc.25.1711530859729; Wed, 27 Mar 2024 02:14:19 -0700 (PDT) Received: from [127.0.1.1] ([120.60.52.77]) by smtp.gmail.com with ESMTPSA id h190-20020a6383c7000000b005dc4fc80b21sm8673871pge.70.2024.03.27.02.14.10 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 27 Mar 2024 02:14:19 -0700 (PDT) From: Manivannan Sadhasivam Date: Wed, 27 Mar 2024 14:43:31 +0530 Subject: [PATCH v12 2/8] PCI: dwc: ep: Add Kernel-doc comments for APIs Precedence: bulk X-Mailing-List: linux-arm-msm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-Id: <20240327-pci-dbi-rework-v12-2-082625472414@linaro.org> References: <20240327-pci-dbi-rework-v12-0-082625472414@linaro.org> In-Reply-To: <20240327-pci-dbi-rework-v12-0-082625472414@linaro.org> To: Jingoo Han , Lorenzo Pieralisi , =?utf-8?q?Krzysztof_Wilczy?= =?utf-8?q?=C5=84ski?= , Rob Herring , Bjorn Helgaas , Marek Vasut , Yoshihiro Shimoda , Thierry Reding , Jonathan Hunter , Vidya Sagar , Vignesh Raghavendra , Richard Zhu , Lucas Stach , Shawn Guo , Sascha Hauer , Pengutronix Kernel Team , Fabio Estevam , NXP Linux Team , Minghuan Lian , Mingkai Hu , Roy Zang , Kunihiko Hayashi , Masami Hiramatsu , Kishon Vijay Abraham I , Jesper Nilsson , Srikanth Thokala , Shawn Lin , Heiko Stuebner , Kishon Vijay Abraham I Cc: linux-pci@vger.kernel.org, linux-kernel@vger.kernel.org, linux-renesas-soc@vger.kernel.org, linux-arm-msm@vger.kernel.org, linux-tegra@vger.kernel.org, linux-omap@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linuxppc-dev@lists.ozlabs.org, Niklas Cassel , linux-arm-kernel@axis.com, linux-rockchip@lists.infradead.org, Manivannan Sadhasivam , Frank Li X-Mailer: b4 0.12.4 X-Developer-Signature: v=1; a=openpgp-sha256; l=5382; i=manivannan.sadhasivam@linaro.org; h=from:subject:message-id; bh=pNo18qkD8Pxin1ExwVA6sv//n2b0xE66vsBA+jskrBo=; b=owEBbQGS/pANAwAKAVWfEeb+kc71AcsmYgBmA+NImhvprmFrGELVQDHV0ZI/sZ+kM69J4CaE+ HElRFx/IL2JATMEAAEKAB0WIQRnpUMqgUjL2KRYJ5dVnxHm/pHO9QUCZgPjSAAKCRBVnxHm/pHO 9W5jB/9zQRHznlVynvYmBiqzCvcB02QT8dW3UjzdximNDPDPbCzqXkccGjVDilD+Mi4X1Xzl8Nm NDfCNc54wBkV62wzDAGL8J5gH6TVAtcorCq3lpbKhJHKEd5i64jvO2wLpnBd6cqJfeO2nD3slks 2PvDyP9rltiK+KfM2e3DPOIwMJ8s/WmG9A6WBSVWj46hgkKlH9qvUQ+1Sn1DJGBzLQKR/lbkJlH YqeH3CV6lK+tXv8kJKdi43CqqrA5ScQr+fU/+8yryhga/HqaM3LUZ1yJFB/NgP28cmXilmbgXD1 Agj1GUZAeXAgAMMUashx7s7FQUNOHLAy2qVG+Q6GQhVhCnma X-Developer-Key: i=manivannan.sadhasivam@linaro.org; a=openpgp; fpr=C668AEC3C3188E4C611465E7488550E901166008 All of the APIs are missing the Kernel-doc comments. Hence, add them. Reviewed-by: Frank Li Reviewed-by: Niklas Cassel Signed-off-by: Manivannan Sadhasivam --- drivers/pci/controller/dwc/pcie-designware-ep.c | 77 +++++++++++++++++++++++++ 1 file changed, 77 insertions(+) diff --git a/drivers/pci/controller/dwc/pcie-designware-ep.c b/drivers/pci/controller/dwc/pcie-designware-ep.c index c43a1479de2c..dc63478f6910 100644 --- a/drivers/pci/controller/dwc/pcie-designware-ep.c +++ b/drivers/pci/controller/dwc/pcie-designware-ep.c @@ -15,6 +15,10 @@ #include #include +/** + * dw_pcie_ep_linkup - Notify EPF drivers about Link Up event + * @ep: DWC EP device + */ void dw_pcie_ep_linkup(struct dw_pcie_ep *ep) { struct pci_epc *epc = ep->epc; @@ -23,6 +27,10 @@ void dw_pcie_ep_linkup(struct dw_pcie_ep *ep) } EXPORT_SYMBOL_GPL(dw_pcie_ep_linkup); +/** + * dw_pcie_ep_init_notify - Notify EPF drivers about EPC initialization complete + * @ep: DWC EP device + */ void dw_pcie_ep_init_notify(struct dw_pcie_ep *ep) { struct pci_epc *epc = ep->epc; @@ -31,6 +39,14 @@ void dw_pcie_ep_init_notify(struct dw_pcie_ep *ep) } EXPORT_SYMBOL_GPL(dw_pcie_ep_init_notify); +/** + * dw_pcie_ep_get_func_from_ep - Get the struct dw_pcie_ep_func corresponding to + * the endpoint function + * @ep: DWC EP device + * @func_no: Function number of the endpoint device + * + * Return: struct dw_pcie_ep_func if success, NULL otherwise. + */ struct dw_pcie_ep_func * dw_pcie_ep_get_func_from_ep(struct dw_pcie_ep *ep, u8 func_no) { @@ -61,6 +77,11 @@ static void __dw_pcie_ep_reset_bar(struct dw_pcie *pci, u8 func_no, dw_pcie_dbi_ro_wr_dis(pci); } +/** + * dw_pcie_ep_reset_bar - Reset endpoint BAR + * @pci: DWC PCI device + * @bar: BAR number of the endpoint + */ void dw_pcie_ep_reset_bar(struct dw_pcie *pci, enum pci_barno bar) { u8 func_no, funcs; @@ -440,6 +461,13 @@ static const struct pci_epc_ops epc_ops = { .get_features = dw_pcie_ep_get_features, }; +/** + * dw_pcie_ep_raise_intx_irq - Raise INTx IRQ to the host + * @ep: DWC EP device + * @func_no: Function number of the endpoint + * + * Return: 0 if success, errono otherwise. + */ int dw_pcie_ep_raise_intx_irq(struct dw_pcie_ep *ep, u8 func_no) { struct dw_pcie *pci = to_dw_pcie_from_ep(ep); @@ -451,6 +479,14 @@ int dw_pcie_ep_raise_intx_irq(struct dw_pcie_ep *ep, u8 func_no) } EXPORT_SYMBOL_GPL(dw_pcie_ep_raise_intx_irq); +/** + * dw_pcie_ep_raise_msi_irq - Raise MSI IRQ to the host + * @ep: DWC EP device + * @func_no: Function number of the endpoint + * @interrupt_num: Interrupt number to be raised + * + * Return: 0 if success, errono otherwise. + */ int dw_pcie_ep_raise_msi_irq(struct dw_pcie_ep *ep, u8 func_no, u8 interrupt_num) { @@ -500,6 +536,15 @@ int dw_pcie_ep_raise_msi_irq(struct dw_pcie_ep *ep, u8 func_no, } EXPORT_SYMBOL_GPL(dw_pcie_ep_raise_msi_irq); +/** + * dw_pcie_ep_raise_msix_irq_doorbell - Raise MSI-X to the host using Doorbell + * method + * @ep: DWC EP device + * @func_no: Function number of the endpoint device + * @interrupt_num: Interrupt number to be raised + * + * Return: 0 if success, errno otherwise. + */ int dw_pcie_ep_raise_msix_irq_doorbell(struct dw_pcie_ep *ep, u8 func_no, u16 interrupt_num) { @@ -519,6 +564,14 @@ int dw_pcie_ep_raise_msix_irq_doorbell(struct dw_pcie_ep *ep, u8 func_no, return 0; } +/** + * dw_pcie_ep_raise_msix_irq - Raise MSI-X to the host + * @ep: DWC EP device + * @func_no: Function number of the endpoint device + * @interrupt_num: Interrupt number to be raised + * + * Return: 0 if success, errno otherwise. + */ int dw_pcie_ep_raise_msix_irq(struct dw_pcie_ep *ep, u8 func_no, u16 interrupt_num) { @@ -566,6 +619,13 @@ int dw_pcie_ep_raise_msix_irq(struct dw_pcie_ep *ep, u8 func_no, return 0; } +/** + * dw_pcie_ep_exit - Deinitialize the endpoint device + * @ep: DWC EP device + * + * Deinitialize the endpoint device. EPC device is not destroyed since that will + * be taken care by Devres. + */ void dw_pcie_ep_exit(struct dw_pcie_ep *ep) { struct dw_pcie *pci = to_dw_pcie_from_ep(ep); @@ -601,6 +661,14 @@ static unsigned int dw_pcie_ep_find_ext_capability(struct dw_pcie *pci, int cap) return 0; } +/** + * dw_pcie_ep_init_complete - Complete DWC EP initialization + * @ep: DWC EP device + * + * Complete the initialization of the registers (CSRs) specific to DWC EP. This + * API should be called only when the endpoint receives an active refclk (either + * from host or generated locally). + */ int dw_pcie_ep_init_complete(struct dw_pcie_ep *ep) { struct dw_pcie *pci = to_dw_pcie_from_ep(ep); @@ -723,6 +791,15 @@ int dw_pcie_ep_init_complete(struct dw_pcie_ep *ep) } EXPORT_SYMBOL_GPL(dw_pcie_ep_init_complete); +/** + * dw_pcie_ep_init - Initialize the endpoint device + * @ep: DWC EP device + * + * Initialize the endpoint device. Allocate resources and create the EPC + * device with the endpoint framework. + * + * Return: 0 if success, errno otherwise. + */ int dw_pcie_ep_init(struct dw_pcie_ep *ep) { int ret; From patchwork Wed Mar 27 09:13:32 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Manivannan Sadhasivam X-Patchwork-Id: 13606038 Received: from mail-pf1-f180.google.com (mail-pf1-f180.google.com [209.85.210.180]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 16C9F374CC for ; Wed, 27 Mar 2024 09:14:30 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.210.180 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1711530873; cv=none; b=XXhtixUMq+zrZFEBO/fvl8rGIHB9Kl+t6L0L5HkQzeCgJ164t/g5RFMz1y/RQNcG5kK2oYyE5k82iJq/JnOhmTbgS0lArT00FfWueieN5285ntZDPyMeGqv1vOU2UUlOGX/0CtmbLJTxdYBLICyLMYCSJTn8SdFhpq5XptMAeR4= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1711530873; c=relaxed/simple; bh=oxVwts31AynSAqvIvFdaJ3BN9dSR3M2c799N6+9XayE=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=nVqskXgvvGlhpYHSJF7I5wF6qE2vpoLybbKmZtxtaTE0HleNFctC1V6bW8hzoPcaqi6BelsAbOf8VNLalIsET1Wbc905UCfWdCMtV7LTSK/02QRRPmcig2KbQ8n9lWoCmjmKSMQAAm3TuSEio8eEK+EsM1R+g1kNpPtjrr6JEUU= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linaro.org; spf=pass smtp.mailfrom=linaro.org; dkim=pass (2048-bit key) header.d=linaro.org header.i=@linaro.org header.b=m5ONv8iC; arc=none smtp.client-ip=209.85.210.180 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linaro.org Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=linaro.org Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=linaro.org header.i=@linaro.org header.b="m5ONv8iC" Received: by mail-pf1-f180.google.com with SMTP id d2e1a72fcca58-6e740fff1d8so4681643b3a.1 for ; Wed, 27 Mar 2024 02:14:30 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1711530870; x=1712135670; darn=vger.kernel.org; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:from:to:cc:subject:date:message-id :reply-to; bh=zPk9OMXL2EDAJPzRk28eQ8ffeZSU9ou0GuU/yWTRHW0=; b=m5ONv8iCXEjJVkvByldej/oDeJ+69Bt+cW+NK7Urwn15/mFsrMjz14BbiMACA/VQko +GFTXc/sd8qcSVGEjm/KwXjNbZwzBsYifjHFz4HAaqevk+OL93zhpVo3YHQCRqEQ7BhT YWSyaJUBUqmBtnR4ouYix/GopR+UCeAcDvsuyxJ1RRO1tNcBsau5UDeWm6qTOrNb3gbC e5jwX5r7S6aY70V0JQT7QEggCZtGsDSBdl2QrVN6GIYuLi1Y5+saQ4FmsTGOaOFqMt1t kND50uJ6DgByPb3WoPBV56Fk1LM5LrAFgR7oyEEmabkjN0+t+BkLEr1l0u0Brn2+0F5Q e1JA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1711530870; x=1712135670; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=zPk9OMXL2EDAJPzRk28eQ8ffeZSU9ou0GuU/yWTRHW0=; b=wF2W7kFdB6JAQhKiUwyKjvAT7PPPAYdiuZMMZDVAd3rweL1pfmvrca6eFgO8ysYzHI 9FFhBsHaCwD3g4UKV10/x+6yZSml6nh/zeP5YuCzcnYHiwH1IsKXwhpdlKhr/xsd1A8G +s+iBK5/at1VAm2C2XSJir15N3aUoQFDNnpw0faVszHPAVandWPjnUaSFDrMI83tDbgx bH8u576t9DBz7w+m/Q3nG4G+LSCevlVFz1wD/xoyL6wQtW5QPLhBYJ6dm+weCyA3kDy8 lEcurYOmsMxVic7wyPZfuzxIGieLwpJThRdEieQxqBQiziC0rgo5qXGldJe475gkQMdM Bemg== X-Forwarded-Encrypted: i=1; AJvYcCXtPJA1Tkm8Y+qTU7iS/CSLaG39xVcW2NrphGol5DzZrPGZeblYr1t6Lvg98lu/eHuzIM6zKoiys7+r7VTUyWidzIDldj3g5Cnw4ueACA== X-Gm-Message-State: AOJu0Yxw9deDJ7IpZrSUmS7YPW76bqETI2tFBaug4/YRVIYtzi6LG/+H 3tZqhQfLTyJ4hHP5JPKvJu3UGsd+UMxAc6+1bYkROLN8vWv6kNOO9d12Apm9Dg== X-Google-Smtp-Source: AGHT+IHUqTOBDCc0FzxMHZPzlvLHKFGoK7XVK6UdIi44MV6apc230jjA2Kps2spz4iW6N2fPM1JOFA== X-Received: by 2002:aa7:888f:0:b0:6ea:ad01:357c with SMTP id z15-20020aa7888f000000b006eaad01357cmr2103804pfe.22.1711530870218; Wed, 27 Mar 2024 02:14:30 -0700 (PDT) Received: from [127.0.1.1] ([120.60.52.77]) by smtp.gmail.com with ESMTPSA id h190-20020a6383c7000000b005dc4fc80b21sm8673871pge.70.2024.03.27.02.14.20 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 27 Mar 2024 02:14:29 -0700 (PDT) From: Manivannan Sadhasivam Date: Wed, 27 Mar 2024 14:43:32 +0530 Subject: [PATCH v12 3/8] PCI: dwc: ep: Remove deinit() callback from struct dw_pcie_ep_ops Precedence: bulk X-Mailing-List: linux-arm-msm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-Id: <20240327-pci-dbi-rework-v12-3-082625472414@linaro.org> References: <20240327-pci-dbi-rework-v12-0-082625472414@linaro.org> In-Reply-To: <20240327-pci-dbi-rework-v12-0-082625472414@linaro.org> To: Jingoo Han , Lorenzo Pieralisi , =?utf-8?q?Krzysztof_Wilczy?= =?utf-8?q?=C5=84ski?= , Rob Herring , Bjorn Helgaas , Marek Vasut , Yoshihiro Shimoda , Thierry Reding , Jonathan Hunter , Vidya Sagar , Vignesh Raghavendra , Richard Zhu , Lucas Stach , Shawn Guo , Sascha Hauer , Pengutronix Kernel Team , Fabio Estevam , NXP Linux Team , Minghuan Lian , Mingkai Hu , Roy Zang , Kunihiko Hayashi , Masami Hiramatsu , Kishon Vijay Abraham I , Jesper Nilsson , Srikanth Thokala , Shawn Lin , Heiko Stuebner , Kishon Vijay Abraham I Cc: linux-pci@vger.kernel.org, linux-kernel@vger.kernel.org, linux-renesas-soc@vger.kernel.org, linux-arm-msm@vger.kernel.org, linux-tegra@vger.kernel.org, linux-omap@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linuxppc-dev@lists.ozlabs.org, Niklas Cassel , linux-arm-kernel@axis.com, linux-rockchip@lists.infradead.org, Manivannan Sadhasivam , Frank Li X-Mailer: b4 0.12.4 X-Developer-Signature: v=1; a=openpgp-sha256; l=4397; i=manivannan.sadhasivam@linaro.org; h=from:subject:message-id; bh=oxVwts31AynSAqvIvFdaJ3BN9dSR3M2c799N6+9XayE=; b=owEBbQGS/pANAwAKAVWfEeb+kc71AcsmYgBmA+NJyLax6YW3Dcb5Sh5QpLv875ecVd4pu/l86 j0PZPCzgsaJATMEAAEKAB0WIQRnpUMqgUjL2KRYJ5dVnxHm/pHO9QUCZgPjSQAKCRBVnxHm/pHO 9XU1B/9zbXi+U6FRqviLhKGscc2BcpWXO/vZZZSbP1V8JFoZQnH13D+vsY4FHCsxxKSu06ZxXci Pur8uJij9gSzGzokzDgbR32/AAtNIxKbJmJgSp7Rm/DFAGPfOYbmm2CM1m8VXNgxphbS/ADHe2c k6+hszGUixD98daIPtNbm7G3Bo2O1PKrhUIRj5+kjN9Evl6Hr1b56Toj7oGZJbzedElT3HOKsa3 Dw7LsKjusaL39VdWv2jKh2IgAZ2qC/VQCjZ7ub0J+yicfYWLIMdl4MPmlL+Ri/OUCJ8AzkGAmXp RJsivu+Qzbyuwo6MRmVdT54dAvHVgWmOq4iue+ylu5TEgsmZ X-Developer-Key: i=manivannan.sadhasivam@linaro.org; a=openpgp; fpr=C668AEC3C3188E4C611465E7488550E901166008 deinit() callback was solely introduced for the pcie-rcar-gen4 driver where it is used to do platform specific resource deallocation. And this callback is called right at the end of the dw_pcie_ep_exit() API. So it doesn't matter whether it is called within or outside of dw_pcie_ep_exit() API. So let's remove this callback and directly call rcar_gen4_pcie_ep_deinit() in pcie-rcar-gen4 driver to do resource deallocation after the completion of dw_pcie_ep_exit() API in rcar_gen4_remove_dw_pcie_ep(). This simplifies the DWC layer. Reviewed-by: Frank Li Reviewed-by: Niklas Cassel Reviewed-by: Yoshihiro Shimoda Signed-off-by: Manivannan Sadhasivam --- drivers/pci/controller/dwc/pcie-designware-ep.c | 9 +-------- drivers/pci/controller/dwc/pcie-designware.h | 1 - drivers/pci/controller/dwc/pcie-rcar-gen4.c | 14 ++++++++------ 3 files changed, 9 insertions(+), 15 deletions(-) diff --git a/drivers/pci/controller/dwc/pcie-designware-ep.c b/drivers/pci/controller/dwc/pcie-designware-ep.c index dc63478f6910..f06598715412 100644 --- a/drivers/pci/controller/dwc/pcie-designware-ep.c +++ b/drivers/pci/controller/dwc/pcie-designware-ep.c @@ -637,9 +637,6 @@ void dw_pcie_ep_exit(struct dw_pcie_ep *ep) epc->mem->window.page_size); pci_epc_mem_exit(epc); - - if (ep->ops->deinit) - ep->ops->deinit(ep); } EXPORT_SYMBOL_GPL(dw_pcie_ep_exit); @@ -844,7 +841,7 @@ int dw_pcie_ep_init(struct dw_pcie_ep *ep) ep->page_size); if (ret < 0) { dev_err(dev, "Failed to initialize address space\n"); - goto err_ep_deinit; + return ret; } ep->msi_mem = pci_epc_mem_alloc_addr(epc, &ep->msi_mem_phys, @@ -881,10 +878,6 @@ int dw_pcie_ep_init(struct dw_pcie_ep *ep) err_exit_epc_mem: pci_epc_mem_exit(epc); -err_ep_deinit: - if (ep->ops->deinit) - ep->ops->deinit(ep); - return ret; } EXPORT_SYMBOL_GPL(dw_pcie_ep_init); diff --git a/drivers/pci/controller/dwc/pcie-designware.h b/drivers/pci/controller/dwc/pcie-designware.h index 26dae4837462..ab7431a37209 100644 --- a/drivers/pci/controller/dwc/pcie-designware.h +++ b/drivers/pci/controller/dwc/pcie-designware.h @@ -333,7 +333,6 @@ struct dw_pcie_rp { struct dw_pcie_ep_ops { void (*pre_init)(struct dw_pcie_ep *ep); void (*init)(struct dw_pcie_ep *ep); - void (*deinit)(struct dw_pcie_ep *ep); int (*raise_irq)(struct dw_pcie_ep *ep, u8 func_no, unsigned int type, u16 interrupt_num); const struct pci_epc_features* (*get_features)(struct dw_pcie_ep *ep); diff --git a/drivers/pci/controller/dwc/pcie-rcar-gen4.c b/drivers/pci/controller/dwc/pcie-rcar-gen4.c index 0be760ed420b..5d29c4cfe0a0 100644 --- a/drivers/pci/controller/dwc/pcie-rcar-gen4.c +++ b/drivers/pci/controller/dwc/pcie-rcar-gen4.c @@ -352,11 +352,8 @@ static void rcar_gen4_pcie_ep_init(struct dw_pcie_ep *ep) dw_pcie_ep_reset_bar(pci, bar); } -static void rcar_gen4_pcie_ep_deinit(struct dw_pcie_ep *ep) +static void rcar_gen4_pcie_ep_deinit(struct rcar_gen4_pcie *rcar) { - struct dw_pcie *dw = to_dw_pcie_from_ep(ep); - struct rcar_gen4_pcie *rcar = to_rcar_gen4_pcie(dw); - writel(0, rcar->base + PCIEDMAINTSTSEN); rcar_gen4_pcie_common_deinit(rcar); } @@ -410,7 +407,6 @@ static unsigned int rcar_gen4_pcie_ep_get_dbi2_offset(struct dw_pcie_ep *ep, static const struct dw_pcie_ep_ops pcie_ep_ops = { .pre_init = rcar_gen4_pcie_ep_pre_init, .init = rcar_gen4_pcie_ep_init, - .deinit = rcar_gen4_pcie_ep_deinit, .raise_irq = rcar_gen4_pcie_ep_raise_irq, .get_features = rcar_gen4_pcie_ep_get_features, .get_dbi_offset = rcar_gen4_pcie_ep_get_dbi_offset, @@ -420,18 +416,24 @@ static const struct dw_pcie_ep_ops pcie_ep_ops = { static int rcar_gen4_add_dw_pcie_ep(struct rcar_gen4_pcie *rcar) { struct dw_pcie_ep *ep = &rcar->dw.ep; + int ret; if (!IS_ENABLED(CONFIG_PCIE_RCAR_GEN4_EP)) return -ENODEV; ep->ops = &pcie_ep_ops; - return dw_pcie_ep_init(ep); + ret = dw_pcie_ep_init(ep); + if (ret) + rcar_gen4_pcie_ep_deinit(rcar); + + return ret; } static void rcar_gen4_remove_dw_pcie_ep(struct rcar_gen4_pcie *rcar) { dw_pcie_ep_exit(&rcar->dw.ep); + rcar_gen4_pcie_ep_deinit(rcar); } /* Common */ From patchwork Wed Mar 27 09:13:33 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Manivannan Sadhasivam X-Patchwork-Id: 13606039 Received: from mail-pf1-f176.google.com (mail-pf1-f176.google.com [209.85.210.176]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id EE0EA4AEF2 for ; Wed, 27 Mar 2024 09:14:43 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.210.176 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1711530885; cv=none; b=ibnR6W7BaPZeTLyPgGVEEiY9mx/z4hCNH1u8IV48uIGfJ0qmPbJB3to58VOoEJ/HgdvsDzIoCCHFzbFJAVdl2Mlq4Y3imAYlgr0BIB1z3jxI8/fSFXKOKNxs3MvbWSsXNJyznpiwDrBOINDWwt4jnp2JX6KH/8N1RTeNd+yNEf0= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1711530885; c=relaxed/simple; bh=xGVEiZ7J2TIauI1NZJAP+R7IoNGzHRfiU2LIamYdE4E=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=lLuhGahN2J071ge1R63BIl9/7rBmGvgyKmr/GJLqrC/7Owc0UacwexqYZN3ftPWK7I3MgGkOT1aGtI5+uAzYe0oxRrCotQaRRBfz2tG4Z/xLscSUwR8fzEr23QKD159nzNGlgoQdkSaMvWKyIgkRW+hytkmN8/FRObnX6zR0MHA= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linaro.org; spf=pass smtp.mailfrom=linaro.org; dkim=pass (2048-bit key) header.d=linaro.org header.i=@linaro.org header.b=nB/muunx; arc=none smtp.client-ip=209.85.210.176 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linaro.org Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=linaro.org Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=linaro.org header.i=@linaro.org header.b="nB/muunx" Received: by mail-pf1-f176.google.com with SMTP id d2e1a72fcca58-6e6afb754fcso5713612b3a.3 for ; Wed, 27 Mar 2024 02:14:43 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1711530883; x=1712135683; darn=vger.kernel.org; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:from:to:cc:subject:date:message-id :reply-to; bh=oZiY/N9QWjiUSrWkYkKKgVbAI8JcvjPgGcqjy1l+QIE=; b=nB/muunxTnoqBk63Sw30EHb7I4acBTzkoB/bJ9gqUWOcu+Jm+tz0oneDhQU/XRmg3n 8vHPfhpkZrVIp8GDhB8lfGmTxXwce5/DU9JCoHYvW/7+m3Bxq7O/s5EMo1GPV/9No1jn wvQS26d4+7aO0S1dnSJ8R2e0rT6mdBaZgvRbmg6WRZ9bgynp8TmjnuEYHXKJaGGyOxbz uTgZfhl8dzkxLCv0P7N1tCkWms8O/o/hO2KSxxHN+4b9xCX/yve0/h2+GxFBWNVCxiNt NSz/+JfIBr1Le3gor9BJSilbxU2aV+EPlV5+hmmJg3Tr2ENKuoArmXjRm0LEyylGskWM +Gxg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1711530883; x=1712135683; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=oZiY/N9QWjiUSrWkYkKKgVbAI8JcvjPgGcqjy1l+QIE=; b=ZKI5uh4swYGU58ujecY6J/ZFzmBmwKVOe9YSrwJiz3DTtxaZFjrFWaXdO7hUtEJwe0 BJkRFuBFZxBq9KCHvuNwklzEAA8WxwKIWUOPktumxQJgxaklOiqjFjhyuF39CsmKu/Za XnxKNtG3cDKNJS7Xe7TRVFOromRWzwttlrGsKZo6v6nL0c0xk3ecx4xhU4+SZHJsqBnZ h1i0BqE/2ZMo52livOhqq332+YbIMh8/AGPtvPfZszwDrMaJNmBv4BqNSC3GO4VOo8LX QOPFQsvDQ/WT5fzx4twb6okYU/HPa95AYR5RIeo89oBl6am+WUr6Rxwnl92mwbwFe270 rtcQ== X-Forwarded-Encrypted: i=1; AJvYcCXaHq7EVZQYg3CuYdk14Ay89qhAJN1PxactzqgRWskgaSk3BuXG2G4HvToaU69dQeuXYDBviDL/8VlkFIlHHFKYV/+CHIhG4qzzdBvoqg== X-Gm-Message-State: AOJu0YynbK+LjoDFesMEx+wyUmMhw+OPmxJSIv6AhFIKikCqGQUlsOP4 lqM/6sb+97xWsnds1IST0foLoXQP7A7u4KGL6SM0wopi7+Rxqo9D5oH5yBWs1A== X-Google-Smtp-Source: AGHT+IEhjrzAmhdc31Ckj+SKUIw8a5+ySLGll4S+n7ONvtok2U56QZlSSqe5kaYrOAdathooGe1xBg== X-Received: by 2002:a05:6a00:2d25:b0:6ea:bf1c:9dfd with SMTP id fa37-20020a056a002d2500b006eabf1c9dfdmr2337979pfb.27.1711530882957; Wed, 27 Mar 2024 02:14:42 -0700 (PDT) Received: from [127.0.1.1] ([120.60.52.77]) by smtp.gmail.com with ESMTPSA id h190-20020a6383c7000000b005dc4fc80b21sm8673871pge.70.2024.03.27.02.14.30 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 27 Mar 2024 02:14:42 -0700 (PDT) From: Manivannan Sadhasivam Date: Wed, 27 Mar 2024 14:43:33 +0530 Subject: [PATCH v12 4/8] PCI: dwc: ep: Rename dw_pcie_ep_exit() to dw_pcie_ep_deinit() Precedence: bulk X-Mailing-List: linux-arm-msm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-Id: <20240327-pci-dbi-rework-v12-4-082625472414@linaro.org> References: <20240327-pci-dbi-rework-v12-0-082625472414@linaro.org> In-Reply-To: <20240327-pci-dbi-rework-v12-0-082625472414@linaro.org> To: Jingoo Han , Lorenzo Pieralisi , =?utf-8?q?Krzysztof_Wilczy?= =?utf-8?q?=C5=84ski?= , Rob Herring , Bjorn Helgaas , Marek Vasut , Yoshihiro Shimoda , Thierry Reding , Jonathan Hunter , Vidya Sagar , Vignesh Raghavendra , Richard Zhu , Lucas Stach , Shawn Guo , Sascha Hauer , Pengutronix Kernel Team , Fabio Estevam , NXP Linux Team , Minghuan Lian , Mingkai Hu , Roy Zang , Kunihiko Hayashi , Masami Hiramatsu , Kishon Vijay Abraham I , Jesper Nilsson , Srikanth Thokala , Shawn Lin , Heiko Stuebner , Kishon Vijay Abraham I Cc: linux-pci@vger.kernel.org, linux-kernel@vger.kernel.org, linux-renesas-soc@vger.kernel.org, linux-arm-msm@vger.kernel.org, linux-tegra@vger.kernel.org, linux-omap@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linuxppc-dev@lists.ozlabs.org, Niklas Cassel , linux-arm-kernel@axis.com, linux-rockchip@lists.infradead.org, Manivannan Sadhasivam , Frank Li X-Mailer: b4 0.12.4 X-Developer-Signature: v=1; a=openpgp-sha256; l=3334; i=manivannan.sadhasivam@linaro.org; h=from:subject:message-id; bh=xGVEiZ7J2TIauI1NZJAP+R7IoNGzHRfiU2LIamYdE4E=; b=owEBbQGS/pANAwAKAVWfEeb+kc71AcsmYgBmA+NJFpiteOu/bMaZydpCj3T9fJPQVQN/vgf+I pB4YUgDlCSJATMEAAEKAB0WIQRnpUMqgUjL2KRYJ5dVnxHm/pHO9QUCZgPjSQAKCRBVnxHm/pHO 9dD4B/0TWr4d5WLYoGlJRNd23GLjZofrVBBEdotNf5AQj9lgW1AwbW1nJPy48qrR6OmFgqtMwJU AoJRwRrLJd44NPcLVDU7k1DLcM2L6J0jwgpyc83rrCjVdhTIpCqP17u/lg9Tr6o3FaJWRAcR3qd UZ29lpeYmZT6uFNuM/VvklfmrSDKH/OoNtDQLszOKd51l/lmKCjdCnM+OEW5UuXSGNNMi2AJGCU 4jyHZy/eESG8OMB4JoGH+B4jhUN1g55aJd+iEVEAHtrh0s/RQs3/EjMpe/ktSaRupYnD/Sa2eTH FDYOiC3JgEjJ7H5spaG21OJihpC5FZLMmkOI3TsWwwBuyCMC X-Developer-Key: i=manivannan.sadhasivam@linaro.org; a=openpgp; fpr=C668AEC3C3188E4C611465E7488550E901166008 dw_pcie_ep_exit() API is undoing what the dw_pcie_ep_init() API has done already (at least partly). But the API name dw_pcie_ep_exit() is not quite reflecting that. So let's rename it to dw_pcie_ep_deinit() to make the purpose of this API clear. This also aligns with the DWC host driver. Reviewed-by: Frank Li Reviewed-by: Niklas Cassel Reviewed-by: Yoshihiro Shimoda Signed-off-by: Manivannan Sadhasivam --- drivers/pci/controller/dwc/pcie-designware-ep.c | 6 +++--- drivers/pci/controller/dwc/pcie-designware.h | 4 ++-- drivers/pci/controller/dwc/pcie-rcar-gen4.c | 2 +- 3 files changed, 6 insertions(+), 6 deletions(-) diff --git a/drivers/pci/controller/dwc/pcie-designware-ep.c b/drivers/pci/controller/dwc/pcie-designware-ep.c index f06598715412..d87f7642d7f6 100644 --- a/drivers/pci/controller/dwc/pcie-designware-ep.c +++ b/drivers/pci/controller/dwc/pcie-designware-ep.c @@ -620,13 +620,13 @@ int dw_pcie_ep_raise_msix_irq(struct dw_pcie_ep *ep, u8 func_no, } /** - * dw_pcie_ep_exit - Deinitialize the endpoint device + * dw_pcie_ep_deinit - Deinitialize the endpoint device * @ep: DWC EP device * * Deinitialize the endpoint device. EPC device is not destroyed since that will * be taken care by Devres. */ -void dw_pcie_ep_exit(struct dw_pcie_ep *ep) +void dw_pcie_ep_deinit(struct dw_pcie_ep *ep) { struct dw_pcie *pci = to_dw_pcie_from_ep(ep); struct pci_epc *epc = ep->epc; @@ -638,7 +638,7 @@ void dw_pcie_ep_exit(struct dw_pcie_ep *ep) pci_epc_mem_exit(epc); } -EXPORT_SYMBOL_GPL(dw_pcie_ep_exit); +EXPORT_SYMBOL_GPL(dw_pcie_ep_deinit); static unsigned int dw_pcie_ep_find_ext_capability(struct dw_pcie *pci, int cap) { diff --git a/drivers/pci/controller/dwc/pcie-designware.h b/drivers/pci/controller/dwc/pcie-designware.h index ab7431a37209..61465203bb60 100644 --- a/drivers/pci/controller/dwc/pcie-designware.h +++ b/drivers/pci/controller/dwc/pcie-designware.h @@ -671,7 +671,7 @@ void dw_pcie_ep_linkup(struct dw_pcie_ep *ep); int dw_pcie_ep_init(struct dw_pcie_ep *ep); int dw_pcie_ep_init_complete(struct dw_pcie_ep *ep); void dw_pcie_ep_init_notify(struct dw_pcie_ep *ep); -void dw_pcie_ep_exit(struct dw_pcie_ep *ep); +void dw_pcie_ep_deinit(struct dw_pcie_ep *ep); int dw_pcie_ep_raise_intx_irq(struct dw_pcie_ep *ep, u8 func_no); int dw_pcie_ep_raise_msi_irq(struct dw_pcie_ep *ep, u8 func_no, u8 interrupt_num); @@ -701,7 +701,7 @@ static inline void dw_pcie_ep_init_notify(struct dw_pcie_ep *ep) { } -static inline void dw_pcie_ep_exit(struct dw_pcie_ep *ep) +static inline void dw_pcie_ep_deinit(struct dw_pcie_ep *ep) { } diff --git a/drivers/pci/controller/dwc/pcie-rcar-gen4.c b/drivers/pci/controller/dwc/pcie-rcar-gen4.c index 5d29c4cfe0a0..de4bdfaecab3 100644 --- a/drivers/pci/controller/dwc/pcie-rcar-gen4.c +++ b/drivers/pci/controller/dwc/pcie-rcar-gen4.c @@ -432,7 +432,7 @@ static int rcar_gen4_add_dw_pcie_ep(struct rcar_gen4_pcie *rcar) static void rcar_gen4_remove_dw_pcie_ep(struct rcar_gen4_pcie *rcar) { - dw_pcie_ep_exit(&rcar->dw.ep); + dw_pcie_ep_deinit(&rcar->dw.ep); rcar_gen4_pcie_ep_deinit(rcar); } From patchwork Wed Mar 27 09:13:34 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Manivannan Sadhasivam X-Patchwork-Id: 13606040 Received: from mail-oo1-f42.google.com (mail-oo1-f42.google.com [209.85.161.42]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 51A234D9E0 for ; Wed, 27 Mar 2024 09:15:01 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.161.42 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1711530904; cv=none; b=NtkWVzZcega74ZrkLz5UL/kquhb2lYb/EdLEVXV/cOwjpUARsCMA4vyHNmM6/0+qA3gd9vfb2o+wsLpgprMR41yqyCq5IF+hhQdIQDVtObxrO0NY+R19Lf66lMKhKW5+GCyo7rzEWPQ+hB80x18NzH/4vlQruBOeZv4KUYgMvpo= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1711530904; c=relaxed/simple; bh=cYPmZhMWF9JrrdBXi4xoNK400WwuLP3vEJRvgS89ChI=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=EIaWglsu34NGZfYFPwxZb+TF12YTSZh83meswLWqcLqMBudi7sHTUO59zZ2gf/xOaDrhz/ihWpTiAEBgFyxwBiDAEBysjf85nma2aVWybiZbiBihqibE81ujFu/jTLsPSpVCic0T7MFLWT1zmyoYOyU5wxYqweJd5itu6Qn2DEo= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linaro.org; spf=pass smtp.mailfrom=linaro.org; dkim=pass (2048-bit key) header.d=linaro.org header.i=@linaro.org header.b=F+fNR5jH; arc=none smtp.client-ip=209.85.161.42 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linaro.org Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=linaro.org Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=linaro.org header.i=@linaro.org header.b="F+fNR5jH" Received: by mail-oo1-f42.google.com with SMTP id 006d021491bc7-5a4f9f94e77so3686182eaf.3 for ; Wed, 27 Mar 2024 02:15:01 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1711530901; x=1712135701; darn=vger.kernel.org; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:from:to:cc:subject:date:message-id :reply-to; bh=+w8+XZFFVZD9serrdKw4v46iT3fU34iMoHh0wJblC08=; b=F+fNR5jHGXqI7iB0nQg/3p6UgQ7b+L4ynULXLf6YKN412YlOWs0tnjyqkb9Jsh539b xTOhQzN38cbp0Equqe0p9fU7gTOGme8YvemGDFyQ7QzEJtfFJjlr6azq5i7Bx0Z/4LKq Ko8Ot6ZbQlf7YQM7CBWR6M44WPWW9ml4cQS+o2fmi3ZfAX/6ad8KmcBxd4TOAworNn44 TGaUL+ShidfgbtV4KkayFd5pvLR6G676oitlfDvsVv9tJkMEslOpJ8J1KoSbsNP/u2xW A3TcznUfQm0j00t4k6EpwsudSoMhfhyT33nu0WQ0j7b/0+u574POIQh1QwTmKwu1wpRN fEqw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1711530901; x=1712135701; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=+w8+XZFFVZD9serrdKw4v46iT3fU34iMoHh0wJblC08=; b=HkxKiNwTbXoHHTY2zvbi+aYkFW2WTCOYBUmzyGkFvT8lVYCRmG/gpxeG7wolCGe5hY itAfaVBGpL5aeIEiXbenF1YVN+lBT86iDPBAJVG0fEBiwVdGhMLNeiJKpl9BuB2/gISL iQWeiNKPQV0n78/YBO/cocZ6W4toQcFrfGhfweumZ5hrfuT7nkw9I6rXXS6P6bq0fg1X xy6UyJ4crkZNgAk3R2ClZMaHEgtAKxroMOc8AKN4sd1DOWvDUc7s5N1ExTJyMT1WK6cI Yz0Nj0qkmOcPdoKWIVe2o39P/Ifn6WXAH4TC4sp+fSH3ip5i7NDN6cDhQB+5/BckYCOS hNRw== X-Forwarded-Encrypted: i=1; AJvYcCUZ0T93xnXf8p91Lp2DxZPhFA4mwAe/EaMaVwsmg3mLE8TNQd2U9EUKytMJGGq2shqX77VOZ4CvwSm2ck1/HWgX3VQtwlVtD2o7CmbDZQ== X-Gm-Message-State: AOJu0Yyn/Rl0C5comLxcv9wDYipoZPRGJDdKs20qvHdPFNfX/gZ+xiU1 I0WKnRI1UxdK5bSR8vOKtwldYaJYXnbvaL36/FBljTzJgttIT0wu7qjaX+i+7A== X-Google-Smtp-Source: AGHT+IG0gU1p3u2cZSNbNacouPypPMZacdlL/OD6GpxQGu1TYUYdgA72yNE40cxd7c52iaQO+ragyw== X-Received: by 2002:a05:6358:7584:b0:17b:b559:2ba3 with SMTP id x4-20020a056358758400b0017bb5592ba3mr819971rwf.11.1711530900939; Wed, 27 Mar 2024 02:15:00 -0700 (PDT) Received: from [127.0.1.1] ([120.60.52.77]) by smtp.gmail.com with ESMTPSA id h190-20020a6383c7000000b005dc4fc80b21sm8673871pge.70.2024.03.27.02.14.43 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 27 Mar 2024 02:15:00 -0700 (PDT) From: Manivannan Sadhasivam Date: Wed, 27 Mar 2024 14:43:34 +0530 Subject: [PATCH v12 5/8] PCI: dwc: ep: Introduce dw_pcie_ep_cleanup() API for drivers supporting PERST# Precedence: bulk X-Mailing-List: linux-arm-msm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-Id: <20240327-pci-dbi-rework-v12-5-082625472414@linaro.org> References: <20240327-pci-dbi-rework-v12-0-082625472414@linaro.org> In-Reply-To: <20240327-pci-dbi-rework-v12-0-082625472414@linaro.org> To: Jingoo Han , Lorenzo Pieralisi , =?utf-8?q?Krzysztof_Wilczy?= =?utf-8?q?=C5=84ski?= , Rob Herring , Bjorn Helgaas , Marek Vasut , Yoshihiro Shimoda , Thierry Reding , Jonathan Hunter , Vidya Sagar , Vignesh Raghavendra , Richard Zhu , Lucas Stach , Shawn Guo , Sascha Hauer , Pengutronix Kernel Team , Fabio Estevam , NXP Linux Team , Minghuan Lian , Mingkai Hu , Roy Zang , Kunihiko Hayashi , Masami Hiramatsu , Kishon Vijay Abraham I , Jesper Nilsson , Srikanth Thokala , Shawn Lin , Heiko Stuebner , Kishon Vijay Abraham I Cc: linux-pci@vger.kernel.org, linux-kernel@vger.kernel.org, linux-renesas-soc@vger.kernel.org, linux-arm-msm@vger.kernel.org, linux-tegra@vger.kernel.org, linux-omap@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linuxppc-dev@lists.ozlabs.org, Niklas Cassel , linux-arm-kernel@axis.com, linux-rockchip@lists.infradead.org, Manivannan Sadhasivam , Frank Li X-Mailer: b4 0.12.4 X-Developer-Signature: v=1; a=openpgp-sha256; l=4250; i=manivannan.sadhasivam@linaro.org; h=from:subject:message-id; bh=cYPmZhMWF9JrrdBXi4xoNK400WwuLP3vEJRvgS89ChI=; b=owEBbQGS/pANAwAKAVWfEeb+kc71AcsmYgBmA+NJCy5UKQajgGLcJFCmTCocVuyMtWTlZ2Ejs QvYSXEZAl2JATMEAAEKAB0WIQRnpUMqgUjL2KRYJ5dVnxHm/pHO9QUCZgPjSQAKCRBVnxHm/pHO 9T6mB/9pFQquf5LOGTNXV2yHivElmVpYY5aK42tRZFhvZZ0Tq1cMStZlxIL1CLcpD/qAJJPoQS+ yVJ9edDCykI7R6KmW+PI1NL5g3gievubaOlD4LHYQpXWT3eRl4G1adOoeFRaOnbqHWAkiKFRgwM APGy4NWJvEX5fEswTOaqdUIxHOR1D8QSfTpyiQjtc6sbN4hICqqYVM/nNy9qVHB543u9n0PPMK5 mwWvNRApMkR5oCw9X9KChFW25uEjtpqUSGFHWzRJqYacYvkodK+xQuRVRbCraKJY/IJgSJouwp4 NYITRCwxRHIPKRVUpx5qz/2wRe4F6MoptuTdyT8F6F+m+R/s X-Developer-Key: i=manivannan.sadhasivam@linaro.org; a=openpgp; fpr=C668AEC3C3188E4C611465E7488550E901166008 For DWC glue drivers supporting PERST# (currently Qcom and Tegra194), some of the DWC resources like eDMA should be cleaned up during the PERST# assert time. So let's introduce a dw_pcie_ep_cleanup() API that could be called by these drivers to cleanup the DWC specific resources. Currently, it just removes eDMA. Reported-by: Niklas Cassel Closes: https://lore.kernel.org/linux-pci/ZWYmX8Y%2F7Q9WMxES@x1-carbon Reviewed-by: Frank Li Reviewed-by: Niklas Cassel Signed-off-by: Manivannan Sadhasivam --- drivers/pci/controller/dwc/pcie-designware-ep.c | 19 +++++++++++++++++-- drivers/pci/controller/dwc/pcie-designware.h | 5 +++++ drivers/pci/controller/dwc/pcie-qcom-ep.c | 1 + drivers/pci/controller/dwc/pcie-tegra194.c | 2 ++ 4 files changed, 25 insertions(+), 2 deletions(-) diff --git a/drivers/pci/controller/dwc/pcie-designware-ep.c b/drivers/pci/controller/dwc/pcie-designware-ep.c index d87f7642d7f6..eeff7f1ff8f1 100644 --- a/drivers/pci/controller/dwc/pcie-designware-ep.c +++ b/drivers/pci/controller/dwc/pcie-designware-ep.c @@ -619,6 +619,22 @@ int dw_pcie_ep_raise_msix_irq(struct dw_pcie_ep *ep, u8 func_no, return 0; } +/** + * dw_pcie_ep_cleanup - Cleanup DWC EP resources after fundamental reset + * @ep: DWC EP device + * + * Cleans up the DWC EP specific resources like eDMA etc... after fundamental + * reset like PERST#. Note that this API is only applicable for drivers + * supporting PERST# or any other methods of fundamental reset. + */ +void dw_pcie_ep_cleanup(struct dw_pcie_ep *ep) +{ + struct dw_pcie *pci = to_dw_pcie_from_ep(ep); + + dw_pcie_edma_remove(pci); +} +EXPORT_SYMBOL_GPL(dw_pcie_ep_cleanup); + /** * dw_pcie_ep_deinit - Deinitialize the endpoint device * @ep: DWC EP device @@ -628,10 +644,9 @@ int dw_pcie_ep_raise_msix_irq(struct dw_pcie_ep *ep, u8 func_no, */ void dw_pcie_ep_deinit(struct dw_pcie_ep *ep) { - struct dw_pcie *pci = to_dw_pcie_from_ep(ep); struct pci_epc *epc = ep->epc; - dw_pcie_edma_remove(pci); + dw_pcie_ep_cleanup(ep); pci_epc_mem_free_addr(epc, ep->msi_mem_phys, ep->msi_mem, epc->mem->window.page_size); diff --git a/drivers/pci/controller/dwc/pcie-designware.h b/drivers/pci/controller/dwc/pcie-designware.h index 61465203bb60..351d2fe3ea4d 100644 --- a/drivers/pci/controller/dwc/pcie-designware.h +++ b/drivers/pci/controller/dwc/pcie-designware.h @@ -672,6 +672,7 @@ int dw_pcie_ep_init(struct dw_pcie_ep *ep); int dw_pcie_ep_init_complete(struct dw_pcie_ep *ep); void dw_pcie_ep_init_notify(struct dw_pcie_ep *ep); void dw_pcie_ep_deinit(struct dw_pcie_ep *ep); +void dw_pcie_ep_cleanup(struct dw_pcie_ep *ep); int dw_pcie_ep_raise_intx_irq(struct dw_pcie_ep *ep, u8 func_no); int dw_pcie_ep_raise_msi_irq(struct dw_pcie_ep *ep, u8 func_no, u8 interrupt_num); @@ -705,6 +706,10 @@ static inline void dw_pcie_ep_deinit(struct dw_pcie_ep *ep) { } +static inline void dw_pcie_ep_cleanup(struct dw_pcie_ep *ep) +{ +} + static inline int dw_pcie_ep_raise_intx_irq(struct dw_pcie_ep *ep, u8 func_no) { return 0; diff --git a/drivers/pci/controller/dwc/pcie-qcom-ep.c b/drivers/pci/controller/dwc/pcie-qcom-ep.c index 36e5e80cd22f..59b1c0110288 100644 --- a/drivers/pci/controller/dwc/pcie-qcom-ep.c +++ b/drivers/pci/controller/dwc/pcie-qcom-ep.c @@ -507,6 +507,7 @@ static void qcom_pcie_perst_assert(struct dw_pcie *pci) return; } + dw_pcie_ep_cleanup(&pci->ep); qcom_pcie_disable_resources(pcie_ep); pcie_ep->link_status = QCOM_PCIE_EP_LINK_DISABLED; } diff --git a/drivers/pci/controller/dwc/pcie-tegra194.c b/drivers/pci/controller/dwc/pcie-tegra194.c index 1f7b662cb8e1..26ea2f8313eb 100644 --- a/drivers/pci/controller/dwc/pcie-tegra194.c +++ b/drivers/pci/controller/dwc/pcie-tegra194.c @@ -1715,6 +1715,8 @@ static void pex_ep_event_pex_rst_assert(struct tegra_pcie_dw *pcie) if (ret) dev_err(pcie->dev, "Failed to go Detect state: %d\n", ret); + dw_pcie_ep_cleanup(&pcie->pci.ep); + reset_control_assert(pcie->core_rst); tegra_pcie_disable_phy(pcie); From patchwork Wed Mar 27 09:13:35 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Manivannan Sadhasivam X-Patchwork-Id: 13606041 Received: from mail-pf1-f170.google.com (mail-pf1-f170.google.com [209.85.210.170]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 483F038DF2 for ; Wed, 27 Mar 2024 09:15:20 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.210.170 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1711530922; cv=none; b=WUhuGq+yjxGuvU+geE9wRupzJ2S6OxDPaup1z8HwtMv9v0++WqjEIHaXKVIR5pLloDeA/eAUYVlnsNzx/9xwTMwz0r/C/JQofEXbCWj0XlCJpSztQECj7Vj2LTD7smdUKhQKYbi4MmYMEyMu4SyyaFNmqxTLBzC4L4Ev60hka9g= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1711530922; c=relaxed/simple; bh=V0Mzth2vl1K0DFypRpWN9TY0MnmoC5wp8l5W1GdqahU=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=JGCIugZ1fa9ssoqn+/EwS0xpeCMOJe3MmG5o9jAXHK/TryR7v7gANfHeMF6mfGAXt7hMVhvTZo3kJODBoMyboCZOKrQL2f1Zol5s7yx8s4xpMZoCAaHXfAdZlnIYmmFDOm/9NkRK+crKTz53KvR5nVS1sUU0kbOKwBTnle0tM0M= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linaro.org; spf=pass smtp.mailfrom=linaro.org; dkim=pass (2048-bit key) header.d=linaro.org header.i=@linaro.org header.b=WrcehUTk; arc=none smtp.client-ip=209.85.210.170 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linaro.org Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=linaro.org Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=linaro.org header.i=@linaro.org header.b="WrcehUTk" Received: by mail-pf1-f170.google.com with SMTP id d2e1a72fcca58-6e6b22af648so497186b3a.0 for ; Wed, 27 Mar 2024 02:15:20 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1711530920; x=1712135720; darn=vger.kernel.org; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:from:to:cc:subject:date:message-id :reply-to; bh=4+s99ic6a4xby36ko4cSNl1g4BMNR39F6N7WDhYUFLA=; b=WrcehUTk03GvAxTi9G1xRBmR+aeHFtunVq+teYiv/ZB8RjSN/JR6OYeMAvagCsH/8j ZPe/BAQfQJmZ6nRws9jmH4foQLLYxAh0T+ax3rxtWCXbtPayWD0ZLyMCb2/DZKr5ySCj n2jcKB8bze/XjcaBTnct9UdJzx8hy6rD7w6uta2kCwDYUYct7CpwtbG3MtVzyh1DLfW7 aUOLCEiWflltXVeThhrAQJoevJm8W5YEKjVCQBXnmse4JgGmaYXkCI9kXdvsYgAxs734 s/xbof+2PfazgOWVDpJYRYIM9Zb4eF3Vx+3ZKp4dKdF2TiJgJ13U968grIMaJ8znik/q b0vA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1711530920; x=1712135720; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=4+s99ic6a4xby36ko4cSNl1g4BMNR39F6N7WDhYUFLA=; b=V+v3fWuLHZzdiDwx+whqMk3f9zGlmXGivhcJHEJ2S44AfXchZUGEucB4U6Nr8H4rFp gPYFD9nXVfx0V5yjwVahUIri0lozwaOSuDI/S8LUWNqXp7XMPcEQIrd2jFg9yjAiU0G1 knRn2AChAXHqpgzK7TOxoWTze0zWv9EQq/dtDiNR0hPRcjh4GypKUJ+osfCMhJt64ICc Up0jB7HvBe/0lbrTkp9HC0+6JqilAMeRwmloZRXkUVabDft2mcGDmoXNqWklipWBj1Qk 1/QUi49eslGKec7H/Svh226hoq/C7f5DXtbuoXI7r9dq2ZV8QedkWIpXC5feVemEvtsc k/fw== X-Forwarded-Encrypted: i=1; AJvYcCUYhGnip9QAHQMRXoAtsC5EmChyjWvGpW+wEfEcUKHj15jdomJwLGVrqVeHWcHEoNqjoox5nU5UKMUWUdWJy0Y/JrwGzt4Z76tet3g9Qg== X-Gm-Message-State: AOJu0YwlR7orKw6tjR6tuXZfh0ieeCaHqxlp2/I2rEnQawrcZuU7VZGG N1E6TFyg+kteDP70sLoGomXxHODgJD7AVEu1gQLreaEi7YqxrqjhqdBThUe5gg== X-Google-Smtp-Source: AGHT+IGGlNwqqhJyPDs53FUp8HnF8MxmatY5hAsgpFI+AE8YxYjYhWVdUxUP+eXF583iNe5GoKe6mw== X-Received: by 2002:a05:6a21:32a4:b0:1a3:63cd:5262 with SMTP id yt36-20020a056a2132a400b001a363cd5262mr5531403pzb.26.1711530919209; Wed, 27 Mar 2024 02:15:19 -0700 (PDT) Received: from [127.0.1.1] ([120.60.52.77]) by smtp.gmail.com with ESMTPSA id h190-20020a6383c7000000b005dc4fc80b21sm8673871pge.70.2024.03.27.02.15.01 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 27 Mar 2024 02:15:18 -0700 (PDT) From: Manivannan Sadhasivam Date: Wed, 27 Mar 2024 14:43:35 +0530 Subject: [PATCH v12 6/8] PCI: dwc: ep: Rename dw_pcie_ep_init_complete() to dw_pcie_ep_init_registers() Precedence: bulk X-Mailing-List: linux-arm-msm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-Id: <20240327-pci-dbi-rework-v12-6-082625472414@linaro.org> References: <20240327-pci-dbi-rework-v12-0-082625472414@linaro.org> In-Reply-To: <20240327-pci-dbi-rework-v12-0-082625472414@linaro.org> To: Jingoo Han , Lorenzo Pieralisi , =?utf-8?q?Krzysztof_Wilczy?= =?utf-8?q?=C5=84ski?= , Rob Herring , Bjorn Helgaas , Marek Vasut , Yoshihiro Shimoda , Thierry Reding , Jonathan Hunter , Vidya Sagar , Vignesh Raghavendra , Richard Zhu , Lucas Stach , Shawn Guo , Sascha Hauer , Pengutronix Kernel Team , Fabio Estevam , NXP Linux Team , Minghuan Lian , Mingkai Hu , Roy Zang , Kunihiko Hayashi , Masami Hiramatsu , Kishon Vijay Abraham I , Jesper Nilsson , Srikanth Thokala , Shawn Lin , Heiko Stuebner , Kishon Vijay Abraham I Cc: linux-pci@vger.kernel.org, linux-kernel@vger.kernel.org, linux-renesas-soc@vger.kernel.org, linux-arm-msm@vger.kernel.org, linux-tegra@vger.kernel.org, linux-omap@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linuxppc-dev@lists.ozlabs.org, Niklas Cassel , linux-arm-kernel@axis.com, linux-rockchip@lists.infradead.org, Manivannan Sadhasivam , Frank Li X-Mailer: b4 0.12.4 X-Developer-Signature: v=1; a=openpgp-sha256; l=4791; i=manivannan.sadhasivam@linaro.org; h=from:subject:message-id; bh=V0Mzth2vl1K0DFypRpWN9TY0MnmoC5wp8l5W1GdqahU=; b=owEBbQGS/pANAwAKAVWfEeb+kc71AcsmYgBmA+NJlxhtcI5x9HWzPDSMHMbS7UUf3ccej2MOr Gzs0KQ0lNqJATMEAAEKAB0WIQRnpUMqgUjL2KRYJ5dVnxHm/pHO9QUCZgPjSQAKCRBVnxHm/pHO 9RqICACXtyJ4U4bh9LLyWGD3MnW+UaIlaEoKFtd4l7YOpLPXe+ZOCiCG2SqP2VwPGBQB0AYX3Xi 0wPUXq/TdoUXUgXkKzNjY2AdItwj+kDbJPVrMu6Wf4VyxDfNwM/X53E7QMmUBynilnn6s4wTATg o/NhZDNTBFFSDkRrLYdPeZdAG+TryXFOBkadhD1Phx/6iy4GOTCQajvuGi9yvDHWu0YTtffO47l ixzD8lGfiQBguL3irb2Oi4TIbZSdC2YOVYto+eG7SU/TTU8cH6O7xzgNj1EmVpx0lwqRohk01PL oc0BF2SEjA/fL1yk3YTlMDuWlzBOmS0ZGJTw6wchBfxS/Wxy X-Developer-Key: i=manivannan.sadhasivam@linaro.org; a=openpgp; fpr=C668AEC3C3188E4C611465E7488550E901166008 The goal of the dw_pcie_ep_init_complete() API is to initialize the DWC specific registers post registering the controller with the EP framework. But the naming doesn't reflect its functionality and causes confusion. So, let's rename it to dw_pcie_ep_init_registers() to make it clear that it initializes the DWC specific registers. Reviewed-by: Frank Li Reviewed-by: Niklas Cassel Signed-off-by: Manivannan Sadhasivam --- drivers/pci/controller/dwc/pcie-designware-ep.c | 14 +++++++------- drivers/pci/controller/dwc/pcie-designware.h | 4 ++-- drivers/pci/controller/dwc/pcie-qcom-ep.c | 2 +- drivers/pci/controller/dwc/pcie-tegra194.c | 2 +- 4 files changed, 11 insertions(+), 11 deletions(-) diff --git a/drivers/pci/controller/dwc/pcie-designware-ep.c b/drivers/pci/controller/dwc/pcie-designware-ep.c index eeff7f1ff8f1..761d3012a073 100644 --- a/drivers/pci/controller/dwc/pcie-designware-ep.c +++ b/drivers/pci/controller/dwc/pcie-designware-ep.c @@ -674,14 +674,14 @@ static unsigned int dw_pcie_ep_find_ext_capability(struct dw_pcie *pci, int cap) } /** - * dw_pcie_ep_init_complete - Complete DWC EP initialization + * dw_pcie_ep_init_registers - Initialize DWC EP specific registers * @ep: DWC EP device * - * Complete the initialization of the registers (CSRs) specific to DWC EP. This - * API should be called only when the endpoint receives an active refclk (either - * from host or generated locally). + * Initialize the registers (CSRs) specific to DWC EP. This API should be called + * only when the endpoint receives an active refclk (either from host or + * generated locally). */ -int dw_pcie_ep_init_complete(struct dw_pcie_ep *ep) +int dw_pcie_ep_init_registers(struct dw_pcie_ep *ep) { struct dw_pcie *pci = to_dw_pcie_from_ep(ep); struct dw_pcie_ep_func *ep_func; @@ -801,7 +801,7 @@ int dw_pcie_ep_init_complete(struct dw_pcie_ep *ep) return ret; } -EXPORT_SYMBOL_GPL(dw_pcie_ep_init_complete); +EXPORT_SYMBOL_GPL(dw_pcie_ep_init_registers); /** * dw_pcie_ep_init - Initialize the endpoint device @@ -880,7 +880,7 @@ int dw_pcie_ep_init(struct dw_pcie_ep *ep) * (Ex: tegra194). Any hardware access on such platforms result * in system hang. */ - ret = dw_pcie_ep_init_complete(ep); + ret = dw_pcie_ep_init_registers(ep); if (ret) goto err_free_epc_mem; diff --git a/drivers/pci/controller/dwc/pcie-designware.h b/drivers/pci/controller/dwc/pcie-designware.h index 351d2fe3ea4d..f8e5431a207b 100644 --- a/drivers/pci/controller/dwc/pcie-designware.h +++ b/drivers/pci/controller/dwc/pcie-designware.h @@ -669,7 +669,7 @@ static inline void __iomem *dw_pcie_own_conf_map_bus(struct pci_bus *bus, #ifdef CONFIG_PCIE_DW_EP void dw_pcie_ep_linkup(struct dw_pcie_ep *ep); int dw_pcie_ep_init(struct dw_pcie_ep *ep); -int dw_pcie_ep_init_complete(struct dw_pcie_ep *ep); +int dw_pcie_ep_init_registers(struct dw_pcie_ep *ep); void dw_pcie_ep_init_notify(struct dw_pcie_ep *ep); void dw_pcie_ep_deinit(struct dw_pcie_ep *ep); void dw_pcie_ep_cleanup(struct dw_pcie_ep *ep); @@ -693,7 +693,7 @@ static inline int dw_pcie_ep_init(struct dw_pcie_ep *ep) return 0; } -static inline int dw_pcie_ep_init_complete(struct dw_pcie_ep *ep) +static inline int dw_pcie_ep_init_registers(struct dw_pcie_ep *ep) { return 0; } diff --git a/drivers/pci/controller/dwc/pcie-qcom-ep.c b/drivers/pci/controller/dwc/pcie-qcom-ep.c index 59b1c0110288..3697b4a944cc 100644 --- a/drivers/pci/controller/dwc/pcie-qcom-ep.c +++ b/drivers/pci/controller/dwc/pcie-qcom-ep.c @@ -463,7 +463,7 @@ static int qcom_pcie_perst_deassert(struct dw_pcie *pci) PARF_INT_ALL_LINK_UP | PARF_INT_ALL_EDMA; writel_relaxed(val, pcie_ep->parf + PARF_INT_ALL_MASK); - ret = dw_pcie_ep_init_complete(&pcie_ep->pci.ep); + ret = dw_pcie_ep_init_registers(&pcie_ep->pci.ep); if (ret) { dev_err(dev, "Failed to complete initialization: %d\n", ret); goto err_disable_resources; diff --git a/drivers/pci/controller/dwc/pcie-tegra194.c b/drivers/pci/controller/dwc/pcie-tegra194.c index 26ea2f8313eb..db043f579fbe 100644 --- a/drivers/pci/controller/dwc/pcie-tegra194.c +++ b/drivers/pci/controller/dwc/pcie-tegra194.c @@ -1897,7 +1897,7 @@ static void pex_ep_event_pex_rst_deassert(struct tegra_pcie_dw *pcie) val = (upper_32_bits(ep->msi_mem_phys) & MSIX_ADDR_MATCH_HIGH_OFF_MASK); dw_pcie_writel_dbi(pci, MSIX_ADDR_MATCH_HIGH_OFF, val); - ret = dw_pcie_ep_init_complete(ep); + ret = dw_pcie_ep_init_registers(ep); if (ret) { dev_err(dev, "Failed to complete initialization: %d\n", ret); goto fail_init_complete; From patchwork Wed Mar 27 09:13:36 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Manivannan Sadhasivam X-Patchwork-Id: 13606042 Received: from mail-il1-f173.google.com (mail-il1-f173.google.com [209.85.166.173]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id C30BD37702 for ; Wed, 27 Mar 2024 09:15:46 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.166.173 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1711530950; cv=none; b=JoLaoY5WbLMPCngC7Pv+t2yrBx5jFj5l0Dbvb6z+iNzuX3Prp9OnhzWyavG5vmzLFTS3GrhVJxv5/ov1ryUaO9XbUvNHFePvRCKeyWicEpX+J2EfPX0F3vEX5iJr/AYQdhvWj8DIJV3u3COOiXvn229g/Yv5MV49a4BfLsq8aj0= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1711530950; c=relaxed/simple; bh=IONhCw0ebndFj0D0FHcgfPfYalCU00+jRBsWXR5KqGc=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=GYW3G1cOXdkmitIWdmzmJjoBLwPNU7j7xa5YPKlbiewr8TiNDvyBCtcN4c+HloXuK5BT2kHStC01G4YTaNiAEunsx1lYTSvXFiGlMxuSr3avcU0HWmaF/i1+k6Jt/9OyJXFvVbaIaWPLOusMS57ohSgjCpgRhzwFH7VcTLQaPtA= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linaro.org; spf=pass smtp.mailfrom=linaro.org; dkim=pass (2048-bit key) header.d=linaro.org header.i=@linaro.org header.b=GdArIhDi; arc=none smtp.client-ip=209.85.166.173 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linaro.org Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=linaro.org Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=linaro.org header.i=@linaro.org header.b="GdArIhDi" Received: by mail-il1-f173.google.com with SMTP id e9e14a558f8ab-3688b3e915cso11275785ab.1 for ; Wed, 27 Mar 2024 02:15:46 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1711530946; x=1712135746; darn=vger.kernel.org; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:from:to:cc:subject:date:message-id :reply-to; bh=oDRwBHiRbqQEPbqIMMuwLPfNBgzS7ecnVO7qDgoOiM4=; b=GdArIhDi3FmhGUbWNzxYydGdF+7gWuCOUJEq0AEgxtOPDHG9Igr9Reo22tab7g6NPV f/ak3kWpUeKGKtHiS8S4e0IrYcBZBbI23wrGwL26QfTnXEuIiGx6BO/mzvyw8vVJe5VX 29m/46mElgJoRF3aEG7B+CVmZR/kCLtNkLDGfHG9syQKoQXH3LZJjFVnM5AqBKrf2uY2 5w6new2xxyLAFqPbGJTfBfxnN6CCyXstT+HuhIN5+K0cVks0JZEOuDjIwS2cmDTadgv8 Kw/LJaeia7RCTQXFpmZo9zUdexQ0YykNZjf4vu79N42RK/PSq88pSVnynsxsKfujhxBZ US0Q== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1711530946; x=1712135746; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=oDRwBHiRbqQEPbqIMMuwLPfNBgzS7ecnVO7qDgoOiM4=; b=wiOm7yEtdt/UR/79gfuQBajLeCaae52bjaYB0jfbDkzoTNXRJ/TTBMJX2++OHcRP8z NXGboeLZQQ9VuEvw8eSegvpHq21mNLPkFbTmOELlPN4HGPe5xwsfM+O6wsVfBhdPomx8 D6cPPToPfTIcx3RlwbwcQFmhHzCFATHUKHX90HWosUpOZaVTeUI6tAk7D1gIw4VCv+Bn PINlCBMOrRYbyu8EuQ3GnBiGfhPRipNTCLmqFdut+bGKWUKL1xL0XPfqFA9O8g4RhcAx KSDO9H+bTmx4BjiA3cl2rUTCSbWpQBoePdayOuwprCWglSXwpdZ7MAYULYuck/jQ8wst IMLQ== X-Forwarded-Encrypted: i=1; AJvYcCWRknunCc5xviwHPmIPmdzLZacIYHtifGNbK8WQ3HKtWbuiREGpfYXsNEz6jlnd2Nv8SBAudJJC7uJQH5+uZlkDwy1Em40ZKEcLlUmoVA== X-Gm-Message-State: AOJu0YxonNoJ6C4ekjtKB3dE9/OfNEggtKo8w0ClaQNtrZBo1l1VfpFi lI+ew2x4QQvEUITS4d/ThPK4soJS29EbKZk/ZZ3drU1UnjbT1eOq1SWIOY4pbQ== X-Google-Smtp-Source: AGHT+IEufUNP1l3Yj4uUlYleyaGx50CKkBEG8OSB8cxTtNznEki2vTEQUdAKopuRntEIfoYHhGsePw== X-Received: by 2002:a92:c8d0:0:b0:368:959d:e19b with SMTP id c16-20020a92c8d0000000b00368959de19bmr3243682ilq.18.1711530945705; Wed, 27 Mar 2024 02:15:45 -0700 (PDT) Received: from [127.0.1.1] ([120.60.52.77]) by smtp.gmail.com with ESMTPSA id h190-20020a6383c7000000b005dc4fc80b21sm8673871pge.70.2024.03.27.02.15.19 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 27 Mar 2024 02:15:44 -0700 (PDT) From: Manivannan Sadhasivam Date: Wed, 27 Mar 2024 14:43:36 +0530 Subject: [PATCH v12 7/8] PCI: dwc: ep: Call dw_pcie_ep_init_registers() API directly from all glue drivers Precedence: bulk X-Mailing-List: linux-arm-msm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-Id: <20240327-pci-dbi-rework-v12-7-082625472414@linaro.org> References: <20240327-pci-dbi-rework-v12-0-082625472414@linaro.org> In-Reply-To: <20240327-pci-dbi-rework-v12-0-082625472414@linaro.org> To: Jingoo Han , Lorenzo Pieralisi , =?utf-8?q?Krzysztof_Wilczy?= =?utf-8?q?=C5=84ski?= , Rob Herring , Bjorn Helgaas , Marek Vasut , Yoshihiro Shimoda , Thierry Reding , Jonathan Hunter , Vidya Sagar , Vignesh Raghavendra , Richard Zhu , Lucas Stach , Shawn Guo , Sascha Hauer , Pengutronix Kernel Team , Fabio Estevam , NXP Linux Team , Minghuan Lian , Mingkai Hu , Roy Zang , Kunihiko Hayashi , Masami Hiramatsu , Kishon Vijay Abraham I , Jesper Nilsson , Srikanth Thokala , Shawn Lin , Heiko Stuebner , Kishon Vijay Abraham I Cc: linux-pci@vger.kernel.org, linux-kernel@vger.kernel.org, linux-renesas-soc@vger.kernel.org, linux-arm-msm@vger.kernel.org, linux-tegra@vger.kernel.org, linux-omap@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linuxppc-dev@lists.ozlabs.org, Niklas Cassel , linux-arm-kernel@axis.com, linux-rockchip@lists.infradead.org, Manivannan Sadhasivam X-Mailer: b4 0.12.4 X-Developer-Signature: v=1; a=openpgp-sha256; l=10284; i=manivannan.sadhasivam@linaro.org; h=from:subject:message-id; bh=IONhCw0ebndFj0D0FHcgfPfYalCU00+jRBsWXR5KqGc=; b=owEBbQGS/pANAwAKAVWfEeb+kc71AcsmYgBmA+NKRIxoOZAmhOTG3obk72yNOH9WGwAGM6Eoo 1dkTQ7/BT6JATMEAAEKAB0WIQRnpUMqgUjL2KRYJ5dVnxHm/pHO9QUCZgPjSgAKCRBVnxHm/pHO 9RbMB/48Y8jv1OxN1gIaWLcu/uaKFJBY4CHxlIh9i3mebEFZsvWoNV8G1PORQcVluBv5mQah3I/ fU4JJxS59jAOW+fFQLAomBCJ+mx1GUePHTUtV0dTYufmGDLC7SCarj2XiNAV4ZeVaN+qS2Vjhoy ugrzVz7Amwa/BOvwg+o72nOizguiOf46jvBL0Fo4iNxijFnASV2ZhuE5o4vgCQdut2F8VM9g1nB lA8Nh3fSXhkYwIs5cJQga2Sh2t9bTMDs9whZJv5WB7sEwm5mUgrtIY4McS0ljTBdo+nXkSzHj8d 97B1h11bPrN9Ws7Ha5tb/eEeg+B8L5EQYvnYSMdoGyBKNaTo X-Developer-Key: i=manivannan.sadhasivam@linaro.org; a=openpgp; fpr=C668AEC3C3188E4C611465E7488550E901166008 Currently, dw_pcie_ep_init_registers() API is directly called by the glue drivers requiring active refclk from host. But for the other drivers, it is getting called implicitly by dw_pcie_ep_init(). This is due to the fact that this API initializes DWC EP specific registers and that requires an active refclk (either from host or generated locally by endpoint itsef). But, this causes a discrepancy among the glue drivers. So to avoid this confusion, let's call this API directly from all glue drivers irrespective of refclk dependency. Only difference here is that the drivers requiring refclk from host will call this API only after the refclk is received and other drivers without refclk dependency will call this API right after dw_pcie_ep_init(). With this change, the check for 'core_init_notifier' flag can now be dropped from dw_pcie_ep_init() API. This will also allow us to remove the 'core_init_notifier' flag completely in the later commits. Reviewed-by: Yoshihiro Shimoda Reviewed-by: Niklas Cassel Signed-off-by: Manivannan Sadhasivam Reviewed-by: Frank Li --- drivers/pci/controller/dwc/pci-dra7xx.c | 7 +++++++ drivers/pci/controller/dwc/pci-imx6.c | 8 ++++++++ drivers/pci/controller/dwc/pci-keystone.c | 9 +++++++++ drivers/pci/controller/dwc/pci-layerscape-ep.c | 7 +++++++ drivers/pci/controller/dwc/pcie-artpec6.c | 13 ++++++++++++- drivers/pci/controller/dwc/pcie-designware-ep.c | 22 ---------------------- drivers/pci/controller/dwc/pcie-designware-plat.c | 9 +++++++++ drivers/pci/controller/dwc/pcie-keembay.c | 16 +++++++++++++++- drivers/pci/controller/dwc/pcie-rcar-gen4.c | 12 +++++++++++- drivers/pci/controller/dwc/pcie-uniphier-ep.c | 13 ++++++++++++- 10 files changed, 90 insertions(+), 26 deletions(-) diff --git a/drivers/pci/controller/dwc/pci-dra7xx.c b/drivers/pci/controller/dwc/pci-dra7xx.c index 0e406677060d..395042b29ffc 100644 --- a/drivers/pci/controller/dwc/pci-dra7xx.c +++ b/drivers/pci/controller/dwc/pci-dra7xx.c @@ -467,6 +467,13 @@ static int dra7xx_add_pcie_ep(struct dra7xx_pcie *dra7xx, return ret; } + ret = dw_pcie_ep_init_registers(ep); + if (ret) { + dev_err(dev, "Failed to initialize DWC endpoint registers\n"); + dw_pcie_ep_deinit(ep); + return ret; + } + return 0; } diff --git a/drivers/pci/controller/dwc/pci-imx6.c b/drivers/pci/controller/dwc/pci-imx6.c index 99a60270b26c..8d28ecc381bc 100644 --- a/drivers/pci/controller/dwc/pci-imx6.c +++ b/drivers/pci/controller/dwc/pci-imx6.c @@ -1123,6 +1123,14 @@ static int imx6_add_pcie_ep(struct imx6_pcie *imx6_pcie, dev_err(dev, "failed to initialize endpoint\n"); return ret; } + + ret = dw_pcie_ep_init_registers(ep); + if (ret) { + dev_err(dev, "Failed to initialize DWC endpoint registers\n"); + dw_pcie_ep_deinit(ep); + return ret; + } + /* Start LTSSM. */ imx6_pcie_ltssm_enable(dev); diff --git a/drivers/pci/controller/dwc/pci-keystone.c b/drivers/pci/controller/dwc/pci-keystone.c index 844de4418724..81ebac520650 100644 --- a/drivers/pci/controller/dwc/pci-keystone.c +++ b/drivers/pci/controller/dwc/pci-keystone.c @@ -1286,6 +1286,13 @@ static int ks_pcie_probe(struct platform_device *pdev) ret = dw_pcie_ep_init(&pci->ep); if (ret < 0) goto err_get_sync; + + ret = dw_pcie_ep_init_registers(&pci->ep); + if (ret) { + dev_err(dev, "Failed to initialize DWC endpoint registers\n"); + goto err_ep_init; + } + break; default: dev_err(dev, "INVALID device type %d\n", mode); @@ -1295,6 +1302,8 @@ static int ks_pcie_probe(struct platform_device *pdev) return 0; +err_ep_init: + dw_pcie_ep_deinit(&pci->ep); err_get_sync: pm_runtime_put(dev); pm_runtime_disable(dev); diff --git a/drivers/pci/controller/dwc/pci-layerscape-ep.c b/drivers/pci/controller/dwc/pci-layerscape-ep.c index 1f6ee1460ec2..9eb2233e3d7f 100644 --- a/drivers/pci/controller/dwc/pci-layerscape-ep.c +++ b/drivers/pci/controller/dwc/pci-layerscape-ep.c @@ -279,6 +279,13 @@ static int __init ls_pcie_ep_probe(struct platform_device *pdev) if (ret) return ret; + ret = dw_pcie_ep_init_registers(&pci->ep); + if (ret) { + dev_err(dev, "Failed to initialize DWC endpoint registers\n"); + dw_pcie_ep_deinit(&pci->ep); + return ret; + } + return ls_pcie_ep_interrupt_init(pcie, pdev); } diff --git a/drivers/pci/controller/dwc/pcie-artpec6.c b/drivers/pci/controller/dwc/pcie-artpec6.c index 9ed0a9ba7619..a6095561db4a 100644 --- a/drivers/pci/controller/dwc/pcie-artpec6.c +++ b/drivers/pci/controller/dwc/pcie-artpec6.c @@ -441,7 +441,18 @@ static int artpec6_pcie_probe(struct platform_device *pdev) pci->ep.ops = &pcie_ep_ops; - return dw_pcie_ep_init(&pci->ep); + ret = dw_pcie_ep_init(&pci->ep); + if (ret) + return ret; + + ret = dw_pcie_ep_init_registers(&pci->ep); + if (ret) { + dev_err(dev, "Failed to initialize DWC endpoint registers\n"); + dw_pcie_ep_deinit(&pci->ep); + return ret; + } + + break; default: dev_err(dev, "INVALID device type %d\n", artpec6_pcie->mode); } diff --git a/drivers/pci/controller/dwc/pcie-designware-ep.c b/drivers/pci/controller/dwc/pcie-designware-ep.c index 761d3012a073..2063cf2049e5 100644 --- a/drivers/pci/controller/dwc/pcie-designware-ep.c +++ b/drivers/pci/controller/dwc/pcie-designware-ep.c @@ -821,7 +821,6 @@ int dw_pcie_ep_init(struct dw_pcie_ep *ep) struct device *dev = pci->dev; struct platform_device *pdev = to_platform_device(dev); struct device_node *np = dev->of_node; - const struct pci_epc_features *epc_features; INIT_LIST_HEAD(&ep->func_list); @@ -867,29 +866,8 @@ int dw_pcie_ep_init(struct dw_pcie_ep *ep) goto err_exit_epc_mem; } - if (ep->ops->get_features) { - epc_features = ep->ops->get_features(ep); - if (epc_features->core_init_notifier) - return 0; - } - - /* - * NOTE:- Avoid accessing the hardware (Ex:- DBI space) before this - * step as platforms that implement 'core_init_notifier' feature may - * not have the hardware ready (i.e. core initialized) for access - * (Ex: tegra194). Any hardware access on such platforms result - * in system hang. - */ - ret = dw_pcie_ep_init_registers(ep); - if (ret) - goto err_free_epc_mem; - return 0; -err_free_epc_mem: - pci_epc_mem_free_addr(epc, ep->msi_mem_phys, ep->msi_mem, - epc->mem->window.page_size); - err_exit_epc_mem: pci_epc_mem_exit(epc); diff --git a/drivers/pci/controller/dwc/pcie-designware-plat.c b/drivers/pci/controller/dwc/pcie-designware-plat.c index 778588b4be70..ca9b22e654cd 100644 --- a/drivers/pci/controller/dwc/pcie-designware-plat.c +++ b/drivers/pci/controller/dwc/pcie-designware-plat.c @@ -145,6 +145,15 @@ static int dw_plat_pcie_probe(struct platform_device *pdev) pci->ep.ops = &pcie_ep_ops; ret = dw_pcie_ep_init(&pci->ep); + if (ret) + return ret; + + ret = dw_pcie_ep_init_registers(&pci->ep); + if (ret) { + dev_err(dev, "Failed to initialize DWC endpoint registers\n"); + dw_pcie_ep_deinit(&pci->ep); + } + break; default: dev_err(dev, "INVALID device type %d\n", dw_plat_pcie->mode); diff --git a/drivers/pci/controller/dwc/pcie-keembay.c b/drivers/pci/controller/dwc/pcie-keembay.c index 5e8e54f597dd..b2556dbcffb5 100644 --- a/drivers/pci/controller/dwc/pcie-keembay.c +++ b/drivers/pci/controller/dwc/pcie-keembay.c @@ -396,6 +396,7 @@ static int keembay_pcie_probe(struct platform_device *pdev) struct keembay_pcie *pcie; struct dw_pcie *pci; enum dw_pcie_device_mode mode; + int ret; data = device_get_match_data(dev); if (!data) @@ -430,11 +431,24 @@ static int keembay_pcie_probe(struct platform_device *pdev) return -ENODEV; pci->ep.ops = &keembay_pcie_ep_ops; - return dw_pcie_ep_init(&pci->ep); + ret = dw_pcie_ep_init(&pci->ep); + if (ret) + return ret; + + ret = dw_pcie_ep_init_registers(&pci->ep); + if (ret) { + dev_err(dev, "Failed to initialize DWC endpoint registers\n"); + dw_pcie_ep_deinit(&pci->ep); + return ret; + } + + break; default: dev_err(dev, "Invalid device type %d\n", pcie->mode); return -ENODEV; } + + return 0; } static const struct keembay_pcie_of_data keembay_pcie_rc_of_data = { diff --git a/drivers/pci/controller/dwc/pcie-rcar-gen4.c b/drivers/pci/controller/dwc/pcie-rcar-gen4.c index de4bdfaecab3..e155a905fb4f 100644 --- a/drivers/pci/controller/dwc/pcie-rcar-gen4.c +++ b/drivers/pci/controller/dwc/pcie-rcar-gen4.c @@ -416,6 +416,7 @@ static const struct dw_pcie_ep_ops pcie_ep_ops = { static int rcar_gen4_add_dw_pcie_ep(struct rcar_gen4_pcie *rcar) { struct dw_pcie_ep *ep = &rcar->dw.ep; + struct device *dev = rcar->dw.dev; int ret; if (!IS_ENABLED(CONFIG_PCIE_RCAR_GEN4_EP)) @@ -424,8 +425,17 @@ static int rcar_gen4_add_dw_pcie_ep(struct rcar_gen4_pcie *rcar) ep->ops = &pcie_ep_ops; ret = dw_pcie_ep_init(ep); - if (ret) + if (ret) { rcar_gen4_pcie_ep_deinit(rcar); + return ret; + } + + ret = dw_pcie_ep_init_registers(ep); + if (ret) { + dev_err(dev, "Failed to initialize DWC endpoint registers\n"); + dw_pcie_ep_deinit(ep); + rcar_gen4_pcie_ep_deinit(rcar); + } return ret; } diff --git a/drivers/pci/controller/dwc/pcie-uniphier-ep.c b/drivers/pci/controller/dwc/pcie-uniphier-ep.c index 639bc2e12476..0e5e7344de48 100644 --- a/drivers/pci/controller/dwc/pcie-uniphier-ep.c +++ b/drivers/pci/controller/dwc/pcie-uniphier-ep.c @@ -399,7 +399,18 @@ static int uniphier_pcie_ep_probe(struct platform_device *pdev) return ret; priv->pci.ep.ops = &uniphier_pcie_ep_ops; - return dw_pcie_ep_init(&priv->pci.ep); + ret = dw_pcie_ep_init(&priv->pci.ep); + if (ret) + return ret; + + ret = dw_pcie_ep_init_registers(&priv->pci.ep); + if (ret) { + dev_err(dev, "Failed to initialize DWC endpoint registers\n"); + dw_pcie_ep_deinit(&priv->pci.ep); + return ret; + } + + return 0; } static const struct uniphier_pcie_ep_soc_data uniphier_pro5_data = { From patchwork Wed Mar 27 09:13:37 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Manivannan Sadhasivam X-Patchwork-Id: 13606043 Received: from mail-pf1-f177.google.com (mail-pf1-f177.google.com [209.85.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 0BA5E482EA for ; Wed, 27 Mar 2024 09:16:04 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.210.177 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1711530967; cv=none; b=E57eg6qq6r7JhqbIVPKZFQSrb3+K0N/KXKxS9FcsIziSxSjfQ1ug56Q6s2DdqeK+k2iN2eXZto+p+HqC5iJy9OLOez2aZkK2RwZN2yPZMA5uUXxA1jW49qbaYIUS/0DmhcirDqM3uvYFtziyxS7Fk6ddsP7qaauSBAcWMRM9Dng= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1711530967; c=relaxed/simple; bh=1TPivoyLy6dKjHctlsWhQVyy7Lj27Gkdto44xO0wB3g=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=CbvHM/ED899BFGdEtthfeSjbuFabXVzfI8FOcUZjZ+BHVxFm0fkz8obfMS36vuuoZbHh0bxSYKBr1zkEweQqfRnwlc9OiOAEs+F4TyUoVydQI1x4JovYPgjRNn643UNfwWklDIsyrI/lkDY1oNKZdikNdsJYtMQG43Hm8u88ZX8= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linaro.org; spf=pass smtp.mailfrom=linaro.org; dkim=pass (2048-bit key) header.d=linaro.org header.i=@linaro.org header.b=VIfIrerl; arc=none smtp.client-ip=209.85.210.177 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linaro.org Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=linaro.org Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=linaro.org header.i=@linaro.org header.b="VIfIrerl" Received: by mail-pf1-f177.google.com with SMTP id d2e1a72fcca58-6e6f4ad4c57so4943105b3a.2 for ; Wed, 27 Mar 2024 02:16:04 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1711530964; x=1712135764; darn=vger.kernel.org; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:from:to:cc:subject:date:message-id :reply-to; bh=GNqX2SjhSgztYn0lGAQahb+nFNmGhCh0QDLrHhBZd44=; b=VIfIrerltlU04eY138Gc2fJrSIEPZgFrqGBTRJBGEYF2lH+b2SBerIYmM34Kyva+x6 cCajJ/JLOljuuCNn5IeVuYlY9qEG7YDUCJc8rukQ61RTEvT/yJ0ZGeFuetGzAfI83ZPi LFRZVay1KbcvBYJ2U3+8ZUwv/QXgTO8OscyTvtfX/N/wyehFIyyOG1linvXA/5B8uZlO Y+77/BUWl8YJLp9o67FPxnzEDhvCJ9Bucahr3rmBbgM4xmd/Q4dP1xjrS7Fm/kTnZrA1 EX9BYHvzP2/FbO/iHQRRhdzYIikBAW9xe83nwuIi+nzDP3ld3iTfXGe760Zoe9uTVdXD 5hvA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1711530964; x=1712135764; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=GNqX2SjhSgztYn0lGAQahb+nFNmGhCh0QDLrHhBZd44=; b=ca6b2+skWrMZNYVBWS1a0G+rh3ClxdrTPkrBjiXTACl0bAjRkrqFAZG8UTnFOPsOF/ 3hQdE6wqO1EXKCNlSRJY5XC6W7byS7Syk3fkMN2aKHwg3xND3xxs1YWF651qcO4h5zgT 7yxfVZZir8aqcPKMM9KOerLgDJQnOtQoFhT4Sq0ofQ2Rli3CMnsCXk3VbG3AM5SQ02Cp S5Jx0Pxhr4VFbAACf9qOyb5uLKL8pAIFEGaW1aYqe8rM9JW7h2jSUoQITMlqBuqYxA4/ DCXjbIU5KqyjepuFcNm5I5Us7DnJp2yd2uLu4myK4bfOIPkvcnSIYd14gUO7xgdTlOa6 Ro9Q== X-Forwarded-Encrypted: i=1; AJvYcCUIYvntT319daXoZ9ARAcHfeRjx+q0ubGWrwkDAtVqEm9e1XNYE8g4+zmibKXidRTitgCvaXLGeC9YYy3mfZoVKiQWCe0Li+l+hsq6ILA== X-Gm-Message-State: AOJu0YzeXR+r5TjxDaX/ss5LuixZYU9obu5hsi9E7fIUiX+IYoGXCM3v QMUDXFPR2DaWPZhTWLSyzzGQ0jcWm3tHqVRXx5EhyQyBtnm2PJhAF1s8AMZOfg== X-Google-Smtp-Source: AGHT+IHKlpHw70lFKCYQiFYdhlzQ/9Qh0LIBfnLm9+kAgkrnMGOpIA7n+sSFXHDJJ9vk7iSUHB9MTQ== X-Received: by 2002:a05:6a00:228a:b0:6e6:88c3:8b7d with SMTP id f10-20020a056a00228a00b006e688c38b7dmr866997pfe.10.1711530964136; Wed, 27 Mar 2024 02:16:04 -0700 (PDT) Received: from [127.0.1.1] ([120.60.52.77]) by smtp.gmail.com with ESMTPSA id h190-20020a6383c7000000b005dc4fc80b21sm8673871pge.70.2024.03.27.02.15.46 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 27 Mar 2024 02:16:03 -0700 (PDT) From: Manivannan Sadhasivam Date: Wed, 27 Mar 2024 14:43:37 +0530 Subject: [PATCH v12 8/8] PCI: endpoint: Remove "core_init_notifier" flag Precedence: bulk X-Mailing-List: linux-arm-msm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-Id: <20240327-pci-dbi-rework-v12-8-082625472414@linaro.org> References: <20240327-pci-dbi-rework-v12-0-082625472414@linaro.org> In-Reply-To: <20240327-pci-dbi-rework-v12-0-082625472414@linaro.org> To: Jingoo Han , Lorenzo Pieralisi , =?utf-8?q?Krzysztof_Wilczy?= =?utf-8?q?=C5=84ski?= , Rob Herring , Bjorn Helgaas , Marek Vasut , Yoshihiro Shimoda , Thierry Reding , Jonathan Hunter , Vidya Sagar , Vignesh Raghavendra , Richard Zhu , Lucas Stach , Shawn Guo , Sascha Hauer , Pengutronix Kernel Team , Fabio Estevam , NXP Linux Team , Minghuan Lian , Mingkai Hu , Roy Zang , Kunihiko Hayashi , Masami Hiramatsu , Kishon Vijay Abraham I , Jesper Nilsson , Srikanth Thokala , Shawn Lin , Heiko Stuebner , Kishon Vijay Abraham I Cc: linux-pci@vger.kernel.org, linux-kernel@vger.kernel.org, linux-renesas-soc@vger.kernel.org, linux-arm-msm@vger.kernel.org, linux-tegra@vger.kernel.org, linux-omap@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linuxppc-dev@lists.ozlabs.org, Niklas Cassel , linux-arm-kernel@axis.com, linux-rockchip@lists.infradead.org, Manivannan Sadhasivam X-Mailer: b4 0.12.4 X-Developer-Signature: v=1; a=openpgp-sha256; l=16286; i=manivannan.sadhasivam@linaro.org; h=from:subject:message-id; bh=1TPivoyLy6dKjHctlsWhQVyy7Lj27Gkdto44xO0wB3g=; b=owEBbQGS/pANAwAKAVWfEeb+kc71AcsmYgBmA+NKBjXrWIxxRWCDSkna7Dpacsbup+jfRhOYC XYZg+WnNLqJATMEAAEKAB0WIQRnpUMqgUjL2KRYJ5dVnxHm/pHO9QUCZgPjSgAKCRBVnxHm/pHO 9e0lB/9urdXsUcp5ZrvjukoGyjJvi4jR3Sl1zOSUEX3XeYsebnJXSRgoAC2SnjI4ysysmU4or/x ogvqN8Gv9afY/xDi1CntblUIyUdbu9BA4Rhv45kwfIjuC2XCwbRgEikk3Uggk9BDD9p1/Mh+B0K EATpiJ8DQ19jvKLNvxS5IsqkCVjKqj2T7LciNL8nvJKBPbRGX0CS90XagQYmfbhPWtI6qzTc1U9 1FRsX+8udlQz9QCxfocjNEyhIyovxvL2Ja7Qw6VkRSA8eWbRzIhxvYkfGunzYeyuy4RHYahJ7cv Ll4RBnsWD7h7K2RhmcCE8orSBo9woDL4ZMLk7d3jMj6qGDat X-Developer-Key: i=manivannan.sadhasivam@linaro.org; a=openpgp; fpr=C668AEC3C3188E4C611465E7488550E901166008 "core_init_notifier" flag is set by the glue drivers requiring refclk from the host to complete the DWC core initialization. Also, those drivers will send a notification to the EPF drivers once the initialization is fully completed using the pci_epc_init_notify() API. Only then, the EPF drivers will start functioning. For the rest of the drivers generating refclk locally, EPF drivers will start functioning post binding with them. EPF drivers rely on the 'core_init_notifier' flag to differentiate between the drivers. Unfortunately, this creates two different flows for the EPF drivers. So to avoid that, let's get rid of the "core_init_notifier" flag and follow a single initialization flow for the EPF drivers. This is done by calling the dw_pcie_ep_init_notify() from all glue drivers after the completion of dw_pcie_ep_init_registers() API. This will allow all the glue drivers to send the notification to the EPF drivers once the initialization is fully completed. Only difference here is that, the drivers requiring refclk from host will send the notification once refclk is received, while others will send it during probe time itself. But this also requires the EPC core driver to deliver the notification after EPF driver bind. Because, the glue driver can send the notification before the EPF drivers bind() and in those cases the EPF drivers will miss the event. To accommodate this, EPC core is now caching the state of the EPC initialization in 'init_complete' flag and pci-ep-cfs driver sends the notification to EPF drivers based on that after each EPF driver bind. Tested-by: Niklas Cassel Signed-off-by: Manivannan Sadhasivam Reviewed-by: Niklas Cassel Reviewed-by: Frank Li --- drivers/pci/controller/cadence/pcie-cadence-ep.c | 2 ++ drivers/pci/controller/dwc/pci-dra7xx.c | 2 ++ drivers/pci/controller/dwc/pci-imx6.c | 2 ++ drivers/pci/controller/dwc/pci-keystone.c | 2 ++ drivers/pci/controller/dwc/pci-layerscape-ep.c | 2 ++ drivers/pci/controller/dwc/pcie-artpec6.c | 2 ++ drivers/pci/controller/dwc/pcie-designware-ep.c | 1 + drivers/pci/controller/dwc/pcie-designware-plat.c | 2 ++ drivers/pci/controller/dwc/pcie-keembay.c | 2 ++ drivers/pci/controller/dwc/pcie-qcom-ep.c | 1 - drivers/pci/controller/dwc/pcie-rcar-gen4.c | 2 ++ drivers/pci/controller/dwc/pcie-tegra194.c | 1 - drivers/pci/controller/dwc/pcie-uniphier-ep.c | 2 ++ drivers/pci/controller/pcie-rcar-ep.c | 2 ++ drivers/pci/controller/pcie-rockchip-ep.c | 2 ++ drivers/pci/endpoint/functions/pci-epf-test.c | 18 +++++------------- drivers/pci/endpoint/pci-ep-cfs.c | 9 +++++++++ drivers/pci/endpoint/pci-epc-core.c | 22 ++++++++++++++++++++++ include/linux/pci-epc.h | 7 ++++--- 19 files changed, 65 insertions(+), 18 deletions(-) diff --git a/drivers/pci/controller/cadence/pcie-cadence-ep.c b/drivers/pci/controller/cadence/pcie-cadence-ep.c index 81c50dc64da9..55c42ca2b777 100644 --- a/drivers/pci/controller/cadence/pcie-cadence-ep.c +++ b/drivers/pci/controller/cadence/pcie-cadence-ep.c @@ -746,6 +746,8 @@ int cdns_pcie_ep_setup(struct cdns_pcie_ep *ep) spin_lock_init(&ep->lock); + pci_epc_init_notify(epc); + return 0; free_epc_mem: diff --git a/drivers/pci/controller/dwc/pci-dra7xx.c b/drivers/pci/controller/dwc/pci-dra7xx.c index 395042b29ffc..d2d17d37d3e0 100644 --- a/drivers/pci/controller/dwc/pci-dra7xx.c +++ b/drivers/pci/controller/dwc/pci-dra7xx.c @@ -474,6 +474,8 @@ static int dra7xx_add_pcie_ep(struct dra7xx_pcie *dra7xx, return ret; } + dw_pcie_ep_init_notify(ep); + return 0; } diff --git a/drivers/pci/controller/dwc/pci-imx6.c b/drivers/pci/controller/dwc/pci-imx6.c index 8d28ecc381bc..917c69edee1d 100644 --- a/drivers/pci/controller/dwc/pci-imx6.c +++ b/drivers/pci/controller/dwc/pci-imx6.c @@ -1131,6 +1131,8 @@ static int imx6_add_pcie_ep(struct imx6_pcie *imx6_pcie, return ret; } + dw_pcie_ep_init_notify(ep); + /* Start LTSSM. */ imx6_pcie_ltssm_enable(dev); diff --git a/drivers/pci/controller/dwc/pci-keystone.c b/drivers/pci/controller/dwc/pci-keystone.c index 81ebac520650..d3a7d14ee685 100644 --- a/drivers/pci/controller/dwc/pci-keystone.c +++ b/drivers/pci/controller/dwc/pci-keystone.c @@ -1293,6 +1293,8 @@ static int ks_pcie_probe(struct platform_device *pdev) goto err_ep_init; } + dw_pcie_ep_init_notify(&pci->ep); + break; default: dev_err(dev, "INVALID device type %d\n", mode); diff --git a/drivers/pci/controller/dwc/pci-layerscape-ep.c b/drivers/pci/controller/dwc/pci-layerscape-ep.c index 9eb2233e3d7f..7dde6d5fa4d8 100644 --- a/drivers/pci/controller/dwc/pci-layerscape-ep.c +++ b/drivers/pci/controller/dwc/pci-layerscape-ep.c @@ -286,6 +286,8 @@ static int __init ls_pcie_ep_probe(struct platform_device *pdev) return ret; } + dw_pcie_ep_init_notify(&pci->ep); + return ls_pcie_ep_interrupt_init(pcie, pdev); } diff --git a/drivers/pci/controller/dwc/pcie-artpec6.c b/drivers/pci/controller/dwc/pcie-artpec6.c index a6095561db4a..a4630b92489b 100644 --- a/drivers/pci/controller/dwc/pcie-artpec6.c +++ b/drivers/pci/controller/dwc/pcie-artpec6.c @@ -452,6 +452,8 @@ static int artpec6_pcie_probe(struct platform_device *pdev) return ret; } + dw_pcie_ep_init_notify(&pci->ep); + break; default: dev_err(dev, "INVALID device type %d\n", artpec6_pcie->mode); diff --git a/drivers/pci/controller/dwc/pcie-designware-ep.c b/drivers/pci/controller/dwc/pcie-designware-ep.c index 2063cf2049e5..47391d7d3a73 100644 --- a/drivers/pci/controller/dwc/pcie-designware-ep.c +++ b/drivers/pci/controller/dwc/pcie-designware-ep.c @@ -632,6 +632,7 @@ void dw_pcie_ep_cleanup(struct dw_pcie_ep *ep) struct dw_pcie *pci = to_dw_pcie_from_ep(ep); dw_pcie_edma_remove(pci); + ep->epc->init_complete = false; } EXPORT_SYMBOL_GPL(dw_pcie_ep_cleanup); diff --git a/drivers/pci/controller/dwc/pcie-designware-plat.c b/drivers/pci/controller/dwc/pcie-designware-plat.c index ca9b22e654cd..8490c5d6ff9f 100644 --- a/drivers/pci/controller/dwc/pcie-designware-plat.c +++ b/drivers/pci/controller/dwc/pcie-designware-plat.c @@ -154,6 +154,8 @@ static int dw_plat_pcie_probe(struct platform_device *pdev) dw_pcie_ep_deinit(&pci->ep); } + dw_pcie_ep_init_notify(&pci->ep); + break; default: dev_err(dev, "INVALID device type %d\n", dw_plat_pcie->mode); diff --git a/drivers/pci/controller/dwc/pcie-keembay.c b/drivers/pci/controller/dwc/pcie-keembay.c index b2556dbcffb5..98bbc83182b4 100644 --- a/drivers/pci/controller/dwc/pcie-keembay.c +++ b/drivers/pci/controller/dwc/pcie-keembay.c @@ -442,6 +442,8 @@ static int keembay_pcie_probe(struct platform_device *pdev) return ret; } + dw_pcie_ep_init_notify(&pci->ep); + break; default: dev_err(dev, "Invalid device type %d\n", pcie->mode); diff --git a/drivers/pci/controller/dwc/pcie-qcom-ep.c b/drivers/pci/controller/dwc/pcie-qcom-ep.c index 3697b4a944cc..2fb8c15e7a91 100644 --- a/drivers/pci/controller/dwc/pcie-qcom-ep.c +++ b/drivers/pci/controller/dwc/pcie-qcom-ep.c @@ -775,7 +775,6 @@ static void qcom_pcie_ep_init_debugfs(struct qcom_pcie_ep *pcie_ep) static const struct pci_epc_features qcom_pcie_epc_features = { .linkup_notifier = true, - .core_init_notifier = true, .msi_capable = true, .msix_capable = false, .align = SZ_4K, diff --git a/drivers/pci/controller/dwc/pcie-rcar-gen4.c b/drivers/pci/controller/dwc/pcie-rcar-gen4.c index e155a905fb4f..cfeccc2f9ee1 100644 --- a/drivers/pci/controller/dwc/pcie-rcar-gen4.c +++ b/drivers/pci/controller/dwc/pcie-rcar-gen4.c @@ -437,6 +437,8 @@ static int rcar_gen4_add_dw_pcie_ep(struct rcar_gen4_pcie *rcar) rcar_gen4_pcie_ep_deinit(rcar); } + dw_pcie_ep_init_notify(ep); + return ret; } diff --git a/drivers/pci/controller/dwc/pcie-tegra194.c b/drivers/pci/controller/dwc/pcie-tegra194.c index db043f579fbe..ddc23602eca7 100644 --- a/drivers/pci/controller/dwc/pcie-tegra194.c +++ b/drivers/pci/controller/dwc/pcie-tegra194.c @@ -2006,7 +2006,6 @@ static int tegra_pcie_ep_raise_irq(struct dw_pcie_ep *ep, u8 func_no, static const struct pci_epc_features tegra_pcie_epc_features = { .linkup_notifier = true, - .core_init_notifier = true, .msi_capable = false, .msix_capable = false, .bar[BAR_0] = { .type = BAR_FIXED, .fixed_size = SZ_1M, diff --git a/drivers/pci/controller/dwc/pcie-uniphier-ep.c b/drivers/pci/controller/dwc/pcie-uniphier-ep.c index 0e5e7344de48..a2b844268e28 100644 --- a/drivers/pci/controller/dwc/pcie-uniphier-ep.c +++ b/drivers/pci/controller/dwc/pcie-uniphier-ep.c @@ -410,6 +410,8 @@ static int uniphier_pcie_ep_probe(struct platform_device *pdev) return ret; } + dw_pcie_ep_init_notify(&priv->pci.ep); + return 0; } diff --git a/drivers/pci/controller/pcie-rcar-ep.c b/drivers/pci/controller/pcie-rcar-ep.c index 05967c6c0b42..047e2cef5afc 100644 --- a/drivers/pci/controller/pcie-rcar-ep.c +++ b/drivers/pci/controller/pcie-rcar-ep.c @@ -542,6 +542,8 @@ static int rcar_pcie_ep_probe(struct platform_device *pdev) goto err_pm_put; } + pci_epc_init_notify(epc); + return 0; err_pm_put: diff --git a/drivers/pci/controller/pcie-rockchip-ep.c b/drivers/pci/controller/pcie-rockchip-ep.c index c9046e97a1d2..8613df8184df 100644 --- a/drivers/pci/controller/pcie-rockchip-ep.c +++ b/drivers/pci/controller/pcie-rockchip-ep.c @@ -609,6 +609,8 @@ static int rockchip_pcie_ep_probe(struct platform_device *pdev) rockchip_pcie_write(rockchip, PCIE_CLIENT_CONF_ENABLE, PCIE_CLIENT_CONFIG); + pci_epc_init_notify(epc); + return 0; err_epc_mem_exit: pci_epc_mem_exit(epc); diff --git a/drivers/pci/endpoint/functions/pci-epf-test.c b/drivers/pci/endpoint/functions/pci-epf-test.c index cd4ffb39dcdc..212fc303fb63 100644 --- a/drivers/pci/endpoint/functions/pci-epf-test.c +++ b/drivers/pci/endpoint/functions/pci-epf-test.c @@ -753,6 +753,7 @@ static int pci_epf_test_core_init(struct pci_epf *epf) const struct pci_epc_features *epc_features; struct pci_epc *epc = epf->epc; struct device *dev = &epf->dev; + bool linkup_notifier = false; bool msix_capable = false; bool msi_capable = true; int ret; @@ -795,6 +796,10 @@ static int pci_epf_test_core_init(struct pci_epf *epf) } } + linkup_notifier = epc_features->linkup_notifier; + if (!linkup_notifier) + queue_work(kpcitest_workqueue, &epf_test->cmd_handler.work); + return 0; } @@ -890,8 +895,6 @@ static int pci_epf_test_bind(struct pci_epf *epf) const struct pci_epc_features *epc_features; enum pci_barno test_reg_bar = BAR_0; struct pci_epc *epc = epf->epc; - bool linkup_notifier = false; - bool core_init_notifier = false; if (WARN_ON_ONCE(!epc)) return -EINVAL; @@ -902,8 +905,6 @@ static int pci_epf_test_bind(struct pci_epf *epf) return -EOPNOTSUPP; } - linkup_notifier = epc_features->linkup_notifier; - core_init_notifier = epc_features->core_init_notifier; test_reg_bar = pci_epc_get_first_free_bar(epc_features); if (test_reg_bar < 0) return -EINVAL; @@ -916,21 +917,12 @@ static int pci_epf_test_bind(struct pci_epf *epf) if (ret) return ret; - if (!core_init_notifier) { - ret = pci_epf_test_core_init(epf); - if (ret) - return ret; - } - epf_test->dma_supported = true; ret = pci_epf_test_init_dma_chan(epf_test); if (ret) epf_test->dma_supported = false; - if (!linkup_notifier && !core_init_notifier) - queue_work(kpcitest_workqueue, &epf_test->cmd_handler.work); - return 0; } diff --git a/drivers/pci/endpoint/pci-ep-cfs.c b/drivers/pci/endpoint/pci-ep-cfs.c index 0ea64e24ed61..3b21e28f9b59 100644 --- a/drivers/pci/endpoint/pci-ep-cfs.c +++ b/drivers/pci/endpoint/pci-ep-cfs.c @@ -64,6 +64,9 @@ static int pci_secondary_epc_epf_link(struct config_item *epf_item, return ret; } + /* Send any pending EPC initialization complete to the EPF driver */ + pci_epc_notify_pending_init(epc, epf); + return 0; } @@ -125,6 +128,9 @@ static int pci_primary_epc_epf_link(struct config_item *epf_item, return ret; } + /* Send any pending EPC initialization complete to the EPF driver */ + pci_epc_notify_pending_init(epc, epf); + return 0; } @@ -230,6 +236,9 @@ static int pci_epc_epf_link(struct config_item *epc_item, return ret; } + /* Send any pending EPC initialization complete to the EPF driver */ + pci_epc_notify_pending_init(epc, epf); + return 0; } diff --git a/drivers/pci/endpoint/pci-epc-core.c b/drivers/pci/endpoint/pci-epc-core.c index da3fc0795b0b..47d27ec7439d 100644 --- a/drivers/pci/endpoint/pci-epc-core.c +++ b/drivers/pci/endpoint/pci-epc-core.c @@ -748,10 +748,32 @@ void pci_epc_init_notify(struct pci_epc *epc) epf->event_ops->core_init(epf); mutex_unlock(&epf->lock); } + epc->init_complete = true; mutex_unlock(&epc->list_lock); } EXPORT_SYMBOL_GPL(pci_epc_init_notify); +/** + * pci_epc_notify_pending_init() - Notify the pending EPC device initialization + * complete to the EPF device + * @epc: the EPC device whose core initialization is pending to be notified + * @epf: the EPF device to be notified + * + * Invoke to notify the pending EPC device initialization complete to the EPF + * device. This is used to deliver the notification if the EPC initialization + * got completed before the EPF driver bind. + */ +void pci_epc_notify_pending_init(struct pci_epc *epc, struct pci_epf *epf) +{ + if (epc->init_complete) { + mutex_lock(&epf->lock); + if (epf->event_ops && epf->event_ops->core_init) + epf->event_ops->core_init(epf); + mutex_unlock(&epf->lock); + } +} +EXPORT_SYMBOL_GPL(pci_epc_notify_pending_init); + /** * pci_epc_bme_notify() - Notify the EPF device that the EPC device has received * the BME event from the Root complex diff --git a/include/linux/pci-epc.h b/include/linux/pci-epc.h index cc2f70d061c8..acc5f96161fe 100644 --- a/include/linux/pci-epc.h +++ b/include/linux/pci-epc.h @@ -128,6 +128,8 @@ struct pci_epc_mem { * @group: configfs group representing the PCI EPC device * @lock: mutex to protect pci_epc ops * @function_num_map: bitmap to manage physical function number + * @init_complete: flag to indicate whether the EPC initialization is complete + * or not */ struct pci_epc { struct device dev; @@ -143,6 +145,7 @@ struct pci_epc { /* mutex to protect against concurrent access of EP controller */ struct mutex lock; unsigned long function_num_map; + bool init_complete; }; /** @@ -179,8 +182,6 @@ struct pci_epc_bar_desc { /** * struct pci_epc_features - features supported by a EPC device per function * @linkup_notifier: indicate if the EPC device can notify EPF driver on link up - * @core_init_notifier: indicate cores that can notify about their availability - * for initialization * @msi_capable: indicate if the endpoint function has MSI capability * @msix_capable: indicate if the endpoint function has MSI-X capability * @bar: array specifying the hardware description for each BAR @@ -188,7 +189,6 @@ struct pci_epc_bar_desc { */ struct pci_epc_features { unsigned int linkup_notifier : 1; - unsigned int core_init_notifier : 1; unsigned int msi_capable : 1; unsigned int msix_capable : 1; struct pci_epc_bar_desc bar[PCI_STD_NUM_BARS]; @@ -225,6 +225,7 @@ int pci_epc_add_epf(struct pci_epc *epc, struct pci_epf *epf, void pci_epc_linkup(struct pci_epc *epc); void pci_epc_linkdown(struct pci_epc *epc); void pci_epc_init_notify(struct pci_epc *epc); +void pci_epc_notify_pending_init(struct pci_epc *epc, struct pci_epf *epf); void pci_epc_bme_notify(struct pci_epc *epc); void pci_epc_remove_epf(struct pci_epc *epc, struct pci_epf *epf, enum pci_epc_interface_type type);