From patchwork Wed Mar 27 08:17:21 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Claudiu Beznea X-Patchwork-Id: 13606155 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from aws-us-west-2-korg-lkml-1.web.codeaurora.org (localhost.localdomain [127.0.0.1]) by smtp.lore.kernel.org (Postfix) with ESMTP id AB0AAC54E67 for ; Wed, 27 Mar 2024 10:37:05 +0000 (UTC) Received: from mail-lj1-f179.google.com (mail-lj1-f179.google.com [209.85.208.179]) by mx.groups.io with SMTP id smtpd.web11.32281.1711527481980478452 for ; Wed, 27 Mar 2024 01:18:02 -0700 Authentication-Results: mx.groups.io; dkim=pass header.i=@tuxon.dev header.s=google header.b=YORZoz48; spf=pass (domain: tuxon.dev, ip: 209.85.208.179, mailfrom: claudiu.beznea@tuxon.dev) Received: by mail-lj1-f179.google.com with SMTP id 38308e7fff4ca-2d476d7972aso102389061fa.1 for ; Wed, 27 Mar 2024 01:18:01 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=tuxon.dev; s=google; t=1711527480; x=1712132280; darn=lists.cip-project.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=7K4zcjyXwjI2HVaogVEUmaT9a9pbF8vHfkiuYWtltuI=; b=YORZoz48boeMO6pWSXQnjx4HmubchkES2pSb4lEuh4YcfoMNFuGsVZiHQicZX2NQNl NTUxiz7lZRf2gCMqM/AU9oZxqCrNj+xW0mDf0Ffi53VsixyYPv47o9p0NyuKuNdQbg/g JWJpmE6Rn8VR4wEdYvs+wX1gSAHw1bHNnkYPevvLvSkulJeSgCv/XDJT8kn2pz0eYn2c c33nhToIt4bNqYdBi/Plu8SipP6QrZNXHcR2FgwCdckSalCShdgiXClhdsrC+4ZXDki9 tffGiSpD6F/s47OqFu6ECWKo/lONVU2DAAatud/YgoArYjHbKiWjc7toqAPtIMckptnD kWEg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1711527480; x=1712132280; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=7K4zcjyXwjI2HVaogVEUmaT9a9pbF8vHfkiuYWtltuI=; b=uw1tPj8Ky8S7Np7gdqlYjtgDOKubip6S0ZQUyR37h3KUpYTJFKQJDMb8/4bUrcHuRs eJb/Z5XgJWbyUcdGcS7pBxJhpUiO2IB7JuYU9f6SiIHte+0Z4Rjjwf+NukfMfSLHvdkr alS9cf4be2HjZKvn4F7npH8uKt91rci04+lGKY2YaKEiIw6q+sQz/4EcDMkSDP1fi6Lt 5DjTy77/Rkxe36gd2b4vDfbvgtdKf41Ujwuc75j/yuUyXN3f28xCPtJxKcCUDIYxOXqZ bGHg82QxWNTHm6H3DDIPu7Ab0CvMBX151GKVKMTPfW8ZZYYiQnfjAXxgk14/PqOHPmTz 65QQ== X-Gm-Message-State: AOJu0YxP/JkWfwW1NG81oSU03tBxgR7tVERNccu4BKpRrntEAgX7H0UL VN7rEtxqULoRovKmJHuISlUuXuqWZ+U+ScJ/Z5mj/EKt6h4bVJf50Uz1XnCII2M= X-Google-Smtp-Source: AGHT+IFD3kb1q31LLbnr+aXT3tpDq6LnoLPYbq37vKXEeM+D29MyN6EVCFmuouCBQUmFQ/jIVYdjDg== X-Received: by 2002:a05:651c:1a2c:b0:2d6:e295:e81f with SMTP id by44-20020a05651c1a2c00b002d6e295e81fmr533310ljb.35.1711527480014; Wed, 27 Mar 2024 01:18:00 -0700 (PDT) Received: from claudiu-X670E-Pro-RS.. ([82.78.167.144]) by smtp.gmail.com with ESMTPSA id c9-20020a7bc2a9000000b0041493615585sm1353783wmk.39.2024.03.27.01.17.58 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 27 Mar 2024 01:17:59 -0700 (PDT) From: Claudiu X-Google-Original-From: Claudiu To: nobuhiro1.iwamatsu@toshiba.co.jp, pavel@denx.de Cc: cip-dev@lists.cip-project.org, biju.das.jz@bp.renesas.com, prabhakar.mahadev-lad.rj@bp.renesas.com, claudiu.beznea@tuxon.dev Subject: [PATCH 5.10.y-cip 01/36] dt-bindings: pinctrl: renesas,rzg2l-pinctrl: Document the properties to handle GPIO IRQ Date: Wed, 27 Mar 2024 10:17:21 +0200 Message-Id: <20240327081756.2228036-2-claudiu.beznea.uj@bp.renesas.com> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20240327081756.2228036-1-claudiu.beznea.uj@bp.renesas.com> References: <20240327081756.2228036-1-claudiu.beznea.uj@bp.renesas.com> MIME-Version: 1.0 List-Id: X-Webhook-Received: from li982-79.members.linode.com [45.33.32.79] by aws-us-west-2-korg-lkml-1.web.codeaurora.org with HTTPS for ; Wed, 27 Mar 2024 10:37:05 -0000 X-Groupsio-URL: https://lists.cip-project.org/g/cip-dev/message/15418 From: Lad Prabhakar commit 35c37efd12733d8ddbdc11ab9c8dbcee472a487f upstream. Document the required properties to handle GPIO IRQ. Signed-off-by: Lad Prabhakar Reviewed-by: Geert Uytterhoeven Reviewed-by: Rob Herring Signed-off-by: Marc Zyngier Link: https://lore.kernel.org/r/20220707182314.66610-6-prabhakar.mahadev-lad.rj@bp.renesas.com Signed-off-by: Claudiu Beznea --- .../bindings/pinctrl/renesas,rzg2l-pinctrl.yaml | 15 +++++++++++++++ 1 file changed, 15 insertions(+) diff --git a/Documentation/devicetree/bindings/pinctrl/renesas,rzg2l-pinctrl.yaml b/Documentation/devicetree/bindings/pinctrl/renesas,rzg2l-pinctrl.yaml index 6bc9c5ebbdb1..b1cbb8a4b0c0 100644 --- a/Documentation/devicetree/bindings/pinctrl/renesas,rzg2l-pinctrl.yaml +++ b/Documentation/devicetree/bindings/pinctrl/renesas,rzg2l-pinctrl.yaml @@ -47,6 +47,17 @@ properties: gpio-ranges: maxItems: 1 + interrupt-controller: true + + '#interrupt-cells': + const: 2 + description: + The first cell contains the global GPIO port index, constructed using the + RZG2L_GPIO() helper macro in and the + second cell is used to specify the flag. + E.g. "interrupts = ;" if P43_0 is + being used as an interrupt. + clocks: maxItems: 1 @@ -107,6 +118,8 @@ required: - gpio-controller - '#gpio-cells' - gpio-ranges + - interrupt-controller + - '#interrupt-cells' - clocks - power-domains - resets @@ -123,6 +136,8 @@ examples: gpio-controller; #gpio-cells = <2>; gpio-ranges = <&pinctrl 0 0 392>; + interrupt-controller; + #interrupt-cells = <2>; clocks = <&cpg CPG_MOD R9A07G044_GPIO_HCLK>; resets = <&cpg R9A07G044_GPIO_RSTN>, <&cpg R9A07G044_GPIO_PORT_RESETN>, From patchwork Wed Mar 27 08:17:22 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Claudiu Beznea X-Patchwork-Id: 13606157 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from aws-us-west-2-korg-lkml-1.web.codeaurora.org (localhost.localdomain [127.0.0.1]) by smtp.lore.kernel.org (Postfix) with ESMTP id B86CCCD1288 for ; Wed, 27 Mar 2024 10:37:05 +0000 (UTC) Received: from mail-wr1-f48.google.com (mail-wr1-f48.google.com [209.85.221.48]) by mx.groups.io with SMTP id smtpd.web11.32283.1711527482954111995 for ; Wed, 27 Mar 2024 01:18:03 -0700 Authentication-Results: mx.groups.io; dkim=pass header.i=@tuxon.dev header.s=google header.b=BK6z+HuB; spf=pass (domain: tuxon.dev, ip: 209.85.221.48, mailfrom: claudiu.beznea@tuxon.dev) Received: by mail-wr1-f48.google.com with SMTP id ffacd0b85a97d-33ed6078884so305059f8f.1 for ; Wed, 27 Mar 2024 01:18:02 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=tuxon.dev; s=google; t=1711527481; x=1712132281; darn=lists.cip-project.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=qQolqFCcDjdTWOh8MFa/SBd2767l/kjGKx7ZoC9R+AM=; b=BK6z+HuBn9t8h7c5pJgj8dFEZdzzWIrJEgM9I6OQP+EGrD7P0rq0O5Budy0zkM6CrM sH4rxgaiQCjVocoXhw+gGvpmLzwayJH87qvm4XgdfWcWY4v2HKX1hJOGtw4B6kmt+hj5 517YOVvHjNyEwBRJLRRl7BqIpg9lWJDVhzg4x/FvznvmksMXyepHkoCm2DjEnGG/mxMF lnJHr+X9xuX/a1oYORF2S2MOg5L9hfBix9HMMgo417xj/8LbR8UZNyTp74o3dSR6fXWy ax1AW0npDE7r7udF0ngB1DSKTIxngTeR8F4OG1QSuSDEUQRe9Cd6PTjWgpDp+jsVy42s bAAw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1711527481; x=1712132281; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=qQolqFCcDjdTWOh8MFa/SBd2767l/kjGKx7ZoC9R+AM=; b=kwsxtwn6fXFHLW2XtH8kVdrGZz/q27zte6fM0mQYlNe0I1qiU6fPZYUqhsEsMAT3xA 8l4pdGTtJIostQH2JpKH6XuaRjAtQTv3jATqCBUdzyL2husPDBrsDR2/nSNRVmOLYQ9Q u+JSo9nI6G1pi7jUueIeTLdlkUbRcei9o/29PpySI/eNMt2Q9RnxfqAdJCTKOex+AbGu XrTv95JdeVExNzIXRgFBQZiwq91n5Ym/kfrWquf/kIjWIMc+McXDxAl8R8IwUYM81vAX xRv41T4W6sj7HnO06FQU6ad0ooWEpwcOzBesO9xgiktn5dfJ+52wU0Dr4FaFMFG46xri yBzg== X-Gm-Message-State: AOJu0YxY5xkm33DZ7lFeJAM3bptfq8wdr0IQhdOh+iqCl3mN7Baz+svV qkPGHbEV7rJ99kzWpkm7WvxmpQ67q4d6etNImhAJKjQfXTJVZQRjH+yTXWovAqk= X-Google-Smtp-Source: AGHT+IHg4J3UDQty2kFqgcgxuPZ+a/9VAiJxBpwjxxLnaBE2XRWeEGqgJcnzm3nbpFJX0zn80XuUWw== X-Received: by 2002:a05:6000:110b:b0:33e:9f16:33c with SMTP id z11-20020a056000110b00b0033e9f16033cmr3249542wrw.18.1711527481286; Wed, 27 Mar 2024 01:18:01 -0700 (PDT) Received: from claudiu-X670E-Pro-RS.. ([82.78.167.144]) by smtp.gmail.com with ESMTPSA id c9-20020a7bc2a9000000b0041493615585sm1353783wmk.39.2024.03.27.01.18.00 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 27 Mar 2024 01:18:00 -0700 (PDT) From: Claudiu X-Google-Original-From: Claudiu To: nobuhiro1.iwamatsu@toshiba.co.jp, pavel@denx.de Cc: cip-dev@lists.cip-project.org, biju.das.jz@bp.renesas.com, prabhakar.mahadev-lad.rj@bp.renesas.com, claudiu.beznea@tuxon.dev Subject: [PATCH 5.10.y-cip 02/36] pinctrl: renesas: rzg2l: Select GPIOLIB_IRQCHIP and IRQ_DOMAIN_HIERARCHY Date: Wed, 27 Mar 2024 10:17:22 +0200 Message-Id: <20240327081756.2228036-3-claudiu.beznea.uj@bp.renesas.com> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20240327081756.2228036-1-claudiu.beznea.uj@bp.renesas.com> References: <20240327081756.2228036-1-claudiu.beznea.uj@bp.renesas.com> MIME-Version: 1.0 List-Id: X-Webhook-Received: from li982-79.members.linode.com [45.33.32.79] by aws-us-west-2-korg-lkml-1.web.codeaurora.org with HTTPS for ; Wed, 27 Mar 2024 10:37:05 -0000 X-Groupsio-URL: https://lists.cip-project.org/g/cip-dev/message/15419 From: Claudiu Beznea commit fda5edd7d66f091770b600f789dd4190ce6a7907 upstream. The pinctrl-rzg2l driver accesses gpio_chip.irq, which is available only if CONFIG_GPIOLIB_IRQCHIP=y, and uses APIs that are defined only if CONFIG_IRQ_DOMAIN_HIERARCHY=y (irq_chip_*_parent() APIs). On ARCH_RZG2L, CONFIG_IRQ_DOMAIN_HIERARCHY is selected anyway, e.g. by CONFIG_ARM_GIC_V3, but CONFIG_GPIOLIB_IRQCHIP is not (it is on R-Car). Make this explicit at the driver level for a clearer view of the dependencies. Signed-off-by: Claudiu Beznea Reviewed-by: Geert Uytterhoeven Link: https://lore.kernel.org/r/20240215124112.2259103-2-claudiu.beznea.uj@bp.renesas.com [geert: select GPIOLIB_IRQCHIP, too] Signed-off-by: Geert Uytterhoeven Signed-off-by: Claudiu Beznea --- drivers/pinctrl/renesas/Kconfig | 2 ++ 1 file changed, 2 insertions(+) diff --git a/drivers/pinctrl/renesas/Kconfig b/drivers/pinctrl/renesas/Kconfig index 97dff258e257..f47cef140cb9 100644 --- a/drivers/pinctrl/renesas/Kconfig +++ b/drivers/pinctrl/renesas/Kconfig @@ -177,9 +177,11 @@ config PINCTRL_RZG2L bool "pin control support for RZ/{G2L,G2UL,V2L}" if COMPILE_TEST depends on OF select GPIOLIB + select GPIOLIB_IRQCHIP select GENERIC_PINCTRL_GROUPS select GENERIC_PINMUX_FUNCTIONS select GENERIC_PINCONF + select IRQ_DOMAIN_HIERARCHY help This selects GPIO and pinctrl driver for Renesas RZ/{G2L,G2UL,V2L} platforms. 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([82.78.167.144]) by smtp.gmail.com with ESMTPSA id c9-20020a7bc2a9000000b0041493615585sm1353783wmk.39.2024.03.27.01.18.01 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 27 Mar 2024 01:18:01 -0700 (PDT) From: Claudiu X-Google-Original-From: Claudiu To: nobuhiro1.iwamatsu@toshiba.co.jp, pavel@denx.de Cc: cip-dev@lists.cip-project.org, biju.das.jz@bp.renesas.com, prabhakar.mahadev-lad.rj@bp.renesas.com, claudiu.beznea@tuxon.dev Subject: [PATCH 5.10.y-cip 03/36] pinctrl: renesas: pinctrl-rzg2l: Add IRQ domain to handle GPIO interrupt Date: Wed, 27 Mar 2024 10:17:23 +0200 Message-Id: <20240327081756.2228036-4-claudiu.beznea.uj@bp.renesas.com> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20240327081756.2228036-1-claudiu.beznea.uj@bp.renesas.com> References: <20240327081756.2228036-1-claudiu.beznea.uj@bp.renesas.com> MIME-Version: 1.0 List-Id: X-Webhook-Received: from li982-79.members.linode.com [45.33.32.79] by aws-us-west-2-korg-lkml-1.web.codeaurora.org with HTTPS for ; Wed, 27 Mar 2024 10:37:06 -0000 X-Groupsio-URL: https://lists.cip-project.org/g/cip-dev/message/15420 From: Lad Prabhakar commit db2e5f21a48edf1d1110d348add54bf22050643b upstream. Add IRQ domain to RZ/G2L pinctrl driver to handle GPIO interrupt. GPIO0-GPIO122 pins can be used as IRQ lines but only 32 pins can be used as IRQ lines at a given time. Selection of pins as IRQ lines is handled by IA55 (which is the IRQC block) which sits in between the GPIO and GIC. Signed-off-by: Lad Prabhakar Reviewed-by: Linus Walleij Signed-off-by: Marc Zyngier Link: https://lore.kernel.org/r/20220707182314.66610-7-prabhakar.mahadev-lad.rj@bp.renesas.com [claudiu.beznea: - fixed conflict in bitmap_lock initialization - removed IRQCHIP_IMMUTABLE from rzg2l_gpio_irqchip.flags as it is not defined in v5.10 - removed GPIOCHIP_IRQ_RESOURCE_HELPERS from rzg2l_gpio_irqchip as it is not defined in v5.10 - adapted rzg2l_gpio_populate_parent_fwspec() to have only 3 arguments, allocate an object of type struct irq_fwspec and return it; also the return type of rzg2l_gpio_populate_parent_fwspec() has been changed to void * to cope with current framework capabilities - do not use gpio_irq_chip_set_chip() to assign the girq->chip in rzg2l_gpio_register() but use direct assignment as gpio_irq_chip_set_chip() is not available in v5.10] Signed-off-by: Claudiu Beznea --- drivers/pinctrl/renesas/pinctrl-rzg2l.c | 234 ++++++++++++++++++++++++ 1 file changed, 234 insertions(+) diff --git a/drivers/pinctrl/renesas/pinctrl-rzg2l.c b/drivers/pinctrl/renesas/pinctrl-rzg2l.c index bad9f3f8cd70..8e33d3a34c06 100644 --- a/drivers/pinctrl/renesas/pinctrl-rzg2l.c +++ b/drivers/pinctrl/renesas/pinctrl-rzg2l.c @@ -9,9 +9,11 @@ #include #include #include +#include #include #include #include +#include #include #include #include @@ -90,6 +92,7 @@ #define PIN(n) (0x0800 + 0x10 + (n)) #define IOLH(n) (0x1000 + (n) * 8) #define IEN(n) (0x1800 + (n) * 8) +#define ISEL(n) (0x2c80 + (n) * 8) #define PWPR (0x3014) #define SD_CH(n) (0x3000 + (n) * 4) #define QSPI (0x3008) @@ -113,6 +116,10 @@ #define RZG2L_PIN_ID_TO_PORT_OFFSET(id) (RZG2L_PIN_ID_TO_PORT(id) + 0x10) #define RZG2L_PIN_ID_TO_PIN(id) ((id) % RZG2L_PINS_PER_PORT) +#define RZG2L_TINT_MAX_INTERRUPT 32 +#define RZG2L_TINT_IRQ_START_INDEX 9 +#define RZG2L_PACK_HWIRQ(t, i) (((t) << 16) | (i)) + struct rzg2l_dedicated_configs { const char *name; u32 config; @@ -138,6 +145,9 @@ struct rzg2l_pinctrl { struct gpio_chip gpio_chip; struct pinctrl_gpio_range gpio_range; + DECLARE_BITMAP(tint_slot, RZG2L_TINT_MAX_INTERRUPT); + spinlock_t bitmap_lock; + unsigned int hwirq[RZG2L_TINT_MAX_INTERRUPT]; spinlock_t lock; /* lock read/write registers */ struct mutex mutex; /* serialize adding groups and functions */ @@ -904,8 +914,14 @@ static int rzg2l_gpio_get(struct gpio_chip *chip, unsigned int offset) static void rzg2l_gpio_free(struct gpio_chip *chip, unsigned int offset) { + unsigned int virq; + pinctrl_gpio_free(chip->base + offset); + virq = irq_find_mapping(chip->irq.domain, offset); + if (virq) + irq_dispose_mapping(virq); + /* * Set the GPIO as an input to ensure that the next GPIO request won't * drive the GPIO pin as an output. @@ -1125,14 +1141,222 @@ static struct { } }; +static int rzg2l_gpio_get_gpioint(unsigned int virq) +{ + unsigned int gpioint; + unsigned int i; + u32 port, bit; + + port = virq / 8; + bit = virq % 8; + + if (port >= ARRAY_SIZE(rzg2l_gpio_configs) || + bit >= RZG2L_GPIO_PORT_GET_PINCNT(rzg2l_gpio_configs[port])) + return -EINVAL; + + gpioint = bit; + for (i = 0; i < port; i++) + gpioint += RZG2L_GPIO_PORT_GET_PINCNT(rzg2l_gpio_configs[i]); + + return gpioint; +} + +static void rzg2l_gpio_irq_disable(struct irq_data *d) +{ + struct gpio_chip *gc = irq_data_get_irq_chip_data(d); + struct rzg2l_pinctrl *pctrl = container_of(gc, struct rzg2l_pinctrl, gpio_chip); + unsigned int hwirq = irqd_to_hwirq(d); + unsigned long flags; + void __iomem *addr; + u32 port; + u8 bit; + + port = RZG2L_PIN_ID_TO_PORT(hwirq); + bit = RZG2L_PIN_ID_TO_PIN(hwirq); + + addr = pctrl->base + ISEL(port); + if (bit >= 4) { + bit -= 4; + addr += 4; + } + + spin_lock_irqsave(&pctrl->lock, flags); + writel(readl(addr) & ~BIT(bit * 8), addr); + spin_unlock_irqrestore(&pctrl->lock, flags); + + gpiochip_disable_irq(gc, hwirq); + irq_chip_disable_parent(d); +} + +static void rzg2l_gpio_irq_enable(struct irq_data *d) +{ + struct gpio_chip *gc = irq_data_get_irq_chip_data(d); + struct rzg2l_pinctrl *pctrl = container_of(gc, struct rzg2l_pinctrl, gpio_chip); + unsigned int hwirq = irqd_to_hwirq(d); + unsigned long flags; + void __iomem *addr; + u32 port; + u8 bit; + + gpiochip_enable_irq(gc, hwirq); + + port = RZG2L_PIN_ID_TO_PORT(hwirq); + bit = RZG2L_PIN_ID_TO_PIN(hwirq); + + addr = pctrl->base + ISEL(port); + if (bit >= 4) { + bit -= 4; + addr += 4; + } + + spin_lock_irqsave(&pctrl->lock, flags); + writel(readl(addr) | BIT(bit * 8), addr); + spin_unlock_irqrestore(&pctrl->lock, flags); + + irq_chip_enable_parent(d); +} + +static int rzg2l_gpio_irq_set_type(struct irq_data *d, unsigned int type) +{ + return irq_chip_set_type_parent(d, type); +} + +static void rzg2l_gpio_irqc_eoi(struct irq_data *d) +{ + irq_chip_eoi_parent(d); +} + +static void rzg2l_gpio_irq_print_chip(struct irq_data *data, struct seq_file *p) +{ + struct gpio_chip *gc = irq_data_get_irq_chip_data(data); + + seq_printf(p, dev_name(gc->parent)); +} + +static const struct irq_chip rzg2l_gpio_irqchip = { + .name = "rzg2l-gpio", + .irq_disable = rzg2l_gpio_irq_disable, + .irq_enable = rzg2l_gpio_irq_enable, + .irq_mask = irq_chip_mask_parent, + .irq_unmask = irq_chip_unmask_parent, + .irq_set_type = rzg2l_gpio_irq_set_type, + .irq_eoi = rzg2l_gpio_irqc_eoi, + .irq_print_chip = rzg2l_gpio_irq_print_chip, +}; + +static int rzg2l_gpio_child_to_parent_hwirq(struct gpio_chip *gc, + unsigned int child, + unsigned int child_type, + unsigned int *parent, + unsigned int *parent_type) +{ + struct rzg2l_pinctrl *pctrl = gpiochip_get_data(gc); + unsigned long flags; + int gpioint, irq; + + gpioint = rzg2l_gpio_get_gpioint(child); + if (gpioint < 0) + return gpioint; + + spin_lock_irqsave(&pctrl->bitmap_lock, flags); + irq = bitmap_find_free_region(pctrl->tint_slot, RZG2L_TINT_MAX_INTERRUPT, get_order(1)); + spin_unlock_irqrestore(&pctrl->bitmap_lock, flags); + if (irq < 0) + return -ENOSPC; + pctrl->hwirq[irq] = child; + irq += RZG2L_TINT_IRQ_START_INDEX; + + /* All these interrupts are level high in the CPU */ + *parent_type = IRQ_TYPE_LEVEL_HIGH; + *parent = RZG2L_PACK_HWIRQ(gpioint, irq); + return 0; +} + +static void *rzg2l_gpio_populate_parent_fwspec(struct gpio_chip *chip, + unsigned int parent_hwirq, + unsigned int parent_type) +{ + struct irq_fwspec *fwspec; + + fwspec = kmalloc(sizeof(*fwspec), GFP_KERNEL); + if (!fwspec) + return NULL; + + fwspec->fwnode = chip->irq.parent_domain->fwnode; + fwspec->param_count = 2; + fwspec->param[0] = parent_hwirq; + fwspec->param[1] = parent_type; + + return fwspec; +} + +static void rzg2l_gpio_irq_domain_free(struct irq_domain *domain, unsigned int virq, + unsigned int nr_irqs) +{ + struct irq_data *d; + + d = irq_domain_get_irq_data(domain, virq); + if (d) { + struct gpio_chip *gc = irq_data_get_irq_chip_data(d); + struct rzg2l_pinctrl *pctrl = container_of(gc, struct rzg2l_pinctrl, gpio_chip); + irq_hw_number_t hwirq = irqd_to_hwirq(d); + unsigned long flags; + unsigned int i; + + for (i = 0; i < RZG2L_TINT_MAX_INTERRUPT; i++) { + if (pctrl->hwirq[i] == hwirq) { + spin_lock_irqsave(&pctrl->bitmap_lock, flags); + bitmap_release_region(pctrl->tint_slot, i, get_order(1)); + spin_unlock_irqrestore(&pctrl->bitmap_lock, flags); + pctrl->hwirq[i] = 0; + break; + } + } + } + irq_domain_free_irqs_common(domain, virq, nr_irqs); +} + +static void rzg2l_init_irq_valid_mask(struct gpio_chip *gc, + unsigned long *valid_mask, + unsigned int ngpios) +{ + struct rzg2l_pinctrl *pctrl = gpiochip_get_data(gc); + struct gpio_chip *chip = &pctrl->gpio_chip; + unsigned int offset; + + /* Forbid unused lines to be mapped as IRQs */ + for (offset = 0; offset < chip->ngpio; offset++) { + u32 port, bit; + + port = offset / 8; + bit = offset % 8; + + if (port >= ARRAY_SIZE(rzg2l_gpio_configs) || + bit >= RZG2L_GPIO_PORT_GET_PINCNT(rzg2l_gpio_configs[port])) + clear_bit(offset, valid_mask); + } +} + static int rzg2l_gpio_register(struct rzg2l_pinctrl *pctrl) { struct device_node *np = pctrl->dev->of_node; struct gpio_chip *chip = &pctrl->gpio_chip; const char *name = dev_name(pctrl->dev); + struct irq_domain *parent_domain; struct of_phandle_args of_args; + struct device_node *parent_np; + struct gpio_irq_chip *girq; int ret; + parent_np = of_irq_find_parent(np); + if (!parent_np) + return -ENXIO; + + parent_domain = irq_find_host(parent_np); + of_node_put(parent_np); + if (!parent_domain) + return -EPROBE_DEFER; + ret = of_parse_phandle_with_fixed_args(np, "gpio-ranges", 3, 0, &of_args); if (ret) { dev_err(pctrl->dev, "Unable to parse gpio-ranges\n"); @@ -1159,6 +1383,15 @@ static int rzg2l_gpio_register(struct rzg2l_pinctrl *pctrl) chip->base = -1; chip->ngpio = of_args.args[2]; + girq = &chip->irq; + girq->chip = (struct irq_chip *)&rzg2l_gpio_irqchip; + girq->fwnode = of_node_to_fwnode(np); + girq->parent_domain = parent_domain; + girq->child_to_parent_hwirq = rzg2l_gpio_child_to_parent_hwirq; + girq->populate_parent_alloc_arg = rzg2l_gpio_populate_parent_fwspec; + girq->child_irq_domain_ops.free = rzg2l_gpio_irq_domain_free; + girq->init_valid_mask = rzg2l_init_irq_valid_mask; + pctrl->gpio_range.id = 0; pctrl->gpio_range.pin_base = 0; pctrl->gpio_range.base = 0; @@ -1274,6 +1507,7 @@ static int rzg2l_pinctrl_probe(struct platform_device *pdev) } spin_lock_init(&pctrl->lock); + spin_lock_init(&pctrl->bitmap_lock); mutex_init(&pctrl->mutex); platform_set_drvdata(pdev, pctrl); From patchwork Wed Mar 27 08:17:24 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Claudiu Beznea X-Patchwork-Id: 13606183 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from aws-us-west-2-korg-lkml-1.web.codeaurora.org (localhost.localdomain [127.0.0.1]) by smtp.lore.kernel.org (Postfix) with ESMTP id 3FF03CD12A1 for ; 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([82.78.167.144]) by smtp.gmail.com with ESMTPSA id c9-20020a7bc2a9000000b0041493615585sm1353783wmk.39.2024.03.27.01.18.02 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 27 Mar 2024 01:18:03 -0700 (PDT) From: Claudiu X-Google-Original-From: Claudiu To: nobuhiro1.iwamatsu@toshiba.co.jp, pavel@denx.de Cc: cip-dev@lists.cip-project.org, biju.das.jz@bp.renesas.com, prabhakar.mahadev-lad.rj@bp.renesas.com, claudiu.beznea@tuxon.dev Subject: [PATCH 5.10.y-cip 04/36] pinctrl: renesas: rzg2l: Fix configuring the GPIO pins as interrupts Date: Wed, 27 Mar 2024 10:17:24 +0200 Message-Id: <20240327081756.2228036-5-claudiu.beznea.uj@bp.renesas.com> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20240327081756.2228036-1-claudiu.beznea.uj@bp.renesas.com> References: <20240327081756.2228036-1-claudiu.beznea.uj@bp.renesas.com> MIME-Version: 1.0 List-Id: X-Webhook-Received: from li982-79.members.linode.com [45.33.32.79] by aws-us-west-2-korg-lkml-1.web.codeaurora.org with HTTPS for ; Wed, 27 Mar 2024 10:37:06 -0000 X-Groupsio-URL: https://lists.cip-project.org/g/cip-dev/message/15421 From: Lad Prabhakar commit 00dfe29887761405ccd23cc0aa07cb86623bb2b7 upstream. On the RZ/G2UL SoC we have less number of pins compared to RZ/G2L and also the pin configs are completely different. This patch makes sure we use the appropriate pin configs for each SoC (which is passed as part of the OF data) while configuring the GPIO pin as interrupts instead of using rzg2l_gpio_configs[] for all the SoCs. Fixes: bfc69bdbaad1 ("pinctrl: renesas: rzg2l: Add RZ/G2UL support") Signed-off-by: Lad Prabhakar Reviewed-by: Geert Uytterhoeven Acked-by: Linus Walleij Link: https://lore.kernel.org/r/20230102221815.273719-3-prabhakar.mahadev-lad.rj@bp.renesas.com Signed-off-by: Geert Uytterhoeven Signed-off-by: Claudiu Beznea --- drivers/pinctrl/renesas/pinctrl-rzg2l.c | 17 ++++++++++------- 1 file changed, 10 insertions(+), 7 deletions(-) diff --git a/drivers/pinctrl/renesas/pinctrl-rzg2l.c b/drivers/pinctrl/renesas/pinctrl-rzg2l.c index 8e33d3a34c06..063f8233a5eb 100644 --- a/drivers/pinctrl/renesas/pinctrl-rzg2l.c +++ b/drivers/pinctrl/renesas/pinctrl-rzg2l.c @@ -128,6 +128,7 @@ struct rzg2l_dedicated_configs { struct rzg2l_pinctrl_data { const char * const *port_pins; const u32 *port_pin_configs; + unsigned int n_ports; struct rzg2l_dedicated_configs *dedicated_pins; unsigned int n_port_pins; unsigned int n_dedicated_pins; @@ -1141,7 +1142,7 @@ static struct { } }; -static int rzg2l_gpio_get_gpioint(unsigned int virq) +static int rzg2l_gpio_get_gpioint(unsigned int virq, const struct rzg2l_pinctrl_data *data) { unsigned int gpioint; unsigned int i; @@ -1150,13 +1151,13 @@ static int rzg2l_gpio_get_gpioint(unsigned int virq) port = virq / 8; bit = virq % 8; - if (port >= ARRAY_SIZE(rzg2l_gpio_configs) || - bit >= RZG2L_GPIO_PORT_GET_PINCNT(rzg2l_gpio_configs[port])) + if (port >= data->n_ports || + bit >= RZG2L_GPIO_PORT_GET_PINCNT(data->port_pin_configs[port])) return -EINVAL; gpioint = bit; for (i = 0; i < port; i++) - gpioint += RZG2L_GPIO_PORT_GET_PINCNT(rzg2l_gpio_configs[i]); + gpioint += RZG2L_GPIO_PORT_GET_PINCNT(data->port_pin_configs[i]); return gpioint; } @@ -1254,7 +1255,7 @@ static int rzg2l_gpio_child_to_parent_hwirq(struct gpio_chip *gc, unsigned long flags; int gpioint, irq; - gpioint = rzg2l_gpio_get_gpioint(child); + gpioint = rzg2l_gpio_get_gpioint(child, pctrl->data); if (gpioint < 0) return gpioint; @@ -1331,8 +1332,8 @@ static void rzg2l_init_irq_valid_mask(struct gpio_chip *gc, port = offset / 8; bit = offset % 8; - if (port >= ARRAY_SIZE(rzg2l_gpio_configs) || - bit >= RZG2L_GPIO_PORT_GET_PINCNT(rzg2l_gpio_configs[port])) + if (port >= pctrl->data->n_ports || + bit >= RZG2L_GPIO_PORT_GET_PINCNT(pctrl->data->port_pin_configs[port])) clear_bit(offset, valid_mask); } } @@ -1538,6 +1539,7 @@ static int rzg2l_pinctrl_probe(struct platform_device *pdev) static struct rzg2l_pinctrl_data r9a07g043_data = { .port_pins = rzg2l_gpio_names, .port_pin_configs = r9a07g043_gpio_configs, + .n_ports = ARRAY_SIZE(r9a07g043_gpio_configs), .dedicated_pins = rzg2l_dedicated_pins.common, .n_port_pins = ARRAY_SIZE(r9a07g043_gpio_configs) * RZG2L_PINS_PER_PORT, .n_dedicated_pins = ARRAY_SIZE(rzg2l_dedicated_pins.common), @@ -1546,6 +1548,7 @@ static struct rzg2l_pinctrl_data r9a07g043_data = { static struct rzg2l_pinctrl_data r9a07g044_data = { .port_pins = rzg2l_gpio_names, .port_pin_configs = rzg2l_gpio_configs, + .n_ports = ARRAY_SIZE(rzg2l_gpio_configs), .dedicated_pins = rzg2l_dedicated_pins.common, .n_port_pins = ARRAY_SIZE(rzg2l_gpio_names), .n_dedicated_pins = ARRAY_SIZE(rzg2l_dedicated_pins.common) + From patchwork Wed Mar 27 08:17:25 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Claudiu Beznea X-Patchwork-Id: 13606185 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from aws-us-west-2-korg-lkml-1.web.codeaurora.org (localhost.localdomain [127.0.0.1]) by smtp.lore.kernel.org (Postfix) with ESMTP id 4DC1FCD12A4 for ; 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([82.78.167.144]) by smtp.gmail.com with ESMTPSA id c9-20020a7bc2a9000000b0041493615585sm1353783wmk.39.2024.03.27.01.18.03 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 27 Mar 2024 01:18:04 -0700 (PDT) From: Claudiu X-Google-Original-From: Claudiu To: nobuhiro1.iwamatsu@toshiba.co.jp, pavel@denx.de Cc: cip-dev@lists.cip-project.org, biju.das.jz@bp.renesas.com, prabhakar.mahadev-lad.rj@bp.renesas.com, claudiu.beznea@tuxon.dev Subject: [PATCH 5.10.y-cip 05/36] pinctrl: renesas: rzg2l: Add BUILD_BUG_ON() checks Date: Wed, 27 Mar 2024 10:17:25 +0200 Message-Id: <20240327081756.2228036-6-claudiu.beznea.uj@bp.renesas.com> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20240327081756.2228036-1-claudiu.beznea.uj@bp.renesas.com> References: <20240327081756.2228036-1-claudiu.beznea.uj@bp.renesas.com> MIME-Version: 1.0 List-Id: X-Webhook-Received: from li982-79.members.linode.com [45.33.32.79] by aws-us-west-2-korg-lkml-1.web.codeaurora.org with HTTPS for ; Wed, 27 Mar 2024 10:37:06 -0000 X-Groupsio-URL: https://lists.cip-project.org/g/cip-dev/message/15422 From: Lad Prabhakar commit 2d4a628cade2fe9cf7aa5629cffe768afe0e7ae1 upstream. Add BUILD_BUG_ON() checks to avoid overflows for GPIO configs for each supported SoC. While at it, for readability set n_port_pins based on the GPIO pin configs and not on GPIO names for r9a07g044_data as done for r9a07g043_data. Suggested-by: Geert Uytterhoeven Signed-off-by: Lad Prabhakar Reviewed-by: Geert Uytterhoeven Acked-by: Linus Walleij Link: https://lore.kernel.org/r/20230102221815.273719-4-prabhakar.mahadev-lad.rj@bp.renesas.com Signed-off-by: Geert Uytterhoeven Signed-off-by: Claudiu Beznea --- drivers/pinctrl/renesas/pinctrl-rzg2l.c | 8 +++++++- 1 file changed, 7 insertions(+), 1 deletion(-) diff --git a/drivers/pinctrl/renesas/pinctrl-rzg2l.c b/drivers/pinctrl/renesas/pinctrl-rzg2l.c index 063f8233a5eb..230075645094 100644 --- a/drivers/pinctrl/renesas/pinctrl-rzg2l.c +++ b/drivers/pinctrl/renesas/pinctrl-rzg2l.c @@ -1486,6 +1486,12 @@ static int rzg2l_pinctrl_probe(struct platform_device *pdev) struct rzg2l_pinctrl *pctrl; int ret; + BUILD_BUG_ON(ARRAY_SIZE(rzg2l_gpio_configs) * RZG2L_PINS_PER_PORT > + ARRAY_SIZE(rzg2l_gpio_names)); + + BUILD_BUG_ON(ARRAY_SIZE(r9a07g043_gpio_configs) * RZG2L_PINS_PER_PORT > + ARRAY_SIZE(rzg2l_gpio_names)); + pctrl = devm_kzalloc(&pdev->dev, sizeof(*pctrl), GFP_KERNEL); if (!pctrl) return -ENOMEM; @@ -1550,7 +1556,7 @@ static struct rzg2l_pinctrl_data r9a07g044_data = { .port_pin_configs = rzg2l_gpio_configs, .n_ports = ARRAY_SIZE(rzg2l_gpio_configs), .dedicated_pins = rzg2l_dedicated_pins.common, - .n_port_pins = ARRAY_SIZE(rzg2l_gpio_names), + .n_port_pins = ARRAY_SIZE(rzg2l_gpio_configs) * RZG2L_PINS_PER_PORT, .n_dedicated_pins = ARRAY_SIZE(rzg2l_dedicated_pins.common) + ARRAY_SIZE(rzg2l_dedicated_pins.rzg2l_pins), }; From patchwork Wed Mar 27 08:17:26 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Claudiu Beznea X-Patchwork-Id: 13606189 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from aws-us-west-2-korg-lkml-1.web.codeaurora.org (localhost.localdomain [127.0.0.1]) by smtp.lore.kernel.org (Postfix) with ESMTP id 59103CD12A9 for ; Wed, 27 Mar 2024 10:37:06 +0000 (UTC) Received: from mail-wm1-f49.google.com (mail-wm1-f49.google.com [209.85.128.49]) by mx.groups.io with SMTP id smtpd.web10.32432.1711527487337625102 for ; Wed, 27 Mar 2024 01:18:07 -0700 Authentication-Results: mx.groups.io; dkim=pass header.i=@tuxon.dev header.s=google header.b=dnrwNeA3; spf=pass (domain: tuxon.dev, ip: 209.85.128.49, mailfrom: claudiu.beznea@tuxon.dev) Received: by mail-wm1-f49.google.com with SMTP id 5b1f17b1804b1-41488e17e1cso17815725e9.0 for ; Wed, 27 Mar 2024 01:18:07 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=tuxon.dev; s=google; t=1711527486; x=1712132286; darn=lists.cip-project.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=L54lWPHYc9HFQiRqSsiWrn83FaCx6Rp3gfoBfFoHZac=; b=dnrwNeA3h1shLimWGh1qQqwT92MtpMRhrgx09kBokyqLs0M5d9UaRdA3yJyquVemBv zVTydlYrP1fuAeC0vG1B+GLd3p5b918CZoOn0Y/4shP15oJipD0ogLSG3PlPtUDYBgv8 1FfnHhnq4bwWB882ZGydchWFgObtqW6LWu5A1eH/JmnumD/B2VKRZVcgwN+IwvtQ+k1t CmrrDeD4JgtTkrCi8xHipe1X4vmr1dLX0f83sJww2mpsN0cFVLw37LUHTuSIFatroOk3 HQcvZPcu+CdpBnIGsaQaO1wkjHPHlrBUpwRzB9aC1egxrKiTAPa65kDI72w6h5xn0LGI b/FA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1711527486; x=1712132286; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=L54lWPHYc9HFQiRqSsiWrn83FaCx6Rp3gfoBfFoHZac=; b=BJIaAWPjDA61WN+gLvYjJzVIV4BndVNsXtI9oFN1FSsBIfvzvazdt9+9YyZ25R4rdZ 7ZZSfUdpSo8p8FBGjqSOIlbQ6bsemxiAVSJ+G2aUbYoSTY09QX4efkuYpJBTN4ljzZHs J6f7L3B/is+UYeh2iSBXsNC1gpmfa9BIZeX6axwkfEc9VA3aZ6QiDv/qEiSAzW3SlUhE e3Yoh9cEYNU/7ovUh25Dx6vbO+5HDjCUmQbGJ/oyf7jESHfMKGPZSB49fxxf3Z/xhmYA 0DF0uJFjCy6RFWVs1emIz8vDY4FYWCjdvVYhdXlGJ3xWo/mAtppyHQAvWrX/gD73hlV9 U+bA== X-Gm-Message-State: AOJu0YwfP+IiUwSW2Yu1WutdZtBoi4UhIRC9+iGrHPPlhI6radXIu68D lXUHVSPav9fwR2ydfo+oG5/Ei2IVi16WQE5F0GJ8UiMmf5B3Rlz9AjmQ0r2P6Fg= X-Google-Smtp-Source: AGHT+IEZmrTHpN441cpLLtYrk2OdUqOxpR8jhVVK1NTgKXOzEJQDtcHQoaKfY+NNRH31vSNo1iVD6Q== X-Received: by 2002:a05:600c:46c7:b0:414:7597:c2dc with SMTP id q7-20020a05600c46c700b004147597c2dcmr3486007wmo.17.1711527485741; Wed, 27 Mar 2024 01:18:05 -0700 (PDT) Received: from claudiu-X670E-Pro-RS.. ([82.78.167.144]) by smtp.gmail.com with ESMTPSA id c9-20020a7bc2a9000000b0041493615585sm1353783wmk.39.2024.03.27.01.18.04 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 27 Mar 2024 01:18:05 -0700 (PDT) From: Claudiu X-Google-Original-From: Claudiu To: nobuhiro1.iwamatsu@toshiba.co.jp, pavel@denx.de Cc: cip-dev@lists.cip-project.org, biju.das.jz@bp.renesas.com, prabhakar.mahadev-lad.rj@bp.renesas.com, claudiu.beznea@tuxon.dev Subject: [PATCH 5.10.y-cip 06/36] pinctrl: renesas: rzg2l: Use devm_clk_get_enabled() helper Date: Wed, 27 Mar 2024 10:17:26 +0200 Message-Id: <20240327081756.2228036-7-claudiu.beznea.uj@bp.renesas.com> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20240327081756.2228036-1-claudiu.beznea.uj@bp.renesas.com> References: <20240327081756.2228036-1-claudiu.beznea.uj@bp.renesas.com> MIME-Version: 1.0 List-Id: X-Webhook-Received: from li982-79.members.linode.com [45.33.32.79] by aws-us-west-2-korg-lkml-1.web.codeaurora.org with HTTPS for ; Wed, 27 Mar 2024 10:37:06 -0000 X-Groupsio-URL: https://lists.cip-project.org/g/cip-dev/message/15423 From: Christophe JAILLET commit 95eb19869401850f069723b296170b8b3bd5be9e upstream. The devm_clk_get_enabled() helper: - calls devm_clk_get() - calls clk_prepare_enable() and registers what is needed in order to call clk_disable_unprepare() when needed, as a managed resource. This simplifies the code and avoids the need of a dedicated function used with devm_add_action_or_reset(). While at it, use dev_err_probe() which filters -EPROBE_DEFER. Signed-off-by: Christophe JAILLET Reviewed-by: Geert Uytterhoeven Link: https://lore.kernel.org/r/a4a586337d692f0ca396b80d275ba634eb419593.1690058500.git.christophe.jaillet@wanadoo.fr [geert: Make clk local to rzg2l_pinctrl_probe()] Signed-off-by: Geert Uytterhoeven Signed-off-by: Claudiu Beznea --- drivers/pinctrl/renesas/pinctrl-rzg2l.c | 32 ++++--------------------- 1 file changed, 5 insertions(+), 27 deletions(-) diff --git a/drivers/pinctrl/renesas/pinctrl-rzg2l.c b/drivers/pinctrl/renesas/pinctrl-rzg2l.c index 230075645094..a0a704449caf 100644 --- a/drivers/pinctrl/renesas/pinctrl-rzg2l.c +++ b/drivers/pinctrl/renesas/pinctrl-rzg2l.c @@ -142,7 +142,6 @@ struct rzg2l_pinctrl { const struct rzg2l_pinctrl_data *data; void __iomem *base; struct device *dev; - struct clk *clk; struct gpio_chip gpio_chip; struct pinctrl_gpio_range gpio_range; @@ -1476,14 +1475,10 @@ static int rzg2l_pinctrl_register(struct rzg2l_pinctrl *pctrl) return 0; } -static void rzg2l_pinctrl_clk_disable(void *data) -{ - clk_disable_unprepare(data); -} - static int rzg2l_pinctrl_probe(struct platform_device *pdev) { struct rzg2l_pinctrl *pctrl; + struct clk *clk; int ret; BUILD_BUG_ON(ARRAY_SIZE(rzg2l_gpio_configs) * RZG2L_PINS_PER_PORT > @@ -1506,12 +1501,10 @@ static int rzg2l_pinctrl_probe(struct platform_device *pdev) if (IS_ERR(pctrl->base)) return PTR_ERR(pctrl->base); - pctrl->clk = devm_clk_get(pctrl->dev, NULL); - if (IS_ERR(pctrl->clk)) { - ret = PTR_ERR(pctrl->clk); - dev_err(pctrl->dev, "failed to get GPIO clk : %i\n", ret); - return ret; - } + clk = devm_clk_get_enabled(pctrl->dev, NULL); + if (IS_ERR(clk)) + return dev_err_probe(pctrl->dev, PTR_ERR(clk), + "failed to enable GPIO clk\n"); spin_lock_init(&pctrl->lock); spin_lock_init(&pctrl->bitmap_lock); @@ -1519,21 +1512,6 @@ static int rzg2l_pinctrl_probe(struct platform_device *pdev) platform_set_drvdata(pdev, pctrl); - ret = clk_prepare_enable(pctrl->clk); - if (ret) { - dev_err(pctrl->dev, "failed to enable GPIO clk: %i\n", ret); - return ret; - } - - ret = devm_add_action_or_reset(&pdev->dev, rzg2l_pinctrl_clk_disable, - pctrl->clk); - if (ret) { - dev_err(pctrl->dev, - "failed to register GPIO clk disable action, %i\n", - ret); - return ret; - } - ret = rzg2l_pinctrl_register(pctrl); if (ret) return ret; From patchwork Wed Mar 27 08:17:27 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Claudiu Beznea X-Patchwork-Id: 13606196 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from aws-us-west-2-korg-lkml-1.web.codeaurora.org (localhost.localdomain [127.0.0.1]) by smtp.lore.kernel.org (Postfix) with ESMTP id 59051CD12A7 for ; Wed, 27 Mar 2024 10:37:06 +0000 (UTC) Received: from mail-wm1-f53.google.com (mail-wm1-f53.google.com [209.85.128.53]) by mx.groups.io with SMTP id smtpd.web11.32288.1711527488365563536 for ; Wed, 27 Mar 2024 01:18:08 -0700 Authentication-Results: mx.groups.io; dkim=pass header.i=@tuxon.dev header.s=google header.b=EcHg27hf; spf=pass (domain: tuxon.dev, ip: 209.85.128.53, mailfrom: claudiu.beznea@tuxon.dev) Received: by mail-wm1-f53.google.com with SMTP id 5b1f17b1804b1-41494714fd1so2171615e9.2 for ; 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([82.78.167.144]) by smtp.gmail.com with ESMTPSA id c9-20020a7bc2a9000000b0041493615585sm1353783wmk.39.2024.03.27.01.18.05 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 27 Mar 2024 01:18:06 -0700 (PDT) From: Claudiu X-Google-Original-From: Claudiu To: nobuhiro1.iwamatsu@toshiba.co.jp, pavel@denx.de Cc: cip-dev@lists.cip-project.org, biju.das.jz@bp.renesas.com, prabhakar.mahadev-lad.rj@bp.renesas.com, claudiu.beznea@tuxon.dev Subject: [PATCH 5.10.y-cip 07/36] pinctrl: renesas: rzg2l: Enhance driver to support interrupt affinity setting Date: Wed, 27 Mar 2024 10:17:27 +0200 Message-Id: <20240327081756.2228036-8-claudiu.beznea.uj@bp.renesas.com> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20240327081756.2228036-1-claudiu.beznea.uj@bp.renesas.com> References: <20240327081756.2228036-1-claudiu.beznea.uj@bp.renesas.com> MIME-Version: 1.0 List-Id: X-Webhook-Received: from li982-79.members.linode.com [45.33.32.79] by aws-us-west-2-korg-lkml-1.web.codeaurora.org with HTTPS for ; Wed, 27 Mar 2024 10:37:06 -0000 X-Groupsio-URL: https://lists.cip-project.org/g/cip-dev/message/15424 From: Lad Prabhakar commit e4c3a81ab88f3230713f4678deb9dd3cb8d0382c upstream. Implement irq_set_affinity callback so that we can set affinity for GPIO IRQs. Signed-off-by: Lad Prabhakar Reviewed-by: Geert Uytterhoeven Link: https://lore.kernel.org/r/20231011195923.67404-1-prabhakar.mahadev-lad.rj@bp.renesas.com Signed-off-by: Geert Uytterhoeven [claudiu.beznea: fixed conflict by removing IRQCHIP_IMMUTABLE and GPIOCHIP_IRQ_RESOURCE_HELPERS as these are not available in v5.10] Signed-off-by: Claudiu Beznea --- drivers/pinctrl/renesas/pinctrl-rzg2l.c | 1 + 1 file changed, 1 insertion(+) diff --git a/drivers/pinctrl/renesas/pinctrl-rzg2l.c b/drivers/pinctrl/renesas/pinctrl-rzg2l.c index a0a704449caf..2965c67d8ad0 100644 --- a/drivers/pinctrl/renesas/pinctrl-rzg2l.c +++ b/drivers/pinctrl/renesas/pinctrl-rzg2l.c @@ -1242,6 +1242,7 @@ static const struct irq_chip rzg2l_gpio_irqchip = { .irq_set_type = rzg2l_gpio_irq_set_type, .irq_eoi = rzg2l_gpio_irqc_eoi, .irq_print_chip = rzg2l_gpio_irq_print_chip, + .irq_set_affinity = irq_chip_set_affinity_parent, }; static int rzg2l_gpio_child_to_parent_hwirq(struct gpio_chip *gc, From patchwork Wed Mar 27 08:17:28 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Claudiu Beznea X-Patchwork-Id: 13606199 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from aws-us-west-2-korg-lkml-1.web.codeaurora.org (localhost.localdomain [127.0.0.1]) by smtp.lore.kernel.org (Postfix) with ESMTP id 7C9A0CD12B0 for ; Wed, 27 Mar 2024 10:37:06 +0000 (UTC) Received: from mail-wm1-f52.google.com (mail-wm1-f52.google.com [209.85.128.52]) by mx.groups.io with SMTP id smtpd.web11.32289.1711527489513052852 for ; Wed, 27 Mar 2024 01:18:09 -0700 Authentication-Results: mx.groups.io; dkim=pass header.i=@tuxon.dev header.s=google header.b=JFH53TpH; spf=pass (domain: tuxon.dev, ip: 209.85.128.52, mailfrom: claudiu.beznea@tuxon.dev) Received: by mail-wm1-f52.google.com with SMTP id 5b1f17b1804b1-4148c5de23fso13651755e9.1 for ; Wed, 27 Mar 2024 01:18:09 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=tuxon.dev; s=google; t=1711527488; x=1712132288; darn=lists.cip-project.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=O2Cc7kAEpFuy//l5Tsh++q77snO4W4RVQYsZaqHJXbk=; b=JFH53TpHcOfqrO93DwR36duClBbh8Hj8f68DgD+LvNL0DAQqh9rxCa2DagYaynmQn4 NvCFyr41eVpS5+gxkrsGRhpwP2DNhZJ3pDFqN2XiFmgU0OJOd62sd3d45ejmecklGQd2 RtkJByw1d20IQkhThZenBz5qG8YFFYfwn/wmnRIm1ESYmOV0MBpiYt7gijKA+lANnV23 L4xughXckcUJ2lp0TgrSbPKTlKl4nDpll42LYMfXS/+b7G73GGG3NvXT9PRnsd+Qk7Ok n4VzVv3kOocn2ioB+BKyIBFFKV3GAOkdlnAuc5aiieNQ0sXXbrPrSU0fssNI56sDFXPA 0kHw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1711527488; x=1712132288; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=O2Cc7kAEpFuy//l5Tsh++q77snO4W4RVQYsZaqHJXbk=; b=DAr4zZyV3dFfBys7TlCYb0aK106m4CacFBMSGznTiLrp1CgWePca9sA5orZ84Mqc92 atJpu2ru4xvAsjgAZ6xb2U3aBjMuk/3Drvil3NuW51+cTkKRKq9rdAQGhRGXwvHr4YU/ eYsC5nT4VFcjeuI/FUfcM5gkd5WbbH3e5Tx29VuoD0b/s5aI9LWyQNl8YAXvlnCjgCU3 uhgfUqlRaBwwGILs3Frwr3xn2ztkp1c4fEOTjE6QdeC6l8lhJ9eZ3xC00Aa2MVuot4Zo FTlRnRCN78Iniavk67jS+DSr5o2KshSPDMH1TZvCVQYntCW+1GOGo/JBCed9bnKDaa/v d/cQ== X-Gm-Message-State: AOJu0YxhLkuzIMLv+0vxqR+6it1qyBmrNY6dH2sDMPwv19EYiIkNHjVj uQxKMujcbvOWS792i/awsiflRU+TCbjt9GObLDDyyHeZDquMFMy4XOzjA1mrSRw= X-Google-Smtp-Source: AGHT+IHLW5TBOfJ5OWIygFTfgOQwlEqp00/Xx2F3UThWpYGhRfQeAo1ZUGexvgSqT/LtM/Yn50kuDA== X-Received: by 2002:a05:600c:54ea:b0:414:8889:5a39 with SMTP id jb10-20020a05600c54ea00b0041488895a39mr1240046wmb.17.1711527487982; Wed, 27 Mar 2024 01:18:07 -0700 (PDT) Received: from claudiu-X670E-Pro-RS.. ([82.78.167.144]) by smtp.gmail.com with ESMTPSA id c9-20020a7bc2a9000000b0041493615585sm1353783wmk.39.2024.03.27.01.18.07 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 27 Mar 2024 01:18:07 -0700 (PDT) From: Claudiu X-Google-Original-From: Claudiu To: nobuhiro1.iwamatsu@toshiba.co.jp, pavel@denx.de Cc: cip-dev@lists.cip-project.org, biju.das.jz@bp.renesas.com, prabhakar.mahadev-lad.rj@bp.renesas.com, claudiu.beznea@tuxon.dev Subject: [PATCH 5.10.y-cip 08/36] dt-bindings: interrupt-controller: Add Renesas RZ/G2L Interrupt Controller Date: Wed, 27 Mar 2024 10:17:28 +0200 Message-Id: <20240327081756.2228036-9-claudiu.beznea.uj@bp.renesas.com> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20240327081756.2228036-1-claudiu.beznea.uj@bp.renesas.com> References: <20240327081756.2228036-1-claudiu.beznea.uj@bp.renesas.com> MIME-Version: 1.0 List-Id: X-Webhook-Received: from li982-79.members.linode.com [45.33.32.79] by aws-us-west-2-korg-lkml-1.web.codeaurora.org with HTTPS for ; Wed, 27 Mar 2024 10:37:06 -0000 X-Groupsio-URL: https://lists.cip-project.org/g/cip-dev/message/15425 From: Lad Prabhakar commit 96fed779d3d4cb3c221bb70e94de59b8dec0abfc upstream. Add DT bindings for the Renesas RZ/G2L Interrupt Controller. Signed-off-by: Lad Prabhakar Reviewed-by: Rob Herring Reviewed-by: Geert Uytterhoeven Signed-off-by: Marc Zyngier Link: https://lore.kernel.org/r/20220707182314.66610-3-prabhakar.mahadev-lad.rj@bp.renesas.com Signed-off-by: Claudiu Beznea --- .../renesas,rzg2l-irqc.yaml | 133 ++++++++++++++++++ 1 file changed, 133 insertions(+) create mode 100644 Documentation/devicetree/bindings/interrupt-controller/renesas,rzg2l-irqc.yaml diff --git a/Documentation/devicetree/bindings/interrupt-controller/renesas,rzg2l-irqc.yaml b/Documentation/devicetree/bindings/interrupt-controller/renesas,rzg2l-irqc.yaml new file mode 100644 index 000000000000..ffbb4ab4d9a7 --- /dev/null +++ b/Documentation/devicetree/bindings/interrupt-controller/renesas,rzg2l-irqc.yaml @@ -0,0 +1,133 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/interrupt-controller/renesas,rzg2l-irqc.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Renesas RZ/G2L (and alike SoC's) Interrupt Controller (IA55) + +maintainers: + - Lad Prabhakar + - Geert Uytterhoeven + +description: | + IA55 performs various interrupt controls including synchronization for the external + interrupts of NMI, IRQ, and GPIOINT and the interrupts of the built-in peripheral + interrupts output by each IP. And it notifies the interrupt to the GIC + - IRQ sense select for 8 external interrupts, mapped to 8 GIC SPI interrupts + - GPIO pins used as external interrupt input pins, mapped to 32 GIC SPI interrupts + - NMI edge select (NMI is not treated as NMI exception and supports fall edge and + stand-up edge detection interrupts) + +allOf: + - $ref: /schemas/interrupt-controller.yaml# + +properties: + compatible: + items: + - enum: + - renesas,r9a07g044-irqc # RZ/G2L + - const: renesas,rzg2l-irqc + + '#interrupt-cells': + description: The first cell should contain external interrupt number (IRQ0-7) and the + second cell is used to specify the flag. + const: 2 + + '#address-cells': + const: 0 + + interrupt-controller: true + + reg: + maxItems: 1 + + interrupts: + maxItems: 41 + + clocks: + maxItems: 2 + + clock-names: + items: + - const: clk + - const: pclk + + power-domains: + maxItems: 1 + + resets: + maxItems: 1 + +required: + - compatible + - '#interrupt-cells' + - '#address-cells' + - interrupt-controller + - reg + - interrupts + - clocks + - clock-names + - power-domains + - resets + +unevaluatedProperties: false + +examples: + - | + #include + #include + + irqc: interrupt-controller@110a0000 { + compatible = "renesas,r9a07g044-irqc", "renesas,rzg2l-irqc"; + reg = <0x110a0000 0x10000>; + #interrupt-cells = <2>; + #address-cells = <0>; + interrupt-controller; + interrupts = , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + ; + clocks = <&cpg CPG_MOD R9A07G044_IA55_CLK>, + <&cpg CPG_MOD R9A07G044_IA55_PCLK>; + clock-names = "clk", "pclk"; + power-domains = <&cpg>; + resets = <&cpg R9A07G044_IA55_RESETN>; + }; From patchwork Wed Mar 27 08:17:29 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Claudiu Beznea X-Patchwork-Id: 13606200 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from aws-us-west-2-korg-lkml-1.web.codeaurora.org (localhost.localdomain [127.0.0.1]) by smtp.lore.kernel.org (Postfix) with ESMTP id 88A93CD12B4 for ; Wed, 27 Mar 2024 10:37:06 +0000 (UTC) Received: from mail-wm1-f43.google.com (mail-wm1-f43.google.com [209.85.128.43]) by mx.groups.io with SMTP id smtpd.web10.32433.1711527490489761232 for ; Wed, 27 Mar 2024 01:18:10 -0700 Authentication-Results: mx.groups.io; dkim=pass header.i=@tuxon.dev header.s=google header.b=HokYqtc4; spf=pass (domain: tuxon.dev, ip: 209.85.128.43, mailfrom: claudiu.beznea@tuxon.dev) Received: by mail-wm1-f43.google.com with SMTP id 5b1f17b1804b1-4148c6132b4so3120275e9.1 for ; Wed, 27 Mar 2024 01:18:10 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=tuxon.dev; s=google; t=1711527489; x=1712132289; darn=lists.cip-project.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=ToSucKwbPqdoHraBZXnmWdJqUnwHYMVZqR4ncg2CPCA=; b=HokYqtc4eP34cGmgp3o3OodsYz/pkBHwk1EZQymk0a9DRxLEdRLSxgrDYVxlaGtymR PAMlaPcFt39ikk/4ROoc4pH65E1NLu2HI3cEilxSWzWLKG7tdkEAwZAftOEWSXynGFOe Ob9l24cO/mbAJj8wytaW/Cp+KPLX2NVSUNvlZiRymQ8z/lXZBpHuVaFyL5a6CHKzx9kR AEy34xhMwc/L9GTNo4B1gJWJD5IvVURM3HLeHpTn6G6t23V4omA4ND78lr7YG20J+WXP KE+VWG5O02nNSGuZuMrmrHna1HE5Tu9u6tySK+lEZEB+L/Ss0NZ+g+GYYiGRiRhkTrsR l8pQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1711527489; x=1712132289; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=ToSucKwbPqdoHraBZXnmWdJqUnwHYMVZqR4ncg2CPCA=; b=hBD4V+tmAiiSwF/2fu0n52Wpjw6fF13tbzog49d6t/JJFYz7Hgkd/MNwH9g6eP/XC2 hSg+bcO5VViavs4mtmmWzcOJi0d/ZfdVXRhkVGMKYSKM7M2xNeUKW8K4QlNbxidUMk11 Lqygz+THgNGSDDyVo21pk/NnA0g7yzzfkFTI6qnBTp/Y5k5fnlaFxFHNO01tqbr5NanD IsFBdIEPVCWC9HUHPLAOu2rqM6P//bGJGFia911S2JQU0ADK86c6kTBIAPorJqYcSw0b YmHitAQSNYJMlZQ+QnLcBPSD3+8H1DkNlefl+T0WIaUjyZwjKv6jawaSvuqBBCU5RP6s RWeg== X-Gm-Message-State: AOJu0YzRKEc2i8ht4uoa8a7A8jLzPacxcVFmq3wvSzZK6W5JM1Wb22S2 diz0csBiNOWinvqPHSWuVmzwim8Kco2xMHtLGH7wt/I7aokWe0isbek2wOGOQoY= X-Google-Smtp-Source: AGHT+IHwTaREpG2JprD9rgxprvxPQoamwTm7+w8ySz9s7XENRqfX4i0hVxQhqIUlhPcEJBfGdK9XKg== X-Received: by 2002:a05:600c:354d:b0:414:8849:947e with SMTP id i13-20020a05600c354d00b004148849947emr3420724wmq.3.1711527488978; Wed, 27 Mar 2024 01:18:08 -0700 (PDT) Received: from claudiu-X670E-Pro-RS.. ([82.78.167.144]) by smtp.gmail.com with ESMTPSA id c9-20020a7bc2a9000000b0041493615585sm1353783wmk.39.2024.03.27.01.18.08 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 27 Mar 2024 01:18:08 -0700 (PDT) From: Claudiu X-Google-Original-From: Claudiu To: nobuhiro1.iwamatsu@toshiba.co.jp, pavel@denx.de Cc: cip-dev@lists.cip-project.org, biju.das.jz@bp.renesas.com, prabhakar.mahadev-lad.rj@bp.renesas.com, claudiu.beznea@tuxon.dev Subject: [PATCH 5.10.y-cip 09/36] irqdomain: Make of_phandle_args_to_fwspec() generally available Date: Wed, 27 Mar 2024 10:17:29 +0200 Message-Id: <20240327081756.2228036-10-claudiu.beznea.uj@bp.renesas.com> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20240327081756.2228036-1-claudiu.beznea.uj@bp.renesas.com> References: <20240327081756.2228036-1-claudiu.beznea.uj@bp.renesas.com> MIME-Version: 1.0 List-Id: X-Webhook-Received: from li982-79.members.linode.com [45.33.32.79] by aws-us-west-2-korg-lkml-1.web.codeaurora.org with HTTPS for ; Wed, 27 Mar 2024 10:37:06 -0000 X-Groupsio-URL: https://lists.cip-project.org/g/cip-dev/message/15426 From: Marc Zyngier commit 8b0b9d113ac2dfedf8daff18429b56f9de6d0fea upstream. of_phandle_args_to_fwspec() can be generally useful to code extracting a DT of_phandle and using an irq_fwspec to use the hierarchical irqdomain API. Make it visible to the rest of the kernel, including modules. Link: https://lore.kernel.org/r/20210929163847.2807812-2-maz@kernel.org Tested-by: Alyssa Rosenzweig Signed-off-by: Marc Zyngier Signed-off-by: Lorenzo Pieralisi Signed-off-by: Bjorn Helgaas Signed-off-by: Claudiu Beznea --- include/linux/irqdomain.h | 4 ++++ kernel/irq/irqdomain.c | 6 +++--- 2 files changed, 7 insertions(+), 3 deletions(-) diff --git a/include/linux/irqdomain.h b/include/linux/irqdomain.h index 9b9743f7538c..7871b4adeb3a 100644 --- a/include/linux/irqdomain.h +++ b/include/linux/irqdomain.h @@ -66,6 +66,10 @@ struct irq_fwspec { u32 param[IRQ_DOMAIN_IRQ_SPEC_PARAMS]; }; +/* Conversion function from of_phandle_args fields to fwspec */ +void of_phandle_args_to_fwspec(struct device_node *np, const u32 *args, + unsigned int count, struct irq_fwspec *fwspec); + /* * Should several domains have the same device node, but serve * different purposes (for example one domain is for PCI/MSI, and the diff --git a/kernel/irq/irqdomain.c b/kernel/irq/irqdomain.c index fd3f7c16c299..b9fda33a2148 100644 --- a/kernel/irq/irqdomain.c +++ b/kernel/irq/irqdomain.c @@ -784,9 +784,8 @@ static int irq_domain_translate(struct irq_domain *d, return 0; } -static void of_phandle_args_to_fwspec(struct device_node *np, const u32 *args, - unsigned int count, - struct irq_fwspec *fwspec) +void of_phandle_args_to_fwspec(struct device_node *np, const u32 *args, + unsigned int count, struct irq_fwspec *fwspec) { int i; @@ -796,6 +795,7 @@ static void of_phandle_args_to_fwspec(struct device_node *np, const u32 *args, for (i = 0; i < count; i++) fwspec->param[i] = args[i]; } +EXPORT_SYMBOL_GPL(of_phandle_args_to_fwspec); unsigned int irq_create_fwspec_mapping(struct irq_fwspec *fwspec) { From patchwork Wed Mar 27 08:17:30 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Claudiu Beznea X-Patchwork-Id: 13606201 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from aws-us-west-2-korg-lkml-1.web.codeaurora.org (localhost.localdomain [127.0.0.1]) by smtp.lore.kernel.org (Postfix) with ESMTP id 71385CD12AE for ; Wed, 27 Mar 2024 10:37:06 +0000 (UTC) Received: from mail-lf1-f54.google.com (mail-lf1-f54.google.com [209.85.167.54]) by mx.groups.io with SMTP id smtpd.web11.32292.1711527491797665936 for ; Wed, 27 Mar 2024 01:18:12 -0700 Authentication-Results: mx.groups.io; dkim=pass header.i=@tuxon.dev header.s=google header.b=fPJTIVHZ; spf=pass (domain: tuxon.dev, ip: 209.85.167.54, mailfrom: claudiu.beznea@tuxon.dev) Received: by mail-lf1-f54.google.com with SMTP id 2adb3069b0e04-513cfc93f4eso7053863e87.3 for ; Wed, 27 Mar 2024 01:18:11 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=tuxon.dev; s=google; t=1711527490; x=1712132290; darn=lists.cip-project.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=RNdJcT/r3Etvi39EvpZvevHsdOmLdQOuqaGvUrg/Uso=; b=fPJTIVHZ9otcLv64uYc6F7S7elOdd+zjrpHt9LMoXgSzwa7dOs+2n1PpdbtNyD631D t68gc/bvF5mA5nPYM06vby4wp1RDdCN7tVlQ6NBAkPATN7hH2kxazCjjlwek3xqnBdYI zYjvPMB8jjvoyT3AC3SUxUJc5LahPR1UnvSlZHajZIrt7vH3XMVGEPy1v4K42CLJNEEP 7rExatsl3s8VkJteDUCNGAq7PfZ0jmwrcewSwKuTaGOUsbcAzcSu4x0hcxMegN91/TD/ TFzZvsGsRT7hAcNJZp7Lt00U3iGDFSVtPL+DM/cX0kHVGwhmkM51icIErpaJ1I3SbtMu k93A== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1711527490; x=1712132290; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=RNdJcT/r3Etvi39EvpZvevHsdOmLdQOuqaGvUrg/Uso=; b=kwHBlzOIGneDquCsiQp4eUmHjdLAmY0pMQIRQayyfMU/WZfaMhoOwz9zRXlGx/w1Nz F2aC9bwKmJMhd9GPRtFyOrnvAuZGbL0+FJ0sOxk0O1jj5d9fFl0ljpvDEh3L1A2foq9y Gwz9xI1cOaIAesvBzcmeYrInPSQn0olSGztxNcI0hZYh4xrE6MFPPQJxau/oyqXownFh DRTRKeMbHQWu4wfq3Ubnn71IwkG17yFouiMeMiDAW/ke+dixArgZCXk5PX4JiHOzIwA1 MJpujAnxqyAsSXldUQbeMRxTLcZpc71nLgtyWD3e1RmCZ5SzKdnv9aihsmQUseGlwGdS T7Fg== X-Gm-Message-State: AOJu0YyWx6d1be5qeUUwp8YUaV8XvsuyPOn8D9vU9AFP8JX7fcDDUpr0 OTkIaaaf118h9rQL9JbizvjFWEW24CmT0UKqY54h9v/O3CWUGtHqtBRNqPa7IV8= X-Google-Smtp-Source: AGHT+IHf8UmbTn8aI1W5et6XE4GSXCRVIxANYyWY/egMXdMOahWAgmi5BUKQjQJya282vvj/fubgkQ== X-Received: by 2002:a19:e01d:0:b0:513:cb0a:9632 with SMTP id x29-20020a19e01d000000b00513cb0a9632mr3717051lfg.50.1711527489995; Wed, 27 Mar 2024 01:18:09 -0700 (PDT) Received: from claudiu-X670E-Pro-RS.. ([82.78.167.144]) by smtp.gmail.com with ESMTPSA id c9-20020a7bc2a9000000b0041493615585sm1353783wmk.39.2024.03.27.01.18.09 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 27 Mar 2024 01:18:09 -0700 (PDT) From: Claudiu X-Google-Original-From: Claudiu To: nobuhiro1.iwamatsu@toshiba.co.jp, pavel@denx.de Cc: cip-dev@lists.cip-project.org, biju.das.jz@bp.renesas.com, prabhakar.mahadev-lad.rj@bp.renesas.com, claudiu.beznea@tuxon.dev Subject: [PATCH 5.10.y-cip 10/36] of: platform: Skip populating IRQ to device resource table Date: Wed, 27 Mar 2024 10:17:30 +0200 Message-Id: <20240327081756.2228036-11-claudiu.beznea.uj@bp.renesas.com> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20240327081756.2228036-1-claudiu.beznea.uj@bp.renesas.com> References: <20240327081756.2228036-1-claudiu.beznea.uj@bp.renesas.com> MIME-Version: 1.0 List-Id: X-Webhook-Received: from li982-79.members.linode.com [45.33.32.79] by aws-us-west-2-korg-lkml-1.web.codeaurora.org with HTTPS for ; Wed, 27 Mar 2024 10:37:06 -0000 X-Groupsio-URL: https://lists.cip-project.org/g/cip-dev/message/15427 From: Claudiu Beznea IA55 IRQ controller is connected to GIC and pin controller, the topology being the following: ┌──────────┐ ┌──────────┐ │ │ SPIX │ │ │ ├─────────►│ │ │ │ │ │ │ │ │ │ ┌────────┐IRQ0-7 │ IA55 │ │ GIC │ Pin0 ───────►│ ├─────────────►│ │ │ │ │ │ │ │ PPIY │ │ ... │ GPIO │ │ ├─────────►│ │ │ │GPIOINT0-127 │ │ │ │ PinN ───────►│ ├─────────────►│ │ │ │ └────────┘ └──────────┘ └──────────┘ where: - Pin0 is the first GPIO controller pin - PinN is the last GPIO controller pin - SPIX is the SPI interrupt with identifier X - PPIY is the PPI interrupt with identifier Y While the initial driver has been developed it has been discovered that there are issues with this kind of topology because the platform_get_resource(pdev, IORESOURCE_IRQ, ...) relies on static allocation of IRQ resources in DT core code (though of_device_alloc()). When hierarchical interrupt domains with "interrupts" property in the node are present the usage of platform_get_resource(pdev, IORESOURCE_IRQ, ...), relying on IRQ resource allocation in DT core, bypasses the hierarchical setup and breaks the IRQ chaining. In the mainline kernel this has been addressed by converting all the IRQ drivers to use platform_get_irq() instead of platform_get_resource(pdev, IORESOURCE_IRQ, ...) and removing the of_irq_to_resource_table() and associated code from of_device_alloc() with commit a1a2b7125e10 ("of/platform: Drop static setup of IRQ resource from DT core")" To keep the same driver code and device tree bindings for IA55 IRQC the of_device_alloc() has been adjusted to not allocate and parse the IA55 IRQ resources. Signed-off-by: Claudiu Beznea --- drivers/of/platform.c | 5 ++++- 1 file changed, 4 insertions(+), 1 deletion(-) diff --git a/drivers/of/platform.c b/drivers/of/platform.c index 43748c6480c8..f7ce5f0faf85 100644 --- a/drivers/of/platform.c +++ b/drivers/of/platform.c @@ -119,7 +119,10 @@ struct platform_device *of_device_alloc(struct device_node *np, /* count the io and irq resources */ while (of_address_to_resource(np, num_reg, &temp_res) == 0) num_reg++; - num_irq = of_irq_count(np); + if (of_device_is_compatible(np, "renesas,rzg2l-irqc")) + num_irq = 0; + else + num_irq = of_irq_count(np); /* Populate the resource table */ if (num_irq || num_reg) { From patchwork Wed Mar 27 08:17:31 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Claudiu Beznea X-Patchwork-Id: 13606204 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from aws-us-west-2-korg-lkml-1.web.codeaurora.org (localhost.localdomain [127.0.0.1]) by smtp.lore.kernel.org (Postfix) with ESMTP id 8D1FCCD12B3 for ; Wed, 27 Mar 2024 10:37:06 +0000 (UTC) Received: from mail-lj1-f176.google.com (mail-lj1-f176.google.com [209.85.208.176]) by mx.groups.io with SMTP id smtpd.web11.32293.1711527493184610686 for ; Wed, 27 Mar 2024 01:18:13 -0700 Authentication-Results: mx.groups.io; dkim=pass header.i=@tuxon.dev header.s=google header.b=ecqDmgcg; spf=pass (domain: tuxon.dev, ip: 209.85.208.176, mailfrom: claudiu.beznea@tuxon.dev) Received: by mail-lj1-f176.google.com with SMTP id 38308e7fff4ca-2d52e65d4a8so85718311fa.0 for ; Wed, 27 Mar 2024 01:18:12 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=tuxon.dev; s=google; t=1711527491; x=1712132291; darn=lists.cip-project.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=Gkzq+JJ7NayQefWLUFbEhgeBTDyLomxUYERpZAUmNj4=; b=ecqDmgcgib5s5UsjX6SvXoI9K5vcV9ODzCIxD5FbTeDuRxyuUmduVJBeKuM8i/O3r+ +s9WaIXkpugWsxxqf2svFgjyrgDopIKGY1/LNypTc7UPyML2ZhRG4z7deY3x5MjAiW99 DSU2nY75kcDhLQTrMQyC6xozpISlgcQ9mOfUzdBpI8YmrBwACa7W0p8Fq0queyBabXAW i2nuVjka2B1DbvNZhkYYu/UTfRCQO1hLv54sPNgK0IqHnHO+IWSgOnwuAMf8ANq4lNCp 0/YD3HbEwt+N4gzHCmAWbDhnADzC422492/eBAWPs7GnShEBVC9gIVlTyY0RI51PwXD3 a6kw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1711527491; x=1712132291; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=Gkzq+JJ7NayQefWLUFbEhgeBTDyLomxUYERpZAUmNj4=; b=YP19fM7qrT+J7MytZ25JE9iAlTt8VzLf3LvM5IYNIkTgiDIBv7mnhUVQDmLLA6rReJ W3/N7vzd/wXO9dQE6VpqBIFI978IXTRy1aTenoQEt+ihd4UTYNtYp7in11fm7WbWV2xg HItQB28Uhxj6woENFgDI/jO8HNKlbGboTAkr76eA359cFDF/H5AAkuut4zlOtNO54FhF 5SLGLo8oKsxlEwz6UfDOzxTje2UyApjDKUFDGYyJLP6Z0wBQrgPBh8Jse8A1ZJxSkCtL 0m9sKN/phEDEBgk7CKmlgkhuOeQdUH2uIvdMzvcnC7hDT1uBBtw62EoIdinbaTU4T2T7 wtZg== X-Gm-Message-State: AOJu0YyTFux7jjkjngZ0EmsWcGcVyp1ovZQg72mzgE3mqymIth/h5C6z Gy93vmAZjXM9rxTnVG0t4nmdtMjtG7Hz3IlkLD1d8o0JUns4cQHuO2ksy10vwL4= X-Google-Smtp-Source: AGHT+IGD1Pt/EdmpcjevIj7aO3xMy/tcIJg/Zkw5O/EJ81RFEa7LOjoPJQfddxovtpVCUyuBPzBX3Q== X-Received: by 2002:a2e:be07:0:b0:2d6:b424:a634 with SMTP id z7-20020a2ebe07000000b002d6b424a634mr429615ljq.15.1711527491154; Wed, 27 Mar 2024 01:18:11 -0700 (PDT) Received: from claudiu-X670E-Pro-RS.. ([82.78.167.144]) by smtp.gmail.com with ESMTPSA id c9-20020a7bc2a9000000b0041493615585sm1353783wmk.39.2024.03.27.01.18.10 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 27 Mar 2024 01:18:10 -0700 (PDT) From: Claudiu X-Google-Original-From: Claudiu To: nobuhiro1.iwamatsu@toshiba.co.jp, pavel@denx.de Cc: cip-dev@lists.cip-project.org, biju.das.jz@bp.renesas.com, prabhakar.mahadev-lad.rj@bp.renesas.com, claudiu.beznea@tuxon.dev Subject: [PATCH 5.10.y-cip 11/36] irqchip: Add RZ/G2L IA55 Interrupt Controller driver Date: Wed, 27 Mar 2024 10:17:31 +0200 Message-Id: <20240327081756.2228036-12-claudiu.beznea.uj@bp.renesas.com> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20240327081756.2228036-1-claudiu.beznea.uj@bp.renesas.com> References: <20240327081756.2228036-1-claudiu.beznea.uj@bp.renesas.com> MIME-Version: 1.0 List-Id: X-Webhook-Received: from li982-79.members.linode.com [45.33.32.79] by aws-us-west-2-korg-lkml-1.web.codeaurora.org with HTTPS for ; Wed, 27 Mar 2024 10:37:06 -0000 X-Groupsio-URL: https://lists.cip-project.org/g/cip-dev/message/15428 From: Lad Prabhakar commit 3fed09559cd8be79568d368ce02bf7f2d56259b6 upstream. Add a driver for the Renesas RZ/G2L Interrupt Controller. This supports external pins being used as interrupts. It supports one line for NMI, 8 external pins and 32 GPIO pins (out of 123) to be used as IRQ lines. Signed-off-by: Lad Prabhakar Signed-off-by: Marc Zyngier Link: https://lore.kernel.org/r/20220707182314.66610-4-prabhakar.mahadev-lad.rj@bp.renesas.com [claudiu.beznea: included to get rid of compilation errors; removed const qualifier for irqc_chip object to get rid of compilation warning due to the type of the 4th argument of irq_domain_set_hwirq_and_chip() not being const struct irq_chip *] Signed-off-by: Claudiu Beznea --- drivers/irqchip/Kconfig | 8 + drivers/irqchip/Makefile | 1 + drivers/irqchip/irq-renesas-rzg2l.c | 394 ++++++++++++++++++++++++++++ 3 files changed, 403 insertions(+) create mode 100644 drivers/irqchip/irq-renesas-rzg2l.c diff --git a/drivers/irqchip/Kconfig b/drivers/irqchip/Kconfig index 63c65deb6737..3225d6aa2b33 100644 --- a/drivers/irqchip/Kconfig +++ b/drivers/irqchip/Kconfig @@ -245,6 +245,14 @@ config RENESAS_RZA1_IRQC Enable support for the Renesas RZ/A1 Interrupt Controller, to use up to 8 external interrupts with configurable sense select. +config RENESAS_RZG2L_IRQC + bool "Renesas RZ/G2L (and alike SoC) IRQC support" if COMPILE_TEST + select GENERIC_IRQ_CHIP + select IRQ_DOMAIN_HIERARCHY + help + Enable support for the Renesas RZ/G2L (and alike SoC) Interrupt Controller + for external devices. + config SL28CPLD_INTC bool "Kontron sl28cpld IRQ controller" depends on MFD_SL28CPLD=y || COMPILE_TEST diff --git a/drivers/irqchip/Makefile b/drivers/irqchip/Makefile index 94c2885882ee..bbf67fbf4edc 100644 --- a/drivers/irqchip/Makefile +++ b/drivers/irqchip/Makefile @@ -51,6 +51,7 @@ obj-$(CONFIG_RDA_INTC) += irq-rda-intc.o obj-$(CONFIG_RENESAS_INTC_IRQPIN) += irq-renesas-intc-irqpin.o obj-$(CONFIG_RENESAS_IRQC) += irq-renesas-irqc.o obj-$(CONFIG_RENESAS_RZA1_IRQC) += irq-renesas-rza1.o +obj-$(CONFIG_RENESAS_RZG2L_IRQC) += irq-renesas-rzg2l.o obj-$(CONFIG_VERSATILE_FPGA_IRQ) += irq-versatile-fpga.o obj-$(CONFIG_ARCH_NSPIRE) += irq-zevio.o obj-$(CONFIG_ARCH_VT8500) += irq-vt8500.o diff --git a/drivers/irqchip/irq-renesas-rzg2l.c b/drivers/irqchip/irq-renesas-rzg2l.c new file mode 100644 index 000000000000..cf99cd6b41c4 --- /dev/null +++ b/drivers/irqchip/irq-renesas-rzg2l.c @@ -0,0 +1,394 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Renesas RZ/G2L IRQC Driver + * + * Copyright (C) 2022 Renesas Electronics Corporation. + * + * Author: Lad Prabhakar + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#define IRQC_IRQ_START 1 +#define IRQC_IRQ_COUNT 8 +#define IRQC_TINT_START (IRQC_IRQ_START + IRQC_IRQ_COUNT) +#define IRQC_TINT_COUNT 32 +#define IRQC_NUM_IRQ (IRQC_TINT_START + IRQC_TINT_COUNT) + +#define ISCR 0x10 +#define IITSR 0x14 +#define TSCR 0x20 +#define TITSR0 0x24 +#define TITSR1 0x28 +#define TITSR0_MAX_INT 16 +#define TITSEL_WIDTH 0x2 +#define TSSR(n) (0x30 + ((n) * 4)) +#define TIEN BIT(7) +#define TSSEL_SHIFT(n) (8 * (n)) +#define TSSEL_MASK GENMASK(7, 0) +#define IRQ_MASK 0x3 + +#define TSSR_OFFSET(n) ((n) % 4) +#define TSSR_INDEX(n) ((n) / 4) + +#define TITSR_TITSEL_EDGE_RISING 0 +#define TITSR_TITSEL_EDGE_FALLING 1 +#define TITSR_TITSEL_LEVEL_HIGH 2 +#define TITSR_TITSEL_LEVEL_LOW 3 + +#define IITSR_IITSEL(n, sense) ((sense) << ((n) * 2)) +#define IITSR_IITSEL_LEVEL_LOW 0 +#define IITSR_IITSEL_EDGE_FALLING 1 +#define IITSR_IITSEL_EDGE_RISING 2 +#define IITSR_IITSEL_EDGE_BOTH 3 +#define IITSR_IITSEL_MASK(n) IITSR_IITSEL((n), 3) + +#define TINT_EXTRACT_HWIRQ(x) FIELD_GET(GENMASK(15, 0), (x)) +#define TINT_EXTRACT_GPIOINT(x) FIELD_GET(GENMASK(31, 16), (x)) + +struct rzg2l_irqc_priv { + void __iomem *base; + struct irq_fwspec fwspec[IRQC_NUM_IRQ]; + raw_spinlock_t lock; +}; + +static struct rzg2l_irqc_priv *irq_data_to_priv(struct irq_data *data) +{ + return data->domain->host_data; +} + +static void rzg2l_irq_eoi(struct irq_data *d) +{ + unsigned int hw_irq = irqd_to_hwirq(d) - IRQC_IRQ_START; + struct rzg2l_irqc_priv *priv = irq_data_to_priv(d); + u32 bit = BIT(hw_irq); + u32 reg; + + reg = readl_relaxed(priv->base + ISCR); + if (reg & bit) + writel_relaxed(reg & ~bit, priv->base + ISCR); +} + +static void rzg2l_tint_eoi(struct irq_data *d) +{ + unsigned int hw_irq = irqd_to_hwirq(d) - IRQC_TINT_START; + struct rzg2l_irqc_priv *priv = irq_data_to_priv(d); + u32 bit = BIT(hw_irq); + u32 reg; + + reg = readl_relaxed(priv->base + TSCR); + if (reg & bit) + writel_relaxed(reg & ~bit, priv->base + TSCR); +} + +static void rzg2l_irqc_eoi(struct irq_data *d) +{ + struct rzg2l_irqc_priv *priv = irq_data_to_priv(d); + unsigned int hw_irq = irqd_to_hwirq(d); + + raw_spin_lock(&priv->lock); + if (hw_irq >= IRQC_IRQ_START && hw_irq <= IRQC_IRQ_COUNT) + rzg2l_irq_eoi(d); + else if (hw_irq >= IRQC_TINT_START && hw_irq < IRQC_NUM_IRQ) + rzg2l_tint_eoi(d); + raw_spin_unlock(&priv->lock); + irq_chip_eoi_parent(d); +} + +static void rzg2l_irqc_irq_disable(struct irq_data *d) +{ + unsigned int hw_irq = irqd_to_hwirq(d); + + if (hw_irq >= IRQC_TINT_START && hw_irq < IRQC_NUM_IRQ) { + struct rzg2l_irqc_priv *priv = irq_data_to_priv(d); + u32 offset = hw_irq - IRQC_TINT_START; + u32 tssr_offset = TSSR_OFFSET(offset); + u8 tssr_index = TSSR_INDEX(offset); + u32 reg; + + raw_spin_lock(&priv->lock); + reg = readl_relaxed(priv->base + TSSR(tssr_index)); + reg &= ~(TSSEL_MASK << tssr_offset); + writel_relaxed(reg, priv->base + TSSR(tssr_index)); + raw_spin_unlock(&priv->lock); + } + irq_chip_disable_parent(d); +} + +static void rzg2l_irqc_irq_enable(struct irq_data *d) +{ + unsigned int hw_irq = irqd_to_hwirq(d); + + if (hw_irq >= IRQC_TINT_START && hw_irq < IRQC_NUM_IRQ) { + struct rzg2l_irqc_priv *priv = irq_data_to_priv(d); + unsigned long tint = (uintptr_t)d->chip_data; + u32 offset = hw_irq - IRQC_TINT_START; + u32 tssr_offset = TSSR_OFFSET(offset); + u8 tssr_index = TSSR_INDEX(offset); + u32 reg; + + raw_spin_lock(&priv->lock); + reg = readl_relaxed(priv->base + TSSR(tssr_index)); + reg |= (TIEN | tint) << TSSEL_SHIFT(tssr_offset); + writel_relaxed(reg, priv->base + TSSR(tssr_index)); + raw_spin_unlock(&priv->lock); + } + irq_chip_enable_parent(d); +} + +static int rzg2l_irq_set_type(struct irq_data *d, unsigned int type) +{ + unsigned int hw_irq = irqd_to_hwirq(d) - IRQC_IRQ_START; + struct rzg2l_irqc_priv *priv = irq_data_to_priv(d); + u16 sense, tmp; + + switch (type & IRQ_TYPE_SENSE_MASK) { + case IRQ_TYPE_LEVEL_LOW: + sense = IITSR_IITSEL_LEVEL_LOW; + break; + + case IRQ_TYPE_EDGE_FALLING: + sense = IITSR_IITSEL_EDGE_FALLING; + break; + + case IRQ_TYPE_EDGE_RISING: + sense = IITSR_IITSEL_EDGE_RISING; + break; + + case IRQ_TYPE_EDGE_BOTH: + sense = IITSR_IITSEL_EDGE_BOTH; + break; + + default: + return -EINVAL; + } + + raw_spin_lock(&priv->lock); + tmp = readl_relaxed(priv->base + IITSR); + tmp &= ~IITSR_IITSEL_MASK(hw_irq); + tmp |= IITSR_IITSEL(hw_irq, sense); + writel_relaxed(tmp, priv->base + IITSR); + raw_spin_unlock(&priv->lock); + + return 0; +} + +static int rzg2l_tint_set_edge(struct irq_data *d, unsigned int type) +{ + struct rzg2l_irqc_priv *priv = irq_data_to_priv(d); + unsigned int hwirq = irqd_to_hwirq(d); + u32 titseln = hwirq - IRQC_TINT_START; + u32 offset; + u8 sense; + u32 reg; + + switch (type & IRQ_TYPE_SENSE_MASK) { + case IRQ_TYPE_EDGE_RISING: + sense = TITSR_TITSEL_EDGE_RISING; + break; + + case IRQ_TYPE_EDGE_FALLING: + sense = TITSR_TITSEL_EDGE_FALLING; + break; + + default: + return -EINVAL; + } + + offset = TITSR0; + if (titseln >= TITSR0_MAX_INT) { + titseln -= TITSR0_MAX_INT; + offset = TITSR1; + } + + raw_spin_lock(&priv->lock); + reg = readl_relaxed(priv->base + offset); + reg &= ~(IRQ_MASK << (titseln * TITSEL_WIDTH)); + reg |= sense << (titseln * TITSEL_WIDTH); + writel_relaxed(reg, priv->base + offset); + raw_spin_unlock(&priv->lock); + + return 0; +} + +static int rzg2l_irqc_set_type(struct irq_data *d, unsigned int type) +{ + unsigned int hw_irq = irqd_to_hwirq(d); + int ret = -EINVAL; + + if (hw_irq >= IRQC_IRQ_START && hw_irq <= IRQC_IRQ_COUNT) + ret = rzg2l_irq_set_type(d, type); + else if (hw_irq >= IRQC_TINT_START && hw_irq < IRQC_NUM_IRQ) + ret = rzg2l_tint_set_edge(d, type); + if (ret) + return ret; + + return irq_chip_set_type_parent(d, IRQ_TYPE_LEVEL_HIGH); +} + +static struct irq_chip irqc_chip = { + .name = "rzg2l-irqc", + .irq_eoi = rzg2l_irqc_eoi, + .irq_mask = irq_chip_mask_parent, + .irq_unmask = irq_chip_unmask_parent, + .irq_disable = rzg2l_irqc_irq_disable, + .irq_enable = rzg2l_irqc_irq_enable, + .irq_get_irqchip_state = irq_chip_get_parent_state, + .irq_set_irqchip_state = irq_chip_set_parent_state, + .irq_retrigger = irq_chip_retrigger_hierarchy, + .irq_set_type = rzg2l_irqc_set_type, + .flags = IRQCHIP_MASK_ON_SUSPEND | + IRQCHIP_SET_TYPE_MASKED | + IRQCHIP_SKIP_SET_WAKE, +}; + +static int rzg2l_irqc_alloc(struct irq_domain *domain, unsigned int virq, + unsigned int nr_irqs, void *arg) +{ + struct rzg2l_irqc_priv *priv = domain->host_data; + unsigned long tint = 0; + irq_hw_number_t hwirq; + unsigned int type; + int ret; + + ret = irq_domain_translate_twocell(domain, arg, &hwirq, &type); + if (ret) + return ret; + + /* + * For TINT interrupts ie where pinctrl driver is child of irqc domain + * the hwirq and TINT are encoded in fwspec->param[0]. + * hwirq for TINT range from 9-40, hwirq is embedded 0-15 bits and TINT + * from 16-31 bits. TINT from the pinctrl driver needs to be programmed + * in IRQC registers to enable a given gpio pin as interrupt. + */ + if (hwirq > IRQC_IRQ_COUNT) { + tint = TINT_EXTRACT_GPIOINT(hwirq); + hwirq = TINT_EXTRACT_HWIRQ(hwirq); + + if (hwirq < IRQC_TINT_START) + return -EINVAL; + } + + if (hwirq > (IRQC_NUM_IRQ - 1)) + return -EINVAL; + + ret = irq_domain_set_hwirq_and_chip(domain, virq, hwirq, &irqc_chip, + (void *)(uintptr_t)tint); + if (ret) + return ret; + + return irq_domain_alloc_irqs_parent(domain, virq, nr_irqs, &priv->fwspec[hwirq]); +} + +static const struct irq_domain_ops rzg2l_irqc_domain_ops = { + .alloc = rzg2l_irqc_alloc, + .free = irq_domain_free_irqs_common, + .translate = irq_domain_translate_twocell, +}; + +static int rzg2l_irqc_parse_interrupts(struct rzg2l_irqc_priv *priv, + struct device_node *np) +{ + struct of_phandle_args map; + unsigned int i; + int ret; + + for (i = 0; i < IRQC_NUM_IRQ; i++) { + ret = of_irq_parse_one(np, i, &map); + if (ret) + return ret; + of_phandle_args_to_fwspec(np, map.args, map.args_count, + &priv->fwspec[i]); + } + + return 0; +} + +static int rzg2l_irqc_init(struct device_node *node, struct device_node *parent) +{ + struct irq_domain *irq_domain, *parent_domain; + struct platform_device *pdev; + struct reset_control *resetn; + struct rzg2l_irqc_priv *priv; + int ret; + + pdev = of_find_device_by_node(node); + if (!pdev) + return -ENODEV; + + parent_domain = irq_find_host(parent); + if (!parent_domain) { + dev_err(&pdev->dev, "cannot find parent domain\n"); + return -ENODEV; + } + + priv = devm_kzalloc(&pdev->dev, sizeof(*priv), GFP_KERNEL); + if (!priv) + return -ENOMEM; + + priv->base = devm_of_iomap(&pdev->dev, pdev->dev.of_node, 0, NULL); + if (IS_ERR(priv->base)) + return PTR_ERR(priv->base); + + ret = rzg2l_irqc_parse_interrupts(priv, node); + if (ret) { + dev_err(&pdev->dev, "cannot parse interrupts: %d\n", ret); + return ret; + } + + resetn = devm_reset_control_get_exclusive(&pdev->dev, NULL); + if (IS_ERR(resetn)) + return PTR_ERR(resetn); + + ret = reset_control_deassert(resetn); + if (ret) { + dev_err(&pdev->dev, "failed to deassert resetn pin, %d\n", ret); + return ret; + } + + pm_runtime_enable(&pdev->dev); + ret = pm_runtime_resume_and_get(&pdev->dev); + if (ret < 0) { + dev_err(&pdev->dev, "pm_runtime_resume_and_get failed: %d\n", ret); + goto pm_disable; + } + + raw_spin_lock_init(&priv->lock); + + irq_domain = irq_domain_add_hierarchy(parent_domain, 0, IRQC_NUM_IRQ, + node, &rzg2l_irqc_domain_ops, + priv); + if (!irq_domain) { + dev_err(&pdev->dev, "failed to add irq domain\n"); + ret = -ENOMEM; + goto pm_put; + } + + return 0; + +pm_put: + pm_runtime_put(&pdev->dev); +pm_disable: + pm_runtime_disable(&pdev->dev); + reset_control_assert(resetn); + return ret; +} + +IRQCHIP_PLATFORM_DRIVER_BEGIN(rzg2l_irqc) +IRQCHIP_MATCH("renesas,rzg2l-irqc", rzg2l_irqc_init) +IRQCHIP_PLATFORM_DRIVER_END(rzg2l_irqc) +MODULE_AUTHOR("Lad Prabhakar "); +MODULE_DESCRIPTION("Renesas RZ/G2L IRQC Driver"); +MODULE_LICENSE("GPL"); From patchwork Wed Mar 27 08:17:32 2024 Content-Type: text/plain; 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([82.78.167.144]) by smtp.gmail.com with ESMTPSA id c9-20020a7bc2a9000000b0041493615585sm1353783wmk.39.2024.03.27.01.18.11 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 27 Mar 2024 01:18:11 -0700 (PDT) From: Claudiu X-Google-Original-From: Claudiu To: nobuhiro1.iwamatsu@toshiba.co.jp, pavel@denx.de Cc: cip-dev@lists.cip-project.org, biju.das.jz@bp.renesas.com, prabhakar.mahadev-lad.rj@bp.renesas.com, claudiu.beznea@tuxon.dev Subject: [PATCH 5.10.y-cip 12/36] irqchip: remove MODULE_LICENSE in non-modules Date: Wed, 27 Mar 2024 10:17:32 +0200 Message-Id: <20240327081756.2228036-13-claudiu.beznea.uj@bp.renesas.com> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20240327081756.2228036-1-claudiu.beznea.uj@bp.renesas.com> References: <20240327081756.2228036-1-claudiu.beznea.uj@bp.renesas.com> MIME-Version: 1.0 List-Id: X-Webhook-Received: from li982-79.members.linode.com [45.33.32.79] by aws-us-west-2-korg-lkml-1.web.codeaurora.org with HTTPS for ; Wed, 27 Mar 2024 10:37:06 -0000 X-Groupsio-URL: https://lists.cip-project.org/g/cip-dev/message/15429 From: Nick Alcock commit e3f1f02548adbf973af29c6ee6304a45121bff03 upstream. Since commit 8b41fc4454e ("kbuild: create modules.builtin without Makefile.modbuiltin or tristate.conf"), MODULE_LICENSE declarations are used to identify modules. As a consequence, uses of the macro in non-modules will cause modprobe to misidentify their containing object file as a module when it is not (false positives), and modprobe might succeed rather than failing with a suitable error message. So remove it in the files in this commit, none of which can be built as modules. Signed-off-by: Nick Alcock Suggested-by: Luis Chamberlain Cc: Luis Chamberlain Cc: linux-modules@vger.kernel.org Cc: linux-kernel@vger.kernel.org Cc: Hitomi Hasegawa Cc: Thomas Gleixner Cc: Marc Zyngier Cc: Philipp Zabel Signed-off-by: Luis Chamberlain Signed-off-by: Claudiu Beznea --- drivers/irqchip/irq-renesas-rzg2l.c | 1 - 1 file changed, 1 deletion(-) diff --git a/drivers/irqchip/irq-renesas-rzg2l.c b/drivers/irqchip/irq-renesas-rzg2l.c index cf99cd6b41c4..17c9f8fd41a8 100644 --- a/drivers/irqchip/irq-renesas-rzg2l.c +++ b/drivers/irqchip/irq-renesas-rzg2l.c @@ -391,4 +391,3 @@ IRQCHIP_MATCH("renesas,rzg2l-irqc", rzg2l_irqc_init) IRQCHIP_PLATFORM_DRIVER_END(rzg2l_irqc) MODULE_AUTHOR("Lad Prabhakar "); MODULE_DESCRIPTION("Renesas RZ/G2L IRQC Driver"); -MODULE_LICENSE("GPL"); From patchwork Wed Mar 27 08:17:33 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Claudiu Beznea X-Patchwork-Id: 13606202 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from aws-us-west-2-korg-lkml-1.web.codeaurora.org (localhost.localdomain [127.0.0.1]) by smtp.lore.kernel.org (Postfix) with ESMTP id 94981CD12B5 for ; Wed, 27 Mar 2024 10:37:06 +0000 (UTC) Received: from mail-wm1-f48.google.com (mail-wm1-f48.google.com [209.85.128.48]) by mx.groups.io with SMTP id smtpd.web11.32294.1711527494946785717 for ; Wed, 27 Mar 2024 01:18:15 -0700 Authentication-Results: mx.groups.io; dkim=pass header.i=@tuxon.dev header.s=google header.b=agODiMBW; spf=pass (domain: tuxon.dev, ip: 209.85.128.48, mailfrom: claudiu.beznea@tuxon.dev) Received: by mail-wm1-f48.google.com with SMTP id 5b1f17b1804b1-414866f92beso20678995e9.3 for ; Wed, 27 Mar 2024 01:18:14 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=tuxon.dev; s=google; t=1711527493; x=1712132293; darn=lists.cip-project.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=8TrED0DZ9NtpPniaJV6I4bOFHL4c2f3zdXrlJxAizjg=; b=agODiMBW0iSI/4tjZr0vPoYcVZiNsJUpoy8qeXreyups0mIYBHCDVjEf0x34XAbjis fLjJfLIBi2lyuGRMCxUkB6q0Y57opIqnTlN7PUGoaZDNEgCBbCTkNWTwWqeRYQG4i00j MNZJhWFxYmlM1dpYGIJNVVpasNpLZa9InKT3ULzZKcB43rEgzEF9tY2l+chQFTDQh35c EU/isDPqxkrujUjc58KwtP5jg5NwFotF2kT9uehrtGJu7/9z2V9puj+8reJi0jetoM23 9KnAYaAuKuc9rhcxs7gx1SdnKbW8iRRa6/GSxBnsd1swrRhIf0a+2eblJoeJPo0dJR3L DIZA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1711527493; x=1712132293; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=8TrED0DZ9NtpPniaJV6I4bOFHL4c2f3zdXrlJxAizjg=; b=EWXqs8ZUonWNaYS6SDa+1/cpspDFMt8f/dp9LB17T/in4PRURh08OGc4HqoJR44tcX C/OjB0q0vXU7XeFFgQQs1CSXLlTwyKshZ5kgkUjCPMYEgkpra1f6osfJzm/ZcH/86x9C yriVjHyOXUvg1sWkz6OwrT7oGjn126alezv9jcGsWgmroX3W+qy6fpyUwYiQPUgMvgPu Q4A+DQKJNxsDNXzUoeL13gWBZo0usZXktxMqVz6nPzZWOCh3fkviNbsTVEC+NrM+P1Bo LiAKbcLFpXPb/aPIeIBvVG8QdMF+HqEYTrD7RMQyEO14Z2ZcUqz/UWgxOXdaVX4TYM5N EXSg== X-Gm-Message-State: AOJu0YxSY8Em1A9nCQ2yLEs0yimCq3v2DJBR2Djalq44xpqC3pDQUBzC +RGAwWHrjyWagrIlFkki7Q33L1gFF99mIp0UAP40G2jiU14ZWdvjBbA+T5Xg8DtHh5WszjnXhWs d X-Google-Smtp-Source: AGHT+IGINvshjG5YIehnXh5Ub5dCqTmCsrn7dTfJM8B6nj1gSU11TfL5y8IGIC96AaYmaFtHd+TzWg== X-Received: by 2002:a05:600c:b59:b0:414:8be4:7f24 with SMTP id k25-20020a05600c0b5900b004148be47f24mr1422017wmr.13.1711527493359; Wed, 27 Mar 2024 01:18:13 -0700 (PDT) Received: from claudiu-X670E-Pro-RS.. ([82.78.167.144]) by smtp.gmail.com with ESMTPSA id c9-20020a7bc2a9000000b0041493615585sm1353783wmk.39.2024.03.27.01.18.12 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 27 Mar 2024 01:18:13 -0700 (PDT) From: Claudiu X-Google-Original-From: Claudiu To: nobuhiro1.iwamatsu@toshiba.co.jp, pavel@denx.de Cc: cip-dev@lists.cip-project.org, biju.das.jz@bp.renesas.com, prabhakar.mahadev-lad.rj@bp.renesas.com, claudiu.beznea@tuxon.dev Subject: [PATCH 5.10.y-cip 13/36] irqchip: renesas-rzg2l: Fix logic to clear TINT interrupt source Date: Wed, 27 Mar 2024 10:17:33 +0200 Message-Id: <20240327081756.2228036-14-claudiu.beznea.uj@bp.renesas.com> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20240327081756.2228036-1-claudiu.beznea.uj@bp.renesas.com> References: <20240327081756.2228036-1-claudiu.beznea.uj@bp.renesas.com> MIME-Version: 1.0 List-Id: X-Webhook-Received: from li982-79.members.linode.com [45.33.32.79] by aws-us-west-2-korg-lkml-1.web.codeaurora.org with HTTPS for ; Wed, 27 Mar 2024 10:37:06 -0000 X-Groupsio-URL: https://lists.cip-project.org/g/cip-dev/message/15430 From: Biju Das commit 9b8df572ba3f4e544366196820a719a40774433e upstream. The logic to clear the TINT interrupt source in rzg2l_irqc_irq_disable() is wrong as the mask is correct only for LSB on the TSSR register. This issue is found when testing with two TINT interrupt sources. So fix the logic for all TINTs by using the macro TSSEL_SHIFT() to multiply tssr_offset with 8. Fixes: 3fed09559cd8 ("irqchip: Add RZ/G2L IA55 Interrupt Controller driver") Signed-off-by: Biju Das Tested-by: Claudiu Beznea Reviewed-by: Geert Uytterhoeven Reviewed-by: Claudiu Beznea Signed-off-by: Marc Zyngier Link: https://lore.kernel.org/r/20230918122411.237635-2-biju.das.jz@bp.renesas.com Signed-off-by: Claudiu Beznea --- drivers/irqchip/irq-renesas-rzg2l.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/irqchip/irq-renesas-rzg2l.c b/drivers/irqchip/irq-renesas-rzg2l.c index 17c9f8fd41a8..24701d38c022 100644 --- a/drivers/irqchip/irq-renesas-rzg2l.c +++ b/drivers/irqchip/irq-renesas-rzg2l.c @@ -119,7 +119,7 @@ static void rzg2l_irqc_irq_disable(struct irq_data *d) raw_spin_lock(&priv->lock); reg = readl_relaxed(priv->base + TSSR(tssr_index)); - reg &= ~(TSSEL_MASK << tssr_offset); + reg &= ~(TSSEL_MASK << TSSEL_SHIFT(tssr_offset)); writel_relaxed(reg, priv->base + TSSR(tssr_index)); raw_spin_unlock(&priv->lock); } From patchwork Wed Mar 27 08:17:34 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Claudiu Beznea X-Patchwork-Id: 13606186 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from aws-us-west-2-korg-lkml-1.web.codeaurora.org (localhost.localdomain [127.0.0.1]) by smtp.lore.kernel.org (Postfix) with ESMTP id 62309CD12AA for ; Wed, 27 Mar 2024 10:37:06 +0000 (UTC) Received: from mail-wm1-f41.google.com (mail-wm1-f41.google.com [209.85.128.41]) by mx.groups.io with SMTP id smtpd.web10.32437.1711527495978523115 for ; Wed, 27 Mar 2024 01:18:16 -0700 Authentication-Results: mx.groups.io; dkim=pass header.i=@tuxon.dev header.s=google header.b=Gk3apxAX; spf=pass (domain: tuxon.dev, ip: 209.85.128.41, mailfrom: claudiu.beznea@tuxon.dev) Received: by mail-wm1-f41.google.com with SMTP id 5b1f17b1804b1-414936696b8so2566105e9.0 for ; Wed, 27 Mar 2024 01:18:15 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=tuxon.dev; s=google; t=1711527494; x=1712132294; darn=lists.cip-project.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=zTFTYyPxK41THmzzwQ+3qPSzWk1QcNohDxoAJus3/kQ=; b=Gk3apxAXb1SgLVOrFlWMPxAKMpGL4/uwh31vgTk/4Mg4tYwAVmsswgnxnq4WGUYM8v A5pcA6qs76zDviBMgpZWkF8DXy+q9q+AdfEbeYa5G+65TsGDCEV0A93iY7zD7zcLmeJi 2Zmcu3entJSXcLflG+EdSkpnJvkiFquW8RWf51W3SMisu28X3zmV7NU2wzyAUcW40+ZK SSobvkF4G9A3tsrOOCsD1ncbdgdug6xypXWTL9eJf3zi0hLw1tYjhImqhExd7deiayOH m5MIMnGK7I13OFGF3R9YMCZge/+JlM8uWiA95qfbgvoT9DRxL+1kyyOOu26vuoG3dfSA TyHg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1711527494; x=1712132294; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=zTFTYyPxK41THmzzwQ+3qPSzWk1QcNohDxoAJus3/kQ=; b=Z6gpnsTJlzCWnLJi7S0RaFwaD7y5FJi0bUv79zjamABmiuWyKXcKZWFzqo10B8RkvM NG2uCOnXZkH78FMaDKA/ya3DNzT/sPw+rM/4v41gN8/AR+HsjpHV0mHxZrwp5yrDumyg 6sz81zVtmpMEiT2tqpGwia414VljP6qj37BzpXNrXA09L7BETmgjrVoVP/JyVkizC+Wg Nn8AaFkqttuGueeS/c7ddlsMQCTKIN6la5honOcsAcX3+SXzjK/zjZkQXwxYQgWDTunY +IRdUsjdjyL6St0joNDubdEYux1/RPldZV+H3VFwZxEqicivlJ2SXC/hqrNhWRB3jEWP euFg== X-Gm-Message-State: AOJu0Yx3bxNL9hRVHXctFFboB4BpqLRdTAnlILcFqHMxGRAW9+wGsKSB amkzqUkq9ctrWGwopXXH2YxLOKjb8MDZSq9QU/S8ACn3Z32brPzm88O8P/EyGaZhuDgGyFz91uv l X-Google-Smtp-Source: AGHT+IGFs9oP1Ik3jkAROJnKk7mX1V9vSavVTxF9sl5Pcy78Q/eMedlzrRZII9T7EZEdIqK+X8EQcw== X-Received: by 2002:a05:600c:3d90:b0:414:90ea:34ad with SMTP id bi16-20020a05600c3d9000b0041490ea34admr2417652wmb.6.1711527494503; Wed, 27 Mar 2024 01:18:14 -0700 (PDT) Received: from claudiu-X670E-Pro-RS.. ([82.78.167.144]) by smtp.gmail.com with ESMTPSA id c9-20020a7bc2a9000000b0041493615585sm1353783wmk.39.2024.03.27.01.18.13 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 27 Mar 2024 01:18:14 -0700 (PDT) From: Claudiu X-Google-Original-From: Claudiu To: nobuhiro1.iwamatsu@toshiba.co.jp, pavel@denx.de Cc: cip-dev@lists.cip-project.org, biju.das.jz@bp.renesas.com, prabhakar.mahadev-lad.rj@bp.renesas.com, claudiu.beznea@tuxon.dev Subject: [PATCH 5.10.y-cip 14/36] irqchip/renesas-rzg2l: Convert to irq_data_get_irq_chip_data() Date: Wed, 27 Mar 2024 10:17:34 +0200 Message-Id: <20240327081756.2228036-15-claudiu.beznea.uj@bp.renesas.com> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20240327081756.2228036-1-claudiu.beznea.uj@bp.renesas.com> References: <20240327081756.2228036-1-claudiu.beznea.uj@bp.renesas.com> MIME-Version: 1.0 List-Id: X-Webhook-Received: from li982-79.members.linode.com [45.33.32.79] by aws-us-west-2-korg-lkml-1.web.codeaurora.org with HTTPS for ; Wed, 27 Mar 2024 10:37:06 -0000 X-Groupsio-URL: https://lists.cip-project.org/g/cip-dev/message/15431 From: Geert Uytterhoeven commit 8a4f44f3e9b05c38606b2ae02f933d6b64a340dd upstream. Use the existing irq_data_get_irq_chip_data() helper instead of open-coding the same operation. Signed-off-by: Geert Uytterhoeven Reviewed-by: Lad Prabhakar Signed-off-by: Marc Zyngier Link: https://lore.kernel.org/r/8e47cc6400e5a82c854c855948d2665a3a3197e3.1695819391.git.geert+renesas@glider.be Signed-off-by: Claudiu Beznea --- drivers/irqchip/irq-renesas-rzg2l.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/irqchip/irq-renesas-rzg2l.c b/drivers/irqchip/irq-renesas-rzg2l.c index 24701d38c022..67856b865e98 100644 --- a/drivers/irqchip/irq-renesas-rzg2l.c +++ b/drivers/irqchip/irq-renesas-rzg2l.c @@ -131,8 +131,8 @@ static void rzg2l_irqc_irq_enable(struct irq_data *d) unsigned int hw_irq = irqd_to_hwirq(d); if (hw_irq >= IRQC_TINT_START && hw_irq < IRQC_NUM_IRQ) { + unsigned long tint = (uintptr_t)irq_data_get_irq_chip_data(d); struct rzg2l_irqc_priv *priv = irq_data_to_priv(d); - unsigned long tint = (uintptr_t)d->chip_data; u32 offset = hw_irq - IRQC_TINT_START; u32 tssr_offset = TSSR_OFFSET(offset); u8 tssr_index = TSSR_INDEX(offset); From patchwork Wed Mar 27 08:17:35 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Claudiu Beznea X-Patchwork-Id: 13606154 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from aws-us-west-2-korg-lkml-1.web.codeaurora.org (localhost.localdomain [127.0.0.1]) by smtp.lore.kernel.org (Postfix) with ESMTP id B7B07CD1283 for ; Wed, 27 Mar 2024 10:37:05 +0000 (UTC) Received: from mail-wm1-f47.google.com (mail-wm1-f47.google.com [209.85.128.47]) by mx.groups.io with SMTP id smtpd.web10.32438.1711527497181731267 for ; Wed, 27 Mar 2024 01:18:17 -0700 Authentication-Results: mx.groups.io; dkim=pass header.i=@tuxon.dev header.s=google header.b=LKxWpGfc; spf=pass (domain: tuxon.dev, ip: 209.85.128.47, mailfrom: claudiu.beznea@tuxon.dev) Received: by mail-wm1-f47.google.com with SMTP id 5b1f17b1804b1-414946b418dso2237885e9.0 for ; Wed, 27 Mar 2024 01:18:16 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=tuxon.dev; s=google; t=1711527495; x=1712132295; darn=lists.cip-project.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=Naezq1Kf17hunjBvl5IksexI6PZLahnE0c3B5nFYe8o=; b=LKxWpGfcVVj7MqLAVh270fbkvBv+AFcT/LLz5y7vmlxqaUW+bc0jY3mZrpV3zLzWdl QQM5PxKUibycgC0Zfo2ilvzaKAPhyzUzCfzJJ34/g7rWW66zdyS6G07Tm57Gqk7sneqG k6nM4SJlHnEMN2/s3c7eIAWL7BZ3R4r8d/ktwisKC3sXnN7O9daofHBUXeztUqcUop5s rIIp0dac0i0eOjlb5qVzU9gTr20pg0lNRhOAM9345lQdjpOHXCAaE2t21xn4tFZWVuOo EyNbxljnOeHyV+PvUDm9l94lte2oVlwUwZEbv9ArrjmQ1o6vf+UBc/3FB8O9edC4DJkM M1nQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1711527495; x=1712132295; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=Naezq1Kf17hunjBvl5IksexI6PZLahnE0c3B5nFYe8o=; b=Hl6HYiziZH3/1SRaOzeTFkUf9+x4EeT5ENNCnixbW9k8VlHtel41j229DBy1mI8w1f wDI7E1srW2FGPpQn7r+97wAnoqWxevVZrsqtszW1GTj66hiuJIdtIulCsVGelLpJiBKo 3pXKenMwZ86K/WH5qODlkRdTpDx1nKfsOV2qEHJCsPhNyOiW6bHa91pEcs6p9ZxA1XzY gGbHuxLnZ5VerCxFB2euZYnJel7BqrvgkgkNOWCH28+Ke0DxK9aUbxlgBQI0xSWJ+HlY oLm4vJo3xxEO5Cmm8y5lR8f0koYscbU4fEII0yx539WRh8XlZ2L2gax5pO2KOuRDWS/R VZjg== X-Gm-Message-State: AOJu0YwbtXPv7f24XgyvF6Si2Tdnv1H/FVdoS5CIhrrwmkvXbfnSCPMv 6/nvC2FLt9lE8uQlpm/Yb34UKGFqeLq9++2NsjLB8Rm0kgBkA64ADKzZgwtKgME= X-Google-Smtp-Source: AGHT+IH5AIot9NiGEBEM8uOoiiAJlhDTkDyjNfjqBxLjWx20hDeO3bkipA44zWGwLkbyZgZhAGhKgg== X-Received: by 2002:a05:600c:4fd6:b0:414:82a8:24c with SMTP id o22-20020a05600c4fd600b0041482a8024cmr2560966wmq.29.1711527495683; Wed, 27 Mar 2024 01:18:15 -0700 (PDT) Received: from claudiu-X670E-Pro-RS.. ([82.78.167.144]) by smtp.gmail.com with ESMTPSA id c9-20020a7bc2a9000000b0041493615585sm1353783wmk.39.2024.03.27.01.18.14 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 27 Mar 2024 01:18:15 -0700 (PDT) From: Claudiu X-Google-Original-From: Claudiu To: nobuhiro1.iwamatsu@toshiba.co.jp, pavel@denx.de Cc: cip-dev@lists.cip-project.org, biju.das.jz@bp.renesas.com, prabhakar.mahadev-lad.rj@bp.renesas.com, claudiu.beznea@tuxon.dev Subject: [PATCH 5.10.y-cip 15/36] irqchip/renesas-rzg2l: Enhance driver to support interrupt affinity setting Date: Wed, 27 Mar 2024 10:17:35 +0200 Message-Id: <20240327081756.2228036-16-claudiu.beznea.uj@bp.renesas.com> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20240327081756.2228036-1-claudiu.beznea.uj@bp.renesas.com> References: <20240327081756.2228036-1-claudiu.beznea.uj@bp.renesas.com> MIME-Version: 1.0 List-Id: X-Webhook-Received: from li982-79.members.linode.com [45.33.32.79] by aws-us-west-2-korg-lkml-1.web.codeaurora.org with HTTPS for ; Wed, 27 Mar 2024 10:37:05 -0000 X-Groupsio-URL: https://lists.cip-project.org/g/cip-dev/message/15432 From: Lad Prabhakar commit f881feb180fd0563809b62faa3f7da234e81d42b upstream. Add support to set the affinity of the IRQC interrupt by implementing the irq_set_affinity callback via the parent interrupt chip. Signed-off-by: Lad Prabhakar Signed-off-by: Thomas Gleixner Link: https://lore.kernel.org/r/20231011195324.66807-1-prabhakar.mahadev-lad.rj@bp.renesas.com Signed-off-by: Claudiu Beznea --- drivers/irqchip/irq-renesas-rzg2l.c | 1 + 1 file changed, 1 insertion(+) diff --git a/drivers/irqchip/irq-renesas-rzg2l.c b/drivers/irqchip/irq-renesas-rzg2l.c index 67856b865e98..93c0d2707fcf 100644 --- a/drivers/irqchip/irq-renesas-rzg2l.c +++ b/drivers/irqchip/irq-renesas-rzg2l.c @@ -248,6 +248,7 @@ static struct irq_chip irqc_chip = { .irq_set_irqchip_state = irq_chip_set_parent_state, .irq_retrigger = irq_chip_retrigger_hierarchy, .irq_set_type = rzg2l_irqc_set_type, + .irq_set_affinity = irq_chip_set_affinity_parent, .flags = IRQCHIP_MASK_ON_SUSPEND | IRQCHIP_SET_TYPE_MASKED | IRQCHIP_SKIP_SET_WAKE, From patchwork Wed Mar 27 08:17:36 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Claudiu Beznea X-Patchwork-Id: 13606164 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from aws-us-west-2-korg-lkml-1.web.codeaurora.org (localhost.localdomain [127.0.0.1]) by smtp.lore.kernel.org (Postfix) with ESMTP id D9E3FCD128C for ; Wed, 27 Mar 2024 10:37:05 +0000 (UTC) Received: from mail-wm1-f52.google.com (mail-wm1-f52.google.com [209.85.128.52]) by mx.groups.io with SMTP id smtpd.web10.32439.1711527498380819569 for ; Wed, 27 Mar 2024 01:18:18 -0700 Authentication-Results: mx.groups.io; dkim=pass header.i=@tuxon.dev header.s=google header.b=JZvb+UGx; spf=pass (domain: tuxon.dev, ip: 209.85.128.52, mailfrom: claudiu.beznea@tuxon.dev) Received: by mail-wm1-f52.google.com with SMTP id 5b1f17b1804b1-414953ec671so1214775e9.1 for ; Wed, 27 Mar 2024 01:18:18 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=tuxon.dev; s=google; t=1711527497; x=1712132297; darn=lists.cip-project.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=mFOTOp0aKjgoYGUwcM6aU8kOf5TopuefAIC2xIUX4GE=; b=JZvb+UGx6XRn6aGPadBhhFkuzRs5ep2JDkprKpFQR9us23spQIFLSpa5XPr42hnS5L Cs4ktcWMbi66H6W1yvrb1S+A5wGxJ4oxY0LX1uUSjIqeRiz7VrOKmG+kLmp6SlbrIsdt AWvDv0RSAs4/6zeritRnbX96FSL5K4kjo+0Nxfs8qaGlcFDLp6YYhK4ciUL2XYTW8UX9 kfladCgp2y5k0vtZdotROuR429TZk/AOmzS4Tyh21DuPPCt+8+aIcg3QCQxK7lExLZBt td2t4zFz2QnBLsi5cRZIlUrWR2BYaMjATcw90fxz9iBRtU10qEo1TwLVRAyilGy9plW2 SU9w== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1711527497; x=1712132297; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=mFOTOp0aKjgoYGUwcM6aU8kOf5TopuefAIC2xIUX4GE=; b=eG0CB56TjboUQoPb+scpNT/ra17a5I4FGVL//k1W+oux/4dOWCbvs9lYTSTIahsIsv 9M1Dzpt0NjYN13A6Kx/bvSjWMlhZ+p4D26PTMXBFx33enpvIisFF9k0mtKEOtim3e8ae dHI0IzULjYHs8jUaOQ5J970RJYq1+vcimpz4oA5cdexMRjcK/2gCI4JgCwuuTXHzdwpW gfc6+gJKpzST3XoZuy5a5Xg/SwcsIDQ+RxFfGVC8T+0Q9GUjvQq+D1y2n2/X/gyrpwJM Usm0u/sJ2Vtbxl6Kht46LJtmb97Eom9SZrJmzfymady+qZE92l3sUoLLRWd3XpcBReDP kT6Q== X-Gm-Message-State: AOJu0YwjhuJ/JCWuSYgosx+AGoN5jzebVZiFqUipFariGoNhVJgB/2PC XNV6NuBEwfqAqcnyWlNLYJzQ8ET0FHxsxtxYdvg4CiUlCWPdwrJxG7OVf4I6mdc= X-Google-Smtp-Source: AGHT+IEwOAUP2AhDqBSKORV8JcRH1kjgL1ry0+ovmXGjWygrQmOui9JEguqYoVmvXucULlRfF4WTbQ== X-Received: by 2002:a05:600c:35cd:b0:414:9467:53c6 with SMTP id r13-20020a05600c35cd00b00414946753c6mr687481wmq.40.1711527496914; Wed, 27 Mar 2024 01:18:16 -0700 (PDT) Received: from claudiu-X670E-Pro-RS.. ([82.78.167.144]) by smtp.gmail.com with ESMTPSA id c9-20020a7bc2a9000000b0041493615585sm1353783wmk.39.2024.03.27.01.18.15 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 27 Mar 2024 01:18:16 -0700 (PDT) From: Claudiu X-Google-Original-From: Claudiu To: nobuhiro1.iwamatsu@toshiba.co.jp, pavel@denx.de Cc: cip-dev@lists.cip-project.org, biju.das.jz@bp.renesas.com, prabhakar.mahadev-lad.rj@bp.renesas.com, claudiu.beznea@tuxon.dev Subject: [PATCH 5.10.y-cip 16/36] irqchip/renesas-rzg2l: Use tabs instead of spaces Date: Wed, 27 Mar 2024 10:17:36 +0200 Message-Id: <20240327081756.2228036-17-claudiu.beznea.uj@bp.renesas.com> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20240327081756.2228036-1-claudiu.beznea.uj@bp.renesas.com> References: <20240327081756.2228036-1-claudiu.beznea.uj@bp.renesas.com> MIME-Version: 1.0 List-Id: X-Webhook-Received: from li982-79.members.linode.com [45.33.32.79] by aws-us-west-2-korg-lkml-1.web.codeaurora.org with HTTPS for ; Wed, 27 Mar 2024 10:37:05 -0000 X-Groupsio-URL: https://lists.cip-project.org/g/cip-dev/message/15433 From: Claudiu Beznea commit c90b5c4e6554c1194d5f7cfe13dfd710a7661cab upstream. Use tabs instead of spaces in definition of TINT_EXTRACT_HWIRQ() and TINT_EXTRACT_GPIOINT() macros to align with coding style requirements described in Documentation/process/coding-style.rst, "Indentation" chapter. Signed-off-by: Claudiu Beznea Signed-off-by: Thomas Gleixner Reviewed-by: Geert Uytterhoeven Link: https://lore.kernel.org/r/20231120111820.87398-3-claudiu.beznea.uj@bp.renesas.com Signed-off-by: Claudiu Beznea --- drivers/irqchip/irq-renesas-rzg2l.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/irqchip/irq-renesas-rzg2l.c b/drivers/irqchip/irq-renesas-rzg2l.c index 93c0d2707fcf..520200292eb9 100644 --- a/drivers/irqchip/irq-renesas-rzg2l.c +++ b/drivers/irqchip/irq-renesas-rzg2l.c @@ -54,8 +54,8 @@ #define IITSR_IITSEL_EDGE_BOTH 3 #define IITSR_IITSEL_MASK(n) IITSR_IITSEL((n), 3) -#define TINT_EXTRACT_HWIRQ(x) FIELD_GET(GENMASK(15, 0), (x)) -#define TINT_EXTRACT_GPIOINT(x) FIELD_GET(GENMASK(31, 16), (x)) +#define TINT_EXTRACT_HWIRQ(x) FIELD_GET(GENMASK(15, 0), (x)) +#define TINT_EXTRACT_GPIOINT(x) FIELD_GET(GENMASK(31, 16), (x)) struct rzg2l_irqc_priv { void __iomem *base; From patchwork Wed Mar 27 08:17:37 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Claudiu Beznea X-Patchwork-Id: 13606174 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from aws-us-west-2-korg-lkml-1.web.codeaurora.org (localhost.localdomain [127.0.0.1]) by smtp.lore.kernel.org (Postfix) with ESMTP id 0F523CD1287 for ; Wed, 27 Mar 2024 10:37:06 +0000 (UTC) Received: from mail-lj1-f171.google.com (mail-lj1-f171.google.com [209.85.208.171]) by mx.groups.io with SMTP id smtpd.web10.32440.1711527499915789669 for ; Wed, 27 Mar 2024 01:18:20 -0700 Authentication-Results: mx.groups.io; dkim=pass header.i=@tuxon.dev header.s=google header.b=RmEOyJuH; spf=pass (domain: tuxon.dev, ip: 209.85.208.171, mailfrom: claudiu.beznea@tuxon.dev) Received: by mail-lj1-f171.google.com with SMTP id 38308e7fff4ca-2d23114b19dso94460211fa.3 for ; Wed, 27 Mar 2024 01:18:19 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=tuxon.dev; s=google; t=1711527498; x=1712132298; darn=lists.cip-project.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=6ZL6C477gTW+NfISWalYHi/00eT8ywLVpfA/stvnenI=; b=RmEOyJuHFl3LGM/B3SpxO5nGHrvY81MKEQ8WMNxui65oy5gp0DY5u2qxp6MTeuNARP YBBBaUTMwUPK0GUip8noKfUk8q924dEB2omZkDzIEqWkBAlZnKczJ4hha9JbJsCFJ2Oo O3qsjbZtmI7FUsKuwtZpa1usCurZ9JIPUlu35BgucBX3uIFv3IzeR1JrbJMwAKX71ZkD oufFaI9tAijPu0Sp09HURUa4hQpUPLRuFW+XF6T6amEDFUnBvIo3RR6u58lr7vPUJWhB z97aw4j5yAobe8ZOcfLSryTjbW0U80NkdIruI/RAHyCaLI+RLvURiwswPPxv+SXnxj7j cBBA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1711527498; x=1712132298; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=6ZL6C477gTW+NfISWalYHi/00eT8ywLVpfA/stvnenI=; b=rU0VCTITqt3cU8GdfVU4nyH7KuE0AVMOQP2BpLVj9aq5G8cPkOYNBNwysnRNA6A0By 2cfdIVIT6ZpLVqRcqqFqjsMsNyyqAhWtnT1fcOAlxF4plemuEfNx3UVSlBGCaWe5oE7m kjmGrFqfwcNfbgpkTitPSutafY0RAMhGH2ynG5zd4hoX4+mJSNFvXd8K+VCTkKW1TQK+ hiHWm9oLHdArCVRJIk11z8MTLU1KZB/SmkPT2TQx73DV7KVz5FK1iXO3xu27/I0nPfFM PIXEMobUjuho+E6aUpNQGR5PUr1pVvYfYqlhFQ8qZupgbBPZ4qO60WzKsrqPakjHp2dC 1ElA== X-Gm-Message-State: AOJu0YwblSr9AlW3gp655mZrzdgbQZ641ItoCFW1Yg8KBoHv5pIAKXV9 NhM0FOjZM9PdfwM751nnQd1flU8vZNMv0k1tfQWhtnlmcsJMIdOAY5EX5GgmpmY= X-Google-Smtp-Source: AGHT+IFPs2WRv60nUMafy5z4ykBdYBvuVrjX2oOyMSzhz64UfHT1Gm1UsQ2+hA6XZnBBu9EUc/Pjzw== X-Received: by 2002:a2e:9013:0:b0:2d4:7532:92f2 with SMTP id h19-20020a2e9013000000b002d4753292f2mr2886201ljg.45.1711527498048; Wed, 27 Mar 2024 01:18:18 -0700 (PDT) Received: from claudiu-X670E-Pro-RS.. ([82.78.167.144]) by smtp.gmail.com with ESMTPSA id c9-20020a7bc2a9000000b0041493615585sm1353783wmk.39.2024.03.27.01.18.17 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 27 Mar 2024 01:18:17 -0700 (PDT) From: Claudiu X-Google-Original-From: Claudiu To: nobuhiro1.iwamatsu@toshiba.co.jp, pavel@denx.de Cc: cip-dev@lists.cip-project.org, biju.das.jz@bp.renesas.com, prabhakar.mahadev-lad.rj@bp.renesas.com, claudiu.beznea@tuxon.dev Subject: [PATCH 5.10.y-cip 17/36] irqchip/renesas-rzg2l: Align struct member names to tabs Date: Wed, 27 Mar 2024 10:17:37 +0200 Message-Id: <20240327081756.2228036-18-claudiu.beznea.uj@bp.renesas.com> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20240327081756.2228036-1-claudiu.beznea.uj@bp.renesas.com> References: <20240327081756.2228036-1-claudiu.beznea.uj@bp.renesas.com> MIME-Version: 1.0 List-Id: X-Webhook-Received: from li982-79.members.linode.com [45.33.32.79] by aws-us-west-2-korg-lkml-1.web.codeaurora.org with HTTPS for ; Wed, 27 Mar 2024 10:37:06 -0000 X-Groupsio-URL: https://lists.cip-project.org/g/cip-dev/message/15434 From: Claudiu Beznea commit 02f6507640173addeeb3af035d2c6f0b3cff1567 upstream. Align struct member names to tabs to follow the requirements from maintainer-tip file. 3 tabs were used at the moment as the next commits will add a new member which requires 3 tabs for a better view. Signed-off-by: Claudiu Beznea Signed-off-by: Thomas Gleixner Reviewed-by: Geert Uytterhoeven Link: https://lore.kernel.org/r/20231120111820.87398-4-claudiu.beznea.uj@bp.renesas.com Signed-off-by: Claudiu Beznea --- drivers/irqchip/irq-renesas-rzg2l.c | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/drivers/irqchip/irq-renesas-rzg2l.c b/drivers/irqchip/irq-renesas-rzg2l.c index 520200292eb9..23492927e8bc 100644 --- a/drivers/irqchip/irq-renesas-rzg2l.c +++ b/drivers/irqchip/irq-renesas-rzg2l.c @@ -58,9 +58,9 @@ #define TINT_EXTRACT_GPIOINT(x) FIELD_GET(GENMASK(31, 16), (x)) struct rzg2l_irqc_priv { - void __iomem *base; - struct irq_fwspec fwspec[IRQC_NUM_IRQ]; - raw_spinlock_t lock; + void __iomem *base; + struct irq_fwspec fwspec[IRQC_NUM_IRQ]; + raw_spinlock_t lock; }; static struct rzg2l_irqc_priv *irq_data_to_priv(struct irq_data *data) From patchwork Wed Mar 27 08:17:38 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Claudiu Beznea X-Patchwork-Id: 13606168 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from aws-us-west-2-korg-lkml-1.web.codeaurora.org (localhost.localdomain [127.0.0.1]) by smtp.lore.kernel.org (Postfix) with ESMTP id 0E827CD1296 for ; Wed, 27 Mar 2024 10:37:06 +0000 (UTC) Received: from mail-lj1-f178.google.com (mail-lj1-f178.google.com [209.85.208.178]) by mx.groups.io with SMTP id smtpd.web10.32442.1711527500838037412 for ; Wed, 27 Mar 2024 01:18:21 -0700 Authentication-Results: mx.groups.io; dkim=pass header.i=@tuxon.dev header.s=google header.b=nMiB3SDN; spf=pass (domain: tuxon.dev, ip: 209.85.208.178, mailfrom: claudiu.beznea@tuxon.dev) Received: by mail-lj1-f178.google.com with SMTP id 38308e7fff4ca-2d4886a1cb4so84120091fa.0 for ; Wed, 27 Mar 2024 01:18:20 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=tuxon.dev; s=google; t=1711527499; x=1712132299; darn=lists.cip-project.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=dwutIGGUJFh3y/lTfjIK6tU0gE3xHO0OjrBTqmbpC+s=; b=nMiB3SDNwttVoiobiTMOrPd3EaPMyGR3ni2ZbOPlH7I0zPpF6QLM5DdlXzwyRT45GN AlCR09lWpv8jjkz5GeIuHYOSFg5wK4I0yAW2tB3fJ/wwP2Dg8ieuL/t2ElFs3+Lz3Hl3 TdGEiKUL7StneUdpMaUZqhf0fcUqsrCHPwyV1nJ/C3AZFIEC0AgYSI9DCntBVGqO8osK 0Mo+accQq4QFmWvfF3Zo05mCxQpjtvhgZfOg/T6/XfbP1RqQWoEsWB//y8hL5l8dkwl0 LIi5a2t0GMgOceoKQSL5smSPvil/HYQ657XF7gvyE8yt2OFqbl0HWA/+SWkPXaC8rO+y aRdw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1711527499; x=1712132299; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=dwutIGGUJFh3y/lTfjIK6tU0gE3xHO0OjrBTqmbpC+s=; b=Un/Sdv+IFZo5wYTxktOuAfU+JNGOk/0DaCTb7w0Z06bR93O6jA8pFiTxLO8EkIsrDq j6bjSUyVSu/xxzUv+oHdB8wFCiW/LH1rmO1cgoobeHY4sH/+D25COS4TwUG+Gi0T8Mj1 Wz+0OlObyBmVTeaSCl1pgVN02JbZI0FpeIBZVolAo9mqmuOUkgpxhIhK66XtXMy3Hv8/ HSkP+LgT4r9MSSQOIEKtd7lCJowaKpnwYJ7jwsI8hPPy6og0UTEaEGZou/i8cP9rU0uQ ECwbAPH1KFMAdZotiDt//uthM0xn7MJx4K3je0INUJNDs1EU45Fun/GohPYw2W4QsrtA MDYw== X-Gm-Message-State: AOJu0Yy+3TXOUXlMSF5XOon2TwjIf32pFblpmoRyD6E0gCPkBUxkXsBJ XViXDTGAblN7ymEaPYcE5Yg218Z8YNMUZgbMUInEcWvDldKygC1+vxrwrUP7FwcJbsH/cqS/KaZ f X-Google-Smtp-Source: AGHT+IGMIrCwATf5p3V8B5HGWCCH6ple92KtzDNR06Q+KdmcFvaWhxc85+HUIjuO0ZmJhn4G/o/Uvw== X-Received: by 2002:a2e:9ad1:0:b0:2d6:dba1:6d37 with SMTP id p17-20020a2e9ad1000000b002d6dba16d37mr379800ljj.11.1711527499197; Wed, 27 Mar 2024 01:18:19 -0700 (PDT) Received: from claudiu-X670E-Pro-RS.. ([82.78.167.144]) by smtp.gmail.com with ESMTPSA id c9-20020a7bc2a9000000b0041493615585sm1353783wmk.39.2024.03.27.01.18.18 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 27 Mar 2024 01:18:18 -0700 (PDT) From: Claudiu X-Google-Original-From: Claudiu To: nobuhiro1.iwamatsu@toshiba.co.jp, pavel@denx.de Cc: cip-dev@lists.cip-project.org, biju.das.jz@bp.renesas.com, prabhakar.mahadev-lad.rj@bp.renesas.com, claudiu.beznea@tuxon.dev Subject: [PATCH 5.10.y-cip 18/36] irqchip/renesas-rzg2l: Document structure members Date: Wed, 27 Mar 2024 10:17:38 +0200 Message-Id: <20240327081756.2228036-19-claudiu.beznea.uj@bp.renesas.com> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20240327081756.2228036-1-claudiu.beznea.uj@bp.renesas.com> References: <20240327081756.2228036-1-claudiu.beznea.uj@bp.renesas.com> MIME-Version: 1.0 List-Id: X-Webhook-Received: from li982-79.members.linode.com [45.33.32.79] by aws-us-west-2-korg-lkml-1.web.codeaurora.org with HTTPS for ; Wed, 27 Mar 2024 10:37:06 -0000 X-Groupsio-URL: https://lists.cip-project.org/g/cip-dev/message/15435 From: Claudiu Beznea commit b94f455372ad6e6b4da8e8ed9864d9c7daaf54b8 upstream. Document structure members to follow the requirements specified in maintainer-tip, section 4.3.7. Struct declarations and initializers. Signed-off-by: Claudiu Beznea Signed-off-by: Thomas Gleixner Reviewed-by: Geert Uytterhoeven Link: https://lore.kernel.org/r/20231120111820.87398-5-claudiu.beznea.uj@bp.renesas.com Signed-off-by: Claudiu Beznea --- drivers/irqchip/irq-renesas-rzg2l.c | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/drivers/irqchip/irq-renesas-rzg2l.c b/drivers/irqchip/irq-renesas-rzg2l.c index 23492927e8bc..92f8d7eeb44b 100644 --- a/drivers/irqchip/irq-renesas-rzg2l.c +++ b/drivers/irqchip/irq-renesas-rzg2l.c @@ -57,6 +57,12 @@ #define TINT_EXTRACT_HWIRQ(x) FIELD_GET(GENMASK(15, 0), (x)) #define TINT_EXTRACT_GPIOINT(x) FIELD_GET(GENMASK(31, 16), (x)) +/** + * struct rzg2l_irqc_priv - IRQ controller private data structure + * @base: Controller's base address + * @fwspec: IRQ firmware specific data + * @lock: Lock to serialize access to hardware registers + */ struct rzg2l_irqc_priv { void __iomem *base; struct irq_fwspec fwspec[IRQC_NUM_IRQ]; From patchwork Wed Mar 27 08:17:39 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Claudiu Beznea X-Patchwork-Id: 13606172 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from aws-us-west-2-korg-lkml-1.web.codeaurora.org (localhost.localdomain [127.0.0.1]) by smtp.lore.kernel.org (Postfix) with ESMTP id 1C8CDCD1299 for ; Wed, 27 Mar 2024 10:37:06 +0000 (UTC) Received: from mail-wm1-f45.google.com (mail-wm1-f45.google.com [209.85.128.45]) by mx.groups.io with SMTP id smtpd.web11.32297.1711527501834518356 for ; Wed, 27 Mar 2024 01:18:22 -0700 Authentication-Results: mx.groups.io; dkim=pass header.i=@tuxon.dev header.s=google header.b=rCbbKZBC; spf=pass (domain: tuxon.dev, ip: 209.85.128.45, mailfrom: claudiu.beznea@tuxon.dev) Received: by mail-wm1-f45.google.com with SMTP id 5b1f17b1804b1-41495d16568so722485e9.1 for ; Wed, 27 Mar 2024 01:18:21 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=tuxon.dev; s=google; t=1711527500; x=1712132300; darn=lists.cip-project.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=ltpkKQ2RPJir58v2TFUhK3ylb98qqSPKNSRYqXM9iYE=; b=rCbbKZBCPGNqfHZjpgz7Miv2eHq1UNPCD2/DnjUMyjvQpZo1wcwR6tQ3ZwdpTSvs/Y mgYVUwLMkLrHevGECma2yIK7iQkdSZA4d9XPx7z7ZBoc/5qxR6yrOhkYXkae65QRmavf WgcHY1fq+slFeoF57S1MPER95Ddl5spltWE93mA7C0Va5rwskZm1ksha4rNwcq2oqub+ /ZGzRx8LfqVIm5/pqv0JyoLL0U8gSWk2VM6WXDPocbkDPBhwpGcDqLUdg6Zy3e7S0M6v jtKykwdR5MC1xNOOdqX3FlVppePW/bqKVW/S+AmAV31vhPr+g2W5trg5yTbspOXs0nyp +pxw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1711527500; x=1712132300; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=ltpkKQ2RPJir58v2TFUhK3ylb98qqSPKNSRYqXM9iYE=; b=USvbi45TRhEkvdfQ2qh+GFLH3FKmqoRscJyBY1a7v1ZcsHd6pi4NsHGFMOYMU8k3H/ 9FnRc/0c10ECF2UpiIR5Hw7UBFuzIXdfYKzBRbnjSlFcmVA+zhlf+NQmBsLclpyYl6aJ bt/PseTiF4EGgbJgdSPqzf9MbQTILU4tLaOHMvzLGw6Twa3m08Zlh9qcGe4SLFNSi31S VG66zd//3V/eqPjJgGyl34IppC80wfAIa2/zy2NAD34yDhR79VdQAAi4xnIa0F85+PhG PYe2kxu2MxXvUIwPDpg4FGLzk5K3HsykDF+TZ8kaEDSUUWeFxGEttRBL8fazzYJKyDNT JQmQ== X-Gm-Message-State: AOJu0Yy7astSyD4M2Xv5vumPUOdV/4+dNuGEzbzSYgkmRIYLEML8tKVW D1kA5XRaXHow+nxhHCSfjaxe3ONaZJD9lUAsDnHqIA9AUqSBnK8N4hiSxBh6xjQ= X-Google-Smtp-Source: AGHT+IHYKq6lRQb5LST9o6+LbhZRyRAwnKa3ZPFmgEEEuW3fMUGD/41H15tLegO86qFA9vUgHJvJMg== X-Received: by 2002:a05:600c:310a:b0:414:9242:e249 with SMTP id g10-20020a05600c310a00b004149242e249mr476056wmo.3.1711527500361; Wed, 27 Mar 2024 01:18:20 -0700 (PDT) Received: from claudiu-X670E-Pro-RS.. ([82.78.167.144]) by smtp.gmail.com with ESMTPSA id c9-20020a7bc2a9000000b0041493615585sm1353783wmk.39.2024.03.27.01.18.19 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 27 Mar 2024 01:18:19 -0700 (PDT) From: Claudiu X-Google-Original-From: Claudiu To: nobuhiro1.iwamatsu@toshiba.co.jp, pavel@denx.de Cc: cip-dev@lists.cip-project.org, biju.das.jz@bp.renesas.com, prabhakar.mahadev-lad.rj@bp.renesas.com, claudiu.beznea@tuxon.dev Subject: [PATCH 5.10.y-cip 19/36] irqchip/renesas-rzg2l: Implement restriction when writing ISCR register Date: Wed, 27 Mar 2024 10:17:39 +0200 Message-Id: <20240327081756.2228036-20-claudiu.beznea.uj@bp.renesas.com> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20240327081756.2228036-1-claudiu.beznea.uj@bp.renesas.com> References: <20240327081756.2228036-1-claudiu.beznea.uj@bp.renesas.com> MIME-Version: 1.0 List-Id: X-Webhook-Received: from li982-79.members.linode.com [45.33.32.79] by aws-us-west-2-korg-lkml-1.web.codeaurora.org with HTTPS for ; Wed, 27 Mar 2024 10:37:06 -0000 X-Groupsio-URL: https://lists.cip-project.org/g/cip-dev/message/15436 From: Claudiu Beznea commit ef88eefb1a81a8701eabb7d5ced761a66a465a49 upstream. The RZ/G2L manual (chapter "IRQ Status Control Register (ISCR)") describes the operation to clear interrupts through the ISCR register as follows: [Write operation] When "Falling-edge detection", "Rising-edge detection" or "Falling/Rising-edge detection" is set in IITSR: - In case ISTAT is 1 0: IRQn interrupt detection status is cleared. 1: Invalid to write. - In case ISTAT is 0 Invalid to write. When "Low-level detection" is set in IITSR.: Invalid to write. Take the interrupt type into account when clearing interrupts through the ISCR register to avoid writing the ISCR when the interrupt type is level. Signed-off-by: Claudiu Beznea Signed-off-by: Thomas Gleixner Reviewed-by: Geert Uytterhoeven Link: https://lore.kernel.org/r/20231120111820.87398-6-claudiu.beznea.uj@bp.renesas.com Signed-off-by: Claudiu Beznea --- drivers/irqchip/irq-renesas-rzg2l.c | 14 ++++++++++---- 1 file changed, 10 insertions(+), 4 deletions(-) diff --git a/drivers/irqchip/irq-renesas-rzg2l.c b/drivers/irqchip/irq-renesas-rzg2l.c index 92f8d7eeb44b..b87d7ea46b40 100644 --- a/drivers/irqchip/irq-renesas-rzg2l.c +++ b/drivers/irqchip/irq-renesas-rzg2l.c @@ -79,11 +79,17 @@ static void rzg2l_irq_eoi(struct irq_data *d) unsigned int hw_irq = irqd_to_hwirq(d) - IRQC_IRQ_START; struct rzg2l_irqc_priv *priv = irq_data_to_priv(d); u32 bit = BIT(hw_irq); - u32 reg; + u32 iitsr, iscr; - reg = readl_relaxed(priv->base + ISCR); - if (reg & bit) - writel_relaxed(reg & ~bit, priv->base + ISCR); + iscr = readl_relaxed(priv->base + ISCR); + iitsr = readl_relaxed(priv->base + IITSR); + + /* + * ISCR can only be cleared if the type is falling-edge, rising-edge or + * falling/rising-edge. + */ + if ((iscr & bit) && (iitsr & IITSR_IITSEL_MASK(hw_irq))) + writel_relaxed(iscr & ~bit, priv->base + ISCR); } static void rzg2l_tint_eoi(struct irq_data *d) From patchwork Wed Mar 27 08:17:40 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Claudiu Beznea X-Patchwork-Id: 13606175 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from aws-us-west-2-korg-lkml-1.web.codeaurora.org (localhost.localdomain [127.0.0.1]) by smtp.lore.kernel.org (Postfix) with ESMTP id 29FD4CD129B for ; Wed, 27 Mar 2024 10:37:06 +0000 (UTC) Received: from mail-wm1-f41.google.com (mail-wm1-f41.google.com [209.85.128.41]) by mx.groups.io with SMTP id smtpd.web11.32298.1711527503047064819 for ; Wed, 27 Mar 2024 01:18:23 -0700 Authentication-Results: mx.groups.io; dkim=pass header.i=@tuxon.dev header.s=google header.b=dDsQ2DeA; spf=pass (domain: tuxon.dev, ip: 209.85.128.41, mailfrom: claudiu.beznea@tuxon.dev) Received: by mail-wm1-f41.google.com with SMTP id 5b1f17b1804b1-4148c6132b4so3121875e9.1 for ; Wed, 27 Mar 2024 01:18:22 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=tuxon.dev; s=google; t=1711527501; x=1712132301; darn=lists.cip-project.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=cLP+HVJJ7s5UZD+KSb9E1ZKiN9ypwYNuAxgrkj2sWko=; b=dDsQ2DeAgfDI4BZigc14X01Zc7L90TyM850bXDX+AThIxDrWHFWXgQbigV2Q5/6AOq EIP6dRgDI1HlGC2Dza5gPi87oKtd5z/Kop0w04rQF/o7fzs2sWhk8BS0jGaAqWayhHja l062BvRriy6ZAQUA0XWIP4XEoFET6bOhQl7eykkpIe26DdFmxGkKYlNcwN+ecyYRNrLz DkYK+iRENZdafkEY+FTh95pwtq5W8ooKujvClJTkUCHXQH/8iajdRHOx4j27T5XY8cMR vDwiZpX2cIu5kh+q2Zs7m4euaUZrc0AI8e947AsJIhekTFMtldhaGpli59RbFM7c0SmC tYng== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1711527501; x=1712132301; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=cLP+HVJJ7s5UZD+KSb9E1ZKiN9ypwYNuAxgrkj2sWko=; b=vfdWN6l+PS9kaALH4Yj0V5mLbNwlUR/+GNbH1pjrPt5tjQsDsA6BY+tQ79DKNiSFDD IJR2hp2IwRs6IqRT52an8RIObPUoOPsp51LOmDUdMdW0012sS6POMQjazPN2cY1T3PBw CtF4pF3qPFfKcei5fSvwHoW3Qt6SankgDi+/wZHRYNHNLSaylssT/IJXgK4TLNR/51BF 49NsXBn5lveigzXafYvStU/doYZHgb3RHNG0OB1Q59PsEw6MfrAiAG2kA+42ljHB6F4I Q2ru0IViDimDS1MceNfPCIn1GnDiHXWBBdVLhRSecIfGC1BsAEqtPv4QdL3LW/xlWT3m BGwA== X-Gm-Message-State: AOJu0YyO9aDzrte3tu5/Stl5kRyZDzUFEgsSA2kAQQlFilOo3qzr53z/ eN9Pshzk7b4HaI8OVkgW+MwlPPr93YE5uhjQ+OJifucHg5Ah4vxS0NU1mpXpZGc= X-Google-Smtp-Source: AGHT+IE4NBddhf9U6wpMJ8Aq2dk0vWaTHcfzV9GIo+h1TtmEe1YOKnu/0iRVf2/7bnCreEyjEPGOOg== X-Received: by 2002:a05:600c:1c9a:b0:414:89c7:c0af with SMTP id k26-20020a05600c1c9a00b0041489c7c0afmr3184622wms.13.1711527501505; Wed, 27 Mar 2024 01:18:21 -0700 (PDT) Received: from claudiu-X670E-Pro-RS.. ([82.78.167.144]) by smtp.gmail.com with ESMTPSA id c9-20020a7bc2a9000000b0041493615585sm1353783wmk.39.2024.03.27.01.18.20 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 27 Mar 2024 01:18:21 -0700 (PDT) From: Claudiu X-Google-Original-From: Claudiu To: nobuhiro1.iwamatsu@toshiba.co.jp, pavel@denx.de Cc: cip-dev@lists.cip-project.org, biju.das.jz@bp.renesas.com, prabhakar.mahadev-lad.rj@bp.renesas.com, claudiu.beznea@tuxon.dev Subject: [PATCH 5.10.y-cip 20/36] irqchip/renesas-rzg2l: Add macro to retrieve TITSR register offset based on register's index Date: Wed, 27 Mar 2024 10:17:40 +0200 Message-Id: <20240327081756.2228036-21-claudiu.beznea.uj@bp.renesas.com> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20240327081756.2228036-1-claudiu.beznea.uj@bp.renesas.com> References: <20240327081756.2228036-1-claudiu.beznea.uj@bp.renesas.com> MIME-Version: 1.0 List-Id: X-Webhook-Received: from li982-79.members.linode.com [45.33.32.79] by aws-us-west-2-korg-lkml-1.web.codeaurora.org with HTTPS for ; Wed, 27 Mar 2024 10:37:06 -0000 X-Groupsio-URL: https://lists.cip-project.org/g/cip-dev/message/15437 From: Claudiu Beznea commit 2eca4731cc66563b3919d8753dbd74d18c39f662 upstream. There are 2 TITSR registers available on the IA55 interrupt controller. Add a macro that retrieves the TITSR register offset based on it's index. This macro is useful in when adding suspend/resume support so both TITSR registers can be accessed in a for loop. Signed-off-by: Claudiu Beznea Signed-off-by: Thomas Gleixner Link: https://lore.kernel.org/r/20231120111820.87398-7-claudiu.beznea.uj@bp.renesas.com Signed-off-by: Claudiu Beznea --- drivers/irqchip/irq-renesas-rzg2l.c | 14 ++++++-------- 1 file changed, 6 insertions(+), 8 deletions(-) diff --git a/drivers/irqchip/irq-renesas-rzg2l.c b/drivers/irqchip/irq-renesas-rzg2l.c index b87d7ea46b40..42ad81708b72 100644 --- a/drivers/irqchip/irq-renesas-rzg2l.c +++ b/drivers/irqchip/irq-renesas-rzg2l.c @@ -29,8 +29,7 @@ #define ISCR 0x10 #define IITSR 0x14 #define TSCR 0x20 -#define TITSR0 0x24 -#define TITSR1 0x28 +#define TITSR(n) (0x24 + (n) * 4) #define TITSR0_MAX_INT 16 #define TITSEL_WIDTH 0x2 #define TSSR(n) (0x30 + ((n) * 4)) @@ -201,8 +200,7 @@ static int rzg2l_tint_set_edge(struct irq_data *d, unsigned int type) struct rzg2l_irqc_priv *priv = irq_data_to_priv(d); unsigned int hwirq = irqd_to_hwirq(d); u32 titseln = hwirq - IRQC_TINT_START; - u32 offset; - u8 sense; + u8 index, sense; u32 reg; switch (type & IRQ_TYPE_SENSE_MASK) { @@ -218,17 +216,17 @@ static int rzg2l_tint_set_edge(struct irq_data *d, unsigned int type) return -EINVAL; } - offset = TITSR0; + index = 0; if (titseln >= TITSR0_MAX_INT) { titseln -= TITSR0_MAX_INT; - offset = TITSR1; + index = 1; } raw_spin_lock(&priv->lock); - reg = readl_relaxed(priv->base + offset); + reg = readl_relaxed(priv->base + TITSR(index)); reg &= ~(IRQ_MASK << (titseln * TITSEL_WIDTH)); reg |= sense << (titseln * TITSEL_WIDTH); - writel_relaxed(reg, priv->base + offset); + writel_relaxed(reg, priv->base + TITSR(index)); raw_spin_unlock(&priv->lock); return 0; From patchwork Wed Mar 27 08:17:41 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Claudiu Beznea X-Patchwork-Id: 13606181 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from aws-us-west-2-korg-lkml-1.web.codeaurora.org (localhost.localdomain [127.0.0.1]) by smtp.lore.kernel.org (Postfix) with ESMTP id 351E9CD12A0 for ; Wed, 27 Mar 2024 10:37:06 +0000 (UTC) Received: from mail-wm1-f42.google.com (mail-wm1-f42.google.com [209.85.128.42]) by mx.groups.io with SMTP id smtpd.web11.32300.1711527504375496332 for ; Wed, 27 Mar 2024 01:18:24 -0700 Authentication-Results: mx.groups.io; dkim=pass header.i=@tuxon.dev header.s=google header.b=oDC3DkPO; spf=pass (domain: tuxon.dev, ip: 209.85.128.42, mailfrom: claudiu.beznea@tuxon.dev) Received: by mail-wm1-f42.google.com with SMTP id 5b1f17b1804b1-4149529f410so2113095e9.3 for ; Wed, 27 Mar 2024 01:18:24 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=tuxon.dev; s=google; t=1711527503; x=1712132303; darn=lists.cip-project.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=AXhsOYL+B+HtTzFlbtmT77Lo94wVvQRAj6kUPbLYrjo=; b=oDC3DkPOyuLs7oA7lfEPPpg2tplXMIEV8QREeq80L2Gp4p2MX47qGomK+dZcVD6dwE 3CY2KNm46AHElZI3AdNogNIlFRLoc71mOdKP8lTukUraJB3u+y/l+fTwgiazBWGG9eFf lyCmM4y0Vi4ByH3IkGqVLkCm46N0PKVTvPkvU79hqqAM5LwCbrGAY61BA57fjVHpWXW9 wogJlJdqT0Rw5reLI7q7d4V5Mgbpl4n5yjUQZGndItLP7UQTLNp4Q6GR5Yra4wIslmfJ 1EA1VnlJBS+zbdHLiljxLw6qDH8i9/jaVbEWT8qX2MbYPcmfOl2HZDolwBulGbqWhGqH ch3w== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1711527503; x=1712132303; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=AXhsOYL+B+HtTzFlbtmT77Lo94wVvQRAj6kUPbLYrjo=; b=Rq61674fTUJpsB2cQByObHe/+2hdfeQQO3suzcBG6DY4fnBjS5ZCIB4J153l4/xYE3 yqe8ozB6b0AWhHQc7/A1l2lFzUcSXYfSnD6Tt1kNBQ4zrJSm0gOERUqNe6D0Zi8uY+8w ksr41pZS0ogQpAI8q7QrNEIILMdOBlhEsdxzTVO5t2gIDZES9S7gogextyr0FPSSQ3nS d5nA+Mk3MynPfyhU/ZgwTmbP/VAme3/B/+GFgqhmpXU20+Sw8a+lVHg68Bwxpcf5EhRa V2qok7gIIwh7GMRIBBHHvpxtH+Q0pqVXHoL7RMGTNsSn2WMJNOXNPMv4UgSjlUD06bGA pwRQ== X-Gm-Message-State: AOJu0YwNLxlrHzYM2u0Hb8jruIaSdoG3f8a7aJwxGMIt4bLGUkYO/aZ4 YZl1QV88Q799tEeSL8TsclH1ARYYc1oOIs9YO/K8URPq67GwxCDWqix5AM9iRFQ= X-Google-Smtp-Source: AGHT+IHhwsHNXfuaMIFZ5u2uloYVEkFUe2gABTxmowJw97m+LLQRl2f8vzW62LKONo0OCoxT1yzfBA== X-Received: by 2002:a05:600c:458e:b0:412:d68c:8229 with SMTP id r14-20020a05600c458e00b00412d68c8229mr1709747wmo.39.1711527502820; Wed, 27 Mar 2024 01:18:22 -0700 (PDT) Received: from claudiu-X670E-Pro-RS.. ([82.78.167.144]) by smtp.gmail.com with ESMTPSA id c9-20020a7bc2a9000000b0041493615585sm1353783wmk.39.2024.03.27.01.18.21 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 27 Mar 2024 01:18:22 -0700 (PDT) From: Claudiu X-Google-Original-From: Claudiu To: nobuhiro1.iwamatsu@toshiba.co.jp, pavel@denx.de Cc: cip-dev@lists.cip-project.org, biju.das.jz@bp.renesas.com, prabhakar.mahadev-lad.rj@bp.renesas.com, claudiu.beznea@tuxon.dev Subject: [PATCH 5.10.y-cip 21/36] irqchip/renesas-rzg2l: Flush posted write in irq_eoi() Date: Wed, 27 Mar 2024 10:17:41 +0200 Message-Id: <20240327081756.2228036-22-claudiu.beznea.uj@bp.renesas.com> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20240327081756.2228036-1-claudiu.beznea.uj@bp.renesas.com> References: <20240327081756.2228036-1-claudiu.beznea.uj@bp.renesas.com> MIME-Version: 1.0 List-Id: X-Webhook-Received: from li982-79.members.linode.com [45.33.32.79] by aws-us-west-2-korg-lkml-1.web.codeaurora.org with HTTPS for ; Wed, 27 Mar 2024 10:37:06 -0000 X-Groupsio-URL: https://lists.cip-project.org/g/cip-dev/message/15438 From: Biju Das commit 9eec61df55c51415409c7cc47e9a1c8de94a0522 upstream. The irq_eoi() callback of the RZ/G2L interrupt chip clears the relevant interrupt cause bit in the TSCR register by writing to it. This write is not sufficient because the write is posted and therefore not guaranteed to immediately clear the bit. Due to that delay the CPU can raise the just handled interrupt again. Prevent this by reading the register back which causes the posted write to be flushed to the hardware before the read completes. Fixes: 3fed09559cd8 ("irqchip: Add RZ/G2L IA55 Interrupt Controller driver") Signed-off-by: Biju Das Signed-off-by: Thomas Gleixner Signed-off-by: Claudiu Beznea --- drivers/irqchip/irq-renesas-rzg2l.c | 16 ++++++++++++++-- 1 file changed, 14 insertions(+), 2 deletions(-) diff --git a/drivers/irqchip/irq-renesas-rzg2l.c b/drivers/irqchip/irq-renesas-rzg2l.c index 42ad81708b72..79ce7ab4d164 100644 --- a/drivers/irqchip/irq-renesas-rzg2l.c +++ b/drivers/irqchip/irq-renesas-rzg2l.c @@ -87,8 +87,14 @@ static void rzg2l_irq_eoi(struct irq_data *d) * ISCR can only be cleared if the type is falling-edge, rising-edge or * falling/rising-edge. */ - if ((iscr & bit) && (iitsr & IITSR_IITSEL_MASK(hw_irq))) + if ((iscr & bit) && (iitsr & IITSR_IITSEL_MASK(hw_irq))) { writel_relaxed(iscr & ~bit, priv->base + ISCR); + /* + * Enforce that the posted write is flushed to prevent that the + * just handled interrupt is raised again. + */ + readl_relaxed(priv->base + ISCR); + } } static void rzg2l_tint_eoi(struct irq_data *d) @@ -99,8 +105,14 @@ static void rzg2l_tint_eoi(struct irq_data *d) u32 reg; reg = readl_relaxed(priv->base + TSCR); - if (reg & bit) + if (reg & bit) { writel_relaxed(reg & ~bit, priv->base + TSCR); + /* + * Enforce that the posted write is flushed to prevent that the + * just handled interrupt is raised again. + */ + readl_relaxed(priv->base + TSCR); + } } static void rzg2l_irqc_eoi(struct irq_data *d) From patchwork Wed Mar 27 08:17:42 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Claudiu Beznea X-Patchwork-Id: 13606182 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from aws-us-west-2-korg-lkml-1.web.codeaurora.org (localhost.localdomain [127.0.0.1]) by smtp.lore.kernel.org (Postfix) with ESMTP id 3D41CCD129F for ; Wed, 27 Mar 2024 10:37:06 +0000 (UTC) Received: from mail-lf1-f48.google.com (mail-lf1-f48.google.com [209.85.167.48]) by mx.groups.io with SMTP id smtpd.web10.32443.1711527505815165073 for ; Wed, 27 Mar 2024 01:18:26 -0700 Authentication-Results: mx.groups.io; dkim=pass header.i=@tuxon.dev header.s=google header.b=dqDWVkoq; spf=pass (domain: tuxon.dev, ip: 209.85.167.48, mailfrom: claudiu.beznea@tuxon.dev) Received: by mail-lf1-f48.google.com with SMTP id 2adb3069b0e04-513d212f818so7295113e87.2 for ; Wed, 27 Mar 2024 01:18:25 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=tuxon.dev; s=google; t=1711527504; x=1712132304; darn=lists.cip-project.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=1XcPdoCzowqFBnTUG3qfKJATd6js+MqTUX5WcMQpHJE=; b=dqDWVkoqcJBc/MJpCT9QAgnwPjK7DrANgq6Ol//vli1VgUp3kR81n7PNxI8VFtNWog jAnVWKKJLqQqvmJMrJm2p+N+vGS9QsXYKJ3v44E590GMiwuP1ebNQjA2DLG2+kZXBVtf XOfGnPNkDQ59olCXQQLxn1xYMQ0O0O+sQ1N7pPGw0EKO01Tz840B2VHmFetIi4g6hdaT ok25lXsTWRcJSlNAG4KEnv6BNmZOqFQLU2BsnN1IO6LRLuNKO8E0nQvoMwzgv+ugBG/A p8ui4Kw5RMvKTENzFGQ3Fl6zwh+4hYU6kT/LGTAekoZNSH9mW7p2ZSp9Zz8oi5Mz8pTx 0x8w== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1711527504; x=1712132304; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=1XcPdoCzowqFBnTUG3qfKJATd6js+MqTUX5WcMQpHJE=; b=ASnlIVgEVc1BeIrPYTfMxrxoiWBSR401qdWlgSW5Iqpj2pb+UoZPRI3X7cRwk83YGP eLF6wbMG2/kRwic56ctjNe7BLygnDuBRJkt3/vtDCgMdFlNn5vITO/cPRXU1W2BTMO1a VJLPb8/m7cLEpu+CBo/WAboswPTyKp2eflqI2GWtxljnyy9XGwFPYcW7CoM6739QRZQr ERMn9RSCN8u46yKqYrHIuHFeFF63l82Qw99zhIAy6uSX7+QXCjYAAmpsKMkZdJOsYHab Y23DElVh+6ljnGHQWpH/h1YJKmuuPrmuEUSlv5YyBZZzg5iIdp8MEOcE29JkvXgBIceg 4LSA== X-Gm-Message-State: AOJu0YxMqY+ug8IxFd87aaH+aGSZNhU9boCzCfg8RtFkX2S/kKLWK3eP zVIYdpkKUyqJ7AUVmHMKTY52u3B2jE2d93k5nh4p3fZp/e5v0NygZO2vxrBjO2U= X-Google-Smtp-Source: AGHT+IEpQyNhEj++J21pssEAY68+/WJYYsnN5EBk91CKPtEHAqp0mEd8tqVqlu9qIuxtZI5Aac7RtA== X-Received: by 2002:ac2:48a4:0:b0:515:a6dd:9657 with SMTP id u4-20020ac248a4000000b00515a6dd9657mr1117013lfg.16.1711527504121; Wed, 27 Mar 2024 01:18:24 -0700 (PDT) Received: from claudiu-X670E-Pro-RS.. ([82.78.167.144]) by smtp.gmail.com with ESMTPSA id c9-20020a7bc2a9000000b0041493615585sm1353783wmk.39.2024.03.27.01.18.23 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 27 Mar 2024 01:18:23 -0700 (PDT) From: Claudiu X-Google-Original-From: Claudiu To: nobuhiro1.iwamatsu@toshiba.co.jp, pavel@denx.de Cc: cip-dev@lists.cip-project.org, biju.das.jz@bp.renesas.com, prabhakar.mahadev-lad.rj@bp.renesas.com, claudiu.beznea@tuxon.dev Subject: [PATCH 5.10.y-cip 22/36] irqchip/renesas-rzg2l: Rename rzg2l_tint_eoi() Date: Wed, 27 Mar 2024 10:17:42 +0200 Message-Id: <20240327081756.2228036-23-claudiu.beznea.uj@bp.renesas.com> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20240327081756.2228036-1-claudiu.beznea.uj@bp.renesas.com> References: <20240327081756.2228036-1-claudiu.beznea.uj@bp.renesas.com> MIME-Version: 1.0 List-Id: X-Webhook-Received: from li982-79.members.linode.com [45.33.32.79] by aws-us-west-2-korg-lkml-1.web.codeaurora.org with HTTPS for ; Wed, 27 Mar 2024 10:37:06 -0000 X-Groupsio-URL: https://lists.cip-project.org/g/cip-dev/message/15439 From: Biju Das commit 7cb6362c63df233172eaecddaf9ce2ce2f769112 upstream. Rename rzg2l_tint_eoi()->rzg2l_clear_tint_int() and simplify the code by removing redundant priv and hw_irq local variables. Signed-off-by: Biju Das Signed-off-by: Thomas Gleixner Reviewed-by: Geert Uytterhoeven Signed-off-by: Claudiu Beznea --- drivers/irqchip/irq-renesas-rzg2l.c | 8 +++----- 1 file changed, 3 insertions(+), 5 deletions(-) diff --git a/drivers/irqchip/irq-renesas-rzg2l.c b/drivers/irqchip/irq-renesas-rzg2l.c index 79ce7ab4d164..315c58d99376 100644 --- a/drivers/irqchip/irq-renesas-rzg2l.c +++ b/drivers/irqchip/irq-renesas-rzg2l.c @@ -97,11 +97,9 @@ static void rzg2l_irq_eoi(struct irq_data *d) } } -static void rzg2l_tint_eoi(struct irq_data *d) +static void rzg2l_clear_tint_int(struct rzg2l_irqc_priv *priv, unsigned int hwirq) { - unsigned int hw_irq = irqd_to_hwirq(d) - IRQC_TINT_START; - struct rzg2l_irqc_priv *priv = irq_data_to_priv(d); - u32 bit = BIT(hw_irq); + u32 bit = BIT(hwirq - IRQC_TINT_START); u32 reg; reg = readl_relaxed(priv->base + TSCR); @@ -124,7 +122,7 @@ static void rzg2l_irqc_eoi(struct irq_data *d) if (hw_irq >= IRQC_IRQ_START && hw_irq <= IRQC_IRQ_COUNT) rzg2l_irq_eoi(d); else if (hw_irq >= IRQC_TINT_START && hw_irq < IRQC_NUM_IRQ) - rzg2l_tint_eoi(d); + rzg2l_clear_tint_int(priv, hw_irq); raw_spin_unlock(&priv->lock); irq_chip_eoi_parent(d); } From patchwork Wed Mar 27 08:17:43 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Claudiu Beznea X-Patchwork-Id: 13606184 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from aws-us-west-2-korg-lkml-1.web.codeaurora.org (localhost.localdomain [127.0.0.1]) by smtp.lore.kernel.org (Postfix) with ESMTP id 4A053CD12A2 for ; Wed, 27 Mar 2024 10:37:06 +0000 (UTC) Received: from mail-wm1-f41.google.com (mail-wm1-f41.google.com [209.85.128.41]) by mx.groups.io with SMTP id smtpd.web11.32301.1711527506948044536 for ; Wed, 27 Mar 2024 01:18:27 -0700 Authentication-Results: mx.groups.io; dkim=pass header.i=@tuxon.dev header.s=google header.b=mHJLGiC7; spf=pass (domain: tuxon.dev, ip: 209.85.128.41, mailfrom: claudiu.beznea@tuxon.dev) Received: by mail-wm1-f41.google.com with SMTP id 5b1f17b1804b1-41495ac5b91so916565e9.0 for ; Wed, 27 Mar 2024 01:18:26 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=tuxon.dev; s=google; t=1711527505; x=1712132305; darn=lists.cip-project.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=zPv1Y9B0fxu0PozBK8+dqYxasHT8vQsQOUiTA2Kx3bY=; b=mHJLGiC74ajPUOZp6IQLl5FRdHbKEym7FPsciGhFDr2AmLTtObUi4fLwmWv+mQW5oo EVwuuYsItl1AdLyC0SsQvwkIySqAPUuloc1XcUSC2WPHRtEvW4ESjhp0WDPCQzIgtv+w PJ39orxi4gwAigm5xUPWJYuYm6Xe0VRobIhocIKRQUdkGJQdyCgVnntFsNEuLNzHRs/o Bb2toddXeCh4AIIyWpSITnty+hCAwNhfw9d38gIGn5ECBi8Rvw7OhFpUkvMxn8U0ocR0 OqVNCxhtgEYYMdK4QiUYKb9vuCeeD72rfm4QTjNrXg7nj7c33YSXoaV6jK5+LNSY3FUh /XVg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1711527505; x=1712132305; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=zPv1Y9B0fxu0PozBK8+dqYxasHT8vQsQOUiTA2Kx3bY=; b=jUxhSF2BAV1vXlimjepL1VvMMi+NEKywEZZmgr2NTgu/qgcP0PBaOge47uDwSMbfIX yDNbe/zah2HeayW1v0wzMtclfMB1R5nEd4mPu/iAUykLw7q87J/Wi/X1JM9C0wartuCJ 12wAHI+WQ/iRupyLXj4D89NrB/PxZw5u4Bgmf3W2ZX8o9Sy4TQIDphg6mwIGKiL8v7Ei oQatHKujRDtjyEoBDwz08ba+6oMrCTORphxs0EHCDmgupWz5wrDigg14mj/HBYT4iQ6V aHkjTmJuy8p3FUkSqSFPIB+qditffsJoRhtmL+gU8LVZQe83Ay3xS+bxeHgl87cZTSFC Dt9Q== X-Gm-Message-State: AOJu0YxofWUG2OZqpCP2XnLNAq5N42pRC4FKgVdQ4u0inU7nFE6SxIuG UkvRsqFyRm8aJR/Tq0VVoTnckfPyGn8PcQPzn87rZ2ztCAMu5L3ejNBcB+GXaiBvmjeY0MdpKVu N X-Google-Smtp-Source: AGHT+IHsKLqqiT+AqslCifFalutnlNUDiMBFtCuiiK2wGBU7xHCdPqgWv9gW+c/flHVAuE7m1FD+uA== X-Received: by 2002:a05:600c:4994:b0:414:12b6:7315 with SMTP id h20-20020a05600c499400b0041412b67315mr479826wmp.17.1711527505465; Wed, 27 Mar 2024 01:18:25 -0700 (PDT) Received: from claudiu-X670E-Pro-RS.. ([82.78.167.144]) by smtp.gmail.com with ESMTPSA id c9-20020a7bc2a9000000b0041493615585sm1353783wmk.39.2024.03.27.01.18.24 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 27 Mar 2024 01:18:25 -0700 (PDT) From: Claudiu X-Google-Original-From: Claudiu To: nobuhiro1.iwamatsu@toshiba.co.jp, pavel@denx.de Cc: cip-dev@lists.cip-project.org, biju.das.jz@bp.renesas.com, prabhakar.mahadev-lad.rj@bp.renesas.com, claudiu.beznea@tuxon.dev Subject: [PATCH 5.10.y-cip 23/36] irqchip/renesas-rzg2l: Rename rzg2l_irq_eoi() Date: Wed, 27 Mar 2024 10:17:43 +0200 Message-Id: <20240327081756.2228036-24-claudiu.beznea.uj@bp.renesas.com> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20240327081756.2228036-1-claudiu.beznea.uj@bp.renesas.com> References: <20240327081756.2228036-1-claudiu.beznea.uj@bp.renesas.com> MIME-Version: 1.0 List-Id: X-Webhook-Received: from li982-79.members.linode.com [45.33.32.79] by aws-us-west-2-korg-lkml-1.web.codeaurora.org with HTTPS for ; Wed, 27 Mar 2024 10:37:06 -0000 X-Groupsio-URL: https://lists.cip-project.org/g/cip-dev/message/15440 From: Biju Das commit b4b5cd61a6fdd92ede0dc39f0850a182affd1323 upstream. Rename rzg2l_irq_eoi()->rzg2l_clear_irq_int() and simplify the code by removing redundant priv local variable. Suggested-by: Geert Uytterhoeven Signed-off-by: Biju Das Signed-off-by: Thomas Gleixner Signed-off-by: Claudiu Beznea --- drivers/irqchip/irq-renesas-rzg2l.c | 7 +++---- 1 file changed, 3 insertions(+), 4 deletions(-) diff --git a/drivers/irqchip/irq-renesas-rzg2l.c b/drivers/irqchip/irq-renesas-rzg2l.c index 315c58d99376..09bae23e5c8f 100644 --- a/drivers/irqchip/irq-renesas-rzg2l.c +++ b/drivers/irqchip/irq-renesas-rzg2l.c @@ -73,10 +73,9 @@ static struct rzg2l_irqc_priv *irq_data_to_priv(struct irq_data *data) return data->domain->host_data; } -static void rzg2l_irq_eoi(struct irq_data *d) +static void rzg2l_clear_irq_int(struct rzg2l_irqc_priv *priv, unsigned int hwirq) { - unsigned int hw_irq = irqd_to_hwirq(d) - IRQC_IRQ_START; - struct rzg2l_irqc_priv *priv = irq_data_to_priv(d); + unsigned int hw_irq = hwirq - IRQC_IRQ_START; u32 bit = BIT(hw_irq); u32 iitsr, iscr; @@ -120,7 +119,7 @@ static void rzg2l_irqc_eoi(struct irq_data *d) raw_spin_lock(&priv->lock); if (hw_irq >= IRQC_IRQ_START && hw_irq <= IRQC_IRQ_COUNT) - rzg2l_irq_eoi(d); + rzg2l_clear_irq_int(priv, hw_irq); else if (hw_irq >= IRQC_TINT_START && hw_irq < IRQC_NUM_IRQ) rzg2l_clear_tint_int(priv, hw_irq); raw_spin_unlock(&priv->lock); From patchwork Wed Mar 27 08:17:44 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Claudiu Beznea X-Patchwork-Id: 13606180 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from aws-us-west-2-korg-lkml-1.web.codeaurora.org (localhost.localdomain [127.0.0.1]) by smtp.lore.kernel.org (Postfix) with ESMTP id 34F89CD129E for ; Wed, 27 Mar 2024 10:37:06 +0000 (UTC) Received: from mail-lf1-f45.google.com (mail-lf1-f45.google.com [209.85.167.45]) by mx.groups.io with SMTP id smtpd.web11.32302.1711527508313419931 for ; Wed, 27 Mar 2024 01:18:28 -0700 Authentication-Results: mx.groups.io; dkim=pass header.i=@tuxon.dev header.s=google header.b=MaNEYmnk; spf=pass (domain: tuxon.dev, ip: 209.85.167.45, mailfrom: claudiu.beznea@tuxon.dev) Received: by mail-lf1-f45.google.com with SMTP id 2adb3069b0e04-515a81928faso4095957e87.1 for ; Wed, 27 Mar 2024 01:18:28 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=tuxon.dev; s=google; t=1711527506; x=1712132306; darn=lists.cip-project.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=79HGkxc3zqzaRqpIOSMeiSnu105LzImNQUCew6Iy78E=; b=MaNEYmnkdnBKKN3kBlBmRoK8hY60K0fgPCU0MuoHuTm0x1w+7Kxykcklmsimj1fUaz RWJaiEVV7y79TzKLC7aLPdf2Is7FG19TbS5vB3fQfPl/I6pcgirx95K+j+2iTXqVtrXt 5zUICJdqSrTwynfvHGq5AYvPRbdzr34wAR1T8r9lBH1563LsZOVQYYl97gq6csXrOD40 4dnaKCoUbucvJJAp1QLUs/+2H1rq0ZezEnv67guWRLlRrG8s0qLL4T5kBotudrrPTs7p nVistMxSEB0uFa/7MN4lJCE5UO8KX+qzzHh3OlAloF7C7nFgOdFcW3IVu0B2vOpY4CfH sEUg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1711527506; x=1712132306; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=79HGkxc3zqzaRqpIOSMeiSnu105LzImNQUCew6Iy78E=; b=eadywWQkIfgBfTbg7nqPzqz4jKfXDS5wRY9m5jPhnUF00om/vHdkVzw4I/o2iUpGjx KCrio0QkEXiMkd+R4MxgPh4oGTBckSW7M8BTbsLXFj6SBosoynaUlZbJcv1ypc+C2DkE lQg8IySErb5iwfV37UM2KspHfZk+zrbkPfcYWQlq+49AspBDzpm4x2Ixjz+GMST97Wbi GtsK/Dieq9ROdSpZ546BNcjdA6hwLUWy7WTGLGvpXFcnFBOroFmZ2L8SNFl0XIQGc3AT PnzS9VDXgMFVYGdi7tuo1xEDKOyTi00VKbnH981vetKbPD6/Nr/PNjsK9ZRI48tD8exU h4/g== X-Gm-Message-State: AOJu0YxwhfGw/Dqxd1TJjh7ZPb7nXZd96c1fb04fYUMkbI0kE1DNkFEg VLwByF08vc7MFA0R3N4gl09ysBlu2S0zt10Z18Wb/VR+4Xkfo8mcJ9LflPT5Zg0= X-Google-Smtp-Source: AGHT+IEU69R4mlPEhe2AR0XWb89XT9JV4dBYxdyvJ4HfhnpdB/0BlG45bJMOhKzsU4WF4iEGZzZqPg== X-Received: by 2002:a05:6512:3082:b0:515:bacd:adbf with SMTP id z2-20020a056512308200b00515bacdadbfmr2704073lfd.34.1711527506629; Wed, 27 Mar 2024 01:18:26 -0700 (PDT) Received: from claudiu-X670E-Pro-RS.. ([82.78.167.144]) by smtp.gmail.com with ESMTPSA id c9-20020a7bc2a9000000b0041493615585sm1353783wmk.39.2024.03.27.01.18.25 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 27 Mar 2024 01:18:26 -0700 (PDT) From: Claudiu X-Google-Original-From: Claudiu To: nobuhiro1.iwamatsu@toshiba.co.jp, pavel@denx.de Cc: cip-dev@lists.cip-project.org, biju.das.jz@bp.renesas.com, prabhakar.mahadev-lad.rj@bp.renesas.com, claudiu.beznea@tuxon.dev Subject: [PATCH 5.10.y-cip 24/36] irqchip/renesas-rzg2l: Prevent spurious interrupts when setting trigger type Date: Wed, 27 Mar 2024 10:17:44 +0200 Message-Id: <20240327081756.2228036-25-claudiu.beznea.uj@bp.renesas.com> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20240327081756.2228036-1-claudiu.beznea.uj@bp.renesas.com> References: <20240327081756.2228036-1-claudiu.beznea.uj@bp.renesas.com> MIME-Version: 1.0 List-Id: X-Webhook-Received: from li982-79.members.linode.com [45.33.32.79] by aws-us-west-2-korg-lkml-1.web.codeaurora.org with HTTPS for ; Wed, 27 Mar 2024 10:37:06 -0000 X-Groupsio-URL: https://lists.cip-project.org/g/cip-dev/message/15441 From: Biju Das commit 853a6030303f8a8fa54929b68e5665d9b21aa405 upstream. RZ/G2L interrupt chips require that the interrupt is masked before changing the NMI, IRQ, TINT interrupt settings. Aside of that, after setting an edge trigger type it is required to clear the interrupt status register in order to avoid spurious interrupts. The current implementation fails to do either of that and therefore is prone to generate spurious interrupts when setting the trigger type. Address this by: - Ensuring that the interrupt is masked at the chip level across the update for the TINT chip - Clearing the interrupt status register after updating the trigger mode for edge type interrupts [ tglx: Massaged changelog and reverted the spin_lock_irqsave() change as the set_type() callback is always called with interrupts disabled. ] Fixes: 3fed09559cd8 ("irqchip: Add RZ/G2L IA55 Interrupt Controller driver") Signed-off-by: Biju Das Signed-off-by: Thomas Gleixner Signed-off-by: Claudiu Beznea --- drivers/irqchip/irq-renesas-rzg2l.c | 36 +++++++++++++++++++++++++---- 1 file changed, 32 insertions(+), 4 deletions(-) diff --git a/drivers/irqchip/irq-renesas-rzg2l.c b/drivers/irqchip/irq-renesas-rzg2l.c index 09bae23e5c8f..7b20af3886c7 100644 --- a/drivers/irqchip/irq-renesas-rzg2l.c +++ b/drivers/irqchip/irq-renesas-rzg2l.c @@ -169,8 +169,10 @@ static void rzg2l_irqc_irq_enable(struct irq_data *d) static int rzg2l_irq_set_type(struct irq_data *d, unsigned int type) { - unsigned int hw_irq = irqd_to_hwirq(d) - IRQC_IRQ_START; struct rzg2l_irqc_priv *priv = irq_data_to_priv(d); + unsigned int hwirq = irqd_to_hwirq(d); + u32 iitseln = hwirq - IRQC_IRQ_START; + bool clear_irq_int = false; u16 sense, tmp; switch (type & IRQ_TYPE_SENSE_MASK) { @@ -180,14 +182,17 @@ static int rzg2l_irq_set_type(struct irq_data *d, unsigned int type) case IRQ_TYPE_EDGE_FALLING: sense = IITSR_IITSEL_EDGE_FALLING; + clear_irq_int = true; break; case IRQ_TYPE_EDGE_RISING: sense = IITSR_IITSEL_EDGE_RISING; + clear_irq_int = true; break; case IRQ_TYPE_EDGE_BOTH: sense = IITSR_IITSEL_EDGE_BOTH; + clear_irq_int = true; break; default: @@ -196,21 +201,40 @@ static int rzg2l_irq_set_type(struct irq_data *d, unsigned int type) raw_spin_lock(&priv->lock); tmp = readl_relaxed(priv->base + IITSR); - tmp &= ~IITSR_IITSEL_MASK(hw_irq); - tmp |= IITSR_IITSEL(hw_irq, sense); + tmp &= ~IITSR_IITSEL_MASK(iitseln); + tmp |= IITSR_IITSEL(iitseln, sense); + if (clear_irq_int) + rzg2l_clear_irq_int(priv, hwirq); writel_relaxed(tmp, priv->base + IITSR); raw_spin_unlock(&priv->lock); return 0; } +static u32 rzg2l_disable_tint_and_set_tint_source(struct irq_data *d, struct rzg2l_irqc_priv *priv, + u32 reg, u32 tssr_offset, u8 tssr_index) +{ + u32 tint = (u32)(uintptr_t)irq_data_get_irq_chip_data(d); + u32 tien = reg & (TIEN << TSSEL_SHIFT(tssr_offset)); + + /* Clear the relevant byte in reg */ + reg &= ~(TSSEL_MASK << TSSEL_SHIFT(tssr_offset)); + /* Set TINT and leave TIEN clear */ + reg |= tint << TSSEL_SHIFT(tssr_offset); + writel_relaxed(reg, priv->base + TSSR(tssr_index)); + + return reg | tien; +} + static int rzg2l_tint_set_edge(struct irq_data *d, unsigned int type) { struct rzg2l_irqc_priv *priv = irq_data_to_priv(d); unsigned int hwirq = irqd_to_hwirq(d); u32 titseln = hwirq - IRQC_TINT_START; + u32 tssr_offset = TSSR_OFFSET(titseln); + u8 tssr_index = TSSR_INDEX(titseln); u8 index, sense; - u32 reg; + u32 reg, tssr; switch (type & IRQ_TYPE_SENSE_MASK) { case IRQ_TYPE_EDGE_RISING: @@ -232,10 +256,14 @@ static int rzg2l_tint_set_edge(struct irq_data *d, unsigned int type) } raw_spin_lock(&priv->lock); + tssr = readl_relaxed(priv->base + TSSR(tssr_index)); + tssr = rzg2l_disable_tint_and_set_tint_source(d, priv, tssr, tssr_offset, tssr_index); reg = readl_relaxed(priv->base + TITSR(index)); reg &= ~(IRQ_MASK << (titseln * TITSEL_WIDTH)); reg |= sense << (titseln * TITSEL_WIDTH); writel_relaxed(reg, priv->base + TITSR(index)); + rzg2l_clear_tint_int(priv, hwirq); + writel_relaxed(tssr, priv->base + TSSR(tssr_index)); raw_spin_unlock(&priv->lock); return 0; From patchwork Wed Mar 27 08:17:45 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Claudiu Beznea X-Patchwork-Id: 13606188 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from aws-us-west-2-korg-lkml-1.web.codeaurora.org (localhost.localdomain [127.0.0.1]) by smtp.lore.kernel.org (Postfix) with ESMTP id 4DD28CD12A6 for ; Wed, 27 Mar 2024 10:37:06 +0000 (UTC) Received: from mail-wm1-f49.google.com (mail-wm1-f49.google.com [209.85.128.49]) by mx.groups.io with SMTP id smtpd.web11.32303.1711527509969048704 for ; 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([82.78.167.144]) by smtp.gmail.com with ESMTPSA id c9-20020a7bc2a9000000b0041493615585sm1353783wmk.39.2024.03.27.01.18.26 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 27 Mar 2024 01:18:27 -0700 (PDT) From: Claudiu X-Google-Original-From: Claudiu To: nobuhiro1.iwamatsu@toshiba.co.jp, pavel@denx.de Cc: cip-dev@lists.cip-project.org, biju.das.jz@bp.renesas.com, prabhakar.mahadev-lad.rj@bp.renesas.com, claudiu.beznea@tuxon.dev Subject: [PATCH 5.10.y-cip 25/36] irqchip/renesas-rzg2l: Do not set TIEN and TINT source at the same time Date: Wed, 27 Mar 2024 10:17:45 +0200 Message-Id: <20240327081756.2228036-26-claudiu.beznea.uj@bp.renesas.com> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20240327081756.2228036-1-claudiu.beznea.uj@bp.renesas.com> References: <20240327081756.2228036-1-claudiu.beznea.uj@bp.renesas.com> MIME-Version: 1.0 List-Id: X-Webhook-Received: from li982-79.members.linode.com [45.33.32.79] by aws-us-west-2-korg-lkml-1.web.codeaurora.org with HTTPS for ; Wed, 27 Mar 2024 10:37:06 -0000 X-Groupsio-URL: https://lists.cip-project.org/g/cip-dev/message/15442 From: Biju Das commit dce0919c83c325ac9dec5bc8838d5de6d32c01b1 upstream. As per the hardware team, TIEN and TINT source should not set at the same time due to a possible hardware race leading to spurious IRQ. Currently on some scenarios hardware settings for TINT detection is not in sync with TINT source as the enable/disable overrides source setting value leading to hardware inconsistent state. For eg: consider the case GPIOINT0 is used as TINT interrupt and configuring GPIOINT5 as edge type. During rzg2l_irq_set_type(), TINT source for GPIOINT5 is set. On disable(), clearing of the entire bytes of TINT source selection for GPIOINT5 is same as GPIOINT0 with TIEN disabled. Apart from this during enable(), the setting of GPIOINT5 with TIEN results in spurious IRQ as due to a HW race, it is possible that IP can use the TIEN with previous source value (GPIOINT0). So, just update TIEN during enable/disable as TINT source is already set during rzg2l_irq_set_type(). This will make the consistent hardware settings for detection method tied with TINT source and allows to simplify the code. Signed-off-by: Biju Das Signed-off-by: Thomas Gleixner Signed-off-by: Claudiu Beznea --- drivers/irqchip/irq-renesas-rzg2l.c | 5 ++--- 1 file changed, 2 insertions(+), 3 deletions(-) diff --git a/drivers/irqchip/irq-renesas-rzg2l.c b/drivers/irqchip/irq-renesas-rzg2l.c index 7b20af3886c7..628b1c606bcf 100644 --- a/drivers/irqchip/irq-renesas-rzg2l.c +++ b/drivers/irqchip/irq-renesas-rzg2l.c @@ -139,7 +139,7 @@ static void rzg2l_irqc_irq_disable(struct irq_data *d) raw_spin_lock(&priv->lock); reg = readl_relaxed(priv->base + TSSR(tssr_index)); - reg &= ~(TSSEL_MASK << TSSEL_SHIFT(tssr_offset)); + reg &= ~(TIEN << TSSEL_SHIFT(tssr_offset)); writel_relaxed(reg, priv->base + TSSR(tssr_index)); raw_spin_unlock(&priv->lock); } @@ -151,7 +151,6 @@ static void rzg2l_irqc_irq_enable(struct irq_data *d) unsigned int hw_irq = irqd_to_hwirq(d); if (hw_irq >= IRQC_TINT_START && hw_irq < IRQC_NUM_IRQ) { - unsigned long tint = (uintptr_t)irq_data_get_irq_chip_data(d); struct rzg2l_irqc_priv *priv = irq_data_to_priv(d); u32 offset = hw_irq - IRQC_TINT_START; u32 tssr_offset = TSSR_OFFSET(offset); @@ -160,7 +159,7 @@ static void rzg2l_irqc_irq_enable(struct irq_data *d) raw_spin_lock(&priv->lock); reg = readl_relaxed(priv->base + TSSR(tssr_index)); - reg |= (TIEN | tint) << TSSEL_SHIFT(tssr_offset); + reg |= TIEN << TSSEL_SHIFT(tssr_offset); writel_relaxed(reg, priv->base + TSSR(tssr_index)); raw_spin_unlock(&priv->lock); } From patchwork Wed Mar 27 08:17:46 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Claudiu Beznea X-Patchwork-Id: 13606177 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from aws-us-west-2-korg-lkml-1.web.codeaurora.org (localhost.localdomain [127.0.0.1]) by smtp.lore.kernel.org (Postfix) with ESMTP id 2FC15CD129C for ; Wed, 27 Mar 2024 10:37:06 +0000 (UTC) Received: from mail-wm1-f54.google.com (mail-wm1-f54.google.com [209.85.128.54]) by mx.groups.io with SMTP id smtpd.web10.32445.1711527510937425671 for ; Wed, 27 Mar 2024 01:18:31 -0700 Authentication-Results: mx.groups.io; dkim=pass header.i=@tuxon.dev header.s=google header.b=lcv476db; spf=pass (domain: tuxon.dev, ip: 209.85.128.54, mailfrom: claudiu.beznea@tuxon.dev) Received: by mail-wm1-f54.google.com with SMTP id 5b1f17b1804b1-41494c43058so1887625e9.1 for ; Wed, 27 Mar 2024 01:18:30 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=tuxon.dev; s=google; t=1711527509; x=1712132309; darn=lists.cip-project.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=J13GT5CFKd8XNBCAXRaaqJ905F64BPOCzVVdHk3M9XE=; b=lcv476dbwBjIpLDAf0PIyLy6tIfILaHFOEPNLgLjIoFKBzuoEnkv8R9Rbt/CLJNt4i afUSvYwkbm/MyjyWbBPmgD4QqFjpe8hvl3zGt0h2T1hDjcLQ9t0K0Pe10+SWYrFa0DsX mzspoGwX/pV9NP4QLHM0jOx9RwvsS5DFD6G/FakyAvsl5RxvSi4ysDMWQObcl078wXIJ ZIomh6mFy2FWi18mmVH8pde/CH3byp1KZXeSTl/O532djTFnaMA0skaMSR2XlIkJ5c9R MJbMcoLelAr8gFof6cdhPjReovXmkedHwbanSppqiixGYY0NJOXMUgjciOn+JmLJINfB OW6g== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1711527509; x=1712132309; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=J13GT5CFKd8XNBCAXRaaqJ905F64BPOCzVVdHk3M9XE=; b=BoStTBQa1QTGEa5wWDlq5WtEi9pVmyl+vK6gZURDQiyeLpSMDLA1/hbDb/rMkiKcgZ g5PGa+BuVTaL3icsUrt0W5tS6fsf9j5F3rYu9h7eJtaUm9zCZeb8o9qm6LoTBBi2YTj3 hvmVf7juG9hrcQLx/yncakhAM+arih1mBSTpzAaiaPLDeHCxUOC8Ge+gxF0QCbSZOMSl EFNoqolg96G8rhMYhbsyZtugAEMSHGXhf5wWprXgzWqnHhm08miFtaTKlvetAIHQy7hQ cBHETsv7FuZpSJrbt3WH0oOrDDBOKYFOsvzpZERk/cAZJP7tbvE72EmvjGmWnzu2ct/E i7Sw== X-Gm-Message-State: AOJu0Yzng0i+RbiepCYF3CtG6aO3UHHx/+MxtlxSH/NUFu/HhVxSo1yE 243fwQm731HNULy2Fw9isZpyG8d/wiwhkmhWWb+9wzo0wvgAFeT89WTpwzxvQpo= X-Google-Smtp-Source: AGHT+IFmr8WoPSSH++XsTP0OltMdVdtsWxJdpT2oarjjst16JVzTy94ELyNIMx0cAVNaeTR2d2WlBw== X-Received: by 2002:a05:600c:444a:b0:414:9075:114a with SMTP id v10-20020a05600c444a00b004149075114amr2391208wmn.2.1711527509472; Wed, 27 Mar 2024 01:18:29 -0700 (PDT) Received: from claudiu-X670E-Pro-RS.. ([82.78.167.144]) by smtp.gmail.com with ESMTPSA id c9-20020a7bc2a9000000b0041493615585sm1353783wmk.39.2024.03.27.01.18.28 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 27 Mar 2024 01:18:29 -0700 (PDT) From: Claudiu X-Google-Original-From: Claudiu To: nobuhiro1.iwamatsu@toshiba.co.jp, pavel@denx.de Cc: cip-dev@lists.cip-project.org, biju.das.jz@bp.renesas.com, prabhakar.mahadev-lad.rj@bp.renesas.com, claudiu.beznea@tuxon.dev Subject: [PATCH 5.10.y-cip 26/36] soc: renesas: Kconfig: Enable IRQC driver for RZ/G2L SoC Date: Wed, 27 Mar 2024 10:17:46 +0200 Message-Id: <20240327081756.2228036-27-claudiu.beznea.uj@bp.renesas.com> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20240327081756.2228036-1-claudiu.beznea.uj@bp.renesas.com> References: <20240327081756.2228036-1-claudiu.beznea.uj@bp.renesas.com> MIME-Version: 1.0 List-Id: X-Webhook-Received: from li982-79.members.linode.com [45.33.32.79] by aws-us-west-2-korg-lkml-1.web.codeaurora.org with HTTPS for ; Wed, 27 Mar 2024 10:37:06 -0000 X-Groupsio-URL: https://lists.cip-project.org/g/cip-dev/message/15443 From: Lad Prabhakar commit 41a21e578da4986685f013d45454a12457f01180 upstream. Select RENESAS_RZG2L_IRQC config option if ARCH_RZG2L is enabled so that IRQC driver is enabled on RZ/G2L (and alike) SoC's. Signed-off-by: Lad Prabhakar Link: https://lore.kernel.org/r/20220718192824.7246-1-prabhakar.mahadev-lad.rj@bp.renesas.com Signed-off-by: Geert Uytterhoeven Signed-off-by: Claudiu Beznea --- drivers/soc/renesas/Kconfig | 1 + 1 file changed, 1 insertion(+) diff --git a/drivers/soc/renesas/Kconfig b/drivers/soc/renesas/Kconfig index d8d0d37948ad..6256fd3b6efd 100644 --- a/drivers/soc/renesas/Kconfig +++ b/drivers/soc/renesas/Kconfig @@ -44,6 +44,7 @@ config ARCH_RZG2L bool select PM select PM_GENERIC_DOMAINS + select RENESAS_RZG2L_IRQC config ARCH_RZN1 bool From patchwork Wed Mar 27 08:17:47 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Claudiu Beznea X-Patchwork-Id: 13606194 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from aws-us-west-2-korg-lkml-1.web.codeaurora.org (localhost.localdomain [127.0.0.1]) by smtp.lore.kernel.org (Postfix) with ESMTP id 565D0CD12A5 for ; Wed, 27 Mar 2024 10:37:06 +0000 (UTC) Received: from mail-wm1-f46.google.com (mail-wm1-f46.google.com [209.85.128.46]) by mx.groups.io with SMTP id smtpd.web10.32446.1711527512101150666 for ; Wed, 27 Mar 2024 01:18:32 -0700 Authentication-Results: mx.groups.io; dkim=pass header.i=@tuxon.dev header.s=google header.b=lHi815mu; spf=pass (domain: tuxon.dev, ip: 209.85.128.46, mailfrom: claudiu.beznea@tuxon.dev) Received: by mail-wm1-f46.google.com with SMTP id 5b1f17b1804b1-4141156f245so43040475e9.2 for ; Wed, 27 Mar 2024 01:18:31 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=tuxon.dev; s=google; t=1711527510; x=1712132310; darn=lists.cip-project.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=PdyZgfh+0fXCvIgscuY3rO8KnCqhWo3mQ+e3XrXfjbc=; b=lHi815mu9oMU+E8hUwmpVZxB9xhQWbcCdL6ud2jDsLNhIfxJbSITqvl7JJDBYYryw0 PDrFKamarNGOjT73VRqjpF3v7hiyBOwXJmtm60tFIJmH6e1rbbUg0VRMUQuyinDls7Ap 9+xu0YnJ+WUwTcXIRcnjDu8lDFzmfVDh4DcNiz0dxaNimZXxCKn2wCdtXGPku5CSxfL/ 1/J7Jmcv/4JcNXX5pn5whQHBrL3FXlGsvKqBYJ5NJswhhMuJ/Id7SOObOfOpgxZg5md3 anKn+0J2n8gO+jhlKdeexeQ+VGPQhDsMfv3Emd1W83x503pmAb4hc8N1eD5dS6jWy0o3 A2rA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1711527510; x=1712132310; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=PdyZgfh+0fXCvIgscuY3rO8KnCqhWo3mQ+e3XrXfjbc=; b=Z4ugCZSQvbVBnWTnicOOxNzXbCfSDgvliyTSiKV6Cl0ZCOq7PpcG3NlaGwE3UkITPo QZyh6eMjxybe+NaaIz4wuyl/GCAVYdvR7XSvKk84jkCj1dfiraVTIvsi1HXEUmzk2Ws6 kOYejuZb3A7GxzHbK/NE3CL2X9y4vgcKEDY/fJTVWkBZPJeTd9/lY7mUUdlrD/px7dM4 HJZRHNM6ifIyKw4zIubTFGkQ2AK0opWAQcogsxp3Yn8VjIkLkmHvWq8Qg30YakDb+H4R gwYFNfVobMpf+AxSsmWJ2u4hv8UKrBXx84+5m+6xJfJyrn8ujzZqQC6Sx3dgiPbeppSf LHBA== X-Gm-Message-State: AOJu0YznT8rxJy4/GoxEVNlX5UX3vPEBscrwt/fAAW7A05wlclv1b20L ilSnT6TdAqTSGW25S6QTqnLzHEMz2h6Y+Zj7Dw0l1My/f8TJxPfH03qme6OQs1E= X-Google-Smtp-Source: AGHT+IF0aAgcitJw3O21ue+ek9gxNjc9KlZt/4IgtaWCwErggQ/rvhLv33oFF6MBOA/ghnaVkrA4Gg== X-Received: by 2002:a05:600c:4fc1:b0:412:e70a:ab8a with SMTP id o1-20020a05600c4fc100b00412e70aab8amr1294314wmq.25.1711527510453; Wed, 27 Mar 2024 01:18:30 -0700 (PDT) Received: from claudiu-X670E-Pro-RS.. ([82.78.167.144]) by smtp.gmail.com with ESMTPSA id c9-20020a7bc2a9000000b0041493615585sm1353783wmk.39.2024.03.27.01.18.29 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 27 Mar 2024 01:18:30 -0700 (PDT) From: Claudiu X-Google-Original-From: Claudiu To: nobuhiro1.iwamatsu@toshiba.co.jp, pavel@denx.de Cc: cip-dev@lists.cip-project.org, biju.das.jz@bp.renesas.com, prabhakar.mahadev-lad.rj@bp.renesas.com, claudiu.beznea@tuxon.dev Subject: [PATCH 5.10.y-cip 27/36] arm64: dts: renesas: r9a07g043u: Add IRQC node Date: Wed, 27 Mar 2024 10:17:47 +0200 Message-Id: <20240327081756.2228036-28-claudiu.beznea.uj@bp.renesas.com> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20240327081756.2228036-1-claudiu.beznea.uj@bp.renesas.com> References: <20240327081756.2228036-1-claudiu.beznea.uj@bp.renesas.com> MIME-Version: 1.0 List-Id: X-Webhook-Received: from li982-79.members.linode.com [45.33.32.79] by aws-us-west-2-korg-lkml-1.web.codeaurora.org with HTTPS for ; Wed, 27 Mar 2024 10:37:06 -0000 X-Groupsio-URL: https://lists.cip-project.org/g/cip-dev/message/15444 From: Lad Prabhakar commit 48ab6eddd8bbcf7e9c8ae27bf42d0b52a777aaba upstream. Add IRQC node to R9A07G043 (RZ/G2UL) SoC DTSI. Signed-off-by: Lad Prabhakar Reviewed-by: Geert Uytterhoeven Link: https://lore.kernel.org/r/20230102221815.273719-5-prabhakar.mahadev-lad.rj@bp.renesas.com Signed-off-by: Geert Uytterhoeven Signed-off-by: Claudiu Beznea --- arch/arm64/boot/dts/renesas/r9a07g043u.dtsi | 68 +++++++++++++++++++++ 1 file changed, 68 insertions(+) diff --git a/arch/arm64/boot/dts/renesas/r9a07g043u.dtsi b/arch/arm64/boot/dts/renesas/r9a07g043u.dtsi index b8bf06b51235..a6e777aee02e 100644 --- a/arch/arm64/boot/dts/renesas/r9a07g043u.dtsi +++ b/arch/arm64/boot/dts/renesas/r9a07g043u.dtsi @@ -51,6 +51,74 @@ timer { &soc { interrupt-parent = <&gic>; + irqc: interrupt-controller@110a0000 { + compatible = "renesas,r9a07g043u-irqc", + "renesas,rzg2l-irqc"; + reg = <0 0x110a0000 0 0x10000>; + #interrupt-cells = <2>; + #address-cells = <0>; + interrupt-controller; + interrupts = , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + ; + interrupt-names = "nmi", + "irq0", "irq1", "irq2", "irq3", + "irq4", "irq5", "irq6", "irq7", + "tint0", "tint1", "tint2", "tint3", + "tint4", "tint5", "tint6", "tint7", + "tint8", "tint9", "tint10", "tint11", + "tint12", "tint13", "tint14", "tint15", + "tint16", "tint17", "tint18", "tint19", + "tint20", "tint21", "tint22", "tint23", + "tint24", "tint25", "tint26", "tint27", + "tint28", "tint29", "tint30", "tint31", + "bus-err"; + clocks = <&cpg CPG_MOD R9A07G043_IA55_CLK>, + <&cpg CPG_MOD R9A07G043_IA55_PCLK>; + clock-names = "clk", "pclk"; + power-domains = <&cpg>; + resets = <&cpg R9A07G043_IA55_RESETN>; + }; + gic: interrupt-controller@11900000 { compatible = "arm,gic-v3"; #interrupt-cells = <3>; From patchwork Wed Mar 27 08:17:48 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Claudiu Beznea X-Patchwork-Id: 13606178 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from aws-us-west-2-korg-lkml-1.web.codeaurora.org (localhost.localdomain [127.0.0.1]) by smtp.lore.kernel.org (Postfix) with ESMTP id 2A025CD129D for ; Wed, 27 Mar 2024 10:37:06 +0000 (UTC) Received: from mail-wm1-f49.google.com (mail-wm1-f49.google.com [209.85.128.49]) by mx.groups.io with SMTP id smtpd.web10.32447.1711527512992185459 for ; Wed, 27 Mar 2024 01:18:33 -0700 Authentication-Results: mx.groups.io; dkim=pass header.i=@tuxon.dev header.s=google header.b=BXtlQ4uv; spf=pass (domain: tuxon.dev, ip: 209.85.128.49, mailfrom: claudiu.beznea@tuxon.dev) Received: by mail-wm1-f49.google.com with SMTP id 5b1f17b1804b1-41495dce900so584755e9.0 for ; Wed, 27 Mar 2024 01:18:32 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=tuxon.dev; s=google; t=1711527511; x=1712132311; darn=lists.cip-project.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=NA/nZ1SUt8zbviRtEJNZhpS2YUAb5gd6lR6iarWytMY=; b=BXtlQ4uv7rmLX2ohufnPzlWkQmFVjiEiR2Tdf7YmFUBXgEjO827MgypjUbkrioDvMl LQDactmZZ+q4xPZ0g8mKPVfSiFtO8Jk1UNRVmJlkqWPBGcPjaX0RwAMjNfKkW9JB7Ndn Jh8s1/pLspm/mIOJCxQCmUJ/jwvAfDwIFuLml6+9SWVZPfuOuguwpGs/S363siLT7Dom 3H1n6ePB4fINC55tW7nut6Xf+5wHbfDBQT2PnllesVCDq9iS6NBAxZVDAnkpp1e6iGCa ADvE4m/xVHcMz8r7W48kJ+ykWwlSGd+FnMT6scXgEZue3UzAe2R+aCimwjOvbjgfEju4 nDJg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1711527511; x=1712132311; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=NA/nZ1SUt8zbviRtEJNZhpS2YUAb5gd6lR6iarWytMY=; b=ewhylgs8o+t9D8n3b0TDkYMjc7BxvCaaScvv0DOmY2KYKhK/wKTOtu19Ukg/JMYjAC y89V3DUfjoXB7OmlsHxe+FExBIsithvY6LtYGXUPL2Z5/mp6Tjvx6FxC4PnCAr46xlgm ecFqaMkohak/5zT/Ct0yti6VlCG/BbmhCXqCZBefFN+T7g/GWnF9ED1Wja7bNw7RlSit B3OdsZm3FPPIP2JMWjzoesOXmJm522yh1JJ52ljP5yxeZ3clpVwAyKFMFskrdmYxWf13 r/zj9DuriWp/f4WKdtuNIgyew4yCn3xv7mZQNuRp+AvV3R8aDZ/UMcVx/9Om2JsYtga1 9bNQ== X-Gm-Message-State: AOJu0Yxdy4wLwkYHV+AH5jjBCHYRACeQznIXu1ku82lFuOFl+Tezsilh gd4KhVKLPpC7yjJvS3o25wmGD3npPtjF+4KZkxEYKA4xZ3jDXyYwllcmlXIsS3I= X-Google-Smtp-Source: AGHT+IFS75TcljIXxYLCddQFjtbYzc8BO9WRiEjp8F/qFUMVV7f+ygx8JC4cUrhtbpnKeMALd98mVA== X-Received: by 2002:a05:600c:3d89:b0:414:95ae:51ff with SMTP id bi9-20020a05600c3d8900b0041495ae51ffmr333121wmb.20.1711527511502; Wed, 27 Mar 2024 01:18:31 -0700 (PDT) Received: from claudiu-X670E-Pro-RS.. ([82.78.167.144]) by smtp.gmail.com with ESMTPSA id c9-20020a7bc2a9000000b0041493615585sm1353783wmk.39.2024.03.27.01.18.30 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 27 Mar 2024 01:18:31 -0700 (PDT) From: Claudiu X-Google-Original-From: Claudiu To: nobuhiro1.iwamatsu@toshiba.co.jp, pavel@denx.de Cc: cip-dev@lists.cip-project.org, biju.das.jz@bp.renesas.com, prabhakar.mahadev-lad.rj@bp.renesas.com, claudiu.beznea@tuxon.dev Subject: [PATCH 5.10.y-cip 28/36] arm64: dts: renesas: r9a07g044: Add IRQC node Date: Wed, 27 Mar 2024 10:17:48 +0200 Message-Id: <20240327081756.2228036-29-claudiu.beznea.uj@bp.renesas.com> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20240327081756.2228036-1-claudiu.beznea.uj@bp.renesas.com> References: <20240327081756.2228036-1-claudiu.beznea.uj@bp.renesas.com> MIME-Version: 1.0 List-Id: X-Webhook-Received: from li982-79.members.linode.com [45.33.32.79] by aws-us-west-2-korg-lkml-1.web.codeaurora.org with HTTPS for ; Wed, 27 Mar 2024 10:37:06 -0000 X-Groupsio-URL: https://lists.cip-project.org/g/cip-dev/message/15445 From: Lad Prabhakar commit 5edc51af5b304a91a957b862d150cd8a89c4aa97 upstream. Add IRQC node to R9A07G044 (RZ/G2L) SoC DTSI. Signed-off-by: Lad Prabhakar Link: https://lore.kernel.org/r/20220718195651.7711-2-prabhakar.mahadev-lad.rj@bp.renesas.com Signed-off-by: Geert Uytterhoeven Signed-off-by: Claudiu Beznea --- arch/arm64/boot/dts/renesas/r9a07g044.dtsi | 55 ++++++++++++++++++++++ 1 file changed, 55 insertions(+) diff --git a/arch/arm64/boot/dts/renesas/r9a07g044.dtsi b/arch/arm64/boot/dts/renesas/r9a07g044.dtsi index f7edace31807..881fecc8d0bc 100644 --- a/arch/arm64/boot/dts/renesas/r9a07g044.dtsi +++ b/arch/arm64/boot/dts/renesas/r9a07g044.dtsi @@ -775,6 +775,61 @@ pinctrl: pinctrl@11030000 { <&cpg R9A07G044_GPIO_SPARE_RESETN>; }; + irqc: interrupt-controller@110a0000 { + compatible = "renesas,r9a07g044-irqc", + "renesas,rzg2l-irqc"; + #interrupt-cells = <2>; + #address-cells = <0>; + interrupt-controller; + reg = <0 0x110a0000 0 0x10000>; + interrupts = , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + ; + clocks = <&cpg CPG_MOD R9A07G044_IA55_CLK>, + <&cpg CPG_MOD R9A07G044_IA55_PCLK>; + clock-names = "clk", "pclk"; + power-domains = <&cpg>; + resets = <&cpg R9A07G044_IA55_RESETN>; + }; + dmac: dma-controller@11820000 { compatible = "renesas,r9a07g044-dmac", "renesas,rz-dmac"; From patchwork Wed Mar 27 08:17:49 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Claudiu Beznea X-Patchwork-Id: 13606179 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from aws-us-west-2-korg-lkml-1.web.codeaurora.org (localhost.localdomain [127.0.0.1]) by smtp.lore.kernel.org (Postfix) with ESMTP id 22906CD1298 for ; Wed, 27 Mar 2024 10:37:06 +0000 (UTC) Received: from mail-lj1-f175.google.com (mail-lj1-f175.google.com [209.85.208.175]) by mx.groups.io with SMTP id smtpd.web11.32306.1711527514297422374 for ; Wed, 27 Mar 2024 01:18:34 -0700 Authentication-Results: mx.groups.io; dkim=pass header.i=@tuxon.dev header.s=google header.b=kQVnhycQ; spf=pass (domain: tuxon.dev, ip: 209.85.208.175, mailfrom: claudiu.beznea@tuxon.dev) Received: by mail-lj1-f175.google.com with SMTP id 38308e7fff4ca-2d094bc2244so84022131fa.1 for ; Wed, 27 Mar 2024 01:18:34 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=tuxon.dev; s=google; t=1711527512; x=1712132312; darn=lists.cip-project.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=gndqMjqTXWbuAAMSpbCUpgJoNh7MBvK07glniHFUq4s=; b=kQVnhycQ04Ux2Hy+5xuDy6xwSB2EiDYSOu1oeWoUCb+v3fADX4vTwrGDjUdqvs81ok iJeRZQDYVjcfZ7zvW+QHxrXWGD6wARYA5MzUW/AgCm1tNltUE/VtvLp58mx/TxPytapT jPIsFg+ijw3gvXMB4eyaeOVO/PD1daaTBntCop1RlWyx/kA+rFMTLE3LWkfnXEC3WKBr M7jZ1UY/b960Po/e7OX4wMK2ORO1XQo8v8XqagLqDi0ZBT29WjxzOlfQ8g6Ls3zLg7kW xXpua5qUJohUkzPWg0u97L42y0HguFRcbYOxjA2e1gjMPpCIkcpPGm55dwF8/1nwjo3n zbag== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1711527512; x=1712132312; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=gndqMjqTXWbuAAMSpbCUpgJoNh7MBvK07glniHFUq4s=; b=VRcuXAKmOuNY1n/h+bStHqv4Cfs4Emthl5LAGeZvShHZJ6NTsLAQFgKgci2u/oKyeF aG22xvaPtRZ+agtzGG4iySwI+6A2QGJTLWZkAyQU/2HMu4NgLaQhTYLU9qneFE0LKpr3 ZMDo2oiEqynXfYt1vRw3wQV2msVX6WcH9Bo6c2Tdb502KL5tyVyvYoJ0E9z9eG0t/epT ZeeP5d/B3jBH4ChE2Zd5BFSNu+g7PIb+Q4QZAZlIM7I5ieAcXEg2xksyPxEcS2ObDfyV 2TE6878PLGvFV6PUC0U7RaQJ0TLGIGW1FZ2WcjdlScB5N4pM9gHv0ryrRMYY03TSwTMk QyRw== X-Gm-Message-State: AOJu0YxaTqcPj8b2mUly7bpi0SIPKfywMMWdKU24Jo7LaoFpsqIudvQZ wZmISTVr5yd6rLxIHKxbSulkY7VhZ7OMUO8Ug0kPYx9wAKQSJJT7gC5BKwSdvIc= X-Google-Smtp-Source: AGHT+IH2qlrMcKUh6dr47TONHbMDiOdAgoQDzGa079tvvOgoE0f0X7ZxidniwDpzGOo7j6AK7QmQmQ== X-Received: by 2002:a2e:3c0b:0:b0:2d5:b33c:1f64 with SMTP id j11-20020a2e3c0b000000b002d5b33c1f64mr301809lja.38.1711527512511; Wed, 27 Mar 2024 01:18:32 -0700 (PDT) Received: from claudiu-X670E-Pro-RS.. ([82.78.167.144]) by smtp.gmail.com with ESMTPSA id c9-20020a7bc2a9000000b0041493615585sm1353783wmk.39.2024.03.27.01.18.31 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 27 Mar 2024 01:18:32 -0700 (PDT) From: Claudiu X-Google-Original-From: Claudiu To: nobuhiro1.iwamatsu@toshiba.co.jp, pavel@denx.de Cc: cip-dev@lists.cip-project.org, biju.das.jz@bp.renesas.com, prabhakar.mahadev-lad.rj@bp.renesas.com, claudiu.beznea@tuxon.dev Subject: [PATCH 5.10.y-cip 29/36] arm64: dts: renesas: r9a07g054: Add IRQC node Date: Wed, 27 Mar 2024 10:17:49 +0200 Message-Id: <20240327081756.2228036-30-claudiu.beznea.uj@bp.renesas.com> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20240327081756.2228036-1-claudiu.beznea.uj@bp.renesas.com> References: <20240327081756.2228036-1-claudiu.beznea.uj@bp.renesas.com> MIME-Version: 1.0 List-Id: X-Webhook-Received: from li982-79.members.linode.com [45.33.32.79] by aws-us-west-2-korg-lkml-1.web.codeaurora.org with HTTPS for ; Wed, 27 Mar 2024 10:37:06 -0000 X-Groupsio-URL: https://lists.cip-project.org/g/cip-dev/message/15446 From: Lad Prabhakar commit 379478ab09e0c25709e804b732ee7910d14a3972 upstream. Add IRQC node to R9A07G054 (RZ/V2L) SoC DTSI. Signed-off-by: Lad Prabhakar Link: https://lore.kernel.org/r/20220718195651.7711-4-prabhakar.mahadev-lad.rj@bp.renesas.com Signed-off-by: Geert Uytterhoeven Signed-off-by: Claudiu Beznea --- arch/arm64/boot/dts/renesas/r9a07g054.dtsi | 55 ++++++++++++++++++++++ 1 file changed, 55 insertions(+) diff --git a/arch/arm64/boot/dts/renesas/r9a07g054.dtsi b/arch/arm64/boot/dts/renesas/r9a07g054.dtsi index fa2dfd5eee41..9a856dda9fa7 100644 --- a/arch/arm64/boot/dts/renesas/r9a07g054.dtsi +++ b/arch/arm64/boot/dts/renesas/r9a07g054.dtsi @@ -782,6 +782,61 @@ pinctrl: pinctrl@11030000 { <&cpg R9A07G054_GPIO_SPARE_RESETN>; }; + irqc: interrupt-controller@110a0000 { + compatible = "renesas,r9a07g054-irqc", + "renesas,rzg2l-irqc"; + #interrupt-cells = <2>; + #address-cells = <0>; + interrupt-controller; + reg = <0 0x110a0000 0 0x10000>; + interrupts = , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + ; + clocks = <&cpg CPG_MOD R9A07G054_IA55_CLK>, + <&cpg CPG_MOD R9A07G054_IA55_PCLK>; + clock-names = "clk", "pclk"; + power-domains = <&cpg>; + resets = <&cpg R9A07G054_IA55_RESETN>; + }; + dmac: dma-controller@11820000 { compatible = "renesas,r9a07g054-dmac", "renesas,rz-dmac"; From patchwork Wed Mar 27 08:17:50 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Claudiu Beznea X-Patchwork-Id: 13606176 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from aws-us-west-2-korg-lkml-1.web.codeaurora.org (localhost.localdomain [127.0.0.1]) by smtp.lore.kernel.org (Postfix) with ESMTP id 1DBADCD129A for ; Wed, 27 Mar 2024 10:37:06 +0000 (UTC) Received: from mail-wm1-f46.google.com (mail-wm1-f46.google.com [209.85.128.46]) by mx.groups.io with SMTP id smtpd.web11.32307.1711527515144671758 for ; Wed, 27 Mar 2024 01:18:35 -0700 Authentication-Results: mx.groups.io; dkim=pass header.i=@tuxon.dev header.s=google header.b=IE7QonBk; spf=pass (domain: tuxon.dev, ip: 209.85.128.46, mailfrom: claudiu.beznea@tuxon.dev) Received: by mail-wm1-f46.google.com with SMTP id 5b1f17b1804b1-41494714fd1so2173675e9.2 for ; Wed, 27 Mar 2024 01:18:34 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=tuxon.dev; s=google; t=1711527513; x=1712132313; darn=lists.cip-project.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=JoguOZ8/L9Z2H+HkxVDx9xniVHZvbKhOowel1bUX5J0=; b=IE7QonBkV88Kxj2rFrR8ZRaGFQM9M1Q9CeICibkCubrp5U7688a+O6AIuOynoysdqo cG+Df50psgLasvYjYmaAwQwdzQnDCE4gLjH7SySvuvuGEFsf2MRzXwgUTFLENZSQda1H nXyjMUDfbdXxNViDejY2n0wgOkx4aAb+MWxOUdoApk1A8JNLXdsO974Fj6JeUPSE5ZVj 6o6WiaYTYBgYTmhzmH+E7vbPJYxcANN8okZskakVP4sOhscn0cEV5zNuUrgNg0oz1jZM iqfwaFL/e6lY1S4amlyp2tX3gbMkaqfCabgZTcyAdsstXm+Kej+sD8HDCLNXxWaBUxMg Ew5Q== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1711527513; x=1712132313; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=JoguOZ8/L9Z2H+HkxVDx9xniVHZvbKhOowel1bUX5J0=; b=cZD0/TecgIwYtYcGoLZdbmCR94iqC+Zsd1vC1IvOeV/TJrrqJNI2QOknb+5wvfd3E0 YqFBQSFbm6KvsTLOu1KwZIeRG6ohSY+oI5haeqJRjYyd+SXcM9/r5rTHxoOju5mDbryk O6t+3g2TNuV0jpEvX/99a3YBcpch2LUHqoFpyahe7i3j2TIsBEDpE7siv8bx1vrPk9ou fY07a3m2PI1IEp0t05pVjiWRoTWGz78f590fsNVzV5DjMb9iREl1I2wTfuZIl7A+qs+0 pet/vWXhwmSrbQLbLh1e0j1QhU2zOoYrzxCVIwrxedWQBu6shd67MrEAbFds9r1JtbzE 4qJQ== X-Gm-Message-State: AOJu0YzlglBSE8Fk08wcZxjQY4xQWhdUm6YDBlbdL4cVEEtMA5t3x+Fk 75ARSc4Pbi68MTJvF4kboE/6fAWEDePgCpoKM2eL5aKcpMC2N2Bqii8/GMmOk1g= X-Google-Smtp-Source: AGHT+IFmZJmKZ6yhN4AaKRpbkL5c4fKR6NX/KMxIMBOVUmthEQCyck3Fhrzn+noo+WXsvDfpjWfszw== X-Received: by 2002:a05:600c:21cc:b0:414:8d7:682f with SMTP id x12-20020a05600c21cc00b0041408d7682fmr2456949wmj.10.1711527513655; Wed, 27 Mar 2024 01:18:33 -0700 (PDT) Received: from claudiu-X670E-Pro-RS.. ([82.78.167.144]) by smtp.gmail.com with ESMTPSA id c9-20020a7bc2a9000000b0041493615585sm1353783wmk.39.2024.03.27.01.18.32 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 27 Mar 2024 01:18:33 -0700 (PDT) From: Claudiu X-Google-Original-From: Claudiu To: nobuhiro1.iwamatsu@toshiba.co.jp, pavel@denx.de Cc: cip-dev@lists.cip-project.org, biju.das.jz@bp.renesas.com, prabhakar.mahadev-lad.rj@bp.renesas.com, claudiu.beznea@tuxon.dev Subject: [PATCH 5.10.y-cip 30/36] arm64: dts: renesas: r9a07g043u: Update pinctrl node to handle GPIO interrupts Date: Wed, 27 Mar 2024 10:17:50 +0200 Message-Id: <20240327081756.2228036-31-claudiu.beznea.uj@bp.renesas.com> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20240327081756.2228036-1-claudiu.beznea.uj@bp.renesas.com> References: <20240327081756.2228036-1-claudiu.beznea.uj@bp.renesas.com> MIME-Version: 1.0 List-Id: X-Webhook-Received: from li982-79.members.linode.com [45.33.32.79] by aws-us-west-2-korg-lkml-1.web.codeaurora.org with HTTPS for ; Wed, 27 Mar 2024 10:37:06 -0000 X-Groupsio-URL: https://lists.cip-project.org/g/cip-dev/message/15447 From: Lad Prabhakar commit 85169df721078bf90fb0fc3bf15e4743fea45b2d upstream. Add required properties in pinctrl node to handle GPIO interrupts. Note as IRQC is not enabled in RZ/Five the phandle for interrupt-parent is added in RZ/G2UL specific dtsi so that RZ/Five pinctrl driver continues without waiting for IRQC to probe. Signed-off-by: Lad Prabhakar Reviewed-by: Geert Uytterhoeven Link: https://lore.kernel.org/r/20230102221815.273719-6-prabhakar.mahadev-lad.rj@bp.renesas.com Signed-off-by: Geert Uytterhoeven Signed-off-by: Claudiu Beznea --- arch/arm64/boot/dts/renesas/r9a07g043.dtsi | 2 ++ arch/arm64/boot/dts/renesas/r9a07g043u.dtsi | 4 ++++ 2 files changed, 6 insertions(+) diff --git a/arch/arm64/boot/dts/renesas/r9a07g043.dtsi b/arch/arm64/boot/dts/renesas/r9a07g043.dtsi index 1d3867aabfa9..8721f4c9fa0f 100644 --- a/arch/arm64/boot/dts/renesas/r9a07g043.dtsi +++ b/arch/arm64/boot/dts/renesas/r9a07g043.dtsi @@ -596,6 +596,8 @@ pinctrl: pinctrl@11030000 { gpio-controller; #gpio-cells = <2>; gpio-ranges = <&pinctrl 0 0 152>; + #interrupt-cells = <2>; + interrupt-controller; clocks = <&cpg CPG_MOD R9A07G043_GPIO_HCLK>; power-domains = <&cpg>; resets = <&cpg R9A07G043_GPIO_RSTN>, diff --git a/arch/arm64/boot/dts/renesas/r9a07g043u.dtsi b/arch/arm64/boot/dts/renesas/r9a07g043u.dtsi index a6e777aee02e..ebaaf82edeca 100644 --- a/arch/arm64/boot/dts/renesas/r9a07g043u.dtsi +++ b/arch/arm64/boot/dts/renesas/r9a07g043u.dtsi @@ -48,6 +48,10 @@ timer { }; }; +&pinctrl { + interrupt-parent = <&irqc>; +}; + &soc { interrupt-parent = <&gic>; From patchwork Wed Mar 27 08:17:51 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Claudiu Beznea X-Patchwork-Id: 13606195 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from aws-us-west-2-korg-lkml-1.web.codeaurora.org (localhost.localdomain [127.0.0.1]) by smtp.lore.kernel.org (Postfix) with ESMTP id 818BACD12A8 for ; Wed, 27 Mar 2024 10:37:06 +0000 (UTC) Received: from mail-wm1-f41.google.com (mail-wm1-f41.google.com [209.85.128.41]) by mx.groups.io with SMTP id smtpd.web10.32450.1711527516332914887 for ; Wed, 27 Mar 2024 01:18:36 -0700 Authentication-Results: mx.groups.io; dkim=pass header.i=@tuxon.dev header.s=google header.b=GKJVgTXe; spf=pass (domain: tuxon.dev, ip: 209.85.128.41, mailfrom: claudiu.beznea@tuxon.dev) Received: by mail-wm1-f41.google.com with SMTP id 5b1f17b1804b1-4141156f245so43040815e9.2 for ; Wed, 27 Mar 2024 01:18:36 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=tuxon.dev; s=google; t=1711527515; x=1712132315; darn=lists.cip-project.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=SmKGK3vdK5uJgoMZKJ3vL7L0C4g0A3QkHWLueTVsAgs=; b=GKJVgTXebS0+zwX5cdBl2pt0jaAKX+f45TarqiTxNKEsorM+0YLX1oJ+ErxhnwvcBq i4V80QH7qYaPaXstEzKVjEyUONZpLhJOnmT0c6vXFDoUVt4MSDuBHBwcMfDePG6/rqju 7vq9HQyt0FIcofezBPktCiNP+NZMUUglO/Qb6K8gZX9YiRM3hkE4ca/CDVdzdiayFwgV Zb/PFCWlFlgRI4IoUz4t7zrRYfIaEwNMeXZX8lVLOKhiNW3x4sEFIvjpMUmYwoomi7N5 bWt/yUUGFoFtTXFzQzVSqmswmRFPz2UxWr067nz2T4pawR9UYZx8zDFMM9qiMZ906fB3 uIqw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1711527515; x=1712132315; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=SmKGK3vdK5uJgoMZKJ3vL7L0C4g0A3QkHWLueTVsAgs=; b=i8BzNNml8YS4EXzNnccUc+2TzRO/FDJUkN+RON/PBbl5Gfdy92OBTyS2YmYJmCAneH cCq9k+8Q+GutV9YjL80n2cupVZ3zhWh9kezdRAtNxm7zlNinwKj+iZX3uIczYxCWERsS yRbJrS9FJQAS0to6qjei5gu8SQVNymVZP/9/+VOp1HbTWt+8a4rLU3vtxGQ1mnLyfyhu 8PmLkXH2Bk5hQuhzVqrgy6eAfjuVVzL6eVqrlqVu9JN153+250HsMIeHHphPBFGJf/sZ e/ENfmVzsyV2Wct9KUdLf3slaxD0RgXVQgB/DYU2cax9n78bEkU1G6PYZaEJOue6QPRB 4GwQ== X-Gm-Message-State: AOJu0Yz/oteEMS4u0PRif/jxthlhgpN2GlXffOkyylGYuilyfcJetwZa Jyu564em6LNG2rb7WU1rXlabS2QRcFrn22e3lxS1cBeR11jJ5v3CLPq4u9PClq9W4/KPukWSatv 7 X-Google-Smtp-Source: AGHT+IH12RGaW59LSoDaSdoT8OLdKgbfz2L3qfcekv4COgTnXD/oiE8bUx7jMqJLE0L0mRtelGXWHw== X-Received: by 2002:a05:600c:4f06:b0:414:95de:6c7a with SMTP id l6-20020a05600c4f0600b0041495de6c7amr198619wmq.40.1711527514852; Wed, 27 Mar 2024 01:18:34 -0700 (PDT) Received: from claudiu-X670E-Pro-RS.. ([82.78.167.144]) by smtp.gmail.com with ESMTPSA id c9-20020a7bc2a9000000b0041493615585sm1353783wmk.39.2024.03.27.01.18.33 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 27 Mar 2024 01:18:34 -0700 (PDT) From: Claudiu X-Google-Original-From: Claudiu To: nobuhiro1.iwamatsu@toshiba.co.jp, pavel@denx.de Cc: cip-dev@lists.cip-project.org, biju.das.jz@bp.renesas.com, prabhakar.mahadev-lad.rj@bp.renesas.com, claudiu.beznea@tuxon.dev Subject: [PATCH 5.10.y-cip 31/36] arm64: dts: renesas: r9a07g044: Update pinctrl node to handle GPIO interrupts Date: Wed, 27 Mar 2024 10:17:51 +0200 Message-Id: <20240327081756.2228036-32-claudiu.beznea.uj@bp.renesas.com> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20240327081756.2228036-1-claudiu.beznea.uj@bp.renesas.com> References: <20240327081756.2228036-1-claudiu.beznea.uj@bp.renesas.com> MIME-Version: 1.0 List-Id: X-Webhook-Received: from li982-79.members.linode.com [45.33.32.79] by aws-us-west-2-korg-lkml-1.web.codeaurora.org with HTTPS for ; Wed, 27 Mar 2024 10:37:06 -0000 X-Groupsio-URL: https://lists.cip-project.org/g/cip-dev/message/15448 From: Lad Prabhakar commit 989fd5a7fb7927da37a004cce5336e3940a842e1 upstream. Add required properties in pinctrl node to handle GPIO interrupts. Signed-off-by: Lad Prabhakar Link: https://lore.kernel.org/r/20220718195651.7711-3-prabhakar.mahadev-lad.rj@bp.renesas.com Signed-off-by: Geert Uytterhoeven Signed-off-by: Claudiu Beznea --- arch/arm64/boot/dts/renesas/r9a07g044.dtsi | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/arch/arm64/boot/dts/renesas/r9a07g044.dtsi b/arch/arm64/boot/dts/renesas/r9a07g044.dtsi index 881fecc8d0bc..390914c8db49 100644 --- a/arch/arm64/boot/dts/renesas/r9a07g044.dtsi +++ b/arch/arm64/boot/dts/renesas/r9a07g044.dtsi @@ -767,6 +767,10 @@ pinctrl: pinctrl@11030000 { reg = <0 0x11030000 0 0x10000>; gpio-controller; #gpio-cells = <2>; + #address-cells = <2>; + #interrupt-cells = <2>; + interrupt-parent = <&irqc>; + interrupt-controller; gpio-ranges = <&pinctrl 0 0 392>; clocks = <&cpg CPG_MOD R9A07G044_GPIO_HCLK>; power-domains = <&cpg>; From patchwork Wed Mar 27 08:17:52 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Claudiu Beznea X-Patchwork-Id: 13606198 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from aws-us-west-2-korg-lkml-1.web.codeaurora.org (localhost.localdomain [127.0.0.1]) by smtp.lore.kernel.org (Postfix) with ESMTP id 88816CD12B2 for ; Wed, 27 Mar 2024 10:37:06 +0000 (UTC) Received: from mail-wm1-f49.google.com (mail-wm1-f49.google.com [209.85.128.49]) by mx.groups.io with SMTP id smtpd.web11.32308.1711527517518814466 for ; Wed, 27 Mar 2024 01:18:37 -0700 Authentication-Results: mx.groups.io; dkim=pass header.i=@tuxon.dev header.s=google header.b=mEXJXJCp; spf=pass (domain: tuxon.dev, ip: 209.85.128.49, mailfrom: claudiu.beznea@tuxon.dev) Received: by mail-wm1-f49.google.com with SMTP id 5b1f17b1804b1-414925ba716so4909935e9.2 for ; Wed, 27 Mar 2024 01:18:37 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=tuxon.dev; s=google; t=1711527516; x=1712132316; darn=lists.cip-project.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=NY19XSvTqDrgS5pUGk6GR0HeloReM8o4NL88k0VnWS4=; b=mEXJXJCpNyGIe/jebOC6xNgnX4dhUWn2SiiRJiorEscBu9WrUwJ/0Y2hbYTBKfmVdz CsgQqntuyfsHo9P1q5pmmmFF2+YbZw0Y1EQHSsXlvKx2ZM1KgFIFqhJkl1Ik6WhmWCUO kGY5lwvw3GX0N8JFzRY2QmNVsaDFskgYJHljbELdyTpf7Zb4TAcehn24lHRseAlt4oHz 1TmUIOKn6V5zMt19cSgRDZ3WuqIXSrWdO5J+p71ZRb4C9Ddchc4tD0HyuSl9lo5Qxqka HWmweAnqqPl0HPiYgIvDyDBN6I4KkIXqgFIQHEmAfxQ/hPkKw+izT3O6TeM9PlfBihan yAvQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1711527516; x=1712132316; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=NY19XSvTqDrgS5pUGk6GR0HeloReM8o4NL88k0VnWS4=; b=ZlNB50d3NwOr+cWXtXZhmkX6GBUK65qKUAO5TATlFOO2Fx8jrrIrxkv+2dJe8DdYa9 4/bjp1FOFARMMAMoX23uyth6lgo4yPb0sbCL+DKpoptWr5xkqtQxdLyKrzs51KTJP/56 ZM0v5kkTET66rEMXavvYSCvW22DJVSG+7KKBCHKJW9IA0C+rFx1cYHj78ifE3v48hUuV Ir/BXeeSUKW1K6KZKgv2BH5o3oXW63e6+sdcG+RTjecYkaAv+uFykmWeC5jKZ4alu3f/ lDIwUYaTOLHa8iQfglI4pXCUEcMlVHogbLrxBgAisHGWouaN3RU5+XrbGGDUBL/59ENe gbug== X-Gm-Message-State: AOJu0YxY5gfY4UDs/Q9zMGWxVmmDaafB+AGVnqoi2eLf65URYfQj1+QN Hqoe1lrMY+WOysZ01R5BPCkTGTRUyTwq4tK/17AjsilL5yDM5L0qv+D87TBMKzw= X-Google-Smtp-Source: AGHT+IHjalQ7fJzb+nK6R4k7jCcYRJ5WKz45QqnNA394pw41xvfsFh8RLlZIVZEpdE6VYDXsjIQ9NA== X-Received: by 2002:a05:600c:310f:b0:414:8fe0:2d16 with SMTP id g15-20020a05600c310f00b004148fe02d16mr2658050wmo.37.1711527516048; Wed, 27 Mar 2024 01:18:36 -0700 (PDT) Received: from claudiu-X670E-Pro-RS.. ([82.78.167.144]) by smtp.gmail.com with ESMTPSA id c9-20020a7bc2a9000000b0041493615585sm1353783wmk.39.2024.03.27.01.18.35 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 27 Mar 2024 01:18:35 -0700 (PDT) From: Claudiu X-Google-Original-From: Claudiu To: nobuhiro1.iwamatsu@toshiba.co.jp, pavel@denx.de Cc: cip-dev@lists.cip-project.org, biju.das.jz@bp.renesas.com, prabhakar.mahadev-lad.rj@bp.renesas.com, claudiu.beznea@tuxon.dev Subject: [PATCH 5.10.y-cip 32/36] arm64: dts: renesas: r9a07g054: Update pinctrl node to handle GPIO interrupts Date: Wed, 27 Mar 2024 10:17:52 +0200 Message-Id: <20240327081756.2228036-33-claudiu.beznea.uj@bp.renesas.com> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20240327081756.2228036-1-claudiu.beznea.uj@bp.renesas.com> References: <20240327081756.2228036-1-claudiu.beznea.uj@bp.renesas.com> MIME-Version: 1.0 List-Id: X-Webhook-Received: from li982-79.members.linode.com [45.33.32.79] by aws-us-west-2-korg-lkml-1.web.codeaurora.org with HTTPS for ; Wed, 27 Mar 2024 10:37:06 -0000 X-Groupsio-URL: https://lists.cip-project.org/g/cip-dev/message/15449 From: Lad Prabhakar commit b2c9af5f47522ae9a6665e98d5ff657972a4db97 upstream. Add required properties in pinctrl node to handle GPIO interrupts. Signed-off-by: Lad Prabhakar Link: https://lore.kernel.org/r/20220718195651.7711-5-prabhakar.mahadev-lad.rj@bp.renesas.com Signed-off-by: Geert Uytterhoeven Signed-off-by: Claudiu Beznea --- arch/arm64/boot/dts/renesas/r9a07g054.dtsi | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/arch/arm64/boot/dts/renesas/r9a07g054.dtsi b/arch/arm64/boot/dts/renesas/r9a07g054.dtsi index 9a856dda9fa7..a432134e1f0a 100644 --- a/arch/arm64/boot/dts/renesas/r9a07g054.dtsi +++ b/arch/arm64/boot/dts/renesas/r9a07g054.dtsi @@ -774,6 +774,10 @@ pinctrl: pinctrl@11030000 { reg = <0 0x11030000 0 0x10000>; gpio-controller; #gpio-cells = <2>; + #address-cells = <2>; + #interrupt-cells = <2>; + interrupt-parent = <&irqc>; + interrupt-controller; gpio-ranges = <&pinctrl 0 0 392>; clocks = <&cpg CPG_MOD R9A07G054_GPIO_HCLK>; power-domains = <&cpg>; From patchwork Wed Mar 27 08:17:53 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Claudiu Beznea X-Patchwork-Id: 13606197 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from aws-us-west-2-korg-lkml-1.web.codeaurora.org (localhost.localdomain [127.0.0.1]) by smtp.lore.kernel.org (Postfix) with ESMTP id 7CCB2CD12B1 for ; Wed, 27 Mar 2024 10:37:06 +0000 (UTC) Received: from mail-wm1-f41.google.com (mail-wm1-f41.google.com [209.85.128.41]) by mx.groups.io with SMTP id smtpd.web11.32309.1711527518675942679 for ; Wed, 27 Mar 2024 01:18:38 -0700 Authentication-Results: mx.groups.io; dkim=pass header.i=@tuxon.dev header.s=google header.b=NIVCK0ls; spf=pass (domain: tuxon.dev, ip: 209.85.128.41, mailfrom: claudiu.beznea@tuxon.dev) Received: by mail-wm1-f41.google.com with SMTP id 5b1f17b1804b1-41495ac5b91so918285e9.0 for ; Wed, 27 Mar 2024 01:18:38 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=tuxon.dev; s=google; t=1711527517; x=1712132317; darn=lists.cip-project.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=ghXDC+ZbHpX7uDYtrrmmbxqKhRZcnO2sAVGG5DmBwIY=; b=NIVCK0ls7K9tHZujbbIbCcn+20/Vt2AoBMqIW2wkGbiIAS+Cm3I4tovJU4S9OQU+RC MNX3Avw667Xomdc5ShjBYHv1IafPAb1C+6dGLRatxTyQPkqLtkkrSgEVfb7aNdUNQtv9 aeg0y3/6WkEwFa8VF3UzCzbwL3cKKOL5zg6n6Z5mq9w1LD9OniUfzrEGa2cjfUvQOoVT 10BaMqx/AkYd1R+ff1aaHFB7ddZqVma+SAv5voRdtfnLb5qdVj84lEeVgc8xku+M8PgE h/lpNIxu2W7uDf3Nd++D+BsTrlPcN9UcPgeVhX1yEtkHnXK+czAIu8/tywJs6XhQd5Uf YNtg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1711527517; x=1712132317; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=ghXDC+ZbHpX7uDYtrrmmbxqKhRZcnO2sAVGG5DmBwIY=; b=LuUcx93SN4WLEu5U2aoFZ06dWfRz/pHveck+2XfG6IrtyTH0RG2OJpXTmx53yuVXaX gR/EJqL3zC308zGQTRSWY63CAXG9wxXUrQjjg42VXZ3EZjKJpepG2T6nXBvjZvGyPyM/ udTOsh9PK9WpZesHm8IPM2W7WU0mdQrPaNHhJE3itvc9mpeYCUJTYmT7HjYLc9Qys2eb gy+pcP5/plsIou+Cs1uzBB//umWqrzfTBkhzM610mXw7VBlfqPC2OSqGbSfSEnzOuclR K+XnbC4mjAxQtj4+4oKS9HE2jfNZowoX5zespXpbAydGhsTtgwWIKXLj7SGBbC6AyHVJ VLIg== X-Gm-Message-State: AOJu0Yx8v5p481E77Y++JAbKqMUSm01u0/La6rvGoemsx9lMll5lQ9ai SXfGoKxj7+8stB7cVBV/VyTKfTIJ/fWlxetAfk7SL2zFnEoyDyEzofjNOPTBb10= X-Google-Smtp-Source: AGHT+IFjrn71id4pzVds+sAu0or3YxUKgXWVRxZ3xQzija+An2NMrGjcgLPdAZKuT3LNRLVjvUGNPA== X-Received: by 2002:a05:600c:3508:b0:413:38ee:69e7 with SMTP id h8-20020a05600c350800b0041338ee69e7mr466750wmq.36.1711527517155; Wed, 27 Mar 2024 01:18:37 -0700 (PDT) Received: from claudiu-X670E-Pro-RS.. ([82.78.167.144]) by smtp.gmail.com with ESMTPSA id c9-20020a7bc2a9000000b0041493615585sm1353783wmk.39.2024.03.27.01.18.36 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 27 Mar 2024 01:18:36 -0700 (PDT) From: Claudiu X-Google-Original-From: Claudiu To: nobuhiro1.iwamatsu@toshiba.co.jp, pavel@denx.de Cc: cip-dev@lists.cip-project.org, biju.das.jz@bp.renesas.com, prabhakar.mahadev-lad.rj@bp.renesas.com, claudiu.beznea@tuxon.dev Subject: [PATCH 5.10.y-cip 33/36] dt-bindings: interrupt-controller: Add macros for NMI and IRQ0-7 interrupts present on RZ/G2L SoC Date: Wed, 27 Mar 2024 10:17:53 +0200 Message-Id: <20240327081756.2228036-34-claudiu.beznea.uj@bp.renesas.com> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20240327081756.2228036-1-claudiu.beznea.uj@bp.renesas.com> References: <20240327081756.2228036-1-claudiu.beznea.uj@bp.renesas.com> MIME-Version: 1.0 List-Id: X-Webhook-Received: from li982-79.members.linode.com [45.33.32.79] by aws-us-west-2-korg-lkml-1.web.codeaurora.org with HTTPS for ; Wed, 27 Mar 2024 10:37:06 -0000 X-Groupsio-URL: https://lists.cip-project.org/g/cip-dev/message/15450 From: Lad Prabhakar commit 80c4ece67b4050559e4e2417e77bbfd57e8b3899 upstream. Add macros for NMI and IRQ0-7 interrupts which map to SPI0-8 present on RZ/G2L (and alike) SoC's so that these can be used in the first cell of interrupt specifiers. Signed-off-by: Lad Prabhakar Acked-by: Rob Herring Link: https://lore.kernel.org/r/20220722151155.21100-2-prabhakar.mahadev-lad.rj@bp.renesas.com Signed-off-by: Geert Uytterhoeven Signed-off-by: Claudiu Beznea --- .../interrupt-controller/irqc-rzg2l.h | 25 +++++++++++++++++++ 1 file changed, 25 insertions(+) create mode 100644 include/dt-bindings/interrupt-controller/irqc-rzg2l.h diff --git a/include/dt-bindings/interrupt-controller/irqc-rzg2l.h b/include/dt-bindings/interrupt-controller/irqc-rzg2l.h new file mode 100644 index 000000000000..34ce778885a1 --- /dev/null +++ b/include/dt-bindings/interrupt-controller/irqc-rzg2l.h @@ -0,0 +1,25 @@ +/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */ +/* + * This header provides constants for Renesas RZ/G2L family IRQC bindings. + * + * Copyright (C) 2022 Renesas Electronics Corp. + * + */ + +#ifndef __DT_BINDINGS_IRQC_RZG2L_H +#define __DT_BINDINGS_IRQC_RZG2L_H + +/* NMI maps to SPI0 */ +#define RZG2L_NMI 0 + +/* IRQ0-7 map to SPI1-8 */ +#define RZG2L_IRQ0 1 +#define RZG2L_IRQ1 2 +#define RZG2L_IRQ2 3 +#define RZG2L_IRQ3 4 +#define RZG2L_IRQ4 5 +#define RZG2L_IRQ5 6 +#define RZG2L_IRQ6 7 +#define RZG2L_IRQ7 8 + +#endif /* __DT_BINDINGS_IRQC_RZG2L_H */ From patchwork Wed Mar 27 08:17:54 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Claudiu Beznea X-Patchwork-Id: 13606166 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from aws-us-west-2-korg-lkml-1.web.codeaurora.org (localhost.localdomain [127.0.0.1]) by smtp.lore.kernel.org (Postfix) with ESMTP id 0EE3FCD1297 for ; Wed, 27 Mar 2024 10:37:06 +0000 (UTC) Received: from mail-wm1-f43.google.com (mail-wm1-f43.google.com [209.85.128.43]) by mx.groups.io with SMTP id smtpd.web11.32311.1711527519942506155 for ; Wed, 27 Mar 2024 01:18:40 -0700 Authentication-Results: mx.groups.io; dkim=pass header.i=@tuxon.dev header.s=google header.b=gd3VJ54s; spf=pass (domain: tuxon.dev, ip: 209.85.128.43, mailfrom: claudiu.beznea@tuxon.dev) Received: by mail-wm1-f43.google.com with SMTP id 5b1f17b1804b1-414946b418dso2239595e9.0 for ; Wed, 27 Mar 2024 01:18:39 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=tuxon.dev; s=google; t=1711527518; x=1712132318; darn=lists.cip-project.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=5YWVM5OqorjOMgRy2rOepDuk30m+2YYgf8uJM5gDFnI=; b=gd3VJ54sCi8pPn5EIeXcw9gp5poMSrSHlfWZTXbPIPt7p4yBB03WviqSfsunjFYnuy x/4Hff4RfuvvhUrsowxiTQYK6QcHux6zOzoDvfZ+HnWAiogwQszpwyc2rEyf241+SJ6g BoEprkcPXfhIUJdbCkxAWDlsHMAQNJmYsDe0iO3gfFOcaDFH35LQukPm9+2NZSLzWbFl GUMsQTUtx9g7AiFOoYk8WoMVyWoW++j/b0SJ3O+/kqAV8YurMdkeyp+Y75V5jE+ppKQK 71lUyoPdNxB6UBVZXeFt/cQyoyFUW2+vA6rH1fEiDs2ijiyvUUy/ltMdaoH1I/INK9nk Sgng== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1711527518; x=1712132318; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=5YWVM5OqorjOMgRy2rOepDuk30m+2YYgf8uJM5gDFnI=; b=K4yvKZL7mvZk9e04H6q1ruUgTFpjwQlY94SPayEcg83OhxdVU5WUoHfeiL16+MlO1D fc68ThyqkrbIelTCxHB7O4PBTvAdFMdoTfZWzaFvi7IrCfVJWAhuek+mhjDXWrf9TZ7j u21adxCkmDBDllgUlF2bz4yVTWQ00kKVFp1sTQQeDOJqhTTnSBknpBkiiGKXEH9tLvrB W17RtrHbXsEx38iYikX7yJx80ukTCHFDM6VGHB6czjOCAdLxrhOPZtHc5zfOygsgUDIn elcHQVSmus6dk4FVhLWR45czJP7JMD4lpXRy4tyxtI9LiTXJEeutQ8qzFaikKyMwxaJI uHbA== X-Gm-Message-State: AOJu0YxZiQQCjHvXIFkIwKnle8TqgqoGmoi1f0gLgw256TOCMoSDZyUP LbTHI2QKNMqA/h78K+p16LPsCwyiZbc/mrO4S0HfXC4bw5eQM1RHrt8jCB/zefE= X-Google-Smtp-Source: AGHT+IHZNvX4mHxLcUogc/sdto8hg6j5DWt+yosTWQqbEgeA/0LI+arqhrFlFVLF8AgJo8Dl/+T8eQ== X-Received: by 2002:a7b:c3c1:0:b0:414:6c34:9ba0 with SMTP id t1-20020a7bc3c1000000b004146c349ba0mr2437563wmj.16.1711527518451; Wed, 27 Mar 2024 01:18:38 -0700 (PDT) Received: from claudiu-X670E-Pro-RS.. ([82.78.167.144]) by smtp.gmail.com with ESMTPSA id c9-20020a7bc2a9000000b0041493615585sm1353783wmk.39.2024.03.27.01.18.37 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 27 Mar 2024 01:18:37 -0700 (PDT) From: Claudiu X-Google-Original-From: Claudiu To: nobuhiro1.iwamatsu@toshiba.co.jp, pavel@denx.de Cc: cip-dev@lists.cip-project.org, biju.das.jz@bp.renesas.com, prabhakar.mahadev-lad.rj@bp.renesas.com, claudiu.beznea@tuxon.dev Subject: [PATCH 5.10.y-cip 34/36] arm64: dts: renesas: rzg2l-smarc-som: Add PHY interrupt support for ETH{0/1} Date: Wed, 27 Mar 2024 10:17:54 +0200 Message-Id: <20240327081756.2228036-35-claudiu.beznea.uj@bp.renesas.com> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20240327081756.2228036-1-claudiu.beznea.uj@bp.renesas.com> References: <20240327081756.2228036-1-claudiu.beznea.uj@bp.renesas.com> MIME-Version: 1.0 List-Id: X-Webhook-Received: from li982-79.members.linode.com [45.33.32.79] by aws-us-west-2-korg-lkml-1.web.codeaurora.org with HTTPS for ; Wed, 27 Mar 2024 10:37:06 -0000 X-Groupsio-URL: https://lists.cip-project.org/g/cip-dev/message/15451 From: Lad Prabhakar commit ffd882417412ea7273ae14deec77711f6df54bbc upstream. The PHY interrupt (INT_N) pin is connected to IRQ2 and IRQ3 for ETH0 and ETH1 respectively. Signed-off-by: Lad Prabhakar Link: https://lore.kernel.org/r/20220722151155.21100-4-prabhakar.mahadev-lad.rj@bp.renesas.com Signed-off-by: Geert Uytterhoeven Signed-off-by: Claudiu Beznea --- arch/arm64/boot/dts/renesas/rzg2l-smarc-som.dtsi | 11 +++++++++-- 1 file changed, 9 insertions(+), 2 deletions(-) diff --git a/arch/arm64/boot/dts/renesas/rzg2l-smarc-som.dtsi b/arch/arm64/boot/dts/renesas/rzg2l-smarc-som.dtsi index 6b785957ab5f..0eb0c624d8c4 100644 --- a/arch/arm64/boot/dts/renesas/rzg2l-smarc-som.dtsi +++ b/arch/arm64/boot/dts/renesas/rzg2l-smarc-som.dtsi @@ -6,6 +6,7 @@ */ #include +#include #include /* SW1[2] should be at position 2/OFF to enable 64 GB eMMC */ @@ -101,6 +102,8 @@ phy0: ethernet-phy@7 { compatible = "ethernet-phy-id0022.1640", "ethernet-phy-ieee802.3-c22"; reg = <7>; + interrupt-parent = <&irqc>; + interrupts = ; rxc-skew-psec = <2400>; txc-skew-psec = <2400>; rxdv-skew-psec = <0>; @@ -127,6 +130,8 @@ phy1: ethernet-phy@7 { compatible = "ethernet-phy-id0022.1640", "ethernet-phy-ieee802.3-c22"; reg = <7>; + interrupt-parent = <&irqc>; + interrupts = ; rxc-skew-psec = <2400>; txc-skew-psec = <2400>; rxdv-skew-psec = <0>; @@ -189,7 +194,8 @@ eth0_pins: eth0 { , /* ET0_RXD0 */ , /* ET0_RXD1 */ , /* ET0_RXD2 */ - ; /* ET0_RXD3 */ + , /* ET0_RXD3 */ + ; /* IRQ2 */ }; eth1_pins: eth1 { @@ -207,7 +213,8 @@ eth1_pins: eth1 { , /* ET1_RXD0 */ , /* ET1_RXD1 */ , /* ET1_RXD2 */ - ; /* ET1_RXD3 */ + , /* ET1_RXD3 */ + ; /* IRQ3 */ }; gpio-sd0-pwr-en-hog { From patchwork Wed Mar 27 08:17:55 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Claudiu Beznea X-Patchwork-Id: 13606193 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from aws-us-west-2-korg-lkml-1.web.codeaurora.org (localhost.localdomain [127.0.0.1]) by smtp.lore.kernel.org (Postfix) with ESMTP id 7090ECD12AD for ; Wed, 27 Mar 2024 10:37:06 +0000 (UTC) Received: from mail-wm1-f52.google.com (mail-wm1-f52.google.com [209.85.128.52]) by mx.groups.io with SMTP id smtpd.web10.32451.1711527521051102206 for ; Wed, 27 Mar 2024 01:18:41 -0700 Authentication-Results: mx.groups.io; dkim=pass header.i=@tuxon.dev header.s=google header.b=JCF8Mq5S; spf=pass (domain: tuxon.dev, ip: 209.85.128.52, mailfrom: claudiu.beznea@tuxon.dev) Received: by mail-wm1-f52.google.com with SMTP id 5b1f17b1804b1-41488f9708fso20260945e9.3 for ; Wed, 27 Mar 2024 01:18:40 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=tuxon.dev; s=google; t=1711527519; x=1712132319; darn=lists.cip-project.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=bbjLZQDt499ZwEF1iBm4NhaAGon96fzXArIcfhll/z0=; b=JCF8Mq5SxasNIYU1vyycEQpFQXwiC9zShoMv5BJL5U+X4Egq4Ma1R5q148naYPbLUu XHjICFG/hbB/auNWUvo+kBf4g0fxaiLplh6/kZMOib2LH2rmT93M2NllIxpWuKx8xjK1 lhkUXmqz6hHjePrId+G0pHvupC1IgMRkcmS1B/yKJhtgbl/9TOwECZj3dTFoaggim+fV xjakiIyMx0ib1grPo8Qdm9JwoC9u6EqICQY6gkX4T4RatoKaVFj9WwCWQXlUdemAVzQz ZJtdksEyjrIfqYQ24e2TD85szsWFQjy9t+OpSVO4kXPTW8taOEB4IsJZ4v/aic5BHjt5 mc6Q== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1711527519; x=1712132319; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=bbjLZQDt499ZwEF1iBm4NhaAGon96fzXArIcfhll/z0=; b=WdjAVaU6wBVwd4r8BC3/nzB2rGP5UFrONk5Rv6hhZPY5t4lG2HwS3zxltXAttkskTI FTss+B+CqmgschthT/NTpPyNEKu3z3OqtYr95eOmkAxuyx2Kkp5BXfQrXiufZIf8e29O bGRHwTF4WFPwVIg9F/UzZyWUCFD7j6KwF03cWd+R12lo+jYEIrPMhlGdbdlWCSSaCoRF wfMT28IziWwxGMo1KKRGwqsDxiulm4l3CaVB5q+nwjxkbsK9c+OHnbo+hldQaocUelkS EGEy7vPKyqRF3WAccinnmtKZCX6puXFpbhMJlqsCYpcFa5qgmTtNCO3SFZIUFDPO/ymJ ETKQ== X-Gm-Message-State: AOJu0Ywv0X7cCINfEJmJ7wHZfIPTMJaF7QLCPQQ5HBub5/vEkekCaJsP rDB0/0lFhDW8ZsKwNYmes6LsqaeUVkuGwahbwUTBrJOvM4im0tg5SpLbkKxvmWw= X-Google-Smtp-Source: AGHT+IHTCB6m53qvq0FCisIRPKXYwxYIPvF561bqgJGNtAPhusYg+mizOMu6CVhVqJ4/fan5N7Ld5Q== X-Received: by 2002:a05:600c:1547:b0:414:88a2:fb7b with SMTP id f7-20020a05600c154700b0041488a2fb7bmr1186085wmg.11.1711527519517; Wed, 27 Mar 2024 01:18:39 -0700 (PDT) Received: from claudiu-X670E-Pro-RS.. ([82.78.167.144]) by smtp.gmail.com with ESMTPSA id c9-20020a7bc2a9000000b0041493615585sm1353783wmk.39.2024.03.27.01.18.38 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 27 Mar 2024 01:18:39 -0700 (PDT) From: Claudiu X-Google-Original-From: Claudiu To: nobuhiro1.iwamatsu@toshiba.co.jp, pavel@denx.de Cc: cip-dev@lists.cip-project.org, biju.das.jz@bp.renesas.com, prabhakar.mahadev-lad.rj@bp.renesas.com, claudiu.beznea@tuxon.dev Subject: [PATCH 5.10.y-cip 35/36] arm64: dts: renesas: rzg2lc-smarc-som: Add PHY interrupt support for ETH0 Date: Wed, 27 Mar 2024 10:17:55 +0200 Message-Id: <20240327081756.2228036-36-claudiu.beznea.uj@bp.renesas.com> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20240327081756.2228036-1-claudiu.beznea.uj@bp.renesas.com> References: <20240327081756.2228036-1-claudiu.beznea.uj@bp.renesas.com> MIME-Version: 1.0 List-Id: X-Webhook-Received: from li982-79.members.linode.com [45.33.32.79] by aws-us-west-2-korg-lkml-1.web.codeaurora.org with HTTPS for ; Wed, 27 Mar 2024 10:37:06 -0000 X-Groupsio-URL: https://lists.cip-project.org/g/cip-dev/message/15452 From: Biju Das commit fe7297bf011bf6910d76010ba1763daf1286cbf4 upstream. The PHY interrupt (INT_N) pin is connected to IRQ0 for ETH0. Signed-off-by: Biju Das Reviewed-by: Geert Uytterhoeven Link: https://lore.kernel.org/r/20230712151153.81965-1-biju.das.jz@bp.renesas.com Signed-off-by: Geert Uytterhoeven Signed-off-by: Claudiu Beznea --- arch/arm64/boot/dts/renesas/rzg2lc-smarc-som.dtsi | 6 +++++- 1 file changed, 5 insertions(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/renesas/rzg2lc-smarc-som.dtsi b/arch/arm64/boot/dts/renesas/rzg2lc-smarc-som.dtsi index 370e9420d380..f5f5d50ff917 100644 --- a/arch/arm64/boot/dts/renesas/rzg2lc-smarc-som.dtsi +++ b/arch/arm64/boot/dts/renesas/rzg2lc-smarc-som.dtsi @@ -6,6 +6,7 @@ */ #include +#include #include / { @@ -81,6 +82,8 @@ phy0: ethernet-phy@7 { compatible = "ethernet-phy-id0022.1640", "ethernet-phy-ieee802.3-c22"; reg = <7>; + interrupt-parent = <&irqc>; + interrupts = ; rxc-skew-psec = <2400>; txc-skew-psec = <2400>; rxdv-skew-psec = <0>; @@ -139,7 +142,8 @@ eth0_pins: eth0 { , /* ET0_RXD0 */ , /* ET0_RXD1 */ , /* ET0_RXD2 */ - ; /* ET0_RXD3 */ + , /* ET0_RXD3 */ + ; /* IRQ0 */ }; gpio-sd0-pwr-en-hog { From patchwork Wed Mar 27 08:17:56 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Claudiu Beznea X-Patchwork-Id: 13606167 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from aws-us-west-2-korg-lkml-1.web.codeaurora.org (localhost.localdomain [127.0.0.1]) by smtp.lore.kernel.org (Postfix) with ESMTP id 00F70CD1295 for ; Wed, 27 Mar 2024 10:37:06 +0000 (UTC) Received: from mail-wm1-f51.google.com (mail-wm1-f51.google.com [209.85.128.51]) by mx.groups.io with SMTP id smtpd.web10.32453.1711527523389792077 for ; Wed, 27 Mar 2024 01:18:43 -0700 Authentication-Results: mx.groups.io; dkim=pass header.i=@tuxon.dev header.s=google header.b=dxuZTOQI; spf=pass (domain: tuxon.dev, ip: 209.85.128.51, mailfrom: claudiu.beznea@tuxon.dev) Received: by mail-wm1-f51.google.com with SMTP id 5b1f17b1804b1-41485fcb8ccso22134995e9.1 for ; Wed, 27 Mar 2024 01:18:43 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=tuxon.dev; s=google; t=1711527522; x=1712132322; darn=lists.cip-project.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=NoNezSeOY/X/XqPk8oPrqtHOHFKx1n/uiU9nKmiVwgI=; b=dxuZTOQIe/Kd5ufX4JKMJXJYWCJiyUhqt1g1mQamgonEeCNSAw+ufev6gAk9DWojy2 AOK7CVE2v0MWEiGEYORZQA4o6veDta7spCwvja9Qe2oMubfZ+1OodkNi4X2sUuHJqFh2 owoKKmWxcouHBUn1oJQAD2Wc6oU29pzQHpJ7T4us3tooV7tJsPOzYy3lOHr+hKd+garB +tcx77b7n4gLvBAo7D7h+dr4qaOcugxWgv6EldbH0YOlKRH5xmPhJP9vm8Ue1Qg9PRnx GxVgr7nqPBT/ZdBh9iw08f96XP2SFiM9SBwVA+WE/bQyZ6St1p+yJVtdrB1umwHiA42B BgKg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1711527522; x=1712132322; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=NoNezSeOY/X/XqPk8oPrqtHOHFKx1n/uiU9nKmiVwgI=; b=xQjD/xXA52aUEkjERqQ/IvAWSnbuNzq0qbpaziqrUU2EH/Oivj35Lw10GkdXO0bRCD I7MOUoul7qJccIHMCEBG/0LVGE28/0t1FT00oFOKmfx/bYwvUBKCfQUiL//K5iaHs4kR GNg79Kl82vvgnjd4v7oxXlUBU0TULvgDnxv3oChTrYikJew0cneTMQuLGDqu2TdZc7XN 4hvaeTZDQEtwaaJ1gHJK+bpmy5A8iiVx95ZMu6/9NJBL/IGsXSwtCERF5/OFgMoqVqws cIQ5dCbj85rK927H11fhP2+vf2OW/tOevazTL3X2Y8iil++tpXfTnHegwWt7tA4aDS4u S+FA== X-Gm-Message-State: AOJu0YznwlaJ3/lZw/Qwlb/HMBfR4wTrcVOKUpmWZvLZEX/vqQ0OtPL1 SGLTfmb+mASG4MyMN/klhibjov1hmR4OEkvJJIHFg7vzCgp9zh4WR5L6HpUH/wg= X-Google-Smtp-Source: AGHT+IEfMV4FN6lpiCugcQWSMFJxeXSzgn0gw6wDvcX3PPXpD4q6lkF+bw4KU9FWTHrYe9yJBul5Dw== X-Received: by 2002:a05:600c:3c96:b0:414:8e02:e432 with SMTP id bg22-20020a05600c3c9600b004148e02e432mr397123wmb.7.1711527520820; Wed, 27 Mar 2024 01:18:40 -0700 (PDT) Received: from claudiu-X670E-Pro-RS.. ([82.78.167.144]) by smtp.gmail.com with ESMTPSA id c9-20020a7bc2a9000000b0041493615585sm1353783wmk.39.2024.03.27.01.18.39 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 27 Mar 2024 01:18:40 -0700 (PDT) From: Claudiu X-Google-Original-From: Claudiu To: nobuhiro1.iwamatsu@toshiba.co.jp, pavel@denx.de Cc: cip-dev@lists.cip-project.org, biju.das.jz@bp.renesas.com, prabhakar.mahadev-lad.rj@bp.renesas.com, claudiu.beznea@tuxon.dev Subject: [PATCH 5.10.y-cip 36/36] arm64: dts: renesas: rzg2ul-smarc-som: Add PHY interrupt support for ETH{0/1} Date: Wed, 27 Mar 2024 10:17:56 +0200 Message-Id: <20240327081756.2228036-37-claudiu.beznea.uj@bp.renesas.com> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20240327081756.2228036-1-claudiu.beznea.uj@bp.renesas.com> References: <20240327081756.2228036-1-claudiu.beznea.uj@bp.renesas.com> MIME-Version: 1.0 List-Id: X-Webhook-Received: from li982-79.members.linode.com [45.33.32.79] by aws-us-west-2-korg-lkml-1.web.codeaurora.org with HTTPS for ; Wed, 27 Mar 2024 10:37:05 -0000 X-Groupsio-URL: https://lists.cip-project.org/g/cip-dev/message/15453 From: Lad Prabhakar commit f4673e52dbab9d890d236ed75264653bcd43bac1 upstream. The PHY interrupt (INT_N) pin is connected to IRQ2 and IRQ7 for ETH0 and ETH1 respectively. Signed-off-by: Lad Prabhakar Reviewed-by: Geert Uytterhoeven Link: https://lore.kernel.org/r/20230102221815.273719-7-prabhakar.mahadev-lad.rj@bp.renesas.com Signed-off-by: Geert Uytterhoeven Signed-off-by: Claudiu Beznea --- arch/arm64/boot/dts/renesas/rzg2ul-smarc-som.dtsi | 11 +++++++++-- 1 file changed, 9 insertions(+), 2 deletions(-) diff --git a/arch/arm64/boot/dts/renesas/rzg2ul-smarc-som.dtsi b/arch/arm64/boot/dts/renesas/rzg2ul-smarc-som.dtsi index 53276350a85e..2df6c95b7826 100644 --- a/arch/arm64/boot/dts/renesas/rzg2ul-smarc-som.dtsi +++ b/arch/arm64/boot/dts/renesas/rzg2ul-smarc-som.dtsi @@ -6,6 +6,7 @@ */ #include +#include #include / { @@ -77,6 +78,8 @@ phy0: ethernet-phy@7 { compatible = "ethernet-phy-id0022.1640", "ethernet-phy-ieee802.3-c22"; reg = <7>; + interrupt-parent = <&irqc>; + interrupts = ; rxc-skew-psec = <2400>; txc-skew-psec = <2400>; rxdv-skew-psec = <0>; @@ -104,6 +107,8 @@ phy1: ethernet-phy@7 { compatible = "ethernet-phy-id0022.1640", "ethernet-phy-ieee802.3-c22"; reg = <7>; + interrupt-parent = <&irqc>; + interrupts = ; rxc-skew-psec = <2400>; txc-skew-psec = <2400>; rxdv-skew-psec = <0>; @@ -151,7 +156,8 @@ eth0_pins: eth0 { , /* ET0_RXD0 */ , /* ET0_RXD1 */ , /* ET0_RXD2 */ - ; /* ET0_RXD3 */ + , /* ET0_RXD3 */ + ; /* IRQ2 */ }; eth1_pins: eth1 { @@ -169,7 +175,8 @@ eth1_pins: eth1 { , /* ET1_RXD0 */ , /* ET1_RXD1 */ , /* ET1_RXD2 */ - ; /* ET1_RXD3 */ + , /* ET1_RXD3 */ + ; /* IRQ7 */ }; sdhi0_emmc_pins: sd0emmc {