From patchwork Wed Mar 27 08:34:56 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Claudiu Beznea X-Patchwork-Id: 13606169 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from aws-us-west-2-korg-lkml-1.web.codeaurora.org (localhost.localdomain [127.0.0.1]) by smtp.lore.kernel.org (Postfix) with ESMTP id E8243CD1290 for ; Wed, 27 Mar 2024 10:37:05 +0000 (UTC) Received: from mail-wr1-f51.google.com (mail-wr1-f51.google.com [209.85.221.51]) by mx.groups.io with SMTP id smtpd.web10.32662.1711528512819974271 for ; Wed, 27 Mar 2024 01:35:13 -0700 Authentication-Results: mx.groups.io; dkim=pass header.i=@tuxon.dev header.s=google header.b=Gs5C5MJk; spf=pass (domain: tuxon.dev, ip: 209.85.221.51, mailfrom: claudiu.beznea@tuxon.dev) Received: by mail-wr1-f51.google.com with SMTP id ffacd0b85a97d-341cf28e013so1894749f8f.3 for ; Wed, 27 Mar 2024 01:35:12 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=tuxon.dev; s=google; t=1711528511; x=1712133311; darn=lists.cip-project.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=KeWqBAajzbxuchwGy9Aip/n4kqo7n9uevcsbMtMHMQ4=; b=Gs5C5MJkpzfun19sep51QzBwTQ754Vi2TVMm2HPwiaeBWT59JXlCKnnsZ7gxc6h1s2 VizfKxk+68lwLf0QTjk+fluV8ofnLb99v37LAr9h9zISnU/s95inHBdSqYX26GuakbxR a1VBrQXTlzvDKhTsrQmsN69awtUPdVtSjUyRHUjVR277PqgCqzw5QjVSe1npVig812re 59q8pTcvzS1pQ4fO9mogCE3I5/PRkdHZ9JXXUJDOcqkliefFwt8P1Z3X7sikZ9q2BEND bDaqVZrNXif7dCLkaUM4vsZ0YvFOf3BKf2KAdNPtv2wJUP8/SSoVpllQbV22BgUPrqQI u3wQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1711528511; x=1712133311; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=KeWqBAajzbxuchwGy9Aip/n4kqo7n9uevcsbMtMHMQ4=; b=g/BnkGZFhj/AopJP07guVERM/TuBjz5neQyYFdJYBK0be4tCCXDWJY6p/GTv3FeM8T DfhUyPXXuGfhnYlU+WKlWHUeroM77s36dAkX8kjGkARRTCXUwu3/AouEpqsM++tbEQKY M7Fkx4j4XLXDzA6eUZ3Q13oGWBFBp4I06SOpOAy4pxNBg8vpzFdf3iuR8daVR7EmMgoS Cidw3rjJkf+YgcMRWRMYyzYF73jFwjfUNeU9xciIKgjqAF+DOq/jYDdc7ztzW+3cM1zr mRlrpa4/wve9MvsyzHns/c6mo/kRNfOEJUgKd9Mj8371/R52DQHejCYu7As4M6cB6OxL ICag== X-Gm-Message-State: AOJu0YyjHhf5KZLAVFJAodZshnvSzQtF73c2Y11eQIzsNB4ugXFNTbIX fa2oUqX+3Y+VrM6SvHLpNzjGy0ugoPGDOn057aZPC9wHS/QMnHltfDv0XErxdms= X-Google-Smtp-Source: AGHT+IELmwvW/s0F6UnPU4+zzYDDC9UZKgNqB13RQB+Ab9DIPVnMFGajYCpmHLTrpnTgWR8J/CCU1A== X-Received: by 2002:a5d:6585:0:b0:33d:26b1:c460 with SMTP id q5-20020a5d6585000000b0033d26b1c460mr485460wru.39.1711528511165; Wed, 27 Mar 2024 01:35:11 -0700 (PDT) Received: from claudiu-X670E-Pro-RS.. ([82.78.167.144]) by smtp.gmail.com with ESMTPSA id bq28-20020a5d5a1c000000b00341d84f641asm3591461wrb.8.2024.03.27.01.35.10 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 27 Mar 2024 01:35:10 -0700 (PDT) From: Claudiu X-Google-Original-From: Claudiu To: nobuhiro1.iwamatsu@toshiba.co.jp, pavel@denx.de Cc: cip-dev@lists.cip-project.org, biju.das.jz@bp.renesas.com, prabhakar.mahadev-lad.rj@bp.renesas.com, claudiu.beznea@tuxon.dev Subject: [PATCH 6.1.y-cip 01/13] pinctrl: renesas: rzg2l: Use devm_clk_get_enabled() helper Date: Wed, 27 Mar 2024 10:34:56 +0200 Message-Id: <20240327083508.2229567-2-claudiu.beznea.uj@bp.renesas.com> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20240327083508.2229567-1-claudiu.beznea.uj@bp.renesas.com> References: <20240327083508.2229567-1-claudiu.beznea.uj@bp.renesas.com> MIME-Version: 1.0 List-Id: X-Webhook-Received: from li982-79.members.linode.com [45.33.32.79] by aws-us-west-2-korg-lkml-1.web.codeaurora.org with HTTPS for ; Wed, 27 Mar 2024 10:37:05 -0000 X-Groupsio-URL: https://lists.cip-project.org/g/cip-dev/message/15455 From: Christophe JAILLET commit 95eb19869401850f069723b296170b8b3bd5be9e upstream. The devm_clk_get_enabled() helper: - calls devm_clk_get() - calls clk_prepare_enable() and registers what is needed in order to call clk_disable_unprepare() when needed, as a managed resource. This simplifies the code and avoids the need of a dedicated function used with devm_add_action_or_reset(). While at it, use dev_err_probe() which filters -EPROBE_DEFER. Signed-off-by: Christophe JAILLET Reviewed-by: Geert Uytterhoeven Link: https://lore.kernel.org/r/a4a586337d692f0ca396b80d275ba634eb419593.1690058500.git.christophe.jaillet@wanadoo.fr [geert: Make clk local to rzg2l_pinctrl_probe()] Signed-off-by: Geert Uytterhoeven Signed-off-by: Claudiu Beznea --- drivers/pinctrl/renesas/pinctrl-rzg2l.c | 32 ++++--------------------- 1 file changed, 5 insertions(+), 27 deletions(-) diff --git a/drivers/pinctrl/renesas/pinctrl-rzg2l.c b/drivers/pinctrl/renesas/pinctrl-rzg2l.c index 22abac051ab6..b0ef821e7016 100644 --- a/drivers/pinctrl/renesas/pinctrl-rzg2l.c +++ b/drivers/pinctrl/renesas/pinctrl-rzg2l.c @@ -145,7 +145,6 @@ struct rzg2l_pinctrl { const struct rzg2l_pinctrl_data *data; void __iomem *base; struct device *dev; - struct clk *clk; struct gpio_chip gpio_chip; struct pinctrl_gpio_range gpio_range; @@ -1480,14 +1479,10 @@ static int rzg2l_pinctrl_register(struct rzg2l_pinctrl *pctrl) return 0; } -static void rzg2l_pinctrl_clk_disable(void *data) -{ - clk_disable_unprepare(data); -} - static int rzg2l_pinctrl_probe(struct platform_device *pdev) { struct rzg2l_pinctrl *pctrl; + struct clk *clk; int ret; BUILD_BUG_ON(ARRAY_SIZE(rzg2l_gpio_configs) * RZG2L_PINS_PER_PORT > @@ -1510,12 +1505,10 @@ static int rzg2l_pinctrl_probe(struct platform_device *pdev) if (IS_ERR(pctrl->base)) return PTR_ERR(pctrl->base); - pctrl->clk = devm_clk_get(pctrl->dev, NULL); - if (IS_ERR(pctrl->clk)) { - ret = PTR_ERR(pctrl->clk); - dev_err(pctrl->dev, "failed to get GPIO clk : %i\n", ret); - return ret; - } + clk = devm_clk_get_enabled(pctrl->dev, NULL); + if (IS_ERR(clk)) + return dev_err_probe(pctrl->dev, PTR_ERR(clk), + "failed to enable GPIO clk\n"); spin_lock_init(&pctrl->lock); spin_lock_init(&pctrl->bitmap_lock); @@ -1523,21 +1516,6 @@ static int rzg2l_pinctrl_probe(struct platform_device *pdev) platform_set_drvdata(pdev, pctrl); - ret = clk_prepare_enable(pctrl->clk); - if (ret) { - dev_err(pctrl->dev, "failed to enable GPIO clk: %i\n", ret); - return ret; - } - - ret = devm_add_action_or_reset(&pdev->dev, rzg2l_pinctrl_clk_disable, - pctrl->clk); - if (ret) { - dev_err(pctrl->dev, - "failed to register GPIO clk disable action, %i\n", - ret); - return ret; - } - ret = rzg2l_pinctrl_register(pctrl); if (ret) return ret; From patchwork Wed Mar 27 08:34:57 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Claudiu Beznea X-Patchwork-Id: 13606192 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from aws-us-west-2-korg-lkml-1.web.codeaurora.org (localhost.localdomain [127.0.0.1]) by smtp.lore.kernel.org (Postfix) with ESMTP id 72712CD12AF for ; Wed, 27 Mar 2024 10:37:06 +0000 (UTC) Received: from mail-wm1-f42.google.com (mail-wm1-f42.google.com [209.85.128.42]) by mx.groups.io with SMTP id smtpd.web10.32663.1711528513929863117 for ; Wed, 27 Mar 2024 01:35:14 -0700 Authentication-Results: mx.groups.io; dkim=pass header.i=@tuxon.dev header.s=google header.b=YRpZomMw; spf=pass (domain: tuxon.dev, ip: 209.85.128.42, mailfrom: claudiu.beznea@tuxon.dev) Received: by mail-wm1-f42.google.com with SMTP id 5b1f17b1804b1-414866f92beso20775045e9.3 for ; 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([82.78.167.144]) by smtp.gmail.com with ESMTPSA id bq28-20020a5d5a1c000000b00341d84f641asm3591461wrb.8.2024.03.27.01.35.11 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 27 Mar 2024 01:35:11 -0700 (PDT) From: Claudiu X-Google-Original-From: Claudiu To: nobuhiro1.iwamatsu@toshiba.co.jp, pavel@denx.de Cc: cip-dev@lists.cip-project.org, biju.das.jz@bp.renesas.com, prabhakar.mahadev-lad.rj@bp.renesas.com, claudiu.beznea@tuxon.dev Subject: [PATCH 6.1.y-cip 02/13] irqchip: remove MODULE_LICENSE in non-modules Date: Wed, 27 Mar 2024 10:34:57 +0200 Message-Id: <20240327083508.2229567-3-claudiu.beznea.uj@bp.renesas.com> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20240327083508.2229567-1-claudiu.beznea.uj@bp.renesas.com> References: <20240327083508.2229567-1-claudiu.beznea.uj@bp.renesas.com> MIME-Version: 1.0 List-Id: X-Webhook-Received: from li982-79.members.linode.com [45.33.32.79] by aws-us-west-2-korg-lkml-1.web.codeaurora.org with HTTPS for ; Wed, 27 Mar 2024 10:37:06 -0000 X-Groupsio-URL: https://lists.cip-project.org/g/cip-dev/message/15456 From: Nick Alcock commit e3f1f02548adbf973af29c6ee6304a45121bff03 upstream. Since commit 8b41fc4454e ("kbuild: create modules.builtin without Makefile.modbuiltin or tristate.conf"), MODULE_LICENSE declarations are used to identify modules. As a consequence, uses of the macro in non-modules will cause modprobe to misidentify their containing object file as a module when it is not (false positives), and modprobe might succeed rather than failing with a suitable error message. So remove it in the files in this commit, none of which can be built as modules. Signed-off-by: Nick Alcock Suggested-by: Luis Chamberlain Cc: Luis Chamberlain Cc: linux-modules@vger.kernel.org Cc: linux-kernel@vger.kernel.org Cc: Hitomi Hasegawa Cc: Thomas Gleixner Cc: Marc Zyngier Cc: Philipp Zabel Signed-off-by: Luis Chamberlain Signed-off-by: Claudiu Beznea --- drivers/irqchip/irq-renesas-rzg2l.c | 1 - 1 file changed, 1 deletion(-) diff --git a/drivers/irqchip/irq-renesas-rzg2l.c b/drivers/irqchip/irq-renesas-rzg2l.c index 0922e7ca04fa..6390d1d78f2e 100644 --- a/drivers/irqchip/irq-renesas-rzg2l.c +++ b/drivers/irqchip/irq-renesas-rzg2l.c @@ -391,4 +391,3 @@ IRQCHIP_MATCH("renesas,rzg2l-irqc", rzg2l_irqc_init) IRQCHIP_PLATFORM_DRIVER_END(rzg2l_irqc) MODULE_AUTHOR("Lad Prabhakar "); MODULE_DESCRIPTION("Renesas RZ/G2L IRQC Driver"); -MODULE_LICENSE("GPL"); From patchwork Wed Mar 27 08:34:58 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Claudiu Beznea X-Patchwork-Id: 13606165 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from aws-us-west-2-korg-lkml-1.web.codeaurora.org (localhost.localdomain [127.0.0.1]) by smtp.lore.kernel.org (Postfix) with ESMTP id E844CCD1291 for ; Wed, 27 Mar 2024 10:37:05 +0000 (UTC) Received: from mail-wr1-f47.google.com (mail-wr1-f47.google.com [209.85.221.47]) by mx.groups.io with SMTP id smtpd.web11.32510.1711528514906722303 for ; Wed, 27 Mar 2024 01:35:15 -0700 Authentication-Results: mx.groups.io; dkim=pass header.i=@tuxon.dev header.s=google header.b=TDU7aMaw; spf=pass (domain: tuxon.dev, ip: 209.85.221.47, mailfrom: claudiu.beznea@tuxon.dev) Received: by mail-wr1-f47.google.com with SMTP id ffacd0b85a97d-341730bfc46so4606215f8f.3 for ; Wed, 27 Mar 2024 01:35:14 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=tuxon.dev; s=google; t=1711528513; x=1712133313; darn=lists.cip-project.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=2kCSbNWejHyTTzQYd+Nyj1hiMp1CRjypKtRG6SEDmCA=; b=TDU7aMawxAPnc4JLnykCTkArbeEQ6vdLJREpqMfi95V6c9uvAFji8gI5CBKdsQFp8R mnZUQNVVo5yqMccb3Tvb98zK5s8DRx6bXwO8KupDwQXsxrwUhUroyOtO2FroO5ZTJ4JO p/Bu37RgjklMi8d4FLe7kkaFq9B/U9BbwTmeEpIQQWHVX7bqGxx53JSn/JpXFvrpLcZD rO6yFrtF+GBGbMUWvXNdzJY+Uas2cxEApIFoI9tBHM9XhBA2t5+UsRlba16p3aWHL6k8 1cmBZ8+xCsZN45d+KK07c4X2cx9Iz2FdfFBBmCuA7VF6TVyBCz7S2UzU+iED9NLntek2 E0xQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1711528513; x=1712133313; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=2kCSbNWejHyTTzQYd+Nyj1hiMp1CRjypKtRG6SEDmCA=; b=fanusRu1YwcsmPh5+THfqr5yXLxF1kSp4C1j1p/sTgd/1B2vmFO1d69C9gPDbHXfo5 wbw81OEBzLD3bogBfc4uxCqMEwQqjuDfmMuVjaoWNRc/7WTzdSHdcOXVvD7ObPmRh7qh UORMifE1gnjFaLjvR1z0JzgAbKrD6hKppnJDyoALzDx2HW2YTmEd6+3n2D0m9YY83z4Q ZYjE9Kbmy7cXT7cKH0pPmFr9NsdbhpMfjazyblMRK42RbaBu5xlgAWFA6wVBb+PCh12q /ZBZzgJWn9BAN8/7/ALTgFZ0JE2P3apX5Jh68Ej7g4XuLyj6tpAz+2D7+3l7p6dzazWc O/ug== X-Gm-Message-State: AOJu0YwC2VtoXvd461r1LXXkXQF6QNYViGJMF9P28cFKOI7K7PC+9Pvc sLR1g1DAxpiP2VpAgzMxBBADR9FNyXSh9TgP3Me33zae2ZNbKXL+PeGKj26Io+0= X-Google-Smtp-Source: AGHT+IHp498OU3/GpHqtCtW7xBVhhOsJVFrI5v08IU4L/CJk7HgHscQa3Ze5Q95Qswo5+mRKMbUR1A== X-Received: by 2002:a5d:58f3:0:b0:33e:1a98:46e2 with SMTP id f19-20020a5d58f3000000b0033e1a9846e2mr3146302wrd.28.1711528513400; Wed, 27 Mar 2024 01:35:13 -0700 (PDT) Received: from claudiu-X670E-Pro-RS.. ([82.78.167.144]) by smtp.gmail.com with ESMTPSA id bq28-20020a5d5a1c000000b00341d84f641asm3591461wrb.8.2024.03.27.01.35.12 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 27 Mar 2024 01:35:12 -0700 (PDT) From: Claudiu X-Google-Original-From: Claudiu To: nobuhiro1.iwamatsu@toshiba.co.jp, pavel@denx.de Cc: cip-dev@lists.cip-project.org, biju.das.jz@bp.renesas.com, prabhakar.mahadev-lad.rj@bp.renesas.com, claudiu.beznea@tuxon.dev Subject: [PATCH 6.1.y-cip 03/13] irqchip/renesas-rzg2l: Convert to irq_data_get_irq_chip_data() Date: Wed, 27 Mar 2024 10:34:58 +0200 Message-Id: <20240327083508.2229567-4-claudiu.beznea.uj@bp.renesas.com> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20240327083508.2229567-1-claudiu.beznea.uj@bp.renesas.com> References: <20240327083508.2229567-1-claudiu.beznea.uj@bp.renesas.com> MIME-Version: 1.0 List-Id: X-Webhook-Received: from li982-79.members.linode.com [45.33.32.79] by aws-us-west-2-korg-lkml-1.web.codeaurora.org with HTTPS for ; Wed, 27 Mar 2024 10:37:05 -0000 X-Groupsio-URL: https://lists.cip-project.org/g/cip-dev/message/15457 From: Geert Uytterhoeven commit 8a4f44f3e9b05c38606b2ae02f933d6b64a340dd upstream. Use the existing irq_data_get_irq_chip_data() helper instead of open-coding the same operation. Signed-off-by: Geert Uytterhoeven Reviewed-by: Lad Prabhakar Signed-off-by: Marc Zyngier Link: https://lore.kernel.org/r/8e47cc6400e5a82c854c855948d2665a3a3197e3.1695819391.git.geert+renesas@glider.be Signed-off-by: Claudiu Beznea --- drivers/irqchip/irq-renesas-rzg2l.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/irqchip/irq-renesas-rzg2l.c b/drivers/irqchip/irq-renesas-rzg2l.c index 6390d1d78f2e..fe8d516f3614 100644 --- a/drivers/irqchip/irq-renesas-rzg2l.c +++ b/drivers/irqchip/irq-renesas-rzg2l.c @@ -130,8 +130,8 @@ static void rzg2l_irqc_irq_enable(struct irq_data *d) unsigned int hw_irq = irqd_to_hwirq(d); if (hw_irq >= IRQC_TINT_START && hw_irq < IRQC_NUM_IRQ) { + unsigned long tint = (uintptr_t)irq_data_get_irq_chip_data(d); struct rzg2l_irqc_priv *priv = irq_data_to_priv(d); - unsigned long tint = (uintptr_t)d->chip_data; u32 offset = hw_irq - IRQC_TINT_START; u32 tssr_offset = TSSR_OFFSET(offset); u8 tssr_index = TSSR_INDEX(offset); From patchwork Wed Mar 27 08:34:59 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Claudiu Beznea X-Patchwork-Id: 13606191 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from aws-us-west-2-korg-lkml-1.web.codeaurora.org (localhost.localdomain [127.0.0.1]) by smtp.lore.kernel.org (Postfix) with ESMTP id 64C76CD12AB for ; Wed, 27 Mar 2024 10:37:06 +0000 (UTC) Received: from mail-wr1-f50.google.com (mail-wr1-f50.google.com [209.85.221.50]) by mx.groups.io with SMTP id smtpd.web11.32512.1711528516087702052 for ; Wed, 27 Mar 2024 01:35:16 -0700 Authentication-Results: mx.groups.io; dkim=pass header.i=@tuxon.dev header.s=google header.b=SmusL/5L; spf=pass (domain: tuxon.dev, ip: 209.85.221.50, mailfrom: claudiu.beznea@tuxon.dev) Received: by mail-wr1-f50.google.com with SMTP id ffacd0b85a97d-33d90dfe73cso319999f8f.0 for ; Wed, 27 Mar 2024 01:35:15 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=tuxon.dev; s=google; t=1711528514; x=1712133314; darn=lists.cip-project.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=xlZNVeHKvbtBeNW38McajTNAPghlBWj9e5vgpxA3xF4=; b=SmusL/5LGcDnFRb7SLmrcY73trkUtzSS54yW4vRe16eyUFicz+GnrEzXnZYoolITTc vQ6413jHBNOBh5ueitnfXFxngfLVQK950UIGhZWRhQ3atjNNdrMshRxbicTrOWt/spWv k5gOnW+ZNHaZMFwvLGJHxhTfHWlQeID09mTCAXOGeTt/Jzs2ef0cOcBF3L3Stjlj9Ohe 2j7KdctU4Srho15TQJ/WINj5mmftfrn9aKDULjuUVlZBF91tScd7rWCVtx9qSdI/vA6U xmdthuh7+uo56X3V32yjGT/hkbbx2W1QCIKLhjBhKwlnWXp1yVOejI1c/xwAsAq3Yhgr 2lhw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1711528514; x=1712133314; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=xlZNVeHKvbtBeNW38McajTNAPghlBWj9e5vgpxA3xF4=; b=Io1lzLbjZC1/7fwRy8b2LloxGJ5bmg7SFkxOtj5rGdV341r52etVmPJ1zY2OnLf9eo xmftjoJEPik0HxdkHBGGD7Mk49EP5F+QLiQG6UoLpkdqyMDZeauWpza6FOfKFaZCa/qD QRX/AVEaP87C7bNE05geejqSdGPGCZmCXYzXvQOc4wBpQ1TVEbnTmlgnzPNBs2IktaZJ 27G8c1PbC1OibvJuBrUSvEYztU7gWu+1QN+8/CIACS4zGOrchyGt3lcKXXNU5d0PxrjA kaPuxUD3n9o4Yh+mSMw+3blNAWSQsPuVxajjRqKc7rZ56bmyoG/vDMc0ZVmD+M1H2zVB Olog== X-Gm-Message-State: AOJu0YyULB6NOyl445ciq23zJlc3XCooZ+AtektMN1Yyyab9taNdJob/ hTqwxzx1OYavTzMN/SUtXCiBx54YpDnCzpdJQBIXOMAS3cTwNF7VBazR1uwW5c4= X-Google-Smtp-Source: AGHT+IGzZGDLKyT8UlrnpDtqNaFEN4bZ49ynBxXi5ruHheLbjMBG7notPeWekszwmiF6GKDUwY27SQ== X-Received: by 2002:a5d:5505:0:b0:341:b5ca:9e9c with SMTP id b5-20020a5d5505000000b00341b5ca9e9cmr3110305wrv.25.1711528514538; Wed, 27 Mar 2024 01:35:14 -0700 (PDT) Received: from claudiu-X670E-Pro-RS.. ([82.78.167.144]) by smtp.gmail.com with ESMTPSA id bq28-20020a5d5a1c000000b00341d84f641asm3591461wrb.8.2024.03.27.01.35.13 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 27 Mar 2024 01:35:14 -0700 (PDT) From: Claudiu X-Google-Original-From: Claudiu To: nobuhiro1.iwamatsu@toshiba.co.jp, pavel@denx.de Cc: cip-dev@lists.cip-project.org, biju.das.jz@bp.renesas.com, prabhakar.mahadev-lad.rj@bp.renesas.com, claudiu.beznea@tuxon.dev Subject: [PATCH 6.1.y-cip 04/13] irqchip/renesas-rzg2l: Use tabs instead of spaces Date: Wed, 27 Mar 2024 10:34:59 +0200 Message-Id: <20240327083508.2229567-5-claudiu.beznea.uj@bp.renesas.com> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20240327083508.2229567-1-claudiu.beznea.uj@bp.renesas.com> References: <20240327083508.2229567-1-claudiu.beznea.uj@bp.renesas.com> MIME-Version: 1.0 List-Id: X-Webhook-Received: from li982-79.members.linode.com [45.33.32.79] by aws-us-west-2-korg-lkml-1.web.codeaurora.org with HTTPS for ; Wed, 27 Mar 2024 10:37:06 -0000 X-Groupsio-URL: https://lists.cip-project.org/g/cip-dev/message/15458 From: Claudiu Beznea commit c90b5c4e6554c1194d5f7cfe13dfd710a7661cab upstream. Use tabs instead of spaces in definition of TINT_EXTRACT_HWIRQ() and TINT_EXTRACT_GPIOINT() macros to align with coding style requirements described in Documentation/process/coding-style.rst, "Indentation" chapter. Signed-off-by: Claudiu Beznea Signed-off-by: Thomas Gleixner Reviewed-by: Geert Uytterhoeven Link: https://lore.kernel.org/r/20231120111820.87398-3-claudiu.beznea.uj@bp.renesas.com Signed-off-by: Claudiu Beznea --- drivers/irqchip/irq-renesas-rzg2l.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/irqchip/irq-renesas-rzg2l.c b/drivers/irqchip/irq-renesas-rzg2l.c index fe8d516f3614..cc42cbd05762 100644 --- a/drivers/irqchip/irq-renesas-rzg2l.c +++ b/drivers/irqchip/irq-renesas-rzg2l.c @@ -53,8 +53,8 @@ #define IITSR_IITSEL_EDGE_BOTH 3 #define IITSR_IITSEL_MASK(n) IITSR_IITSEL((n), 3) -#define TINT_EXTRACT_HWIRQ(x) FIELD_GET(GENMASK(15, 0), (x)) -#define TINT_EXTRACT_GPIOINT(x) FIELD_GET(GENMASK(31, 16), (x)) +#define TINT_EXTRACT_HWIRQ(x) FIELD_GET(GENMASK(15, 0), (x)) +#define TINT_EXTRACT_GPIOINT(x) FIELD_GET(GENMASK(31, 16), (x)) struct rzg2l_irqc_priv { void __iomem *base; From patchwork Wed Mar 27 08:35:00 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Claudiu Beznea X-Patchwork-Id: 13606161 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from aws-us-west-2-korg-lkml-1.web.codeaurora.org (localhost.localdomain [127.0.0.1]) by smtp.lore.kernel.org (Postfix) with ESMTP id D9F60CD128D for ; Wed, 27 Mar 2024 10:37:05 +0000 (UTC) Received: from mail-wr1-f41.google.com (mail-wr1-f41.google.com [209.85.221.41]) by mx.groups.io with SMTP id smtpd.web11.32513.1711528517278649678 for ; Wed, 27 Mar 2024 01:35:17 -0700 Authentication-Results: mx.groups.io; dkim=pass header.i=@tuxon.dev header.s=google header.b=qf0bkbrv; spf=pass (domain: tuxon.dev, ip: 209.85.221.41, mailfrom: claudiu.beznea@tuxon.dev) Received: by mail-wr1-f41.google.com with SMTP id ffacd0b85a97d-33ed4dd8659so362150f8f.0 for ; Wed, 27 Mar 2024 01:35:17 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=tuxon.dev; s=google; t=1711528516; x=1712133316; darn=lists.cip-project.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=6Fze5/lGaw9sDH4GuBtKEA1ITP5tQphUFfDdOOSgiPk=; b=qf0bkbrvyb8Q9+SjmgeQh6iE+UsqxYd4e6PmM+IXVlHNLA4YgfQg0DTUKD+YxZcgL/ mz7l/R6q6j6HTDm5PZ7zkp1tMB4Z7qdDbnXiL9nVRtALQbP9391nelXHslnU3nQQeE+4 5AK+OENBdHA8HqarvzVsjNgJpLmeaRlQ0xZrgNWUytEZM/bVl4/yD3r8SWcQHlLtOd79 XWJyHolU80fnYO6R1X3u/5HKxCoKQSttHJqQei/fF5QdSdzrnHLoVgrw+kpwtiZV20Oj OzKAh/KPEC79LW1v5Nnag7SOSBtDAEW4FRLaZd1h0MQRcD+wi781DHpWOinBIjqTRrEd d0eg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1711528516; x=1712133316; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=6Fze5/lGaw9sDH4GuBtKEA1ITP5tQphUFfDdOOSgiPk=; b=nXS6eKppOcVaDf8Mh15TijCV/3CqKauGgt1Mg6j8QMkH4TJ4jSD8qe5FG3mBXVlHSu zrHT61B0sC1VG3TdOh4FcAUnt/PdHrKwfG20m2KSQFxKkUC4bDZ13wGh8o+U8iDgvB+D p0IOvd9W2KrprrNqlK/JezVZ6TFN9RCmSezo2CJ908YNs1m8p0xyLEDEP755j6rwxfoI Yldu1VkD19IaWcFqo0uAXwRFpppCmzNRpfX8hgRh1ZZa4UYElcwJQJwARcd/cPZOv/W5 WAumAuByJt00RkbY0hJvBUG1f20hdhu2uK4FRi7UfMsedaa4N8dVgKifqfSkcoPnkYDj dQBg== X-Gm-Message-State: AOJu0YwT1Wnd2OE8Ip8ajyHWCk2B49BJCmwaQCmtbYxKlUSEdEWVsW+p SJR830Mi9aYc4KYiCeYhDCveaO9s9kPGXAC0PL1OMUzMDCRYjrEOCCwMXqtPJd0= X-Google-Smtp-Source: AGHT+IElQHW/AxqYubxAUUlh+ekGMrzUjBZBrp3K0ZSJbdFbM9m4n0FTVxPmSCQblnYhiC929nypsw== X-Received: by 2002:adf:f1c8:0:b0:33d:61c7:9b2c with SMTP id z8-20020adff1c8000000b0033d61c79b2cmr3362106wro.34.1711528515760; Wed, 27 Mar 2024 01:35:15 -0700 (PDT) Received: from claudiu-X670E-Pro-RS.. ([82.78.167.144]) by smtp.gmail.com with ESMTPSA id bq28-20020a5d5a1c000000b00341d84f641asm3591461wrb.8.2024.03.27.01.35.14 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 27 Mar 2024 01:35:15 -0700 (PDT) From: Claudiu X-Google-Original-From: Claudiu To: nobuhiro1.iwamatsu@toshiba.co.jp, pavel@denx.de Cc: cip-dev@lists.cip-project.org, biju.das.jz@bp.renesas.com, prabhakar.mahadev-lad.rj@bp.renesas.com, claudiu.beznea@tuxon.dev Subject: [PATCH 6.1.y-cip 05/13] irqchip/renesas-rzg2l: Align struct member names to tabs Date: Wed, 27 Mar 2024 10:35:00 +0200 Message-Id: <20240327083508.2229567-6-claudiu.beznea.uj@bp.renesas.com> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20240327083508.2229567-1-claudiu.beznea.uj@bp.renesas.com> References: <20240327083508.2229567-1-claudiu.beznea.uj@bp.renesas.com> MIME-Version: 1.0 List-Id: X-Webhook-Received: from li982-79.members.linode.com [45.33.32.79] by aws-us-west-2-korg-lkml-1.web.codeaurora.org with HTTPS for ; Wed, 27 Mar 2024 10:37:05 -0000 X-Groupsio-URL: https://lists.cip-project.org/g/cip-dev/message/15459 From: Claudiu Beznea commit 02f6507640173addeeb3af035d2c6f0b3cff1567 upstream. Align struct member names to tabs to follow the requirements from maintainer-tip file. 3 tabs were used at the moment as the next commits will add a new member which requires 3 tabs for a better view. Signed-off-by: Claudiu Beznea Signed-off-by: Thomas Gleixner Reviewed-by: Geert Uytterhoeven Link: https://lore.kernel.org/r/20231120111820.87398-4-claudiu.beznea.uj@bp.renesas.com Signed-off-by: Claudiu Beznea --- drivers/irqchip/irq-renesas-rzg2l.c | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/drivers/irqchip/irq-renesas-rzg2l.c b/drivers/irqchip/irq-renesas-rzg2l.c index cc42cbd05762..90971ab06f0c 100644 --- a/drivers/irqchip/irq-renesas-rzg2l.c +++ b/drivers/irqchip/irq-renesas-rzg2l.c @@ -57,9 +57,9 @@ #define TINT_EXTRACT_GPIOINT(x) FIELD_GET(GENMASK(31, 16), (x)) struct rzg2l_irqc_priv { - void __iomem *base; - struct irq_fwspec fwspec[IRQC_NUM_IRQ]; - raw_spinlock_t lock; + void __iomem *base; + struct irq_fwspec fwspec[IRQC_NUM_IRQ]; + raw_spinlock_t lock; }; static struct rzg2l_irqc_priv *irq_data_to_priv(struct irq_data *data) From patchwork Wed Mar 27 08:35:01 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Claudiu Beznea X-Patchwork-Id: 13606190 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from aws-us-west-2-korg-lkml-1.web.codeaurora.org (localhost.localdomain [127.0.0.1]) by smtp.lore.kernel.org (Postfix) with ESMTP id 65078CD12AC for ; Wed, 27 Mar 2024 10:37:06 +0000 (UTC) Received: from mail-wr1-f54.google.com (mail-wr1-f54.google.com [209.85.221.54]) by mx.groups.io with SMTP id smtpd.web11.32514.1711528518426879478 for ; Wed, 27 Mar 2024 01:35:18 -0700 Authentication-Results: mx.groups.io; dkim=pass header.i=@tuxon.dev header.s=google header.b=aYB0rq/i; spf=pass (domain: tuxon.dev, ip: 209.85.221.54, mailfrom: claudiu.beznea@tuxon.dev) Received: by mail-wr1-f54.google.com with SMTP id ffacd0b85a97d-33ed7ba1a42so4349922f8f.2 for ; Wed, 27 Mar 2024 01:35:18 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=tuxon.dev; s=google; t=1711528517; x=1712133317; darn=lists.cip-project.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=x7g5fTc14qsP28r1k5RjYQCPW18M91Dr5/3NKQ3Cp/Q=; b=aYB0rq/i0QRMQyJWryjc55J1mGazhshg8Jauk0fn/0baLZ+4aAYs9hkhH3DEitI6iU Gb2zqfxXzBUMBodF6qEVGqothC8zYZVZbi+0Se/XcslYzZUCs+HIJs16c+V+EAMnG2sB kB5VrlqCxi4KVGI77g2/yBtcQ1BeZYCtXKWPiglBu4eZBH2Dfg7FM8YkZQTX1PzRtJkC RbFw9gQaioBJFnvPkPCFDPybje5O/Nc1v4vITNjFIEKm1xGdm0V5Le+/qixM+T8w6WDT oq7Gr/fKHaIAQsQG3W3WQvIdrWzPPO+ZiHmMw+g7kZMmvOluxJ++iciPTBFsOpmnmMXw fEqA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1711528517; x=1712133317; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=x7g5fTc14qsP28r1k5RjYQCPW18M91Dr5/3NKQ3Cp/Q=; b=OKVtBsBZLn/wjfFTekd0ICgmtvN9b7PImkIS3wIJYJXfLow6vLy90molQuF5Q6rLRW OU4sWqB9SmHejsO5e74pxir/MjVNCH5h3zatI5WAo8lvwoXnOpVzn6OCCEpnLCO+4a7w QQmW0BuCFVShkxT6b5oiiYpWxpMdWgw7Rr4alJWkqD/+AR8DYtMIm4svOg1NHxrs6NdB 2Az1ro2CbjI3vx69G3oFHtUaOYIEM/2sypoaH7+KaV+C+pbX2ZE6hAHZVOOLy0fhSVVN dGoSC+sbOXmBQK3fC1BNT7eJm+KEPlMcvt5j66yerZweycHaOU6NZrG/vuKAKtQ7COrK VuXA== X-Gm-Message-State: AOJu0Yx7A7zU+Z/Vah1/9tLrZMSBbP9CP+gfm2FYp7R5f7g18DDdWI3L gM3R8jNpc2XcwW7Mh9JN9iRATeBfM2MTCWPqzpP+iUc4rnyd3vB3dubROamJBgwPfkQmmM9ibbY L X-Google-Smtp-Source: AGHT+IHsz5JIG6D73WGjO6IlaQh4qB7uRw4DE7sGTr5k5mI8HBNOZo3iRMwd5NrCR5haBFdzdo04UQ== X-Received: by 2002:a05:6000:174a:b0:33d:d7be:3bec with SMTP id m10-20020a056000174a00b0033dd7be3becmr556117wrf.58.1711528516899; Wed, 27 Mar 2024 01:35:16 -0700 (PDT) Received: from claudiu-X670E-Pro-RS.. ([82.78.167.144]) by smtp.gmail.com with ESMTPSA id bq28-20020a5d5a1c000000b00341d84f641asm3591461wrb.8.2024.03.27.01.35.16 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 27 Mar 2024 01:35:16 -0700 (PDT) From: Claudiu X-Google-Original-From: Claudiu To: nobuhiro1.iwamatsu@toshiba.co.jp, pavel@denx.de Cc: cip-dev@lists.cip-project.org, biju.das.jz@bp.renesas.com, prabhakar.mahadev-lad.rj@bp.renesas.com, claudiu.beznea@tuxon.dev Subject: [PATCH 6.1.y-cip 06/13] irqchip/renesas-rzg2l: Document structure members Date: Wed, 27 Mar 2024 10:35:01 +0200 Message-Id: <20240327083508.2229567-7-claudiu.beznea.uj@bp.renesas.com> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20240327083508.2229567-1-claudiu.beznea.uj@bp.renesas.com> References: <20240327083508.2229567-1-claudiu.beznea.uj@bp.renesas.com> MIME-Version: 1.0 List-Id: X-Webhook-Received: from li982-79.members.linode.com [45.33.32.79] by aws-us-west-2-korg-lkml-1.web.codeaurora.org with HTTPS for ; Wed, 27 Mar 2024 10:37:06 -0000 X-Groupsio-URL: https://lists.cip-project.org/g/cip-dev/message/15460 From: Claudiu Beznea commit b94f455372ad6e6b4da8e8ed9864d9c7daaf54b8 upstream. Document structure members to follow the requirements specified in maintainer-tip, section 4.3.7. Struct declarations and initializers. Signed-off-by: Claudiu Beznea Signed-off-by: Thomas Gleixner Reviewed-by: Geert Uytterhoeven Link: https://lore.kernel.org/r/20231120111820.87398-5-claudiu.beznea.uj@bp.renesas.com Signed-off-by: Claudiu Beznea --- drivers/irqchip/irq-renesas-rzg2l.c | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/drivers/irqchip/irq-renesas-rzg2l.c b/drivers/irqchip/irq-renesas-rzg2l.c index 90971ab06f0c..0a77927b678b 100644 --- a/drivers/irqchip/irq-renesas-rzg2l.c +++ b/drivers/irqchip/irq-renesas-rzg2l.c @@ -56,6 +56,12 @@ #define TINT_EXTRACT_HWIRQ(x) FIELD_GET(GENMASK(15, 0), (x)) #define TINT_EXTRACT_GPIOINT(x) FIELD_GET(GENMASK(31, 16), (x)) +/** + * struct rzg2l_irqc_priv - IRQ controller private data structure + * @base: Controller's base address + * @fwspec: IRQ firmware specific data + * @lock: Lock to serialize access to hardware registers + */ struct rzg2l_irqc_priv { void __iomem *base; struct irq_fwspec fwspec[IRQC_NUM_IRQ]; From patchwork Wed Mar 27 08:35:02 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Claudiu Beznea X-Patchwork-Id: 13606160 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from aws-us-west-2-korg-lkml-1.web.codeaurora.org (localhost.localdomain [127.0.0.1]) by smtp.lore.kernel.org (Postfix) with ESMTP id C6BA5CD1289 for ; Wed, 27 Mar 2024 10:37:05 +0000 (UTC) Received: from mail-wr1-f42.google.com (mail-wr1-f42.google.com [209.85.221.42]) by mx.groups.io with SMTP id smtpd.web10.32664.1711528519390737639 for ; Wed, 27 Mar 2024 01:35:19 -0700 Authentication-Results: mx.groups.io; dkim=pass header.i=@tuxon.dev header.s=google header.b=kSZO0CjP; spf=pass (domain: tuxon.dev, ip: 209.85.221.42, mailfrom: claudiu.beznea@tuxon.dev) Received: by mail-wr1-f42.google.com with SMTP id ffacd0b85a97d-33ed6078884so314196f8f.1 for ; Wed, 27 Mar 2024 01:35:19 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=tuxon.dev; s=google; t=1711528518; x=1712133318; darn=lists.cip-project.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=4klHwwGvFefUrgbr/340K/aXWghF68u461LnquTd7wI=; b=kSZO0CjPSwNRv94+SZt7coPh5RxxhBJOcuR/bfbW9uxa10IgerjEamCeyMY5sKWU5o iHGuvTMGQCFWa3x9MgXb9zlecQCFvacXNyew1faR3Qvh45R0b9Sq+bovQclusm9XSzLY 8sumJzBNJWAXJr4WiEENGYDCaCazNVmfca8sZWXS8eoKjzwYGcVhC6caqvxUb9RQESqn S93KbsyR6iv0XIxxYeZKNj2xqF/yHVWHtOF8Iac5QbvKjNNVYb3fwhmMQ+rjUlZ+lQLG 7kH6dXZUaN+wG47RwpZZpyPsGF8ay5jMx9p/Wk58JdtFgLVkPFCasBNkYibDKlpa+gN0 StEA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1711528518; x=1712133318; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=4klHwwGvFefUrgbr/340K/aXWghF68u461LnquTd7wI=; b=AuzeIGedNs4EqqjXf9BMCMU/YVFwzMKrVk0l+HIi/a6VpF6zIjm/63vMH4Xy3N24V1 iuM2UCPFhqKVZ3NBUB6BA6+mGbHL6GUnSU0D4j63Gzh9NsjR5kpd1Mka0x+vokNzccql eGCB0/Lk90gph1PCfHlNV7zAKZ5E2akuxUxJR9hTyDB/ORZF84aCADJFZfS50c37rddZ SG2w+CzmLLT09sT5QfXhH9SpDRBN4KTe2P95bcpTUjkxAPxzuW07JgEsIPwaJxQhZyaA OijNw2w+iNRHb0+i4qxA8259qIMfxa+G7gD91PLE8aynkZULaC/hVX7TkDuQXJUnuGa8 1pTw== X-Gm-Message-State: AOJu0YxTRkLgJT2ABXMRcIaKYbvpKxv++zM2F1R/7GyIsnN9uTouCM8z j7n4Tv7S3eKwZ53cEzvsLdU0GQqZv1Ocr7LmOGcOxe4YkDdV1Lo17ZWq+jEACtA= X-Google-Smtp-Source: AGHT+IGcHsjxzelCiqCG5MyirHUlzF5LALJ0wmrjtPC2nAvI7EtYtyDtXnbFADejwPuVBXXjffp64A== X-Received: by 2002:a05:6000:1376:b0:341:ab6c:71e4 with SMTP id q22-20020a056000137600b00341ab6c71e4mr3516331wrz.19.1711528517893; Wed, 27 Mar 2024 01:35:17 -0700 (PDT) Received: from claudiu-X670E-Pro-RS.. ([82.78.167.144]) by smtp.gmail.com with ESMTPSA id bq28-20020a5d5a1c000000b00341d84f641asm3591461wrb.8.2024.03.27.01.35.17 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 27 Mar 2024 01:35:17 -0700 (PDT) From: Claudiu X-Google-Original-From: Claudiu To: nobuhiro1.iwamatsu@toshiba.co.jp, pavel@denx.de Cc: cip-dev@lists.cip-project.org, biju.das.jz@bp.renesas.com, prabhakar.mahadev-lad.rj@bp.renesas.com, claudiu.beznea@tuxon.dev Subject: [PATCH 6.1.y-cip 07/13] irqchip/renesas-rzg2l: Implement restriction when writing ISCR register Date: Wed, 27 Mar 2024 10:35:02 +0200 Message-Id: <20240327083508.2229567-8-claudiu.beznea.uj@bp.renesas.com> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20240327083508.2229567-1-claudiu.beznea.uj@bp.renesas.com> References: <20240327083508.2229567-1-claudiu.beznea.uj@bp.renesas.com> MIME-Version: 1.0 List-Id: X-Webhook-Received: from li982-79.members.linode.com [45.33.32.79] by aws-us-west-2-korg-lkml-1.web.codeaurora.org with HTTPS for ; Wed, 27 Mar 2024 10:37:05 -0000 X-Groupsio-URL: https://lists.cip-project.org/g/cip-dev/message/15461 From: Claudiu Beznea commit ef88eefb1a81a8701eabb7d5ced761a66a465a49 upstream. The RZ/G2L manual (chapter "IRQ Status Control Register (ISCR)") describes the operation to clear interrupts through the ISCR register as follows: [Write operation] When "Falling-edge detection", "Rising-edge detection" or "Falling/Rising-edge detection" is set in IITSR: - In case ISTAT is 1 0: IRQn interrupt detection status is cleared. 1: Invalid to write. - In case ISTAT is 0 Invalid to write. When "Low-level detection" is set in IITSR.: Invalid to write. Take the interrupt type into account when clearing interrupts through the ISCR register to avoid writing the ISCR when the interrupt type is level. Signed-off-by: Claudiu Beznea Signed-off-by: Thomas Gleixner Reviewed-by: Geert Uytterhoeven Link: https://lore.kernel.org/r/20231120111820.87398-6-claudiu.beznea.uj@bp.renesas.com Signed-off-by: Claudiu Beznea --- drivers/irqchip/irq-renesas-rzg2l.c | 14 ++++++++++---- 1 file changed, 10 insertions(+), 4 deletions(-) diff --git a/drivers/irqchip/irq-renesas-rzg2l.c b/drivers/irqchip/irq-renesas-rzg2l.c index 0a77927b678b..d450417948e4 100644 --- a/drivers/irqchip/irq-renesas-rzg2l.c +++ b/drivers/irqchip/irq-renesas-rzg2l.c @@ -78,11 +78,17 @@ static void rzg2l_irq_eoi(struct irq_data *d) unsigned int hw_irq = irqd_to_hwirq(d) - IRQC_IRQ_START; struct rzg2l_irqc_priv *priv = irq_data_to_priv(d); u32 bit = BIT(hw_irq); - u32 reg; + u32 iitsr, iscr; - reg = readl_relaxed(priv->base + ISCR); - if (reg & bit) - writel_relaxed(reg & ~bit, priv->base + ISCR); + iscr = readl_relaxed(priv->base + ISCR); + iitsr = readl_relaxed(priv->base + IITSR); + + /* + * ISCR can only be cleared if the type is falling-edge, rising-edge or + * falling/rising-edge. + */ + if ((iscr & bit) && (iitsr & IITSR_IITSEL_MASK(hw_irq))) + writel_relaxed(iscr & ~bit, priv->base + ISCR); } static void rzg2l_tint_eoi(struct irq_data *d) From patchwork Wed Mar 27 08:35:03 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Claudiu Beznea X-Patchwork-Id: 13606159 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from aws-us-west-2-korg-lkml-1.web.codeaurora.org (localhost.localdomain [127.0.0.1]) by smtp.lore.kernel.org (Postfix) with ESMTP id C6C71CD128A for ; Wed, 27 Mar 2024 10:37:05 +0000 (UTC) Received: from mail-wr1-f42.google.com (mail-wr1-f42.google.com [209.85.221.42]) by mx.groups.io with SMTP id smtpd.web11.32516.1711528520449403787 for ; Wed, 27 Mar 2024 01:35:20 -0700 Authentication-Results: mx.groups.io; dkim=pass header.i=@tuxon.dev header.s=google header.b=TYvILXBw; spf=pass (domain: tuxon.dev, ip: 209.85.221.42, mailfrom: claudiu.beznea@tuxon.dev) Received: by mail-wr1-f42.google.com with SMTP id ffacd0b85a97d-33ececeb19eso4252456f8f.3 for ; Wed, 27 Mar 2024 01:35:20 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=tuxon.dev; s=google; t=1711528519; x=1712133319; darn=lists.cip-project.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=Mgz5IOTWnZ/x53u6wP29b38SXIQbKurIEUwiPvQMgbI=; b=TYvILXBwps/RptxcQZeC4RN4xNDzReDZbCiigKzu+sF3+2ogVrbHjq5FG2nBLVQhCv wr+7Mqdoaw4nNCWGEffYCVU2qk/PtCXtT5ZZ2/iP4QSVzWB4wR16UQiii7B6R47GVYTm fDR6WtSdDqbhcMtFnzC3dgMKXoOGg58619CQiMOl0Bi6GNvesuO3yFu2tTDAoa29bLUC yHciaNcnQCh29ju+P6cyX/R751gNgHTG1rKSV8RruqyfrU19o99/A7TbAAKFZcs9TbRP Zbd9PADyrItyIsjFR+9FhRx6Yh+bx7y5f0n98/EBhcxGxW4MSUBEkogYkar5NqdUhend qolg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1711528519; x=1712133319; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=Mgz5IOTWnZ/x53u6wP29b38SXIQbKurIEUwiPvQMgbI=; b=tOt5gDCGvlEbBNPWz2/ynYpoTbAsXKxNrcP0VS47GebVK7zQEIMtMbUlySZV+7metZ OybIjnlCxA/i9Lvjde42m8QPj0LBurc2yFJTCMxhEKpGyQ3FpTNHmaWbbZoLXWtCeQKb ZR5gqQC3N7H0Ps7Hj4cRjzvroX6rkD/VX10ajYQ0oAoHRur2d/tyyN46Jh2P/6T4NCTl QQR22qIYHBqS3XOIu9HR+HQc0zpyXayQIHoFm7A8A3/4CadetsV/QgEiHQRIvYxNiT1A xAdAW/5KXkWAgNHjPUTaZKXIVpim0QEJT2Dyu+rvl72Nmu+BsA2QRillXAia3aBeSz1k TrUw== X-Gm-Message-State: AOJu0YzCOZQ3P1OVZTqtlOwJ/xYvecJ9lMTaI2iWfv/73dXWn9tr71yH t3jy1d/hiNBl0ItiB+sDrOEnUKyGob9c4p7NPYhOZHqQuEd3a+C8mj4kGWX9mmAzvY0c0S/Wmx6 v X-Google-Smtp-Source: AGHT+IH2l4N2dp8Anf+h22DWO2hmsnDBhXvyOnGqfcJDNv9PZ64Dmvur5pwz7zLiZszG5WFRtbfYpQ== X-Received: by 2002:adf:e3c9:0:b0:33e:38f1:77f6 with SMTP id k9-20020adfe3c9000000b0033e38f177f6mr1140472wrm.39.1711528518922; Wed, 27 Mar 2024 01:35:18 -0700 (PDT) Received: from claudiu-X670E-Pro-RS.. ([82.78.167.144]) by smtp.gmail.com with ESMTPSA id bq28-20020a5d5a1c000000b00341d84f641asm3591461wrb.8.2024.03.27.01.35.18 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 27 Mar 2024 01:35:18 -0700 (PDT) From: Claudiu X-Google-Original-From: Claudiu To: nobuhiro1.iwamatsu@toshiba.co.jp, pavel@denx.de Cc: cip-dev@lists.cip-project.org, biju.das.jz@bp.renesas.com, prabhakar.mahadev-lad.rj@bp.renesas.com, claudiu.beznea@tuxon.dev Subject: [PATCH 6.1.y-cip 08/13] irqchip/renesas-rzg2l: Add macro to retrieve TITSR register offset based on register's index Date: Wed, 27 Mar 2024 10:35:03 +0200 Message-Id: <20240327083508.2229567-9-claudiu.beznea.uj@bp.renesas.com> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20240327083508.2229567-1-claudiu.beznea.uj@bp.renesas.com> References: <20240327083508.2229567-1-claudiu.beznea.uj@bp.renesas.com> MIME-Version: 1.0 List-Id: X-Webhook-Received: from li982-79.members.linode.com [45.33.32.79] by aws-us-west-2-korg-lkml-1.web.codeaurora.org with HTTPS for ; Wed, 27 Mar 2024 10:37:05 -0000 X-Groupsio-URL: https://lists.cip-project.org/g/cip-dev/message/15462 From: Claudiu Beznea commit 2eca4731cc66563b3919d8753dbd74d18c39f662 upstream. There are 2 TITSR registers available on the IA55 interrupt controller. Add a macro that retrieves the TITSR register offset based on it's index. This macro is useful in when adding suspend/resume support so both TITSR registers can be accessed in a for loop. Signed-off-by: Claudiu Beznea Signed-off-by: Thomas Gleixner Link: https://lore.kernel.org/r/20231120111820.87398-7-claudiu.beznea.uj@bp.renesas.com Signed-off-by: Claudiu Beznea --- drivers/irqchip/irq-renesas-rzg2l.c | 14 ++++++-------- 1 file changed, 6 insertions(+), 8 deletions(-) diff --git a/drivers/irqchip/irq-renesas-rzg2l.c b/drivers/irqchip/irq-renesas-rzg2l.c index d450417948e4..34add75080e0 100644 --- a/drivers/irqchip/irq-renesas-rzg2l.c +++ b/drivers/irqchip/irq-renesas-rzg2l.c @@ -28,8 +28,7 @@ #define ISCR 0x10 #define IITSR 0x14 #define TSCR 0x20 -#define TITSR0 0x24 -#define TITSR1 0x28 +#define TITSR(n) (0x24 + (n) * 4) #define TITSR0_MAX_INT 16 #define TITSEL_WIDTH 0x2 #define TSSR(n) (0x30 + ((n) * 4)) @@ -200,8 +199,7 @@ static int rzg2l_tint_set_edge(struct irq_data *d, unsigned int type) struct rzg2l_irqc_priv *priv = irq_data_to_priv(d); unsigned int hwirq = irqd_to_hwirq(d); u32 titseln = hwirq - IRQC_TINT_START; - u32 offset; - u8 sense; + u8 index, sense; u32 reg; switch (type & IRQ_TYPE_SENSE_MASK) { @@ -217,17 +215,17 @@ static int rzg2l_tint_set_edge(struct irq_data *d, unsigned int type) return -EINVAL; } - offset = TITSR0; + index = 0; if (titseln >= TITSR0_MAX_INT) { titseln -= TITSR0_MAX_INT; - offset = TITSR1; + index = 1; } raw_spin_lock(&priv->lock); - reg = readl_relaxed(priv->base + offset); + reg = readl_relaxed(priv->base + TITSR(index)); reg &= ~(IRQ_MASK << (titseln * TITSEL_WIDTH)); reg |= sense << (titseln * TITSEL_WIDTH); - writel_relaxed(reg, priv->base + offset); + writel_relaxed(reg, priv->base + TITSR(index)); raw_spin_unlock(&priv->lock); return 0; From patchwork Wed Mar 27 08:35:04 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Claudiu Beznea X-Patchwork-Id: 13606162 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from aws-us-west-2-korg-lkml-1.web.codeaurora.org (localhost.localdomain [127.0.0.1]) by smtp.lore.kernel.org (Postfix) with ESMTP id CB24FCD128B for ; Wed, 27 Mar 2024 10:37:05 +0000 (UTC) Received: from mail-wm1-f44.google.com (mail-wm1-f44.google.com [209.85.128.44]) by mx.groups.io with SMTP id smtpd.web11.32517.1711528521518579148 for ; Wed, 27 Mar 2024 01:35:21 -0700 Authentication-Results: mx.groups.io; dkim=pass header.i=@tuxon.dev header.s=google header.b=R/n/IrQk; spf=pass (domain: tuxon.dev, ip: 209.85.128.44, mailfrom: claudiu.beznea@tuxon.dev) Received: by mail-wm1-f44.google.com with SMTP id 5b1f17b1804b1-41488f9708fso20351755e9.3 for ; Wed, 27 Mar 2024 01:35:21 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=tuxon.dev; s=google; t=1711528520; x=1712133320; darn=lists.cip-project.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=K5Dudfu5jvncBoxABSbnmSnuPj4UMJnxtxSyuwyBwyc=; b=R/n/IrQkttlkCxs7pM/GHbRMgqe/30xyS115zExYPdIBV0IbyCHsehVEsjKhNB0gJ5 Xnokl5NeZmE7qL43iNyqfwtpxMi+LpLqa93C6RbuuqCU7LEx1t5MerxGiovPxmNTsc0i Ev5hP4/ZX45Cnyjme0Fe91OgTLlxVSlfyL2V1Qc6o/CSNsa1qzAEzrJpzOvfHmo9zWjd 7kgKq/8G+b2Uq7JS27b8ZwQoykydyUDTTJP6ItLh87ywI4LhJprIy+aRCdgNxwPeO7cf gCd0euKaP+kzjjGRuUdivHqDnRnpEneJEaW+9JBH/okp8z4XQAb2zfMx1lLQFTARgKy/ 3MjA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1711528520; x=1712133320; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=K5Dudfu5jvncBoxABSbnmSnuPj4UMJnxtxSyuwyBwyc=; b=TjMRoT6r+SAn7gPsSyeIV/a251lWrsauaxkJcbHGl0/sjv8KhHaRxFPKT0yJ2PbRfb BwDkHVAOylEEDuxEG/6T0Uw4AQwRHgd+hHBAF28vE7Fu6cMAqCqw5ZOdJmJlGxGNXxek 2JoXy1R1CDMX4SaTGOIOAvN8Tyzm6PMbPmq4ZkKa08JGvGYlEfq33inSL80+bVTj89in 37k76imvZjioPcNbRuTCsdw20SkEI2kvSOx4GvkO3/jt+/hxagRnrftjsE1mtABtEMAm mz/RBFc10a9NLrI3BibWlKqLo6281Ngv+TCm+zwgRjGCCb5FcChQb1kkzhhdS7cnMMvE pXEA== X-Gm-Message-State: AOJu0Yw557xbHwIBFE9xKHsX8wWace/d5ctf2Xx4KIglEwAIzrW2V2pi Tfwigc0tVbaSdV+q7p0IQlInMgNmwLx+Go5pYaJL/fc7TG6HU+ksJ48oMIY1YC/arTPXUTEBAjR a X-Google-Smtp-Source: AGHT+IFVGvmTahV7Dy0rTfqT8hkWGs1dEoBGPxBdLfH9sLVphgV5TPIE2ysEautDolJPWrvjbcmQ8w== X-Received: by 2002:a05:600c:1391:b0:414:7ddd:b92e with SMTP id u17-20020a05600c139100b004147dddb92emr1292563wmf.39.1711528519947; Wed, 27 Mar 2024 01:35:19 -0700 (PDT) Received: from claudiu-X670E-Pro-RS.. ([82.78.167.144]) by smtp.gmail.com with ESMTPSA id bq28-20020a5d5a1c000000b00341d84f641asm3591461wrb.8.2024.03.27.01.35.19 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 27 Mar 2024 01:35:19 -0700 (PDT) From: Claudiu X-Google-Original-From: Claudiu To: nobuhiro1.iwamatsu@toshiba.co.jp, pavel@denx.de Cc: cip-dev@lists.cip-project.org, biju.das.jz@bp.renesas.com, prabhakar.mahadev-lad.rj@bp.renesas.com, claudiu.beznea@tuxon.dev Subject: [PATCH 6.1.y-cip 09/13] irqchip/renesas-rzg2l: Flush posted write in irq_eoi() Date: Wed, 27 Mar 2024 10:35:04 +0200 Message-Id: <20240327083508.2229567-10-claudiu.beznea.uj@bp.renesas.com> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20240327083508.2229567-1-claudiu.beznea.uj@bp.renesas.com> References: <20240327083508.2229567-1-claudiu.beznea.uj@bp.renesas.com> MIME-Version: 1.0 List-Id: X-Webhook-Received: from li982-79.members.linode.com [45.33.32.79] by aws-us-west-2-korg-lkml-1.web.codeaurora.org with HTTPS for ; Wed, 27 Mar 2024 10:37:05 -0000 X-Groupsio-URL: https://lists.cip-project.org/g/cip-dev/message/15463 From: Biju Das commit 9eec61df55c51415409c7cc47e9a1c8de94a0522 upstream. The irq_eoi() callback of the RZ/G2L interrupt chip clears the relevant interrupt cause bit in the TSCR register by writing to it. This write is not sufficient because the write is posted and therefore not guaranteed to immediately clear the bit. Due to that delay the CPU can raise the just handled interrupt again. Prevent this by reading the register back which causes the posted write to be flushed to the hardware before the read completes. Fixes: 3fed09559cd8 ("irqchip: Add RZ/G2L IA55 Interrupt Controller driver") Signed-off-by: Biju Das Signed-off-by: Thomas Gleixner Signed-off-by: Claudiu Beznea --- drivers/irqchip/irq-renesas-rzg2l.c | 16 ++++++++++++++-- 1 file changed, 14 insertions(+), 2 deletions(-) diff --git a/drivers/irqchip/irq-renesas-rzg2l.c b/drivers/irqchip/irq-renesas-rzg2l.c index 34add75080e0..552bc7fa7cff 100644 --- a/drivers/irqchip/irq-renesas-rzg2l.c +++ b/drivers/irqchip/irq-renesas-rzg2l.c @@ -86,8 +86,14 @@ static void rzg2l_irq_eoi(struct irq_data *d) * ISCR can only be cleared if the type is falling-edge, rising-edge or * falling/rising-edge. */ - if ((iscr & bit) && (iitsr & IITSR_IITSEL_MASK(hw_irq))) + if ((iscr & bit) && (iitsr & IITSR_IITSEL_MASK(hw_irq))) { writel_relaxed(iscr & ~bit, priv->base + ISCR); + /* + * Enforce that the posted write is flushed to prevent that the + * just handled interrupt is raised again. + */ + readl_relaxed(priv->base + ISCR); + } } static void rzg2l_tint_eoi(struct irq_data *d) @@ -98,8 +104,14 @@ static void rzg2l_tint_eoi(struct irq_data *d) u32 reg; reg = readl_relaxed(priv->base + TSCR); - if (reg & bit) + if (reg & bit) { writel_relaxed(reg & ~bit, priv->base + TSCR); + /* + * Enforce that the posted write is flushed to prevent that the + * just handled interrupt is raised again. + */ + readl_relaxed(priv->base + TSCR); + } } static void rzg2l_irqc_eoi(struct irq_data *d) From patchwork Wed Mar 27 08:35:05 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Claudiu Beznea X-Patchwork-Id: 13606163 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from aws-us-west-2-korg-lkml-1.web.codeaurora.org (localhost.localdomain [127.0.0.1]) by smtp.lore.kernel.org (Postfix) with ESMTP id DA02BCD128E for ; Wed, 27 Mar 2024 10:37:05 +0000 (UTC) Received: from mail-lj1-f177.google.com (mail-lj1-f177.google.com [209.85.208.177]) by mx.groups.io with SMTP id smtpd.web10.32665.1711528523352686860 for ; Wed, 27 Mar 2024 01:35:23 -0700 Authentication-Results: mx.groups.io; dkim=pass header.i=@tuxon.dev header.s=google header.b=iEvA/e8D; spf=pass (domain: tuxon.dev, ip: 209.85.208.177, mailfrom: claudiu.beznea@tuxon.dev) Received: by mail-lj1-f177.google.com with SMTP id 38308e7fff4ca-2d109e82bd0so88033891fa.3 for ; Wed, 27 Mar 2024 01:35:23 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=tuxon.dev; s=google; t=1711528521; x=1712133321; darn=lists.cip-project.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=UrYgqeVdwYnOeWQIz1CrzpPUetGM+bBopl7k6wIVYc8=; b=iEvA/e8DSXw2/S6sT/G2/HOu3BScAf2COPcizt0XobinS78Z3jTD5Lh/xYSLL5AIKm lScrcPEhmdwLu03s9pkjLqMO/OOd18rek8ZqdNs2TUzVtqwpa/h94bAu1jirnqjCH9aV uKzl5xek4S76gs+TbT/ckNoiZRyzRnH9eo3YzWd/s8eFq2ToOeZ98bRoPG8RbcSm/HQ5 gf/iWddfTgE8/AE8G2UF7TVjmjeVjwmWlq2MpxjMZPnak7NY1n2+Vugw2J7dK7HWjGfv xkSjEiH+FsLnI2OhvesHiaRjOUEhSrnAt8fAk8/Mdkv2tzF/I7TcjuheIrFpC63dvjZ2 /iTQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1711528521; x=1712133321; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=UrYgqeVdwYnOeWQIz1CrzpPUetGM+bBopl7k6wIVYc8=; b=p/9woTQhnOXeYoZICPRJ/moKScrsYFqAD3Ag8zSybM4GKXnFKRLYG/mnw3Uryu9gam HttL8riNyAlFAHO0Xl1tiirTUxeaLHYqQAn7K0r7JEWpph6kawq670mWC7hALjprTIgL I/rhwp7sx/JaqeZLsaiyK5HZ84s9RcmlMWQMYiaaObxsgl8w2SregyY/ppbmAXY7F1v4 60jje9++7aGoshrpybXo/5lMD757r8YMrbP/gv6EzGqx0USXqb+cIt9Bq3p5At5oYViU mHwRk3bmuUpWvoDo6jjxWyNh/xRrMU45BaBHCqK3v72UEJpgre1qz314PrUU3D2nel2s 0q7Q== X-Gm-Message-State: AOJu0YyEONx55+phRGzwJLkmdV7zI+cG9Weqd/SJSUH6m6YZ9Au7Ooqe UsdXVnUyeKdGCvHDGN1JFga+gfRzypZLsGMqy/uUrF5fYwB3wjRAGLlLy9ebfEM= X-Google-Smtp-Source: AGHT+IGhEBonEAdqFyDfXHcMHGOkILKizatj9SMVw3ye9oti7jh/Id9myLXNwI4/PFU0OYij16lk6A== X-Received: by 2002:a2e:2e1a:0:b0:2d4:8fd0:b5f2 with SMTP id u26-20020a2e2e1a000000b002d48fd0b5f2mr397465lju.7.1711528521123; Wed, 27 Mar 2024 01:35:21 -0700 (PDT) Received: from claudiu-X670E-Pro-RS.. ([82.78.167.144]) by smtp.gmail.com with ESMTPSA id bq28-20020a5d5a1c000000b00341d84f641asm3591461wrb.8.2024.03.27.01.35.20 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 27 Mar 2024 01:35:20 -0700 (PDT) From: Claudiu X-Google-Original-From: Claudiu To: nobuhiro1.iwamatsu@toshiba.co.jp, pavel@denx.de Cc: cip-dev@lists.cip-project.org, biju.das.jz@bp.renesas.com, prabhakar.mahadev-lad.rj@bp.renesas.com, claudiu.beznea@tuxon.dev Subject: [PATCH 6.1.y-cip 10/13] irqchip/renesas-rzg2l: Rename rzg2l_tint_eoi() Date: Wed, 27 Mar 2024 10:35:05 +0200 Message-Id: <20240327083508.2229567-11-claudiu.beznea.uj@bp.renesas.com> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20240327083508.2229567-1-claudiu.beznea.uj@bp.renesas.com> References: <20240327083508.2229567-1-claudiu.beznea.uj@bp.renesas.com> MIME-Version: 1.0 List-Id: X-Webhook-Received: from li982-79.members.linode.com [45.33.32.79] by aws-us-west-2-korg-lkml-1.web.codeaurora.org with HTTPS for ; Wed, 27 Mar 2024 10:37:05 -0000 X-Groupsio-URL: https://lists.cip-project.org/g/cip-dev/message/15464 From: Biju Das commit 7cb6362c63df233172eaecddaf9ce2ce2f769112 upstream. Rename rzg2l_tint_eoi()->rzg2l_clear_tint_int() and simplify the code by removing redundant priv and hw_irq local variables. Signed-off-by: Biju Das Signed-off-by: Thomas Gleixner Reviewed-by: Geert Uytterhoeven Signed-off-by: Claudiu Beznea --- drivers/irqchip/irq-renesas-rzg2l.c | 8 +++----- 1 file changed, 3 insertions(+), 5 deletions(-) diff --git a/drivers/irqchip/irq-renesas-rzg2l.c b/drivers/irqchip/irq-renesas-rzg2l.c index 552bc7fa7cff..41b47572c294 100644 --- a/drivers/irqchip/irq-renesas-rzg2l.c +++ b/drivers/irqchip/irq-renesas-rzg2l.c @@ -96,11 +96,9 @@ static void rzg2l_irq_eoi(struct irq_data *d) } } -static void rzg2l_tint_eoi(struct irq_data *d) +static void rzg2l_clear_tint_int(struct rzg2l_irqc_priv *priv, unsigned int hwirq) { - unsigned int hw_irq = irqd_to_hwirq(d) - IRQC_TINT_START; - struct rzg2l_irqc_priv *priv = irq_data_to_priv(d); - u32 bit = BIT(hw_irq); + u32 bit = BIT(hwirq - IRQC_TINT_START); u32 reg; reg = readl_relaxed(priv->base + TSCR); @@ -123,7 +121,7 @@ static void rzg2l_irqc_eoi(struct irq_data *d) if (hw_irq >= IRQC_IRQ_START && hw_irq <= IRQC_IRQ_COUNT) rzg2l_irq_eoi(d); else if (hw_irq >= IRQC_TINT_START && hw_irq < IRQC_NUM_IRQ) - rzg2l_tint_eoi(d); + rzg2l_clear_tint_int(priv, hw_irq); raw_spin_unlock(&priv->lock); irq_chip_eoi_parent(d); } From patchwork Wed Mar 27 08:35:06 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Claudiu Beznea X-Patchwork-Id: 13606171 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from aws-us-west-2-korg-lkml-1.web.codeaurora.org (localhost.localdomain [127.0.0.1]) by smtp.lore.kernel.org (Postfix) with ESMTP id E8943CD1292 for ; Wed, 27 Mar 2024 10:37:05 +0000 (UTC) Received: from mail-wr1-f54.google.com (mail-wr1-f54.google.com [209.85.221.54]) by mx.groups.io with SMTP id smtpd.web11.32518.1711528523803034073 for ; Wed, 27 Mar 2024 01:35:24 -0700 Authentication-Results: mx.groups.io; dkim=pass header.i=@tuxon.dev header.s=google header.b=Bm09GCB8; spf=pass (domain: tuxon.dev, ip: 209.85.221.54, mailfrom: claudiu.beznea@tuxon.dev) Received: by mail-wr1-f54.google.com with SMTP id ffacd0b85a97d-3416a975840so4868948f8f.0 for ; Wed, 27 Mar 2024 01:35:23 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=tuxon.dev; s=google; t=1711528522; x=1712133322; darn=lists.cip-project.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=L+Hq2Scq0ORnlZyCyAOyivVEz7ED/K9AXWQbnXxXutw=; b=Bm09GCB8ufJmPnN8ygFJ6p+K3ErU6raFlgvhu/ifPDdvplzMaJC9tuf57I0MvalTwC YsnKMBBo9aEcuyGVT7HfcyJsfSltiwAc9r2e0DytwYy4iMgnFfFzXlZ0+trMvCtakskZ baaMEopJ5g9ZGTDjI55SMW3ANlBl5PGm9KY6lwm2pczF4HlkE7OeuEW7cu1U+jh1WW6w LNVc95GUYox3sGdBext90WBAUEH8YdBHvZHMhYa5nYk9eENdlXn/x6UmNzRqKBBd3BXq YC2NMHaxErg+k3RYz8zDSLju8ztomeA1AKI9vdSb6wAKiTOOu4P/4tQf17V4QuM4tbKM OoPw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1711528522; x=1712133322; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=L+Hq2Scq0ORnlZyCyAOyivVEz7ED/K9AXWQbnXxXutw=; b=ZCnIVXvxi/GUgo9KLl0qaW3UYCmnTfL8kazKXgjmzG5+CCVQuZ8R8vkHBaf3A6D/wY TErvGUp9SJkEOwvXVuRk4XPeM9z2fjyK5DW3IXcSfzGrHXxKnEhmz92awsXy0TIjRQfy BfoMLCLD7TGefMYlwRpZ5UMkqGUkGtDT6C3VqhxH6KkSLjtJlHbONBsmokN2R+DJhOnN jNeDcUr+skt1d9jg/ft5TRaVZiz71a5mR6sul+7+hV2jic3zQL8el99Mo+mkf5asz77v S3VXUnwjOfQwOtag3U/5F1IsRmp+0UmmpKP+0ppEw6inMtwv9kw+DD77hcOZ7V30TOeT 63QQ== X-Gm-Message-State: AOJu0Yyn90yRnlXsQ40BLuolnYD7gE6vpirQzfmIhZyKI0j9rok64GJR AR9IBn5KnbOF0PMVZOTlpavuVyOpAtFh/4ENjn/g6cIAsOdZYisYW5IsG76O3qk= X-Google-Smtp-Source: AGHT+IEVjkkIL2QApLTLdpBafqz1i8qj9CBSzAnauTtMGDcYm8Tq7IeaMF2nFkJ2RHpT5cX00M//sw== X-Received: by 2002:adf:f88a:0:b0:33e:6056:6b8b with SMTP id u10-20020adff88a000000b0033e60566b8bmr3808437wrp.7.1711528522276; Wed, 27 Mar 2024 01:35:22 -0700 (PDT) Received: from claudiu-X670E-Pro-RS.. ([82.78.167.144]) by smtp.gmail.com with ESMTPSA id bq28-20020a5d5a1c000000b00341d84f641asm3591461wrb.8.2024.03.27.01.35.21 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 27 Mar 2024 01:35:21 -0700 (PDT) From: Claudiu X-Google-Original-From: Claudiu To: nobuhiro1.iwamatsu@toshiba.co.jp, pavel@denx.de Cc: cip-dev@lists.cip-project.org, biju.das.jz@bp.renesas.com, prabhakar.mahadev-lad.rj@bp.renesas.com, claudiu.beznea@tuxon.dev Subject: [PATCH 6.1.y-cip 11/13] irqchip/renesas-rzg2l: Rename rzg2l_irq_eoi() Date: Wed, 27 Mar 2024 10:35:06 +0200 Message-Id: <20240327083508.2229567-12-claudiu.beznea.uj@bp.renesas.com> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20240327083508.2229567-1-claudiu.beznea.uj@bp.renesas.com> References: <20240327083508.2229567-1-claudiu.beznea.uj@bp.renesas.com> MIME-Version: 1.0 List-Id: X-Webhook-Received: from li982-79.members.linode.com [45.33.32.79] by aws-us-west-2-korg-lkml-1.web.codeaurora.org with HTTPS for ; Wed, 27 Mar 2024 10:37:05 -0000 X-Groupsio-URL: https://lists.cip-project.org/g/cip-dev/message/15465 From: Biju Das commit b4b5cd61a6fdd92ede0dc39f0850a182affd1323 upstream. Rename rzg2l_irq_eoi()->rzg2l_clear_irq_int() and simplify the code by removing redundant priv local variable. Suggested-by: Geert Uytterhoeven Signed-off-by: Biju Das Signed-off-by: Thomas Gleixner Signed-off-by: Claudiu Beznea --- drivers/irqchip/irq-renesas-rzg2l.c | 7 +++---- 1 file changed, 3 insertions(+), 4 deletions(-) diff --git a/drivers/irqchip/irq-renesas-rzg2l.c b/drivers/irqchip/irq-renesas-rzg2l.c index 41b47572c294..fb04e5450497 100644 --- a/drivers/irqchip/irq-renesas-rzg2l.c +++ b/drivers/irqchip/irq-renesas-rzg2l.c @@ -72,10 +72,9 @@ static struct rzg2l_irqc_priv *irq_data_to_priv(struct irq_data *data) return data->domain->host_data; } -static void rzg2l_irq_eoi(struct irq_data *d) +static void rzg2l_clear_irq_int(struct rzg2l_irqc_priv *priv, unsigned int hwirq) { - unsigned int hw_irq = irqd_to_hwirq(d) - IRQC_IRQ_START; - struct rzg2l_irqc_priv *priv = irq_data_to_priv(d); + unsigned int hw_irq = hwirq - IRQC_IRQ_START; u32 bit = BIT(hw_irq); u32 iitsr, iscr; @@ -119,7 +118,7 @@ static void rzg2l_irqc_eoi(struct irq_data *d) raw_spin_lock(&priv->lock); if (hw_irq >= IRQC_IRQ_START && hw_irq <= IRQC_IRQ_COUNT) - rzg2l_irq_eoi(d); + rzg2l_clear_irq_int(priv, hw_irq); else if (hw_irq >= IRQC_TINT_START && hw_irq < IRQC_NUM_IRQ) rzg2l_clear_tint_int(priv, hw_irq); raw_spin_unlock(&priv->lock); From patchwork Wed Mar 27 08:35:07 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Claudiu Beznea X-Patchwork-Id: 13606170 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from aws-us-west-2-korg-lkml-1.web.codeaurora.org (localhost.localdomain [127.0.0.1]) by smtp.lore.kernel.org (Postfix) with ESMTP id 008EBCD1293 for ; Wed, 27 Mar 2024 10:37:06 +0000 (UTC) Received: from mail-wr1-f45.google.com (mail-wr1-f45.google.com [209.85.221.45]) by mx.groups.io with SMTP id smtpd.web10.32667.1711528524827209331 for ; Wed, 27 Mar 2024 01:35:25 -0700 Authentication-Results: mx.groups.io; dkim=pass header.i=@tuxon.dev header.s=google header.b=DxJ2VapV; spf=pass (domain: tuxon.dev, ip: 209.85.221.45, mailfrom: claudiu.beznea@tuxon.dev) Received: by mail-wr1-f45.google.com with SMTP id ffacd0b85a97d-341b01dbebbso5017080f8f.0 for ; Wed, 27 Mar 2024 01:35:24 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=tuxon.dev; s=google; t=1711528523; x=1712133323; darn=lists.cip-project.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=q1z0IJwHMKaIHUipl9L+gJ/oXlxgEc4M8WRcCg0pMBc=; b=DxJ2VapVh5IWNHoSKksmbcZHaTuWvQUbw5mkCRUF/7MwNTbdI2ZOtGrmv9FwqIjZuo xuq7iD1HW4+hLkrrvkZwxnymHfZAgaYjjzYV3UNuHKt/zda6w4I3SLArqxZxF8HCgS2f uGSm0cMPbkaxINsU+uHAJTg5mkbku/+Yp1+TMl2GfvwPOeFzpzAcpfkI0oxTtTnlZTqE bGVf835YYhpmOffSRwk8gcwBRJ2uHXgAcNBttm08it+EQ0n33IxnrHj/62Er9r5VoS6n sNAwVtExsx3hNMrkm7tHFwHyv91YSJSs7hF6Ms0UgpXeEGn9rzuLJjJR36G/PuCC9wSb sI2g== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1711528523; x=1712133323; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=q1z0IJwHMKaIHUipl9L+gJ/oXlxgEc4M8WRcCg0pMBc=; b=nKZ9rqNHNGliuDyt+zf6J5kfcW+seOETRbcrqKZziayXEzSgq8WgBvu1nZrdOGdvw7 fe5F7zPYhaZyWmK9kJ8wsngocvh4KnDkVHyS8tmIosM+RW5TIdMhAAJAz1z2S4Wg2OJE 3d7YTnqnoxqp5FDB+eivLqPL6q2gyyjyNtbPIMC6zulzRGMiVgrJLcBsGOVjLt4uoF8D 5iXgHI9s/SvJsGHqWG1HzqMjqBLzCjtplBXIQbPhS0H2jQbKe8ZfaAx7aNozvwIeyNs4 CqqmDt85Om41KlQvIz3G3XhYftIHoip6mVQUZyitMMTgfKNbKBlyoxyJYPblfW08d7J8 Zk1Q== X-Gm-Message-State: AOJu0Yw8kQ1pkQ/G/1vGAz7mdC6KAH7mnpDC8TOLQwiLtjPnxc48wGws iyKICbdX0GMoYtOdGzmwX82lmiEwVpLqJXPbT7gE3c1Gn4ip4IRIKrDDrbF78xo= X-Google-Smtp-Source: AGHT+IFq8iUSiJ4FiRIT8rMd8qpWM/bTAnZaiuh2ropT89Dq3qMsQr07IB7UmCYtfmtlUx9BJoXmOQ== X-Received: by 2002:adf:ee89:0:b0:33d:2474:5aa with SMTP id b9-20020adfee89000000b0033d247405aamr1453940wro.40.1711528523350; Wed, 27 Mar 2024 01:35:23 -0700 (PDT) Received: from claudiu-X670E-Pro-RS.. ([82.78.167.144]) by smtp.gmail.com with ESMTPSA id bq28-20020a5d5a1c000000b00341d84f641asm3591461wrb.8.2024.03.27.01.35.22 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 27 Mar 2024 01:35:22 -0700 (PDT) From: Claudiu X-Google-Original-From: Claudiu To: nobuhiro1.iwamatsu@toshiba.co.jp, pavel@denx.de Cc: cip-dev@lists.cip-project.org, biju.das.jz@bp.renesas.com, prabhakar.mahadev-lad.rj@bp.renesas.com, claudiu.beznea@tuxon.dev Subject: [PATCH 6.1.y-cip 12/13] irqchip/renesas-rzg2l: Prevent spurious interrupts when setting trigger type Date: Wed, 27 Mar 2024 10:35:07 +0200 Message-Id: <20240327083508.2229567-13-claudiu.beznea.uj@bp.renesas.com> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20240327083508.2229567-1-claudiu.beznea.uj@bp.renesas.com> References: <20240327083508.2229567-1-claudiu.beznea.uj@bp.renesas.com> MIME-Version: 1.0 List-Id: X-Webhook-Received: from li982-79.members.linode.com [45.33.32.79] by aws-us-west-2-korg-lkml-1.web.codeaurora.org with HTTPS for ; Wed, 27 Mar 2024 10:37:05 -0000 X-Groupsio-URL: https://lists.cip-project.org/g/cip-dev/message/15466 From: Biju Das commit 853a6030303f8a8fa54929b68e5665d9b21aa405 upstream. RZ/G2L interrupt chips require that the interrupt is masked before changing the NMI, IRQ, TINT interrupt settings. Aside of that, after setting an edge trigger type it is required to clear the interrupt status register in order to avoid spurious interrupts. The current implementation fails to do either of that and therefore is prone to generate spurious interrupts when setting the trigger type. Address this by: - Ensuring that the interrupt is masked at the chip level across the update for the TINT chip - Clearing the interrupt status register after updating the trigger mode for edge type interrupts [ tglx: Massaged changelog and reverted the spin_lock_irqsave() change as the set_type() callback is always called with interrupts disabled. ] Fixes: 3fed09559cd8 ("irqchip: Add RZ/G2L IA55 Interrupt Controller driver") Signed-off-by: Biju Das Signed-off-by: Thomas Gleixner Signed-off-by: Claudiu Beznea --- drivers/irqchip/irq-renesas-rzg2l.c | 36 +++++++++++++++++++++++++---- 1 file changed, 32 insertions(+), 4 deletions(-) diff --git a/drivers/irqchip/irq-renesas-rzg2l.c b/drivers/irqchip/irq-renesas-rzg2l.c index fb04e5450497..3acdecf39404 100644 --- a/drivers/irqchip/irq-renesas-rzg2l.c +++ b/drivers/irqchip/irq-renesas-rzg2l.c @@ -168,8 +168,10 @@ static void rzg2l_irqc_irq_enable(struct irq_data *d) static int rzg2l_irq_set_type(struct irq_data *d, unsigned int type) { - unsigned int hw_irq = irqd_to_hwirq(d) - IRQC_IRQ_START; struct rzg2l_irqc_priv *priv = irq_data_to_priv(d); + unsigned int hwirq = irqd_to_hwirq(d); + u32 iitseln = hwirq - IRQC_IRQ_START; + bool clear_irq_int = false; u16 sense, tmp; switch (type & IRQ_TYPE_SENSE_MASK) { @@ -179,14 +181,17 @@ static int rzg2l_irq_set_type(struct irq_data *d, unsigned int type) case IRQ_TYPE_EDGE_FALLING: sense = IITSR_IITSEL_EDGE_FALLING; + clear_irq_int = true; break; case IRQ_TYPE_EDGE_RISING: sense = IITSR_IITSEL_EDGE_RISING; + clear_irq_int = true; break; case IRQ_TYPE_EDGE_BOTH: sense = IITSR_IITSEL_EDGE_BOTH; + clear_irq_int = true; break; default: @@ -195,21 +200,40 @@ static int rzg2l_irq_set_type(struct irq_data *d, unsigned int type) raw_spin_lock(&priv->lock); tmp = readl_relaxed(priv->base + IITSR); - tmp &= ~IITSR_IITSEL_MASK(hw_irq); - tmp |= IITSR_IITSEL(hw_irq, sense); + tmp &= ~IITSR_IITSEL_MASK(iitseln); + tmp |= IITSR_IITSEL(iitseln, sense); + if (clear_irq_int) + rzg2l_clear_irq_int(priv, hwirq); writel_relaxed(tmp, priv->base + IITSR); raw_spin_unlock(&priv->lock); return 0; } +static u32 rzg2l_disable_tint_and_set_tint_source(struct irq_data *d, struct rzg2l_irqc_priv *priv, + u32 reg, u32 tssr_offset, u8 tssr_index) +{ + u32 tint = (u32)(uintptr_t)irq_data_get_irq_chip_data(d); + u32 tien = reg & (TIEN << TSSEL_SHIFT(tssr_offset)); + + /* Clear the relevant byte in reg */ + reg &= ~(TSSEL_MASK << TSSEL_SHIFT(tssr_offset)); + /* Set TINT and leave TIEN clear */ + reg |= tint << TSSEL_SHIFT(tssr_offset); + writel_relaxed(reg, priv->base + TSSR(tssr_index)); + + return reg | tien; +} + static int rzg2l_tint_set_edge(struct irq_data *d, unsigned int type) { struct rzg2l_irqc_priv *priv = irq_data_to_priv(d); unsigned int hwirq = irqd_to_hwirq(d); u32 titseln = hwirq - IRQC_TINT_START; + u32 tssr_offset = TSSR_OFFSET(titseln); + u8 tssr_index = TSSR_INDEX(titseln); u8 index, sense; - u32 reg; + u32 reg, tssr; switch (type & IRQ_TYPE_SENSE_MASK) { case IRQ_TYPE_EDGE_RISING: @@ -231,10 +255,14 @@ static int rzg2l_tint_set_edge(struct irq_data *d, unsigned int type) } raw_spin_lock(&priv->lock); + tssr = readl_relaxed(priv->base + TSSR(tssr_index)); + tssr = rzg2l_disable_tint_and_set_tint_source(d, priv, tssr, tssr_offset, tssr_index); reg = readl_relaxed(priv->base + TITSR(index)); reg &= ~(IRQ_MASK << (titseln * TITSEL_WIDTH)); reg |= sense << (titseln * TITSEL_WIDTH); writel_relaxed(reg, priv->base + TITSR(index)); + rzg2l_clear_tint_int(priv, hwirq); + writel_relaxed(tssr, priv->base + TSSR(tssr_index)); raw_spin_unlock(&priv->lock); return 0; From patchwork Wed Mar 27 08:35:08 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Claudiu Beznea X-Patchwork-Id: 13606158 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from aws-us-west-2-korg-lkml-1.web.codeaurora.org (localhost.localdomain [127.0.0.1]) by smtp.lore.kernel.org (Postfix) with ESMTP id A86C0C47DD9 for ; Wed, 27 Mar 2024 10:37:05 +0000 (UTC) Received: from mail-wr1-f52.google.com (mail-wr1-f52.google.com [209.85.221.52]) by mx.groups.io with SMTP id smtpd.web10.32668.1711528525917814058 for ; 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([82.78.167.144]) by smtp.gmail.com with ESMTPSA id bq28-20020a5d5a1c000000b00341d84f641asm3591461wrb.8.2024.03.27.01.35.23 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 27 Mar 2024 01:35:24 -0700 (PDT) From: Claudiu X-Google-Original-From: Claudiu To: nobuhiro1.iwamatsu@toshiba.co.jp, pavel@denx.de Cc: cip-dev@lists.cip-project.org, biju.das.jz@bp.renesas.com, prabhakar.mahadev-lad.rj@bp.renesas.com, claudiu.beznea@tuxon.dev Subject: [PATCH 6.1.y-cip 13/13] irqchip/renesas-rzg2l: Do not set TIEN and TINT source at the same time Date: Wed, 27 Mar 2024 10:35:08 +0200 Message-Id: <20240327083508.2229567-14-claudiu.beznea.uj@bp.renesas.com> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20240327083508.2229567-1-claudiu.beznea.uj@bp.renesas.com> References: <20240327083508.2229567-1-claudiu.beznea.uj@bp.renesas.com> MIME-Version: 1.0 List-Id: X-Webhook-Received: from li982-79.members.linode.com [45.33.32.79] by aws-us-west-2-korg-lkml-1.web.codeaurora.org with HTTPS for ; Wed, 27 Mar 2024 10:37:05 -0000 X-Groupsio-URL: https://lists.cip-project.org/g/cip-dev/message/15467 From: Biju Das commit dce0919c83c325ac9dec5bc8838d5de6d32c01b1 upstream. As per the hardware team, TIEN and TINT source should not set at the same time due to a possible hardware race leading to spurious IRQ. Currently on some scenarios hardware settings for TINT detection is not in sync with TINT source as the enable/disable overrides source setting value leading to hardware inconsistent state. For eg: consider the case GPIOINT0 is used as TINT interrupt and configuring GPIOINT5 as edge type. During rzg2l_irq_set_type(), TINT source for GPIOINT5 is set. On disable(), clearing of the entire bytes of TINT source selection for GPIOINT5 is same as GPIOINT0 with TIEN disabled. Apart from this during enable(), the setting of GPIOINT5 with TIEN results in spurious IRQ as due to a HW race, it is possible that IP can use the TIEN with previous source value (GPIOINT0). So, just update TIEN during enable/disable as TINT source is already set during rzg2l_irq_set_type(). This will make the consistent hardware settings for detection method tied with TINT source and allows to simplify the code. Signed-off-by: Biju Das Signed-off-by: Thomas Gleixner Signed-off-by: Claudiu Beznea --- drivers/irqchip/irq-renesas-rzg2l.c | 5 ++--- 1 file changed, 2 insertions(+), 3 deletions(-) diff --git a/drivers/irqchip/irq-renesas-rzg2l.c b/drivers/irqchip/irq-renesas-rzg2l.c index 3acdecf39404..9b0a748ea2cb 100644 --- a/drivers/irqchip/irq-renesas-rzg2l.c +++ b/drivers/irqchip/irq-renesas-rzg2l.c @@ -138,7 +138,7 @@ static void rzg2l_irqc_irq_disable(struct irq_data *d) raw_spin_lock(&priv->lock); reg = readl_relaxed(priv->base + TSSR(tssr_index)); - reg &= ~(TSSEL_MASK << TSSEL_SHIFT(tssr_offset)); + reg &= ~(TIEN << TSSEL_SHIFT(tssr_offset)); writel_relaxed(reg, priv->base + TSSR(tssr_index)); raw_spin_unlock(&priv->lock); } @@ -150,7 +150,6 @@ static void rzg2l_irqc_irq_enable(struct irq_data *d) unsigned int hw_irq = irqd_to_hwirq(d); if (hw_irq >= IRQC_TINT_START && hw_irq < IRQC_NUM_IRQ) { - unsigned long tint = (uintptr_t)irq_data_get_irq_chip_data(d); struct rzg2l_irqc_priv *priv = irq_data_to_priv(d); u32 offset = hw_irq - IRQC_TINT_START; u32 tssr_offset = TSSR_OFFSET(offset); @@ -159,7 +158,7 @@ static void rzg2l_irqc_irq_enable(struct irq_data *d) raw_spin_lock(&priv->lock); reg = readl_relaxed(priv->base + TSSR(tssr_index)); - reg |= (TIEN | tint) << TSSEL_SHIFT(tssr_offset); + reg |= TIEN << TSSEL_SHIFT(tssr_offset); writel_relaxed(reg, priv->base + TSSR(tssr_index)); raw_spin_unlock(&priv->lock); }