From patchwork Wed Mar 27 19:07:23 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Ryan Roberts X-Patchwork-Id: 13607299 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 25C32C54E67 for ; Wed, 27 Mar 2024 19:08:15 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:MIME-Version:References:In-Reply-To: Message-Id:Date:Subject:Cc:To:From:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; bh=hq4qMqQAwQdIbtd9kLChW4qeIvH7xGHUUCcLWZS5hxk=; b=VKd5jTb/FbToQh +TFSVy3WUszkuTtEBoFHCORxD5nGlDcy22M5Sv+n+VGunBAcEot66k3bzSZDkyMPvIjaSNhBJZv57 B0kopH1gBunTSKUR7LzbA9jZDoWoN8/5A04kruVrdz/J2MiD5D20YnzEIkI6sFDjv+89BZ5D53MV4 ZUkwf9f61GchIkmeyF2QimiJ1f14eyuXfMTgHLfT20CNktveyMMw97GKK9aNx5wFXZ4VvzcI50th0 kaNxPuFJ6KqG8Fj4PS0Oxfra7BNqsS+lAiVVvx4tQk0beq8pJfQhIFaAIeL1zMqkqvqtY+zcQRaKq QQywjUnHWLj0vxRlIXTA==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.97.1 #2 (Red Hat Linux)) id 1rpYd0-0000000AiYV-44Ib; Wed, 27 Mar 2024 19:08:02 +0000 Received: from foss.arm.com ([217.140.110.172]) by bombadil.infradead.org with esmtp (Exim 4.97.1 #2 (Red Hat Linux)) id 1rpYcy-0000000AiTO-2RrI for linux-arm-kernel@lists.infradead.org; Wed, 27 Mar 2024 19:08:02 +0000 Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 7D45C2F4; Wed, 27 Mar 2024 12:08:12 -0700 (PDT) Received: from e125769.cambridge.arm.com (e125769.cambridge.arm.com [10.1.196.27]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id F1BA63F694; Wed, 27 Mar 2024 12:07:36 -0700 (PDT) From: Ryan Roberts To: Catalin Marinas , Will Deacon , Mark Rutland , Ard Biesheuvel , David Hildenbrand , Donald Dutile , Eric Chanudet Cc: Ryan Roberts , linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org Subject: [PATCH v1] arm64: mm: Batch dsb and isb when populating pgtables Date: Wed, 27 Mar 2024 19:07:23 +0000 Message-Id: <20240327190723.185232-1-ryan.roberts@arm.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20240326101448.3453626-1-ryan.roberts@arm.com> References: <20240326101448.3453626-1-ryan.roberts@arm.com> MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20240327_120800_705198_5CDE47CA X-CRM114-Status: GOOD ( 12.49 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org After removing uneccessary TLBIs, the next bottleneck when creating the page tables for the linear map is DSB and ISB, which were previously issued per-pte in __set_pte(). Since we are writing multiple ptes in a given pte table, we can elide these barriers and insert them once we have finished writing to the table. Signed-off-by: Ryan Roberts --- arch/arm64/include/asm/pgtable.h | 7 ++++++- arch/arm64/mm/mmu.c | 13 ++++++++++++- 2 files changed, 18 insertions(+), 2 deletions(-) -- 2.25.1 diff --git a/arch/arm64/include/asm/pgtable.h b/arch/arm64/include/asm/pgtable.h index bd5d02f3f0a3..81e427b23b3f 100644 --- a/arch/arm64/include/asm/pgtable.h +++ b/arch/arm64/include/asm/pgtable.h @@ -271,9 +271,14 @@ static inline pte_t pte_mkdevmap(pte_t pte) return set_pte_bit(pte, __pgprot(PTE_DEVMAP | PTE_SPECIAL)); } -static inline void __set_pte(pte_t *ptep, pte_t pte) +static inline void ___set_pte(pte_t *ptep, pte_t pte) { WRITE_ONCE(*ptep, pte); +} + +static inline void __set_pte(pte_t *ptep, pte_t pte) +{ + ___set_pte(ptep, pte); /* * Only if the new pte is valid and kernel, otherwise TLB maintenance diff --git a/arch/arm64/mm/mmu.c b/arch/arm64/mm/mmu.c index 1b2a2a2d09b7..c6d5a76732d4 100644 --- a/arch/arm64/mm/mmu.c +++ b/arch/arm64/mm/mmu.c @@ -301,7 +301,11 @@ static pte_t *init_pte(pte_t *ptep, unsigned long addr, unsigned long end, do { pte_t old_pte = __ptep_get(ptep); - __set_pte(ptep, pfn_pte(__phys_to_pfn(phys), prot)); + /* + * Required barriers to make this visible to the table walker + * are deferred to the end of alloc_init_cont_pte(). + */ + ___set_pte(ptep, pfn_pte(__phys_to_pfn(phys), prot)); /* * After the PTE entry has been populated once, we @@ -358,6 +362,13 @@ static void alloc_init_cont_pte(pmd_t *pmdp, unsigned long addr, } while (addr = next, addr != end); ops->unmap(TYPE_PTE); + + /* + * Ensure all previous pgtable writes are visible to the table walker. + * See init_pte(). + */ + dsb(ishst); + isb(); } static pmd_t *init_pmd(pmd_t *pmdp, unsigned long addr, unsigned long end,