From patchwork Wed Mar 27 21:48:30 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Bjorn Helgaas X-Patchwork-Id: 13607511 X-Patchwork-Delegate: bhelgaas@google.com Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 68206153823; Wed, 27 Mar 2024 21:48:39 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1711576119; cv=none; b=CBGtahS+c+v8TShXu+gEZ8/Gs2RLOyhpTuyIZwQYRAgO7lQ3FGdXaIvUZFvhTR+aRVCuv1Idi/THLK3U3ry93JaqPM9Xjc+m+evDxXQVRlaj3PTBXCPRmTAWitedsXi43dCHP5gZU+E56HaxfgVcnjuKFYo7s/NIJm5pbXAPNxE= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1711576119; c=relaxed/simple; bh=JhM7uD+0y9lsMj8Ti7Upt2hgdOSgQZ9r3BnntyFvl+k=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=WEThtVlzGHQ3GD+jfkcWrAeFSp/rCn5ctucrQUSgkLZgRRoW9sY4iuVTj7rQ/5DtKHBLhEgy4Q6IGXsVUfl50uomBcAYWXDyibOAaSx72oCqWg1GlTIR/cSzo5AxMP0/sWfLWX5w8CIiIUWAO2/GytIQtelfNg2E+8nyN6GYB4c= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=HtiVL/C0; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="HtiVL/C0" Received: by smtp.kernel.org (Postfix) with ESMTPSA id AEF5BC433C7; Wed, 27 Mar 2024 21:48:38 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1711576118; bh=JhM7uD+0y9lsMj8Ti7Upt2hgdOSgQZ9r3BnntyFvl+k=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=HtiVL/C0fh453RGWFRbhL/C3fV0BGa4axK6035RH03+TgUrT/Cb+L1aozk5Ievoa4 fzskSDP6L5+BLM8ZdLxjIpyfc+lAYE9WJVyS4EitA3tIlNg+XlnhYzviPiDID5hAlu s2HFbl006lsrci74MMxB0MRU9NnOJZf0dXwLDoQLNtucA9D8xU7QIoe8fyNuPMjRXS fD3u9EbDVKIaoEuORHrFaNJ84WVu+qFd/Ng5dA4VesNMLxeTHT+562d03K5AjI5MoP FC+rBW9ZRKTUoozoEVQYGyKJvMBw/ysWfyZTPj7xeuoMzJeAEEvASa7+tEIPSsJQv9 yq8t3lve5DPGQ== From: Bjorn Helgaas To: Adrian Hunter , Ulf Hansson , Victor Shih , Ben Chuang Cc: Kai-Heng Feng , Sven van Ashbrook , Stanislaw Kardach , Brian Norris , Jason Lai , Renius Chen , linux-pci@vger.kernel.org, linux-mmc@vger.kernel.org, linux-kernel@vger.kernel.org, Bjorn Helgaas Subject: [PATCH 1/2] mmc: sdhci-pci-gli: Use PCI AER definitions, not hard-coded values Date: Wed, 27 Mar 2024 16:48:30 -0500 Message-Id: <20240327214831.1544595-2-helgaas@kernel.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240327214831.1544595-1-helgaas@kernel.org> References: <20240327214831.1544595-1-helgaas@kernel.org> Precedence: bulk X-Mailing-List: linux-pci@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 From: Bjorn Helgaas 015c9cbcf0ad ("mmc: sdhci-pci-gli: GL9750: Mask the replay timer timeout of AER") added PCI_GLI_9750_CORRERR_MASK, the offset of the AER Capability in config space, and PCI_GLI_9750_CORRERR_MASK_REPLAY_TIMER_TIMEOUT, the Replay Timer Timeout bit in the AER Correctable Error Status register. Use pci_find_ext_capability() to locate the AER Capability and use the existing PCI_ERR_COR_REP_TIMER definition to mask the bit. This removes a little bit of unnecessarily device-specific code and makes AER-related things more greppable. Signed-off-by: Bjorn Helgaas --- drivers/mmc/host/sdhci-pci-gli.c | 26 ++++++++++++++------------ 1 file changed, 14 insertions(+), 12 deletions(-) diff --git a/drivers/mmc/host/sdhci-pci-gli.c b/drivers/mmc/host/sdhci-pci-gli.c index 77911a57b12c..3d5543581537 100644 --- a/drivers/mmc/host/sdhci-pci-gli.c +++ b/drivers/mmc/host/sdhci-pci-gli.c @@ -28,9 +28,6 @@ #define PCI_GLI_9750_PM_CTRL 0xFC #define PCI_GLI_9750_PM_STATE GENMASK(1, 0) -#define PCI_GLI_9750_CORRERR_MASK 0x214 -#define PCI_GLI_9750_CORRERR_MASK_REPLAY_TIMER_TIMEOUT BIT(12) - #define SDHCI_GLI_9750_CFG2 0x848 #define SDHCI_GLI_9750_CFG2_L1DLY GENMASK(28, 24) #define GLI_9750_CFG2_L1DLY_VALUE 0x1F @@ -155,9 +152,6 @@ #define PCI_GLI_9755_PM_CTRL 0xFC #define PCI_GLI_9755_PM_STATE GENMASK(1, 0) -#define PCI_GLI_9755_CORRERR_MASK 0x214 -#define PCI_GLI_9755_CORRERR_MASK_REPLAY_TIMER_TIMEOUT BIT(12) - #define SDHCI_GLI_9767_GM_BURST_SIZE 0x510 #define SDHCI_GLI_9767_GM_BURST_SIZE_AXI_ALWAYS_SET BIT(8) @@ -547,6 +541,7 @@ static void gl9750_hw_setting(struct sdhci_host *host) { struct sdhci_pci_slot *slot = sdhci_priv(host); struct pci_dev *pdev; + int aer; u32 value; pdev = slot->chip->pdev; @@ -568,9 +563,12 @@ static void gl9750_hw_setting(struct sdhci_host *host) pci_write_config_dword(pdev, PCI_GLI_9750_PM_CTRL, value); /* mask the replay timer timeout of AER */ - pci_read_config_dword(pdev, PCI_GLI_9750_CORRERR_MASK, &value); - value |= PCI_GLI_9750_CORRERR_MASK_REPLAY_TIMER_TIMEOUT; - pci_write_config_dword(pdev, PCI_GLI_9750_CORRERR_MASK, value); + aer = pci_find_ext_capability(pdev, PCI_EXT_CAP_ID_ERR); + if (aer) { + pci_read_config_dword(pdev, aer + PCI_ERR_COR_MASK, &value); + value |= PCI_ERR_COR_REP_TIMER; + pci_write_config_dword(pdev, aer + PCI_ERR_COR_MASK, value); + } gl9750_wt_off(host); } @@ -745,6 +743,7 @@ static void sdhci_gl9755_set_clock(struct sdhci_host *host, unsigned int clock) static void gl9755_hw_setting(struct sdhci_pci_slot *slot) { struct pci_dev *pdev = slot->chip->pdev; + int aer; u32 value; gl9755_wt_on(pdev); @@ -782,9 +781,12 @@ static void gl9755_hw_setting(struct sdhci_pci_slot *slot) pci_write_config_dword(pdev, PCI_GLI_9755_PM_CTRL, value); /* mask the replay timer timeout of AER */ - pci_read_config_dword(pdev, PCI_GLI_9755_CORRERR_MASK, &value); - value |= PCI_GLI_9755_CORRERR_MASK_REPLAY_TIMER_TIMEOUT; - pci_write_config_dword(pdev, PCI_GLI_9755_CORRERR_MASK, value); + aer = pci_find_ext_capability(pdev, PCI_EXT_CAP_ID_ERR); + if (aer) { + pci_read_config_dword(pdev, aer + PCI_ERR_COR_MASK, &value); + value |= PCI_ERR_COR_REP_TIMER; + pci_write_config_dword(pdev, aer + PCI_ERR_COR_MASK, value); + } gl9755_wt_off(pdev); } From patchwork Wed Mar 27 21:48:31 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Bjorn Helgaas X-Patchwork-Id: 13607512 X-Patchwork-Delegate: bhelgaas@google.com Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 3214A153BD8; Wed, 27 Mar 2024 21:48:41 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; 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Wed, 27 Mar 2024 21:48:40 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1711576121; bh=v2BT4UBipgbf5NwZ/1uQCPFkKMYGJLIBNZ8gTeusg0M=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=HIrybzyxD/r6vPtLYB9RgY2NIjkmaNefdNocv+sRqxL7TYvpAt1r2qsMLgxvLElgW MbU/19c/1c3LouFayMk2tH52ZwP5ZzYVeRbUX3YfTdxkwXikfVu3CZ6cpEBXzTYTqT irv+wfY9JGhUMCxXMZgmNLWYtha6JWK1ZuhRU06FBXP4+/3TPGVzHK9zXLLXU0s3WM jcoQVnbOzk/j8Nzn/Ezk2zHvbs17vMDxsn3ZYw0KZvoY4iuJmQ0S7rXGMoQmmv35Wx SkYtjIMlaxyJYlnoIH3+0B7iyyrGmdyVX+nHZ5CC9U7nhZ3bXMt2X49iSmBhIcd70C xZr98J0IgfSKw== From: Bjorn Helgaas To: Adrian Hunter , Ulf Hansson , Victor Shih , Ben Chuang Cc: Kai-Heng Feng , Sven van Ashbrook , Stanislaw Kardach , Brian Norris , Jason Lai , Renius Chen , linux-pci@vger.kernel.org, linux-mmc@vger.kernel.org, linux-kernel@vger.kernel.org, Bjorn Helgaas Subject: [PATCH 2/2] mmc: sdhci-pci-gli: Use pci_set_power_state(), not direct PMCSR writes Date: Wed, 27 Mar 2024 16:48:31 -0500 Message-Id: <20240327214831.1544595-3-helgaas@kernel.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240327214831.1544595-1-helgaas@kernel.org> References: <20240327214831.1544595-1-helgaas@kernel.org> Precedence: bulk X-Mailing-List: linux-pci@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 From: Bjorn Helgaas d7133797e9e1 ("mmc: sdhci-pci-gli: A workaround to allow GL9750 to enter ASPM L1.2") and 36ed2fd32b2c ("mmc: sdhci-pci-gli: A workaround to allow GL9755 to enter ASPM L1.2") added writes to the Control register in the Power Management Capability to put the device in D3hot and back to D0. Use the pci_set_power_state() interface instead because these are generic operations that don't need to be driver-specific. Also, the PCI spec requires some delays after these power transitions, and pci_set_power_state() takes care of those, while d7133797e9e1 and 36ed2fd32b2c did not. Signed-off-by: Bjorn Helgaas --- drivers/mmc/host/sdhci-pci-gli.c | 20 ++++---------------- 1 file changed, 4 insertions(+), 16 deletions(-) diff --git a/drivers/mmc/host/sdhci-pci-gli.c b/drivers/mmc/host/sdhci-pci-gli.c index 3d5543581537..0f81586a19df 100644 --- a/drivers/mmc/host/sdhci-pci-gli.c +++ b/drivers/mmc/host/sdhci-pci-gli.c @@ -25,9 +25,6 @@ #define GLI_9750_WT_EN_ON 0x1 #define GLI_9750_WT_EN_OFF 0x0 -#define PCI_GLI_9750_PM_CTRL 0xFC -#define PCI_GLI_9750_PM_STATE GENMASK(1, 0) - #define SDHCI_GLI_9750_CFG2 0x848 #define SDHCI_GLI_9750_CFG2_L1DLY GENMASK(28, 24) #define GLI_9750_CFG2_L1DLY_VALUE 0x1F @@ -149,9 +146,6 @@ #define PCI_GLI_9755_MISC 0x78 #define PCI_GLI_9755_MISC_SSC_OFF BIT(26) -#define PCI_GLI_9755_PM_CTRL 0xFC -#define PCI_GLI_9755_PM_STATE GENMASK(1, 0) - #define SDHCI_GLI_9767_GM_BURST_SIZE 0x510 #define SDHCI_GLI_9767_GM_BURST_SIZE_AXI_ALWAYS_SET BIT(8) @@ -556,11 +550,8 @@ static void gl9750_hw_setting(struct sdhci_host *host) sdhci_writel(host, value, SDHCI_GLI_9750_CFG2); /* toggle PM state to allow GL9750 to enter ASPM L1.2 */ - pci_read_config_dword(pdev, PCI_GLI_9750_PM_CTRL, &value); - value |= PCI_GLI_9750_PM_STATE; - pci_write_config_dword(pdev, PCI_GLI_9750_PM_CTRL, value); - value &= ~PCI_GLI_9750_PM_STATE; - pci_write_config_dword(pdev, PCI_GLI_9750_PM_CTRL, value); + pci_set_power_state(pdev, PCI_D3hot); + pci_set_power_state(pdev, PCI_D0); /* mask the replay timer timeout of AER */ aer = pci_find_ext_capability(pdev, PCI_EXT_CAP_ID_ERR); @@ -774,11 +765,8 @@ static void gl9755_hw_setting(struct sdhci_pci_slot *slot) pci_write_config_dword(pdev, PCI_GLI_9755_CFG2, value); /* toggle PM state to allow GL9755 to enter ASPM L1.2 */ - pci_read_config_dword(pdev, PCI_GLI_9755_PM_CTRL, &value); - value |= PCI_GLI_9755_PM_STATE; - pci_write_config_dword(pdev, PCI_GLI_9755_PM_CTRL, value); - value &= ~PCI_GLI_9755_PM_STATE; - pci_write_config_dword(pdev, PCI_GLI_9755_PM_CTRL, value); + pci_set_power_state(pdev, PCI_D3hot); + pci_set_power_state(pdev, PCI_D0); /* mask the replay timer timeout of AER */ aer = pci_find_ext_capability(pdev, PCI_EXT_CAP_ID_ERR);