From patchwork Thu Mar 28 07:41:30 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Sibi Sankar X-Patchwork-Id: 13608082 Received: from mx0b-0031df01.pphosted.com (mx0b-0031df01.pphosted.com [205.220.180.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 3B3EE1EF0E; Thu, 28 Mar 2024 07:42:07 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=205.220.180.131 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1711611729; cv=none; b=eiV8UJKLB4CjdeF2E/84v9J1GlxrB6qZqNnbcDyNt/nM7UhWkf9k3kZOrErJw8Kbm0c7lzDBhDhLVLrgjaZvonH/nX33wYcgt4hYmQj+19U32NCkeUrdCf2DJjLAmBMjIrpnxe++FtBxdkULLxmReZl+UEDGpa6MmECe79LqZYo= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1711611729; c=relaxed/simple; bh=B2NQLnfrMKDnXljb6AV2F1GcYBsPOWnJ1u4ulbgQ+jA=; h=From:To:CC:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=C4bQBzgGNHYPbG886pJJ8Vc8KFkYWvC+mJaqL3sNmBkp/kToetl6SCp4xEna5Z2PRXcsCvQOx9sSiVwC308/NOnf9PZxfcZmkNyePsCEcbRk6xgm4+/RLs8368gF2TrrVcxkbcDtxyRASV+eiuVg13KgGm9ljbs5pQqbXaJyM/k= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=quicinc.com; spf=pass smtp.mailfrom=quicinc.com; dkim=pass (2048-bit key) header.d=quicinc.com header.i=@quicinc.com header.b=H8Px2FPr; arc=none smtp.client-ip=205.220.180.131 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=quicinc.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=quicinc.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=quicinc.com header.i=@quicinc.com header.b="H8Px2FPr" Received: from pps.filterd (m0279869.ppops.net [127.0.0.1]) by mx0a-0031df01.pphosted.com (8.17.1.24/8.17.1.24) with ESMTP id 42S4BphL029571; Thu, 28 Mar 2024 07:41:56 GMT DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=quicinc.com; h= from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding:content-type; s= qcppdkim1; bh=drb69SBwlfCleDTP31exbb1vs06Ku/JLJT2ZasNqYfs=; b=H8 Px2FPr9HcEQkEbWeKZhwFMrq36rWgqxf4zcwno5pQSSuzgcXVoBwawe3beoJlAdr S2Ar8ry5v28kSOxYDiQfvs9IFeoV2q0fzsVYVcXMEt/aF+L5GZg2GBYqeu6EjODL EROk71+llThmwU6+oXT+njiSug0MCEkRR2ZzY+uqv0u7HqhH1hEUmgLLDwIBMjpZ F921L6OyJktEYRBVxbv8R+5yR6mmQCZZTIiy7I1D1uNHUF50Q+x6ZBBHJ0s77zpj S6CM9dQurWgpaR+IlxNslcAyp0FjfQPZOl+3UliX8QYUjG6IcsG6eslC+XErUvjF Zf4JhHIUyVr3wR1TKtDg== Received: from nalasppmta04.qualcomm.com (Global_NAT1.qualcomm.com [129.46.96.20]) by mx0a-0031df01.pphosted.com (PPS) with ESMTPS id 3x4u1wjcfq-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Thu, 28 Mar 2024 07:41:56 +0000 (GMT) Received: from nalasex01a.na.qualcomm.com (nalasex01a.na.qualcomm.com [10.47.209.196]) by NALASPPMTA04.qualcomm.com (8.17.1.5/8.17.1.5) with ESMTPS id 42S7ftTF028054 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Thu, 28 Mar 2024 07:41:55 GMT Received: from hu-sibis-blr.qualcomm.com (10.80.80.8) by nalasex01a.na.qualcomm.com (10.47.209.196) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1118.40; Thu, 28 Mar 2024 00:41:50 -0700 From: Sibi Sankar To: , , , , , , , CC: , , , , , Sibi Sankar Subject: [PATCH V4 1/2] cpufreq: Export cpufreq_update_pressure Date: Thu, 28 Mar 2024 13:11:30 +0530 Message-ID: <20240328074131.2839871-2-quic_sibis@quicinc.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240328074131.2839871-1-quic_sibis@quicinc.com> References: <20240328074131.2839871-1-quic_sibis@quicinc.com> Precedence: bulk X-Mailing-List: linux-arm-msm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-ClientProxiedBy: nasanex01b.na.qualcomm.com (10.46.141.250) To nalasex01a.na.qualcomm.com (10.47.209.196) X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-GUID: BZM9InMquIEwRtoy6xJDTrS08nxiFq-U X-Proofpoint-ORIG-GUID: BZM9InMquIEwRtoy6xJDTrS08nxiFq-U X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.272,Aquarius:18.0.1011,Hydra:6.0.619,FMLib:17.11.176.26 definitions=2024-03-28_06,2024-03-27_01,2023-05-22_02 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 clxscore=1015 malwarescore=0 adultscore=0 lowpriorityscore=0 bulkscore=0 phishscore=0 impostorscore=0 mlxlogscore=938 mlxscore=0 spamscore=0 suspectscore=0 priorityscore=1501 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.19.0-2403210001 definitions=main-2403280048 The SCMI cpufreq driver doesn't require any additional signal smoothing provided by arch_update_hw_pressure interface, export cpufreq_update_pressure so that it can be called upon directly instead. Suggested-by: Lukasz Luba Signed-off-by: Sibi Sankar --- v4: * Use EXPORT_SYMBOL_GPL instead. [Trilok] drivers/cpufreq/cpufreq.c | 3 ++- include/linux/cpufreq.h | 2 ++ 2 files changed, 4 insertions(+), 1 deletion(-) diff --git a/drivers/cpufreq/cpufreq.c b/drivers/cpufreq/cpufreq.c index 1de8bd105934..656320554bb7 100644 --- a/drivers/cpufreq/cpufreq.c +++ b/drivers/cpufreq/cpufreq.c @@ -2590,7 +2590,7 @@ DEFINE_PER_CPU(unsigned long, cpufreq_pressure); * * Update the value of cpufreq pressure for all @cpus in the policy. */ -static void cpufreq_update_pressure(struct cpufreq_policy *policy) +void cpufreq_update_pressure(struct cpufreq_policy *policy) { unsigned long max_capacity, capped_freq, pressure; u32 max_freq; @@ -2615,6 +2615,7 @@ static void cpufreq_update_pressure(struct cpufreq_policy *policy) for_each_cpu(cpu, policy->related_cpus) WRITE_ONCE(per_cpu(cpufreq_pressure, cpu), pressure); } +EXPORT_SYMBOL_GPL(cpufreq_update_pressure); /** * cpufreq_set_policy - Modify cpufreq policy parameters. diff --git a/include/linux/cpufreq.h b/include/linux/cpufreq.h index 20f7e98ee8af..7410a1bade23 100644 --- a/include/linux/cpufreq.h +++ b/include/linux/cpufreq.h @@ -241,6 +241,7 @@ struct kobject *get_governor_parent_kobj(struct cpufreq_policy *policy); void cpufreq_enable_fast_switch(struct cpufreq_policy *policy); void cpufreq_disable_fast_switch(struct cpufreq_policy *policy); bool has_target_index(void); +void cpufreq_update_pressure(struct cpufreq_policy *policy); DECLARE_PER_CPU(unsigned long, cpufreq_pressure); static inline unsigned long cpufreq_get_pressure(int cpu) @@ -270,6 +271,7 @@ static inline bool cpufreq_supports_freq_invariance(void) } static inline void disable_cpufreq(void) { } static inline void cpufreq_update_limits(unsigned int cpu) { } +static inline void cpufreq_update_pressure(struct cpufreq_policy *policy) { } static inline unsigned long cpufreq_get_pressure(int cpu) { return 0; From patchwork Thu Mar 28 07:41:31 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Sibi Sankar X-Patchwork-Id: 13608084 Received: from mx0b-0031df01.pphosted.com (mx0b-0031df01.pphosted.com [205.220.180.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id C18742C6B8; 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Thu, 28 Mar 2024 07:42:00 +0000 (GMT) Received: from nalasex01a.na.qualcomm.com (nalasex01a.na.qualcomm.com [10.47.209.196]) by NALASPPMTA01.qualcomm.com (8.17.1.5/8.17.1.5) with ESMTPS id 42S7fxp1016704 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Thu, 28 Mar 2024 07:41:59 GMT Received: from hu-sibis-blr.qualcomm.com (10.80.80.8) by nalasex01a.na.qualcomm.com (10.47.209.196) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1118.40; Thu, 28 Mar 2024 00:41:55 -0700 From: Sibi Sankar To: , , , , , , , CC: , , , , , Sibi Sankar Subject: [PATCH V4 2/2] cpufreq: scmi: Register for limit change notifications Date: Thu, 28 Mar 2024 13:11:31 +0530 Message-ID: <20240328074131.2839871-3-quic_sibis@quicinc.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240328074131.2839871-1-quic_sibis@quicinc.com> References: <20240328074131.2839871-1-quic_sibis@quicinc.com> Precedence: bulk X-Mailing-List: linux-arm-msm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-ClientProxiedBy: nasanex01b.na.qualcomm.com (10.46.141.250) To nalasex01a.na.qualcomm.com (10.47.209.196) X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-ORIG-GUID: NlwpuC1ladQDIM-Y7RJSncSwwAOXEFAh X-Proofpoint-GUID: NlwpuC1ladQDIM-Y7RJSncSwwAOXEFAh X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.272,Aquarius:18.0.1011,Hydra:6.0.619,FMLib:17.11.176.26 definitions=2024-03-28_06,2024-03-27_01,2023-05-22_02 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 clxscore=1015 malwarescore=0 bulkscore=0 priorityscore=1501 mlxlogscore=999 impostorscore=0 mlxscore=0 adultscore=0 suspectscore=0 phishscore=0 lowpriorityscore=0 spamscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.19.0-2403210001 definitions=main-2403280048 Register for limit change notifications if supported and use the throttled frequency from the notification to apply HW pressure. Signed-off-by: Sibi Sankar Reviewed-by: Lukasz Luba Reviewed-by: Cristian Marussi --- v4: * Use a interim variable to show the khz calc. [Lukasz] * Use driver_data to pass on the handle and scmi_dev instead of using global variables. Dropped Lukasz's Rb due to adding these minor changes. drivers/cpufreq/scmi-cpufreq.c | 44 ++++++++++++++++++++++++++++++++++ 1 file changed, 44 insertions(+) diff --git a/drivers/cpufreq/scmi-cpufreq.c b/drivers/cpufreq/scmi-cpufreq.c index 3b4f6bfb2f4c..d946b7a08258 100644 --- a/drivers/cpufreq/scmi-cpufreq.c +++ b/drivers/cpufreq/scmi-cpufreq.c @@ -21,11 +21,18 @@ #include #include +struct scmi_cpufreq_driver_data { + struct scmi_device *sdev; + const struct scmi_handle *handle; +}; + struct scmi_data { int domain_id; int nr_opp; struct device *cpu_dev; + struct cpufreq_policy *policy; cpumask_var_t opp_shared_cpus; + struct notifier_block limit_notify_nb; }; static struct scmi_protocol_handle *ph; @@ -174,6 +181,22 @@ static struct freq_attr *scmi_cpufreq_hw_attr[] = { NULL, }; +static int scmi_limit_notify_cb(struct notifier_block *nb, unsigned long event, void *data) +{ + struct scmi_data *priv = container_of(nb, struct scmi_data, limit_notify_nb); + struct scmi_perf_limits_report *limit_notify = data; + struct cpufreq_policy *policy = priv->policy; + unsigned int limit_freq_khz; + + limit_freq_khz = limit_notify->range_max_freq / HZ_PER_KHZ; + + policy->max = clamp(limit_freq_khz, policy->cpuinfo.min_freq, policy->cpuinfo.max_freq); + + cpufreq_update_pressure(policy); + + return NOTIFY_OK; +} + static int scmi_cpufreq_init(struct cpufreq_policy *policy) { int ret, nr_opp, domain; @@ -181,6 +204,7 @@ static int scmi_cpufreq_init(struct cpufreq_policy *policy) struct device *cpu_dev; struct scmi_data *priv; struct cpufreq_frequency_table *freq_table; + struct scmi_cpufreq_driver_data *data = cpufreq_get_driver_data(); cpu_dev = get_cpu_device(policy->cpu); if (!cpu_dev) { @@ -294,6 +318,17 @@ static int scmi_cpufreq_init(struct cpufreq_policy *policy) } } + priv->limit_notify_nb.notifier_call = scmi_limit_notify_cb; + ret = data->handle->notify_ops->devm_event_notifier_register(data->sdev, SCMI_PROTOCOL_PERF, + SCMI_EVENT_PERFORMANCE_LIMITS_CHANGED, + &domain, + &priv->limit_notify_nb); + if (ret) + dev_warn(cpu_dev, + "failed to register for limits change notifier for domain %d\n", domain); + + priv->policy = policy; + return 0; out_free_opp: @@ -366,12 +401,21 @@ static int scmi_cpufreq_probe(struct scmi_device *sdev) int ret; struct device *dev = &sdev->dev; const struct scmi_handle *handle; + struct scmi_cpufreq_driver_data *data; handle = sdev->handle; if (!handle) return -ENODEV; + data = devm_kzalloc(dev, sizeof(*data), GFP_KERNEL); + if (!data) + return -ENOMEM; + + data->sdev = sdev; + data->handle = handle; + scmi_cpufreq_driver.driver_data = data; + perf_ops = handle->devm_protocol_get(sdev, SCMI_PROTOCOL_PERF, &ph); if (IS_ERR(perf_ops)) return PTR_ERR(perf_ops);