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Set 'power-domains' as required property for compatible string fsl,imx8qm-asrc/spdif and fsl,imx8qxp-asrc/spdif. Acked-by: Conor Dooley Signed-off-by: Frank Li --- Documentation/devicetree/bindings/sound/fsl,imx-asrc.yaml | 14 ++++++++++++++ Documentation/devicetree/bindings/sound/fsl,spdif.yaml | 15 +++++++++++++++ 2 files changed, 29 insertions(+) diff --git a/Documentation/devicetree/bindings/sound/fsl,imx-asrc.yaml b/Documentation/devicetree/bindings/sound/fsl,imx-asrc.yaml index bfef2fcb75b14..76aa1f2484883 100644 --- a/Documentation/devicetree/bindings/sound/fsl,imx-asrc.yaml +++ b/Documentation/devicetree/bindings/sound/fsl,imx-asrc.yaml @@ -74,6 +74,9 @@ properties: - const: asrck_f - const: spba + power-domains: + maxItems: 1 + fsl,asrc-rate: $ref: /schemas/types.yaml#/definitions/uint32 description: The mutual sample rate used by DPCM Back Ends @@ -131,6 +134,17 @@ allOf: properties: fsl,asrc-clk-map: false + - if: + properties: + compatible: + contains: + enum: + - fsl,imx8qm-asrc + - fsl,imx8qxp-asrc + then: + required: + - power-domains + additionalProperties: false examples: diff --git a/Documentation/devicetree/bindings/sound/fsl,spdif.yaml b/Documentation/devicetree/bindings/sound/fsl,spdif.yaml index 1d64e8337aa4b..56f8c0c8afdea 100644 --- a/Documentation/devicetree/bindings/sound/fsl,spdif.yaml +++ b/Documentation/devicetree/bindings/sound/fsl,spdif.yaml @@ -86,6 +86,9 @@ properties: registers. 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Other platforms have 1 interrupt. Increase max interrupt number to 2 and add restriction for platforms except i.MX8QXP and i.MX8QM. Reviewed-by: Rob Herring Signed-off-by: Frank Li --- .../devicetree/bindings/sound/fsl,spdif.yaml | 20 +++++++++++++++++++- 1 file changed, 19 insertions(+), 1 deletion(-) diff --git a/Documentation/devicetree/bindings/sound/fsl,spdif.yaml b/Documentation/devicetree/bindings/sound/fsl,spdif.yaml index 56f8c0c8afdea..204f361cea27a 100644 --- a/Documentation/devicetree/bindings/sound/fsl,spdif.yaml +++ b/Documentation/devicetree/bindings/sound/fsl,spdif.yaml @@ -31,7 +31,10 @@ properties: maxItems: 1 interrupts: - maxItems: 1 + minItems: 1 + items: + - description: Combined or receive interrupt + - description: Transmit interrupt dmas: items: @@ -101,6 +104,21 @@ required: additionalProperties: false allOf: + - if: + properties: + compatible: + enum: + - fsl,imx8qm-spdif + - fsl,imx8qxp-spdif + then: + properties: + interrupts: + minItems: 2 + else: + properties: + interrupts: + maxItems: 1 + - if: properties: compatible: From patchwork Thu Mar 28 14:51:35 2024 Content-Type: text/plain; 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X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: =?utf-8?q?EJEy17U8NKcHe/3/v1a+kkvmko34?= =?utf-8?q?rNxI92wlJnQNHsBk4cIKKdOhwOwE6A3v/1fS/g5MRpa0ikvIDnp2PcLLGlkxrMWc/?= =?utf-8?q?FOPU7Ak0yWe0AwP5rKQ4l/XRuwweHNW33lo8uYpF0atVhUAi7TBEOoDT3Zbpmd5Yl?= =?utf-8?q?umji4KvJXteo3hX9QZcJC7h3+H7KhXxUFapcfPLZyAO4KdEVE8hgijF+UxaqhmKqI?= =?utf-8?q?w4LikBgPxFEkXCSvEM5h34BCa2V56Wu3F4mJckDc/SCydDN7MHJxbLVAc/kY7E3UR?= =?utf-8?q?CsVNiyRhqKF9Og8qHvDAdesMSSVaPj9bDNgB5wITxjxPnRR8AFMxxwjSZI/TU/yB1?= =?utf-8?q?Myo9KaeM+4QmEHEp4r11S3Oru0Hngpt9A72KisxLuWh3n+13/FBEdQqJ5z3Zv+DH6?= =?utf-8?q?hBDrrFta4YDBSiT3CjP7K/WklArcZFl1Tz6OmMvTO+dH5bGYShQp8PulMLtEvpFQO?= =?utf-8?q?KivzQWkd/V3y/Sb4WO+G8k2YnpQWIVggGFqGIFQbbg4h2lqccalwm5lzfNiO2LtTl?= =?utf-8?q?ZZfY5+j4f7dq77IQvBrQ4TgdbdsFOcMtKz2Jc9a9ToEhj63FtQySaXR0B8yKdHDwu?= =?utf-8?q?7g+b9sWLARsAHGhGAeADvLl+ofEyUYkd/kM/a/nbLwV37MJIRiNqKbJKmlH579J0K?= =?utf-8?q?sfM7+HkhK3TNT9omHGkaBTGRSG1/sw04D85iCFuZ8KnofDd6BOwcYYnZmqQPkfwtP?= =?utf-8?q?/neleelhkVBwH4ZJ3uQKjSKuh9VJLqA4ADD+HycWrAqDbTnMEY4h1egm+rDrJJ3yG?= =?utf-8?q?OA60ilAxYWRLwAxtMwqCB5eKeWVHqqDGg4ZaGWKLbWvy+kiczcD+bTa2FJ9N6CKHJ?= =?utf-8?q?BuO+b6uEiutMdfYO8nnc6pPc6y0OX/5rf6lVJK+DC17Vl7WGSZ+mGAtrfTopkhs37?= =?utf-8?q?lhpx0obLYLjkDGCnaoszdnuy2J0UjwWHDIlI+s3o5jjcOXNldaEPNHQLIRhgQm1Hv?= =?utf-8?q?mHmOhcwgLY+qQnVtmVNQ77/mOmvB/n2Og1hE/7Y/mRREnAGY6eQa0KgFgyvQdmey9?= =?utf-8?q?LQdTxTOy1VIzTmszFeKRPf74czChRitPjbtkCgZRbjdS0HO0GEZXdxp5LeNIQt2qS?= =?utf-8?q?hBak3k9l4SO0hzGQNU7tFS9QFtp4A97mqkyGnGgEv7gUfB0N/WAAT1InCOZ+TcSOj?= =?utf-8?q?vMiC0EkX4dLfN5rYDDrtt2JyVyDMyYOt0u0M0NakdnO3dJ57T5kqIzky7Qk8MARKV?= =?utf-8?q?eLOCgKLO2vGl8h4w4cUf7RlsPD/Gt9VQbpYtk2wdLpEWUroj988gjLQwKScwqi91G?= =?utf-8?q?TyPPV48f7C0ZL/KjSeqxOjN/L0QN1kf0dL+ixFRJAdJ8g+uDrwNsOeG6uHWS/T6Fh?= =?utf-8?q?YsilX1X1cwj7j/FrClqc9jA8glTFxo10yQpcxaq0DwvK5/boOv6sSg8C2u+doJXuJ?= =?utf-8?q?rDB7kiLrsFc6Q9TTzIHNtQqozxJWav+hx58emC0GpGNaJMZXeZiJ1gIEsgcPYQSie?= =?utf-8?q?jxO/HI+IY2tzLUIQ/IAbHEVKDMTWcPW6L3HFV0r2L3ziqWWVqw82I6P93bOMmHOGg?= =?utf-8?q?BPkhATzGwxsb?= X-OriginatorOrg: nxp.com X-MS-Exchange-CrossTenant-Network-Message-Id: 4260e557-ecd8-40e4-66b4-08dc4f36a7ac X-MS-Exchange-CrossTenant-AuthSource: PAXPR04MB9642.eurprd04.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Internal X-MS-Exchange-CrossTenant-OriginalArrivalTime: 28 Mar 2024 14:52:14.0622 (UTC) X-MS-Exchange-CrossTenant-FromEntityHeader: Hosted X-MS-Exchange-CrossTenant-Id: 686ea1d3-bc2b-4c6f-a92c-d99c5c301635 X-MS-Exchange-CrossTenant-MailboxType: HOSTED X-MS-Exchange-CrossTenant-UserPrincipalName: XQCuzW0JdAKK4dZ4EpQG2a4KVoZrn5FxudU6HM4v1V2mILDDxMqNcDHwmiVc4azd1RjMzG6VBZ0rBcfVUJhDeQ== X-MS-Exchange-Transport-CrossTenantHeadersStamped: PAXPR04MB8880 Some sai only connect one direction dma (rx/tx) in SOC. For example: imx8qxp sai5 only connect tx dma channel. So allow only one "rx" or "tx" for dma-names. Remove description under dmas because no user use index to get dma channel. All user use 'dma-names' to get correct dma channel. dma-names already in 'required' list. Reviewed-by: Rob Herring Signed-off-by: Frank Li --- Documentation/devicetree/bindings/sound/fsl,sai.yaml | 6 ++---- 1 file changed, 2 insertions(+), 4 deletions(-) diff --git a/Documentation/devicetree/bindings/sound/fsl,sai.yaml b/Documentation/devicetree/bindings/sound/fsl,sai.yaml index 2456d958adeef..a5d9c246cc476 100644 --- a/Documentation/devicetree/bindings/sound/fsl,sai.yaml +++ b/Documentation/devicetree/bindings/sound/fsl,sai.yaml @@ -81,14 +81,12 @@ properties: dmas: minItems: 1 - items: - - description: DMA controller phandle and request line for RX - - description: DMA controller phandle and request line for TX + maxItems: 2 dma-names: minItems: 1 items: - - const: rx + - enum: [ rx, tx ] - const: tx interrupts: From patchwork Thu Mar 28 14:51:36 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Frank Li X-Patchwork-Id: 13608694 Received: from EUR04-HE1-obe.outbound.protection.outlook.com (mail-he1eur04on2043.outbound.protection.outlook.com [40.107.7.43]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 3CCE012FF80; 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unsigned int idx = clkspec->args[0] / 4; .... } <@sai0_lpcg 1> will be the same as <@sai_lpcg 0>. Replace 0 with IMX_LPCG_CLK_0 and replace 1 with IMX_LPCG_CLK_4. It can work at iMX8QXP because IMX_LPCG_CLK_4 is ipg clock, which already enabled. But for iMX8QM IMX_LPCG_CLK_4 is mclk, which trigger issue. Fixes: 0a9279e9ae88 ("arm64: dts: imx8qxp: Add audio SAI nodes") Signed-off-by: Frank Li --- arch/arm64/boot/dts/freescale/imx8-ss-audio.dtsi | 16 ++++++++-------- 1 file changed, 8 insertions(+), 8 deletions(-) diff --git a/arch/arm64/boot/dts/freescale/imx8-ss-audio.dtsi b/arch/arm64/boot/dts/freescale/imx8-ss-audio.dtsi index 07afeb78ed564..d8bbe53320bce 100644 --- a/arch/arm64/boot/dts/freescale/imx8-ss-audio.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8-ss-audio.dtsi @@ -123,9 +123,9 @@ sai0: sai@59040000 { compatible = "fsl,imx8qm-sai"; reg = <0x59040000 0x10000>; interrupts = ; - clocks = <&sai0_lpcg 1>, + clocks = <&sai0_lpcg IMX_LPCG_CLK_4>, <&clk_dummy>, - <&sai0_lpcg 0>, + <&sai0_lpcg IMX_LPCG_CLK_0>, <&clk_dummy>, <&clk_dummy>; clock-names = "bus", "mclk0", "mclk1", "mclk2", "mclk3"; @@ -139,9 +139,9 @@ sai1: sai@59050000 { compatible = "fsl,imx8qm-sai"; reg = <0x59050000 0x10000>; interrupts = ; - clocks = <&sai1_lpcg 1>, + clocks = <&sai1_lpcg IMX_LPCG_CLK_4>, <&clk_dummy>, - <&sai1_lpcg 0>, + <&sai1_lpcg IMX_LPCG_CLK_0>, <&clk_dummy>, <&clk_dummy>; clock-names = "bus", "mclk0", "mclk1", "mclk2", "mclk3"; @@ -155,9 +155,9 @@ sai2: sai@59060000 { compatible = "fsl,imx8qm-sai"; reg = <0x59060000 0x10000>; interrupts = ; - clocks = <&sai2_lpcg 1>, + clocks = <&sai2_lpcg IMX_LPCG_CLK_4>, <&clk_dummy>, - <&sai2_lpcg 0>, + <&sai2_lpcg IMX_LPCG_CLK_0>, <&clk_dummy>, <&clk_dummy>; clock-names = "bus", "mclk0", "mclk1", "mclk2", "mclk3"; @@ -171,9 +171,9 @@ sai3: sai@59070000 { compatible = "fsl,imx8qm-sai"; reg = <0x59070000 0x10000>; interrupts = ; - clocks = <&sai3_lpcg 1>, + clocks = <&sai3_lpcg IMX_LPCG_CLK_4>, <&clk_dummy>, - <&sai3_lpcg 0>, + <&sai3_lpcg IMX_LPCG_CLK_0>, <&clk_dummy>, <&clk_dummy>; clock-names = "bus", "mclk0", "mclk1", "mclk2", "mclk3"; From patchwork Thu Mar 28 14:51:37 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Frank Li X-Patchwork-Id: 13608695 Received: from EUR04-HE1-obe.outbound.protection.outlook.com (mail-he1eur04on2043.outbound.protection.outlook.com [40.107.7.43]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 6540112FF8C; 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Signed-off-by: Frank Li --- arch/arm64/boot/dts/freescale/imx8-ss-audio.dtsi | 269 +++++++++++++++++++++++ 1 file changed, 269 insertions(+) diff --git a/arch/arm64/boot/dts/freescale/imx8-ss-audio.dtsi b/arch/arm64/boot/dts/freescale/imx8-ss-audio.dtsi index d8bbe53320bce..897cbb7b67422 100644 --- a/arch/arm64/boot/dts/freescale/imx8-ss-audio.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8-ss-audio.dtsi @@ -6,6 +6,7 @@ #include #include +#include #include audio_ipg_clk: clock-audio-ipg { @@ -119,6 +120,89 @@ audio_subsys: bus@59000000 { #size-cells = <1>; ranges = <0x59000000 0x0 0x59000000 0x1000000>; + asrc0: asrc@59000000 { + compatible = "fsl,imx8qm-asrc"; + reg = <0x59000000 0x10000>; + interrupts = ; + clocks = <&asrc0_lpcg IMX_LPCG_CLK_0>, + <&asrc0_lpcg IMX_LPCG_CLK_0>, + <&aud_pll_div0_lpcg IMX_LPCG_CLK_4>, + <&aud_pll_div1_lpcg IMX_LPCG_CLK_4>, + <&acm IMX_ADMA_ACM_AUD_CLK0_SEL>, + <&acm IMX_ADMA_ACM_AUD_CLK1_SEL>, + <&clk_dummy>, + <&clk_dummy>, + <&clk_dummy>, + <&clk_dummy>, + <&clk_dummy>, + <&clk_dummy>, + <&clk_dummy>, + <&clk_dummy>, + <&clk_dummy>, + <&clk_dummy>, + <&clk_dummy>, + <&clk_dummy>, + <&clk_dummy>; + clock-names = "mem", "ipg", + "asrck_0", "asrck_1", "asrck_2", "asrck_3", + "asrck_4", "asrck_5", "asrck_6", "asrck_7", + "asrck_8", "asrck_9", "asrck_a", "asrck_b", + "asrck_c", "asrck_d", "asrck_e", "asrck_f", + "spba"; + dmas = <&edma0 0 0 0>, + <&edma0 1 0 0>, + <&edma0 2 0 0>, + <&edma0 3 0 FSL_EDMA_RX>, + <&edma0 4 0 FSL_EDMA_RX>, + <&edma0 5 0 FSL_EDMA_RX>; + /* tx* is output channel of asrc, it is rx channel for eDMA */ + dma-names = "rxa", "rxb", "rxc", "txa", "txb", "txc"; + fsl,asrc-rate = <8000>; + fsl,asrc-width = <16>; + fsl,asrc-clk-map = <0>; + power-domains = <&pd IMX_SC_R_ASRC_0>; + status = "disabled"; + }; + + esai0: esai@59010000 { + compatible = "fsl,imx8qm-esai"; + reg = <0x59010000 0x10000>; + interrupts = ; + clocks = <&esai0_lpcg IMX_LPCG_CLK_4>, + <&esai0_lpcg IMX_LPCG_CLK_0>, + <&esai0_lpcg IMX_LPCG_CLK_4>, + <&clk_dummy>; + clock-names = "core", "extal", "fsys", "spba"; + dmas = <&edma0 6 0 FSL_EDMA_RX>, <&edma0 7 0 0>; + dma-names = "rx", "tx"; + power-domains = <&pd IMX_SC_R_ESAI_0>; + status = "disabled"; + }; + + spdif0: spdif@59020000 { + compatible = "fsl,imx8qm-spdif"; + reg = <0x59020000 0x10000>; + interrupts = , /* rx */ + ; /* tx */ + clocks = <&spdif0_lpcg IMX_LPCG_CLK_4>, /* core */ + <&clk_dummy>, /* rxtx0 */ + <&spdif0_lpcg IMX_LPCG_CLK_0>, /* rxtx1 */ + <&clk_dummy>, /* rxtx2 */ + <&clk_dummy>, /* rxtx3 */ + <&clk_dummy>, /* rxtx4 */ + <&audio_ipg_clk>, /* rxtx5 */ + <&clk_dummy>, /* rxtx6 */ + <&clk_dummy>, /* rxtx7 */ + <&clk_dummy>; /* spba */ + clock-names = "core", "rxtx0", "rxtx1", "rxtx2", "rxtx3", "rxtx4", + "rxtx5", "rxtx6", "rxtx7", "spba"; + dmas = <&edma0 8 0 (FSL_EDMA_MULTI_FIFO | FSL_EDMA_RX)>, + <&edma0 9 0 FSL_EDMA_MULTI_FIFO>; + dma-names = "rx", "tx"; + power-domains = <&pd IMX_SC_R_SPDIF_0>; + status = "disabled"; + }; + sai0: sai@59040000 { compatible = "fsl,imx8qm-sai"; reg = <0x59040000 0x10000>; @@ -239,6 +323,40 @@ edma0: dma-controller@591f0000 { <&pd IMX_SC_R_DMA_0_CH23>; }; + asrc0_lpcg: clock-controller@59400000 { + compatible = "fsl,imx8qxp-lpcg"; + reg = <0x59400000 0x10000>; + #clock-cells = <1>; + clocks = <&audio_ipg_clk>; + clock-indices = ; + clock-output-names = "asrc0_lpcg_ipg_clk"; + power-domains = <&pd IMX_SC_R_ASRC_0>; + }; + + esai0_lpcg: clock-controller@59410000 { + compatible = "fsl,imx8qxp-lpcg"; + reg = <0x59410000 0x10000>; + #clock-cells = <1>; + clocks = <&acm IMX_ADMA_ACM_ESAI0_MCLK_SEL>, + <&audio_ipg_clk>; + clock-indices = , ; + clock-output-names = "esai0_lpcg_extal_clk", + "esai0_lpcg_ipg_clk"; + power-domains = <&pd IMX_SC_R_ESAI_0>; + }; + + spdif0_lpcg: clock-controller@59420000 { + compatible = "fsl,imx8qxp-lpcg"; + reg = <0x59420000 0x10000>; + #clock-cells = <1>; + clocks = <&acm IMX_ADMA_ACM_SPDIF0_TX_CLK_SEL>, + <&audio_ipg_clk>; + clock-indices = , ; + clock-output-names = "spdif0_lpcg_tx_clk", + "spdif0_lpcg_gclkw"; + power-domains = <&pd IMX_SC_R_SPDIF_0>; + }; + sai0_lpcg: clock-controller@59440000 { compatible = "fsl,imx8qxp-lpcg"; reg = <0x59440000 0x10000>; @@ -333,6 +451,101 @@ dsp: dsp@596e8000 { status = "disabled"; }; + asrc1: asrc@59800000 { + compatible = "fsl,imx8qm-asrc"; + reg = <0x59800000 0x10000>; + interrupts = ; + clocks = <&asrc1_lpcg IMX_LPCG_CLK_4>, + <&asrc1_lpcg IMX_LPCG_CLK_4>, + <&aud_pll_div0_lpcg IMX_LPCG_CLK_0>, + <&aud_pll_div1_lpcg IMX_LPCG_CLK_0>, + <&acm IMX_ADMA_ACM_AUD_CLK0_SEL>, + <&acm IMX_ADMA_ACM_AUD_CLK1_SEL>, + <&clk_dummy>, + <&clk_dummy>, + <&clk_dummy>, + <&clk_dummy>, + <&clk_dummy>, + <&clk_dummy>, + <&clk_dummy>, + <&clk_dummy>, + <&clk_dummy>, + <&clk_dummy>, + <&clk_dummy>, + <&clk_dummy>, + <&clk_dummy>; + clock-names = "mem", "ipg", + "asrck_0", "asrck_1", "asrck_2", "asrck_3", + "asrck_4", "asrck_5", "asrck_6", "asrck_7", + "asrck_8", "asrck_9", "asrck_a", "asrck_b", + "asrck_c", "asrck_d", "asrck_e", "asrck_f", + "spba"; + dmas = <&edma1 0 0 0>, + <&edma1 1 0 0>, + <&edma1 2 0 0>, + <&edma1 3 0 FSL_EDMA_RX>, + <&edma1 4 0 FSL_EDMA_RX>, + <&edma1 5 0 FSL_EDMA_RX>; + /* tx* is output channel of asrc, it is rx channel for eDMA */ + dma-names = "rxa", "rxb", "rxc", "txa", "txb", "txc"; + fsl,asrc-rate = <8000>; + fsl,asrc-width = <16>; + fsl,asrc-clk-map = <1>; + power-domains = <&pd IMX_SC_R_ASRC_1>; + status = "disabled"; + }; + + sai4: sai@59820000 { + compatible = "fsl,imx8qm-sai"; + reg = <0x59820000 0x10000>; + interrupts = ; + clocks = <&sai4_lpcg IMX_LPCG_CLK_4>, + <&clk_dummy>, + <&sai4_lpcg IMX_LPCG_CLK_0>, + <&clk_dummy>, + <&clk_dummy>; + clock-names = "bus", "mclk0", "mclk1", "mclk2", "mclk3"; + dmas = <&edma1 8 0 FSL_EDMA_RX>, <&edma1 9 0 0>; + dma-names = "rx", "tx"; + power-domains = <&pd IMX_SC_R_SAI_4>; + status = "disabled"; + }; + + sai5: sai@59830000 { + compatible = "fsl,imx8qm-sai"; + reg = <0x59830000 0x10000>; + interrupts = ; + clocks = <&sai5_lpcg IMX_LPCG_CLK_4>, + <&clk_dummy>, + <&sai5_lpcg IMX_LPCG_CLK_0>, + <&clk_dummy>, + <&clk_dummy>; + clock-names = "bus", "mclk0", "mclk1", "mclk2", "mclk3"; + dmas = <&edma1 10 0 0>; + dma-names = "tx"; + power-domains = <&pd IMX_SC_R_SAI_5>; + status = "disabled"; + }; + + amix: amix@59840000 { + compatible = "fsl,imx8qm-audmix"; + reg = <0x59840000 0x10000>; + clocks = <&amix_lpcg IMX_LPCG_CLK_0>; + clock-names = "ipg"; + power-domains = <&pd IMX_SC_R_AMIX>; + dais = <&sai4>, <&sai5>; + status = "disabled"; + }; + + mqs: mqs@59850000 { + compatible = "fsl,imx8qm-mqs"; + reg = <0x59850000 0x10000>; + clocks = <&mqs0_lpcg IMX_LPCG_CLK_4>, <&mqs0_lpcg IMX_LPCG_CLK_0>; + clock-names = "mclk", "core"; + power-domains = <&pd IMX_SC_R_MQS_0>; + status = "disabled"; + }; + edma1: dma-controller@599f0000 { compatible = "fsl,imx8qm-edma"; reg = <0x599f0000 0xc0000>; @@ -481,4 +694,60 @@ acm: acm@59e00000 { "sai3_rx_bclk", "sai4_rx_bclk"; }; + + asrc1_lpcg: clock-controller@59c00000 { + compatible = "fsl,imx8qxp-lpcg"; + reg = <0x59c00000 0x10000>; + #clock-cells = <1>; + clocks = <&audio_ipg_clk>; + clock-indices = ; + clock-output-names = "asrc1_lpcg_ipg_clk"; + power-domains = <&pd IMX_SC_R_ASRC_1>; + }; + + sai4_lpcg: clock-controller@59c20000 { + compatible = "fsl,imx8qxp-lpcg"; + reg = <0x59c20000 0x10000>; + #clock-cells = <1>; + clocks = <&acm IMX_ADMA_ACM_SAI4_MCLK_SEL>, + <&audio_ipg_clk>; + clock-indices = , ; + clock-output-names = "sai4_lpcg_mclk", + "sai4_lpcg_ipg_clk"; + power-domains = <&pd IMX_SC_R_SAI_4>; + }; + + sai5_lpcg: clock-controller@59c30000 { + compatible = "fsl,imx8qxp-lpcg"; + reg = <0x59c30000 0x10000>; + #clock-cells = <1>; + clocks = <&acm IMX_ADMA_ACM_SAI5_MCLK_SEL>, + <&audio_ipg_clk>; + clock-indices = , ; + clock-output-names = "sai5_lpcg_mclk", + "sai5_lpcg_ipg_clk"; + power-domains = <&pd IMX_SC_R_SAI_5>; + }; + + amix_lpcg: clock-controller@59c40000 { + compatible = "fsl,imx8qxp-lpcg"; + reg = <0x59c40000 0x10000>; + #clock-cells = <1>; + clocks = <&audio_ipg_clk>; + clock-indices = ; + clock-output-names = "amix_lpcg_ipg_clk"; + power-domains = <&pd IMX_SC_R_AMIX>; + }; + + mqs0_lpcg: clock-controller@59c50000 { + compatible = "fsl,imx8qxp-lpcg"; + reg = <0x59c50000 0x10000>; + #clock-cells = <1>; + clocks = <&acm IMX_ADMA_ACM_MQS_TX_CLK_SEL>, + <&audio_ipg_clk>; + clock-indices = , ; + clock-output-names = "mqs0_lpcg_mclk", + "mqs0_lpcg_ipg_clk"; + power-domains = <&pd IMX_SC_R_MQS_0>; + }; };