From patchwork Fri Mar 29 09:17:13 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Kelvin Zhang via B4 Relay X-Patchwork-Id: 13610427 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id F3E7DC6FD1F for ; Fri, 29 Mar 2024 09:17:52 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:Reply-To:List-Subscribe:List-Help: List-Post:List-Archive:List-Unsubscribe:List-Id:Cc:To:In-Reply-To:References: Message-Id:MIME-Version:Subject:Date:From:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; bh=GiEhtRGYjYhK2zkJHTR58TsQvmthS+l7AXaZfZQvZj0=; b=br6a5gKNW8SOGX 1hPyO2ifyKUqui18LyAaeiQay08KICmy8yhszhlRjf8BvPcC4XGaK3OUpcN7nNWvJqg2/ErKFmtA+ Vxqt2Wm3Tib3Zw9gIEC6SEeAdNoZNZpZ/vDeLDLnR9BGBBRHJYy2xuN3oJbTjZftC6dyjUmFNyR3p vw0mS7XbM/189hwmEIfIumTWdV9F40aYfLJA1GSmQ0Xdr6eUgVYQOleUH2dia+NNKE1gidgBP9jAZ Ncw1q7/yi3fIBBG4EH6ey2o3z1AWh7GifziGzVw7UciuwIFoHC+XKeIilm1jqXkzyFZu+AcARNOHz RFupKSWSxbFXN8ZF+3SQ==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.97.1 #2 (Red Hat Linux)) id 1rq8Mo-0000000HRzn-13La; Fri, 29 Mar 2024 09:17:42 +0000 Received: from dfw.source.kernel.org ([139.178.84.217]) by bombadil.infradead.org with esmtps (Exim 4.97.1 #2 (Red Hat Linux)) id 1rq8Mi-0000000HRxl-3iqQ; Fri, 29 Mar 2024 09:17:38 +0000 Received: from smtp.kernel.org (transwarp.subspace.kernel.org [100.75.92.58]) by dfw.source.kernel.org (Postfix) with ESMTP id A364E618F6; Fri, 29 Mar 2024 09:17:35 +0000 (UTC) Received: by smtp.kernel.org (Postfix) with ESMTPS id 49129C43390; Fri, 29 Mar 2024 09:17:35 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1711703855; bh=wTTt2oWAUpdvp/Jby37qhdU7Cy3yJY7C1pEsGj2HtOg=; h=From:Date:Subject:References:In-Reply-To:To:Cc:Reply-To:From; b=Zg3xu9IYVljLLYwSeJi1feRS2ECt6TwFeLOKnwsR7kOaN+8YBDyPtL3arb/eqcyWz 1MurpMUNiBy8pr6fSAoc76ZgyTM72lrSc4c3zj5tg6DxorcLnCIlh26zaQSdDiephO +1CkjVGqQ27FuAnufeOOWvh2pxbQQLpC4Iu3zaM3FG5n70tzdJYqQBH3uBgFsN9mlJ MwNWc0ofb1NjATJrnVw6RII3vvupG/temK4nn8xgY1K7t8ugwtGvrjAG6ctCaawYrA w2/leAkcl1VxKig4DmeoD0pLEvBHROQ0YFOJqyWu4Lhajx57VafGzPqZleO9gWDiyr hjusy8KQshzWw== Received: from aws-us-west-2-korg-lkml-1.web.codeaurora.org (localhost.localdomain [127.0.0.1]) by smtp.lore.kernel.org (Postfix) with ESMTP id 3291FCD1288; Fri, 29 Mar 2024 09:17:35 +0000 (UTC) From: Kelvin Zhang via B4 Relay Date: Fri, 29 Mar 2024 17:17:13 +0800 Subject: [PATCH 1/3] dt-bindings: reset: Add Amlogic T7 Reset Controller MIME-Version: 1.0 Message-Id: <20240329-t7-reset-v1-1-4c6e2e68359e@amlogic.com> References: <20240329-t7-reset-v1-0-4c6e2e68359e@amlogic.com> In-Reply-To: <20240329-t7-reset-v1-0-4c6e2e68359e@amlogic.com> To: Philipp Zabel , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Neil Armstrong , Kevin Hilman , Jerome Brunet , Martin Blumenstingl Cc: devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-amlogic@lists.infradead.org, linux-kernel@vger.kernel.org, Zelong Dong , Kelvin Zhang X-Mailer: b4 0.12.4 X-Developer-Signature: v=1; a=ed25519-sha256; t=1711703853; l=7020; i=kelvin.zhang@amlogic.com; s=20240329; h=from:subject:message-id; bh=mluS+tHhwQAUrUJxW0K+7LJ2Wjk2i0Km6qCpYYcquZo=; b=Nx96vMfnWtH6zdahWonwuNnsrj3vbehWWJXGHgK8O2gkXmMmzhjZP6T4P3XYVHoziVH3hXGrK pazxVUWy6tpDN/b8xUFTL/j+mBEZ2LdUNWvRbh2KAsRS9BLaucZh/cv X-Developer-Key: i=kelvin.zhang@amlogic.com; a=ed25519; pk=pgnle7HTNvnNTcOoGejvtTC7BJT30HUNXfMHRRXSylI= X-Endpoint-Received: by B4 Relay for kelvin.zhang@amlogic.com/20240329 with auth_id=148 X-Original-From: Kelvin Zhang X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20240329_021737_289689_AC5C188F X-CRM114-Status: GOOD ( 11.29 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Reply-To: kelvin.zhang@amlogic.com Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org From: Zelong Dong Add a new compatible and the related header file for Amlogic T7 Reset Controller. Signed-off-by: Zelong Dong Signed-off-by: Kelvin Zhang Acked-by: Krzysztof Kozlowski --- .../bindings/reset/amlogic,meson-reset.yaml | 1 + include/dt-bindings/reset/amlogic,t7-reset.h | 197 +++++++++++++++++++++ 2 files changed, 198 insertions(+) diff --git a/Documentation/devicetree/bindings/reset/amlogic,meson-reset.yaml b/Documentation/devicetree/bindings/reset/amlogic,meson-reset.yaml index f0c6c0df0ce3..fefe343e5afe 100644 --- a/Documentation/devicetree/bindings/reset/amlogic,meson-reset.yaml +++ b/Documentation/devicetree/bindings/reset/amlogic,meson-reset.yaml @@ -19,6 +19,7 @@ properties: - amlogic,meson-a1-reset # Reset Controller on A1 and compatible SoCs - amlogic,meson-s4-reset # Reset Controller on S4 and compatible SoCs - amlogic,c3-reset # Reset Controller on C3 and compatible SoCs + - amlogic,t7-reset # Reset Controller on T7 and compatible SoCs reg: maxItems: 1 diff --git a/include/dt-bindings/reset/amlogic,t7-reset.h b/include/dt-bindings/reset/amlogic,t7-reset.h new file mode 100644 index 000000000000..ca4a832eeeec --- /dev/null +++ b/include/dt-bindings/reset/amlogic,t7-reset.h @@ -0,0 +1,197 @@ +/* SPDX-License-Identifier: (GPL-2.0-only OR MIT) */ +/* + * Copyright (c) 2024 Amlogic, Inc. All rights reserved. + */ + +#ifndef _DT_BINDINGS_AMLOGIC_T7_RESET_H +#define _DT_BINDINGS_AMLOGIC_T7_RESET_H + +/* RESET0 */ +/* 0-3 */ +#define RESET_USB 4 +#define RESET_U2DRD 5 +#define RESET_U3DRD 6 +#define RESET_U3DRD_PIPE0 7 +#define RESET_U2PHY20 8 +#define RESET_U2PHY21 9 +#define RESET_GDC 10 +#define RESET_HDMI20_AES 11 +#define RESET_HDMIRX 12 +#define RESET_HDMIRX_APB 13 +#define RESET_DEWARP 14 +/* 15 */ +#define RESET_HDMITX_CAPB3 16 +#define RESET_BRG_VCBUG_DEC 17 +#define RESET_VCBUS 18 +#define RESET_VID_PLL_DIV 19 +#define RESET_VDI6 20 +#define RESET_GE2D 21 +#define RESET_HDMITXPHY 22 +#define RESET_VID_LOCK 23 +#define RESET_VENC0 24 +#define RESET_VDAC 25 +#define RESET_VENC2 26 +#define RESET_VENC1 27 +#define RESET_RDMA 28 +#define RESET_HDMITX 29 +#define RESET_VIU 30 +#define RESET_VENC 31 + +/* RESET1 */ +#define RESET_AUDIO 32 +#define RESET_MALI_CAPB3 33 +#define RESET_MALI 34 +#define RESET_DDR_APB 35 +#define RESET_DDR 36 +#define RESET_DOS_CAPB3 37 +#define RESET_DOS 38 +#define RESET_COMBO_DPHY_CHAN2 39 +#define RESET_DEBUG_B 40 +#define RESET_DEBUG_A 41 +#define RESET_DSP_B 42 +#define RESET_DSP_A 43 +#define RESET_PCIE_A 44 +#define RESET_PCIE_PHY 45 +#define RESET_PCIE_APB 46 +#define RESET_ANAKIN 47 +#define RESET_ETH 48 +#define RESET_EDP0_CTRL 49 +#define RESET_EDP1_CTRL 50 +#define RESET_COMBO_DPHY_CHAN0 51 +#define RESET_COMBO_DPHY_CHAN1 52 +#define RESET_DSI_LVDS_EDP_TOP 53 +#define RESET_PCIE1_PHY 54 +#define RESET_PCIE1_APB 55 +#define RESET_DDR_1 56 +/* 57 */ +#define RESET_EDP1_PIPELINE 58 +#define RESET_EDP0_PIPELINE 59 +#define RESET_MIPI_DSI1_PHY 60 +#define RESET_MIPI_DSI0_PHY 61 +#define RESET_MIPI_DSI_A_HOST 62 +#define RESET_MIPI_DSI_B_HOST 63 + +/* RESET2 */ +#define RESET_DEVICE_MMC_ARB 64 +#define RESET_IR_CTRL 65 +#define RESET_TS_A73 66 +#define RESET_TS_A53 67 +#define RESET_SPICC_2 68 +#define RESET_SPICC_3 69 +#define RESET_SPICC_4 70 +#define RESET_SPICC_5 71 +#define RESET_SMART_CARD 72 +#define RESET_SPICC_0 73 +#define RESET_SPICC_1 74 +#define RESET_RSA 75 +/* 76-79 */ +#define RESET_MSR_CLK 80 +#define RESET_SPIFC 81 +#define RESET_SAR_ADC 82 +#define RESET_BT 83 +/* 84-87 */ +#define RESET_ACODEC 88 +#define RESET_CEC 89 +#define RESET_AFIFO 90 +#define RESET_WATCHDOG 91 +/* 92-95 */ + +/* RESET3 */ +#define RESET_BRG_NIC1_GPV 96 +#define RESET_BRG_NIC2_GPV 97 +#define RESET_BRG_NIC3_GPV 98 +#define RESET_BRG_NIC4_GPV 99 +#define RESET_BRG_NIC5_GPV 100 +/* 101-121 */ +#define RESET_MIPI_ISP 122 +#define RESET_BRG_ADB_MALI_1 123 +#define RESET_BRG_ADB_MALI_0 124 +#define RESET_BRG_ADB_A73 125 +#define RESET_BRG_ADB_A53 126 +#define RESET_BRG_CCI 127 + +/* RESET4 */ +#define RESET_PWM_AO_AB 128 +#define RESET_PWM_AO_CD 129 +#define RESET_PWM_AO_EF 130 +#define RESET_PWM_AO_GH 131 +#define RESET_PWM_AB 132 +#define RESET_PWM_CD 133 +#define RESET_PWM_EF 134 +/* 135-137 */ +#define RESET_UART_A 138 +#define RESET_UART_B 139 +#define RESET_UART_C 140 +#define RESET_UART_D 141 +#define RESET_UART_E 142 +#define RESET_UART_F 143 +#define RESET_I2C_S_A 144 +#define RESET_I2C_M_A 145 +#define RESET_I2C_M_B 146 +#define RESET_I2C_M_C 147 +#define RESET_I2C_M_D 148 +#define RESET_I2C_M_E 149 +#define RESET_I2C_M_F 150 +#define RESET_I2C_M_AO_A 151 +#define RESET_SD_EMMC_A 152 +#define RESET_SD_EMMC_B 153 +#define RESET_SD_EMMC_C 154 +#define RESET_I2C_M_AO_B 155 +#define RESET_TS_GPU 156 +#define RESET_TS_NNA 157 +#define RESET_TS_VPN 158 +#define RESET_TS_HEVC 159 + +/* RESET5 */ +#define RESET_BRG_NOC_DDR_1 160 +#define RESET_BRG_NOC_DDR_0 161 +#define RESET_BRG_NOC_MAIN 162 +#define RESET_BRG_NOC_ALL 163 +/* 164-167 */ +#define RESET_BRG_NIC2_SYS 168 +#define RESET_BRG_NIC2_MAIN 169 +#define RESET_BRG_NIC2_HDMI 170 +#define RESET_BRG_NIC2_ALL 171 +#define RESET_BRG_NIC3_WAVE 172 +#define RESET_BRG_NIC3_VDEC 173 +#define RESET_BRG_NIC3_HEVCF 174 +#define RESET_BRG_NIC3_HEVCB 175 +#define RESET_BRG_NIC3_HCODEC 176 +#define RESET_BRG_NIC3_GE2D 177 +#define RESET_BRG_NIC3_GDC 178 +#define RESET_BRG_NIC3_AMLOGIC 179 +#define RESET_BRG_NIC3_MAIN 180 +#define RESET_BRG_NIC3_ALL 181 +#define RESET_BRG_NIC5_VPU 182 +/* 183-185 */ +#define RESET_BRG_NIC4_DSPB 186 +#define RESET_BRG_NIC4_DSPA 187 +#define RESET_BRG_NIC4_VAPB 188 +#define RESET_BRG_NIC4_CLK81 189 +#define RESET_BRG_NIC4_MAIN 190 +#define RESET_BRG_NIC4_ALL 191 + +/* RESET6 */ +#define RESET_BRG_VDEC_PIPEL 192 +#define RESET_BRG_HEVCF_DMC_PIPEL 193 +#define RESET_BRG_NIC2TONIC4_PIPEL 194 +#define RESET_BRG_HDMIRXTONIC2_PIPEL 195 +#define RESET_BRG_SECTONIC4_PIPEL 196 +#define RESET_BRG_VPUTONOC_PIPEL 197 +#define RESET_BRG_NIC4TONOC_PIPEL 198 +#define RESET_BRG_NIC3TONOC_PIPEL 199 +#define RESET_BRG_NIC2TONOC_PIPEL 200 +#define RESET_BRG_NNATONOC_PIPEL 201 +#define RESET_BRG_FRISP3_PIPEL 202 +#define RESET_BRG_FRISP2_PIPEL 203 +#define RESET_BRG_FRISP1_PIPEL 204 +#define RESET_BRG_FRISP0_PIPEL 205 +/* 206-217 */ +#define RESET_BRG_AMPIPE_NAND 218 +#define RESET_BRG_AMPIPE_ETH 219 +/* 220 */ +#define RESET_BRG_AM2AXI0 221 +#define RESET_BRG_AM2AXI1 222 +#define RESET_BRG_AM2AXI2 223 + +#endif From patchwork Fri Mar 29 09:17:14 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Kelvin Zhang via B4 Relay X-Patchwork-Id: 13610429 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 471A2C6FD1F for ; Fri, 29 Mar 2024 09:17:56 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:Reply-To:List-Subscribe:List-Help: List-Post:List-Archive:List-Unsubscribe:List-Id:Cc:To:In-Reply-To:References: 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(UTC) From: Kelvin Zhang via B4 Relay Date: Fri, 29 Mar 2024 17:17:14 +0800 Subject: [PATCH 2/3] reset: reset-meson: add support for Amlogic T7 SoC Reset Controller MIME-Version: 1.0 Message-Id: <20240329-t7-reset-v1-2-4c6e2e68359e@amlogic.com> References: <20240329-t7-reset-v1-0-4c6e2e68359e@amlogic.com> In-Reply-To: <20240329-t7-reset-v1-0-4c6e2e68359e@amlogic.com> To: Philipp Zabel , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Neil Armstrong , Kevin Hilman , Jerome Brunet , Martin Blumenstingl Cc: devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-amlogic@lists.infradead.org, linux-kernel@vger.kernel.org, Zelong Dong , Kelvin Zhang X-Mailer: b4 0.12.4 X-Developer-Signature: v=1; a=ed25519-sha256; t=1711703853; l=1485; i=kelvin.zhang@amlogic.com; s=20240329; h=from:subject:message-id; bh=4b5hJs6BojBwxeqHYbAP2s8Gj7Cc9H0Mgr5d5A9mC30=; b=gqs56u0cQ7PfE8Ihc4OxU0xkuogLNMu6dXnKoh4cnJadFPaUm10p+kwp+RuMafudpRJ4EbMKV 2LSb7zLlIKLCu3X5UMYNahpJ8jZZw0xMPlyVmw94qAc2JiT4+XBlc6H X-Developer-Key: i=kelvin.zhang@amlogic.com; a=ed25519; pk=pgnle7HTNvnNTcOoGejvtTC7BJT30HUNXfMHRRXSylI= X-Endpoint-Received: by B4 Relay for kelvin.zhang@amlogic.com/20240329 with auth_id=148 X-Original-From: Kelvin Zhang X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20240329_021737_289873_E3C31F75 X-CRM114-Status: UNSURE ( 9.65 ) X-CRM114-Notice: Please train this message. X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Reply-To: kelvin.zhang@amlogic.com Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org From: Zelong Dong There are 7 sets of Reset Source in Amlogic T7 SoC Reset Controller, and the offset between base and level registers is 0x40. Add a new compatible string and struct meson_reset_param to support the reset controller on T7 SoC. Signed-off-by: Zelong Dong Signed-off-by: Kelvin Zhang Reviewed-by: Neil Armstrong Reviewed-by: Neil Armstrong --- drivers/reset/reset-meson.c | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/drivers/reset/reset-meson.c b/drivers/reset/reset-meson.c index f78be97898bc..1e9fca3e30e8 100644 --- a/drivers/reset/reset-meson.c +++ b/drivers/reset/reset-meson.c @@ -102,6 +102,11 @@ static const struct meson_reset_param meson_s4_param = { .level_offset = 0x40, }; +static const struct meson_reset_param t7_param = { + .reg_count = 7, + .level_offset = 0x40, +}; + static const struct of_device_id meson_reset_dt_ids[] = { { .compatible = "amlogic,meson8b-reset", .data = &meson8b_param}, { .compatible = "amlogic,meson-gxbb-reset", .data = &meson8b_param}, @@ -109,6 +114,7 @@ static const struct of_device_id meson_reset_dt_ids[] = { { .compatible = "amlogic,meson-a1-reset", .data = &meson_a1_param}, { .compatible = "amlogic,meson-s4-reset", .data = &meson_s4_param}, { .compatible = "amlogic,c3-reset", .data = &meson_s4_param}, + { .compatible = "amlogic,t7-reset", .data = &t7_param}, { /* sentinel */ }, }; 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Fri, 29 Mar 2024 09:17:35 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1711703855; bh=stRn40k3Wznn/gwcVteftCGGh9Q8iyBgC3XO/vR9ah4=; h=From:Date:Subject:References:In-Reply-To:To:Cc:Reply-To:From; b=AZpEFsqyYwMBCtFoX62cC5ri85w8HDkTs8aNFFzgLxCRTyYZip4k9Psofp2kT1e9r XR5azjAXVmHcBXg5HW16Y27uSEHC/xTAdq1+ufUPQwnj9P26o73e03WvD1VWHv5O7u /BKch4lSUmsawiqXvVYS8nAOaV86bLtOGUt2GS9CZHMileOrw6Ijl9bfP406mPx/8p cUR0zcfHDKkMUXJaxhNAc9M2vSq3J4Qyxh1lkVNcZ+GyZME/a6CgzKDosvqQTeY6S0 SsSvmQ/lWgv2gZSMDK+NX/EZbR7mrbs4D5trnUo/zSlAA7QpcT5AdH+zTRBDR3PG2P HgA7WRGfWnF0Q== Received: from aws-us-west-2-korg-lkml-1.web.codeaurora.org (localhost.localdomain [127.0.0.1]) by smtp.lore.kernel.org (Postfix) with ESMTP id 59311CD128E; Fri, 29 Mar 2024 09:17:35 +0000 (UTC) From: Kelvin Zhang via B4 Relay Date: Fri, 29 Mar 2024 17:17:15 +0800 Subject: [PATCH 3/3] arm64: dts: amlogic: add reset controller for Amlogic T7 SoC MIME-Version: 1.0 Message-Id: <20240329-t7-reset-v1-3-4c6e2e68359e@amlogic.com> References: <20240329-t7-reset-v1-0-4c6e2e68359e@amlogic.com> In-Reply-To: <20240329-t7-reset-v1-0-4c6e2e68359e@amlogic.com> To: Philipp Zabel , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Neil Armstrong , Kevin Hilman , Jerome Brunet , Martin Blumenstingl Cc: devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-amlogic@lists.infradead.org, linux-kernel@vger.kernel.org, Zelong Dong , Kelvin Zhang X-Mailer: b4 0.12.4 X-Developer-Signature: v=1; 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X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Reply-To: kelvin.zhang@amlogic.com Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org From: Zelong Dong Add the reset controller device of Amlogic T7 SoC family Signed-off-by: Zelong Dong Signed-off-by: Kelvin Zhang Reviewed-by: Neil Armstrong --- arch/arm64/boot/dts/amlogic/amlogic-t7.dtsi | 7 +++++++ 1 file changed, 7 insertions(+) diff --git a/arch/arm64/boot/dts/amlogic/amlogic-t7.dtsi b/arch/arm64/boot/dts/amlogic/amlogic-t7.dtsi index 5248bdf824ea..e94bb85b5292 100644 --- a/arch/arm64/boot/dts/amlogic/amlogic-t7.dtsi +++ b/arch/arm64/boot/dts/amlogic/amlogic-t7.dtsi @@ -5,6 +5,7 @@ #include #include +#include / { interrupt-parent = <&gic>; @@ -149,6 +150,12 @@ apb4: bus@fe000000 { #size-cells = <2>; ranges = <0x0 0x0 0x0 0xfe000000 0x0 0x480000>; + reset: reset-controller@2000 { + compatible = "amlogic,t7-reset"; + reg = <0x0 0x2000 0x0 0x98>; + #reset-cells = <1>; + }; + watchdog@2100 { compatible = "amlogic,t7-wdt"; reg = <0x0 0x2100 0x0 0x10>;