From patchwork Fri Mar 29 11:47:28 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Charles Keepax X-Patchwork-Id: 13610587 Received: from mx0b-001ae601.pphosted.com (mx0a-001ae601.pphosted.com [67.231.149.25]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 665DB3D0A1; Fri, 29 Mar 2024 11:47:38 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=67.231.149.25 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1711712860; cv=none; b=Ju7EUA7bG2QxCHIwq1dTOQtDv6ixA/+CeXPAwR9EHVbrpOpizSunh6nIHM8zYvmXy2DLSX2WibCxZiQczfIs4zbj+m7r21oPMvmkoduHsjBGXeEP3uEZfJYjB4A8iEBP8+K6wiwkWgfgElCPyuy3Ck4Cdqq1/X0yHO3w8d7IkzA= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1711712860; c=relaxed/simple; bh=Pw0an15Ryf+cccx17VkcKxitygXsbkxpPvE+wCyiFt4=; h=From:To:CC:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=bup0Tg8XgUlmYxWYb3GRuegGR/NJLYTCAdV4KWjFqqx/fPdh9NJZGPHpGy3AcIyzGjwSUrAopdT5ce9q/m4Br4pmFP45oGMw2RYXBePv7TtdB9JfpQZwW6qyKmOsPPRvTtQjT2NUk4ZJPH13YMIC1y3zJpWZVswokaWRA1sDBVk= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=opensource.cirrus.com; spf=pass smtp.mailfrom=opensource.cirrus.com; dkim=pass (2048-bit key) header.d=cirrus.com header.i=@cirrus.com header.b=ai7myRKd; arc=none smtp.client-ip=67.231.149.25 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=opensource.cirrus.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=opensource.cirrus.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=cirrus.com header.i=@cirrus.com header.b="ai7myRKd" Received: from pps.filterd (m0077473.ppops.net [127.0.0.1]) by mx0a-001ae601.pphosted.com (8.17.1.24/8.17.1.24) with ESMTP id 42T51HNI032384; Fri, 29 Mar 2024 06:47:32 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=cirrus.com; h= from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding:content-type; s= PODMain02222019; bh=357eE4xzGzzgIlIH685EBtNkhR3++TI4U8Ms5TSwQoI=; b= ai7myRKd3yDXGxseNPtAXur5CJOwIIGp9Ywpw26m492imyoZX1YoPrGFUAUuFoZE WeUR9PuqPj3UBf33D7QZPuADihMmTaCBvRd8DQWG3eIB1Myl5UD79r9zfj6Uyc0J +J4HDtTMboaecqs+r6duGWY17W8OgyAAKvNKq1KKPY5VBcruka7ceTpGIyh8Nf/r WDrQJltoC0U88SOI5qVbBSFOsR3KbY9Nombro2Pkkrm5ivdN1HggQt0Qbjvu6d/S GasVFcGDKw/op0p5FJQC+hn4ffLa7AYYNu4g0rKJBm/8gAPaMvvKNuwRp9E0RiHn IYBXsSq+wgbhUT27PydI1g== Received: from ediex01.ad.cirrus.com ([84.19.233.68]) by mx0a-001ae601.pphosted.com (PPS) with ESMTPS id 3x4k7k4747-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Fri, 29 Mar 2024 06:47:32 -0500 (CDT) Received: from ediex01.ad.cirrus.com (198.61.84.80) by ediex01.ad.cirrus.com (198.61.84.80) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1544.4; Fri, 29 Mar 2024 11:47:30 +0000 Received: from ediswmail9.ad.cirrus.com (198.61.86.93) by ediex01.ad.cirrus.com (198.61.84.80) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1544.4 via Frontend Transport; Fri, 29 Mar 2024 11:47:30 +0000 Received: from ediswws07.ad.cirrus.com (ediswws07.ad.cirrus.com [198.90.208.14]) by ediswmail9.ad.cirrus.com (Postfix) with ESMTP id 45C3D82024A; Fri, 29 Mar 2024 11:47:30 +0000 (UTC) From: Charles Keepax To: , , CC: , , Subject: [PATCH v3 1/3] gpio: swnode: Add ability to specify native chip selects for SPI Date: Fri, 29 Mar 2024 11:47:28 +0000 Message-ID: <20240329114730.360313-2-ckeepax@opensource.cirrus.com> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20240329114730.360313-1-ckeepax@opensource.cirrus.com> References: <20240329114730.360313-1-ckeepax@opensource.cirrus.com> Precedence: bulk X-Mailing-List: linux-spi@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-Proofpoint-GUID: MVqB_ZbE_vwCH_-IV6YxddtM6qwapT3F X-Proofpoint-ORIG-GUID: MVqB_ZbE_vwCH_-IV6YxddtM6qwapT3F X-Proofpoint-Spam-Reason: safe SPI devices can specify a cs-gpios property to enumerate their chip selects. Under device tree, a zero entry in this property can be used to specify that a particular chip select is using the SPI controllers native chip select, for example: cs-gpios = <&gpio1 0 0>, <0>; Here the second chip select is native. However, when using swnodes there is currently no way to specify a native chip select. The proposal here is to register a swnode_gpio_undefined software node, that can be specified to allow the indication of a native chip select. For example: static const struct software_node_ref_args device_cs_refs[] = { { .node = &device_gpiochip_swnode, .nargs = 2, .args = { 0, GPIO_ACTIVE_LOW }, }, { .node = &swnode_gpio_undefined, .nargs = 0, }, }; Register the swnode as the gpiolib is initialised and check in swnode_get_gpio_device if the returned node matches swnode_gpio_undefined and return -ENOENT, which matches the behaviour of the device tree system when it encounters a 0 phandle. Signed-off-by: Charles Keepax --- No changes since v2. Thanks, Charles drivers/gpio/gpiolib-swnode.c | 8 ++++++++ drivers/gpio/gpiolib.c | 9 +++++++++ include/linux/gpio/consumer.h | 4 ++++ 3 files changed, 21 insertions(+) diff --git a/drivers/gpio/gpiolib-swnode.c b/drivers/gpio/gpiolib-swnode.c index fa52bdb1a29a3..801b5a660307f 100644 --- a/drivers/gpio/gpiolib-swnode.c +++ b/drivers/gpio/gpiolib-swnode.c @@ -17,6 +17,11 @@ #include "gpiolib.h" #include "gpiolib-swnode.h" +const struct software_node swnode_gpio_undefined = { + .name = "gpio-internal-undefined", +}; +EXPORT_SYMBOL_GPL(swnode_gpio_undefined); + static void swnode_format_propname(const char *con_id, char *propname, size_t max_size) { @@ -40,6 +45,9 @@ static struct gpio_device *swnode_get_gpio_device(struct fwnode_handle *fwnode) if (!gdev_node || !gdev_node->name) return ERR_PTR(-EINVAL); + if (!strcmp(gdev_node->name, "gpio-internal-undefined")) + return ERR_PTR(-ENOENT); + gdev = gpio_device_find_by_label(gdev_node->name); return gdev ?: ERR_PTR(-EPROBE_DEFER); } diff --git a/drivers/gpio/gpiolib.c b/drivers/gpio/gpiolib.c index ce94e37bcbee7..e3a7e2a3a323e 100644 --- a/drivers/gpio/gpiolib.c +++ b/drivers/gpio/gpiolib.c @@ -4892,8 +4892,17 @@ DEFINE_SEQ_ATTRIBUTE(gpiolib); static int __init gpiolib_debugfs_init(void) { + int ret; + + ret = software_node_register(&swnode_gpio_undefined); + if (ret < 0) { + pr_err("gpiolib: failed to register swnode: %d\n", ret); + return ret; + } + /* /sys/kernel/debug/gpio */ debugfs_create_file("gpio", 0444, NULL, NULL, &gpiolib_fops); + return 0; } subsys_initcall(gpiolib_debugfs_init); diff --git a/include/linux/gpio/consumer.h b/include/linux/gpio/consumer.h index db2dfbae8edbd..e685fac43398d 100644 --- a/include/linux/gpio/consumer.h +++ b/include/linux/gpio/consumer.h @@ -12,6 +12,8 @@ struct fwnode_handle; struct gpio_array; struct gpio_desc; +struct software_node; + /** * struct gpio_descs - Struct containing an array of descriptors that can be * obtained using gpiod_get_array() @@ -54,6 +56,8 @@ enum gpiod_flags { GPIOD_OUT_HIGH_OPEN_DRAIN = GPIOD_OUT_HIGH | GPIOD_FLAGS_BIT_OPEN_DRAIN, }; +extern const struct software_node swnode_gpio_undefined; + #ifdef CONFIG_GPIOLIB /* Return the number of GPIOs associated with a device / function */ From patchwork Fri Mar 29 11:47:29 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Charles Keepax X-Patchwork-Id: 13610589 Received: from mx0b-001ae601.pphosted.com (mx0a-001ae601.pphosted.com [67.231.149.25]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 430B36A026; Fri, 29 Mar 2024 11:47:38 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=67.231.149.25 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1711712860; cv=none; b=Q46Z1nlSP4HEd0zA5MD5Bez9yDD18BEEPYACFKSnnd+gLp5KbcvHBVN/a1BZz5NKBsU9vehC2W7Xx4rxk7X1Hdu/VEkP7bxQvxswStD8byMmgHj0u+JpeQUgRAkzrnBsGQ6psaUt/EE4HI7+ylFZ3ZRHWhXsqf5mF+EP+wFI8qA= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1711712860; c=relaxed/simple; bh=v1LxQ5YjmxS092pnx1Mx33QXtxtUl7MuKIwFnJmJrHc=; h=From:To:CC:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=aWgdaAHUE9naPTsQcv2+tucKuFEi2BhSO58uObwRmookfWihtwFNCWPP6J7fZVnYl6tFlO2Pnflk1h1kqQQKAn0FsrsCJ1Roly1GNmrKm9sabZN4U8Y5lFzcYa/oJZIC7oMqvndG7jSikIzt25an8hwu7dlsQ1JYKxHRt++pxvU= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=opensource.cirrus.com; spf=pass smtp.mailfrom=opensource.cirrus.com; dkim=pass (2048-bit key) header.d=cirrus.com header.i=@cirrus.com header.b=M67BFP6P; arc=none smtp.client-ip=67.231.149.25 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=opensource.cirrus.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=opensource.cirrus.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=cirrus.com header.i=@cirrus.com header.b="M67BFP6P" Received: from pps.filterd (m0077473.ppops.net [127.0.0.1]) by mx0a-001ae601.pphosted.com (8.17.1.24/8.17.1.24) with ESMTP id 42T6uj1C024362; Fri, 29 Mar 2024 06:47:32 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=cirrus.com; h= from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding:content-type; s= PODMain02222019; bh=BDyUt3oHAWEQV0CrT1w+UvB+a7MzJpCpZIMhThA78mw=; b= M67BFP6PWEjwih7d4CrtUOf7XRhSoq+anp6N+zxXpaNUwp4hCVbwldTaZoyr12Dd zwkKO1KH+8djqf83M8HyjevQfpHzqTSnFNpcH9uUNGS7iySdtczsaC9pPMta9NDB GVW3QyEDaSA4+jwONS8YM0V/2j5lTlgkZyPGQN9yraex1yrFDCBoKvcNHm/MIXsc pvQeIQApZ3vKMuadGb2xO6mDtDQFCpZJ/K+8QFT5aQo6UVa3X9PQsorgItKZFoJf pDrV1tO2RdK928oCOhVEWKkaN/tMu+j9Jn6noJYFo4KJ+OH+ScfZaOppOdTxl4tp rfhN0MsIWD6k3CcBt+GuYg== Received: from ediex02.ad.cirrus.com ([84.19.233.68]) by mx0a-001ae601.pphosted.com (PPS) with ESMTPS id 3x4k7k4748-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Fri, 29 Mar 2024 06:47:32 -0500 (CDT) Received: from ediex01.ad.cirrus.com (198.61.84.80) by ediex02.ad.cirrus.com (198.61.84.81) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1544.4; Fri, 29 Mar 2024 11:47:30 +0000 Received: from ediswmail9.ad.cirrus.com (198.61.86.93) by ediex01.ad.cirrus.com (198.61.84.80) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1544.4 via Frontend Transport; Fri, 29 Mar 2024 11:47:30 +0000 Received: from ediswws07.ad.cirrus.com (ediswws07.ad.cirrus.com [198.90.208.14]) by ediswmail9.ad.cirrus.com (Postfix) with ESMTP id 48CA982024B; Fri, 29 Mar 2024 11:47:30 +0000 (UTC) From: Charles Keepax To: , , CC: , , Subject: [PATCH v3 2/3] spi: Add a mechanism to use the fwnode name for the SPI device Date: Fri, 29 Mar 2024 11:47:29 +0000 Message-ID: <20240329114730.360313-3-ckeepax@opensource.cirrus.com> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20240329114730.360313-1-ckeepax@opensource.cirrus.com> References: <20240329114730.360313-1-ckeepax@opensource.cirrus.com> Precedence: bulk X-Mailing-List: linux-spi@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-Proofpoint-GUID: ztLN6ysgwOR2UPbWezUCIOiKiE3E9Omi X-Proofpoint-ORIG-GUID: ztLN6ysgwOR2UPbWezUCIOiKiE3E9Omi X-Proofpoint-Spam-Reason: safe Add a mechanism to force the use of the fwnode name for the name of the SPI device itself. This is useful when devices need to be manually added within the kernel. Signed-off-by: Charles Keepax --- No changes since v2. Thanks, Charles drivers/spi/spi.c | 7 +++++++ include/linux/spi/spi.h | 2 ++ 2 files changed, 9 insertions(+) diff --git a/drivers/spi/spi.c b/drivers/spi/spi.c index a2f01116ba092..a38a4960032b8 100644 --- a/drivers/spi/spi.c +++ b/drivers/spi/spi.c @@ -598,6 +598,12 @@ EXPORT_SYMBOL_GPL(spi_alloc_device); static void spi_dev_set_name(struct spi_device *spi) { struct acpi_device *adev = ACPI_COMPANION(&spi->dev); + struct fwnode_handle *fwnode = dev_fwnode(&spi->dev); + + if (spi->use_fwnode_name && fwnode) { + dev_set_name(&spi->dev, "spi-%s", fwnode_get_name(fwnode)); + return; + } if (adev) { dev_set_name(&spi->dev, "spi-%s", acpi_dev_name(adev)); @@ -830,6 +836,7 @@ struct spi_device *spi_new_device(struct spi_controller *ctlr, * spi->cs_index_mask as 0x01. */ proxy->cs_index_mask = 0x01; + proxy->use_fwnode_name = chip->use_fwnode_name; if (chip->swnode) { status = device_add_software_node(&proxy->dev, chip->swnode); diff --git a/include/linux/spi/spi.h b/include/linux/spi/spi.h index b589e25474393..265f5d0c15304 100644 --- a/include/linux/spi/spi.h +++ b/include/linux/spi/spi.h @@ -222,6 +222,7 @@ struct spi_device { struct spi_delay cs_setup; struct spi_delay cs_hold; struct spi_delay cs_inactive; + bool use_fwnode_name; /* The statistics */ struct spi_statistics __percpu *pcpu_statistics; @@ -1603,6 +1604,7 @@ struct spi_board_info { char modalias[SPI_NAME_SIZE]; const void *platform_data; const struct software_node *swnode; + bool use_fwnode_name; void *controller_data; int irq; From patchwork Fri Mar 29 11:47:30 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Charles Keepax X-Patchwork-Id: 13610590 Received: from mx0b-001ae601.pphosted.com (mx0a-001ae601.pphosted.com [67.231.149.25]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 14D124F606; Fri, 29 Mar 2024 11:47:38 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=67.231.149.25 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1711712860; cv=none; b=l2qNBrAvyN58wzUjRyNO5HtD9kkacbmGE1pJ/MPFlBaZkOaGCeucj+rRxXbHMpyrs85TFstkzl8Yfzhjz2HJKZ+KPiIW/2S7N9LvQ0kH9NncT2GAhBYwmkyak0K91SaYhdEE6k1ft2mvU+tmuiKVcLyIJx8nMUkW+bFvvfFKFnQ= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1711712860; c=relaxed/simple; bh=VLYZT/jTNY2MdMLW10fktg8Qi2AxjSBvAG3LDd+YZUo=; h=From:To:CC:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=i82QoTMA7Z6I2o6AYpjUN5sXtzSoojMX1mBkHZQxsNhPmANXF2bKcDLJSz+RWgNjdCDED2aCNvd+9EnZJSGI4Zo2d0HUlN3WiIaKTqo0nRQDPTrMTjBtM3AOQh9kuUupxAd8c54DjyTHrpQBpd//cujEzMnWs1uV5ZJExY+19JM= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=opensource.cirrus.com; spf=pass smtp.mailfrom=opensource.cirrus.com; dkim=pass (2048-bit key) header.d=cirrus.com header.i=@cirrus.com header.b=I9Fa7KWG; arc=none smtp.client-ip=67.231.149.25 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=opensource.cirrus.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=opensource.cirrus.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=cirrus.com header.i=@cirrus.com header.b="I9Fa7KWG" Received: from pps.filterd (m0077473.ppops.net [127.0.0.1]) by mx0a-001ae601.pphosted.com (8.17.1.24/8.17.1.24) with ESMTP id 42T51HNK032384; Fri, 29 Mar 2024 06:47:34 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=cirrus.com; h= from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding:content-type; s= PODMain02222019; bh=0vJgnHi3VGwYeuRAuisAL4gmPmLutHAb0+lrGohDqDM=; b= I9Fa7KWG+cBKY1gCsb1SwfPesS8+YiLw+7dUJ3vUNsqegHcx+N19FkxWonw3jXAI +TiNgiormuY7z+pLJdnpMRW9IGYkg5v+VCq2iZB3Ibt7AZyOefOfvgdH8fXEbH1s q+Y2kbcXmsuwQ9NyQmXz5a5fTST8MX1g+7Hf9Xi1eUtsyFKavQ9sRxBoU5hxPhpl o/4l+gzQdhfXYR7wme3z61/V+3s/uRQkIACu4ODUj+m3+AYc4ydkKSEZQlRuxGPl ICEdjdowlduYihpNEJIWPtVRjOvTa1J1anKRiZ9vIuF9sTfAF3pwK86ZQRyeEClt h9g0W7MJJfx4AEiCT7rbng== Received: from ediex01.ad.cirrus.com ([84.19.233.68]) by mx0a-001ae601.pphosted.com (PPS) with ESMTPS id 3x4k7k4747-3 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Fri, 29 Mar 2024 06:47:34 -0500 (CDT) Received: from ediex02.ad.cirrus.com (198.61.84.81) by ediex01.ad.cirrus.com (198.61.84.80) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1544.4; Fri, 29 Mar 2024 11:47:30 +0000 Received: from ediswmail9.ad.cirrus.com (198.61.86.93) by anon-ediex02.ad.cirrus.com (198.61.84.81) with Microsoft SMTP Server id 15.2.1544.4 via Frontend Transport; Fri, 29 Mar 2024 11:47:30 +0000 Received: from ediswws07.ad.cirrus.com (ediswws07.ad.cirrus.com [198.90.208.14]) by ediswmail9.ad.cirrus.com (Postfix) with ESMTP id 4C555820258; Fri, 29 Mar 2024 11:47:30 +0000 (UTC) From: Charles Keepax To: , , CC: , , Subject: [PATCH v3 3/3] spi: cs42l43: Add bridged cs35l56 amplifiers Date: Fri, 29 Mar 2024 11:47:30 +0000 Message-ID: <20240329114730.360313-4-ckeepax@opensource.cirrus.com> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20240329114730.360313-1-ckeepax@opensource.cirrus.com> References: <20240329114730.360313-1-ckeepax@opensource.cirrus.com> Precedence: bulk X-Mailing-List: linux-spi@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-Proofpoint-GUID: h17682zc8J-Bm0bkbYmPmXJVmBLA_KRM X-Proofpoint-ORIG-GUID: h17682zc8J-Bm0bkbYmPmXJVmBLA_KRM X-Proofpoint-Spam-Reason: safe From: Maciej Strozek On some cs42l43 systems a couple of cs35l56 amplifiers are attached to the cs42l43's SPI and I2S. On Windows the cs42l43 is controlled by a SDCA class driver and these two amplifiers are controlled by firmware running on the cs42l43. However, under Linux the decision was made to interact with the cs42l43 directly, affording the user greater control over the audio system. However, this has resulted in an issue where these two bridged cs35l56 amplifiers are not populated in ACPI and must be added manually. Check for the presence of the "01fa-cirrus-sidecar-instances" property in the SDCA extension unit's ACPI properties to confirm the presence of these two amplifiers and if they exist add them manually onto the SPI bus. Signed-off-by: Maciej Strozek Signed-off-by: Charles Keepax --- Changes since v2: - Add missing fwnode_handle_puts in cs42l43_has_sidecar Thanks, Charles drivers/spi/spi-cs42l43.c | 155 +++++++++++++++++++++++++++++++++++++- 1 file changed, 154 insertions(+), 1 deletion(-) diff --git a/drivers/spi/spi-cs42l43.c b/drivers/spi/spi-cs42l43.c index aabef9fc84bdf..15e93ef7b74d0 100644 --- a/drivers/spi/spi-cs42l43.c +++ b/drivers/spi/spi-cs42l43.c @@ -5,6 +5,8 @@ // Copyright (C) 2022-2023 Cirrus Logic, Inc. and // Cirrus Logic International Semiconductor Ltd. +#include +#include #include #include #include @@ -39,6 +41,59 @@ static const unsigned int cs42l43_clock_divs[] = { 2, 2, 4, 6, 8, 10, 12, 14, 16, 18, 20, 22, 24, 26, 28, 30 }; +static const struct software_node ampl = { + .name = "cs35l56-left", +}; + +static const struct software_node ampr = { + .name = "cs35l56-right", +}; + +static struct spi_board_info ampl_info = { + .modalias = "cs35l56", + .max_speed_hz = 2000000, + .chip_select = 0, + .mode = SPI_MODE_0, + .swnode = &l, + .use_fwnode_name = true, +}; + +static struct spi_board_info ampr_info = { + .modalias = "cs35l56", + .max_speed_hz = 2000000, + .chip_select = 1, + .mode = SPI_MODE_0, + .swnode = &r, + .use_fwnode_name = true, +}; + +static const struct software_node cs42l43_gpiochip_swnode = { + .name = "cs42l43-pinctrl", +}; + +static const struct software_node_ref_args cs42l43_cs_refs[] = { + { + .node = &cs42l43_gpiochip_swnode, + .nargs = 2, + .args = { 0, GPIO_ACTIVE_LOW }, + }, + { + .node = &swnode_gpio_undefined, + .nargs = 0, + }, +}; + +static const struct property_entry cs42l43_cs_props[] = { + { + .name = "cs-gpios", + .length = ARRAY_SIZE(cs42l43_cs_refs) * + sizeof(struct software_node_ref_args), + .type = DEV_PROP_REF, + .pointer = cs42l43_cs_refs, + }, + {} +}; + static int cs42l43_spi_tx(struct regmap *regmap, const u8 *buf, unsigned int len) { const u8 *end = buf + len; @@ -203,6 +258,54 @@ static size_t cs42l43_spi_max_length(struct spi_device *spi) return CS42L43_SPI_MAX_LENGTH; } +#if IS_ENABLED(CONFIG_ACPI) +static bool cs42l43_has_sidecar(struct fwnode_handle *fwnode) +{ + static const int func_smart_amp = 0x1; + struct fwnode_handle *child_fwnode, *ext_fwnode; + unsigned long long function; + unsigned int val; + int ret; + + if (!is_acpi_node(fwnode)) + return false; + + fwnode_for_each_child_node(fwnode, child_fwnode) { + struct acpi_device *adev = to_acpi_device_node(child_fwnode); + + ret = acpi_evaluate_integer(adev->handle, "_ADR", NULL, &function); + if (ACPI_FAILURE(ret) || function != func_smart_amp) { + fwnode_handle_put(fwnode); + continue; + } + + ext_fwnode = fwnode_get_named_child_node(child_fwnode, + "mipi-sdca-function-expansion-subproperties"); + if (!ext_fwnode) { + fwnode_handle_put(fwnode); + continue; + } + + ret = fwnode_property_read_u32(ext_fwnode, + "01fa-cirrus-sidecar-instances", + &val); + + fwnode_handle_put(ext_fwnode); + fwnode_handle_put(fwnode); + + if (!ret) + return !!val; + } + + return false; +} +#else +static bool cs42l43_has_sidecar(struct fwnode_handle *fwnode) +{ + return false; +} +#endif + static void cs42l43_release_of_node(void *data) { fwnode_handle_put(data); @@ -213,6 +316,7 @@ static int cs42l43_spi_probe(struct platform_device *pdev) struct cs42l43 *cs42l43 = dev_get_drvdata(pdev->dev.parent); struct cs42l43_spi *priv; struct fwnode_handle *fwnode = dev_fwnode(cs42l43->dev); + bool has_sidecar = cs42l43_has_sidecar(fwnode); int ret; priv = devm_kzalloc(&pdev->dev, sizeof(*priv), GFP_KERNEL); @@ -266,16 +370,64 @@ static int cs42l43_spi_probe(struct platform_device *pdev) } } - device_set_node(&priv->ctlr->dev, fwnode); + if (has_sidecar) { + ret = software_node_register(&cs42l43_gpiochip_swnode); + if (ret) { + dev_err(priv->dev, "Failed to register gpio swnode: %d\n", ret); + return ret; + } + + ret = device_create_managed_software_node(&priv->ctlr->dev, cs42l43_cs_props, NULL); + if (ret) { + dev_err(priv->dev, "Failed to add swnode: %d\n", ret); + goto err; + } + + } else { + device_set_node(&priv->ctlr->dev, fwnode); + } ret = devm_spi_register_controller(priv->dev, priv->ctlr); if (ret) { dev_err(priv->dev, "Failed to register SPI controller: %d\n", ret); + goto err; + } + + if (has_sidecar) { + if (!spi_new_device(priv->ctlr, &l_info)) { + ret = -ENODEV; + dev_err(priv->dev, "Failed to create left amp slave\n"); + goto err; + } + + if (!spi_new_device(priv->ctlr, &r_info)) { + ret = -ENODEV; + dev_err(priv->dev, "Failed to create right amp slave\n"); + goto err; + } } + return 0; + +err: + if (has_sidecar) + software_node_unregister(&cs42l43_gpiochip_swnode); + return ret; } +static int cs42l43_spi_remove(struct platform_device *pdev) +{ + struct cs42l43 *cs42l43 = dev_get_drvdata(pdev->dev.parent); + struct fwnode_handle *fwnode = dev_fwnode(cs42l43->dev); + bool has_sidecar = cs42l43_has_sidecar(fwnode); + + if (has_sidecar) + software_node_unregister(&cs42l43_gpiochip_swnode); + + return 0; +}; + static const struct platform_device_id cs42l43_spi_id_table[] = { { "cs42l43-spi", }, {} @@ -288,6 +440,7 @@ static struct platform_driver cs42l43_spi_driver = { }, .probe = cs42l43_spi_probe, .id_table = cs42l43_spi_id_table, + .remove = cs42l43_spi_remove, }; module_platform_driver(cs42l43_spi_driver);