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Fri, 29 Mar 2024 23:59:13 +0300 From: Dmitry Rokosov To: , , , , , , , CC: , , , , , , , Dmitry Rokosov Subject: [PATCH v1 1/6] dt-bindings: clock: meson: a1: pll: introduce new syspll bindings Date: Fri, 29 Mar 2024 23:58:41 +0300 Message-ID: <20240329205904.25002-2-ddrokosov@salutedevices.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20240329205904.25002-1-ddrokosov@salutedevices.com> References: <20240329205904.25002-1-ddrokosov@salutedevices.com> MIME-Version: 1.0 X-Originating-IP: [100.64.160.123] X-ClientProxiedBy: p-i-exch-sc-m02.sberdevices.ru (172.16.192.103) To p-i-exch-sc-m02.sberdevices.ru (172.16.192.103) X-KSMG-Rule-ID: 10 X-KSMG-Message-Action: clean X-KSMG-AntiSpam-Lua-Profiles: 184500 [Mar 29 2024] X-KSMG-AntiSpam-Version: 6.1.0.4 X-KSMG-AntiSpam-Envelope-From: ddrokosov@salutedevices.com X-KSMG-AntiSpam-Rate: 0 X-KSMG-AntiSpam-Status: not_detected X-KSMG-AntiSpam-Method: none X-KSMG-AntiSpam-Auth: dkim=none X-KSMG-AntiSpam-Info: LuaCore: 14 0.3.14 5a0c43d8a1c3c0e5b0916cc02a90d4b950c01f96, {Tracking_from_domain_doesnt_match_to}, salutedevices.com:7.1.1;d41d8cd98f00b204e9800998ecf8427e.com:7.1.1;127.0.0.199:7.1.2;100.64.160.123:7.1.2;smtp.sberdevices.ru:5.0.1,7.1.1, FromAlignment: s, ApMailHostAddress: 100.64.160.123 X-MS-Exchange-Organization-SCL: -1 X-KSMG-AntiSpam-Interceptor-Info: scan successful X-KSMG-AntiPhishing: Clean X-KSMG-LinksScanning: Clean X-KSMG-AntiVirus: Kaspersky Secure Mail Gateway, version 2.0.1.6960, bases: 2024/03/29 16:52:00 #24511844 X-KSMG-AntiVirus-Status: Clean, skipped X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20240329_135920_967978_D7D688CC X-CRM114-Status: GOOD ( 11.77 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org The 'syspll' PLL is a general-purpose PLL designed specifically for the CPU clock. It is capable of producing output frequencies within the range of 768MHz to 1536MHz. Signed-off-by: Dmitry Rokosov --- .../devicetree/bindings/clock/amlogic,a1-pll-clkc.yaml | 7 +++++-- include/dt-bindings/clock/amlogic,a1-pll-clkc.h | 2 ++ 2 files changed, 7 insertions(+), 2 deletions(-) diff --git a/Documentation/devicetree/bindings/clock/amlogic,a1-pll-clkc.yaml b/Documentation/devicetree/bindings/clock/amlogic,a1-pll-clkc.yaml index a59b188a8bf5..fbba57031278 100644 --- a/Documentation/devicetree/bindings/clock/amlogic,a1-pll-clkc.yaml +++ b/Documentation/devicetree/bindings/clock/amlogic,a1-pll-clkc.yaml @@ -26,11 +26,13 @@ properties: items: - description: input fixpll_in - description: input hifipll_in + - description: input syspll_in clock-names: items: - const: fixpll_in - const: hifipll_in + - const: syspll_in required: - compatible @@ -53,7 +55,8 @@ examples: reg = <0 0x7c80 0 0x18c>; #clock-cells = <1>; clocks = <&clkc_periphs CLKID_FIXPLL_IN>, - <&clkc_periphs CLKID_HIFIPLL_IN>; - clock-names = "fixpll_in", "hifipll_in"; + <&clkc_periphs CLKID_HIFIPLL_IN>, + <&clkc_periphs CLKID_SYSPLL_IN>; + clock-names = "fixpll_in", "hifipll_in", "syspll_in"; }; }; diff --git a/include/dt-bindings/clock/amlogic,a1-pll-clkc.h b/include/dt-bindings/clock/amlogic,a1-pll-clkc.h index 2b660c0f2c9f..a702d610589c 100644 --- a/include/dt-bindings/clock/amlogic,a1-pll-clkc.h +++ b/include/dt-bindings/clock/amlogic,a1-pll-clkc.h @@ -21,5 +21,7 @@ #define CLKID_FCLK_DIV5 8 #define CLKID_FCLK_DIV7 9 #define CLKID_HIFI_PLL 10 +#define CLKID_SYS_PLL 11 +#define CLKID_SYS_PLL_DIV16 12 #endif /* __A1_PLL_CLKC_H */ From patchwork Fri Mar 29 20:58:42 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dmitry Rokosov X-Patchwork-Id: 13611064 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id C6D68CD128A for ; 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Fri, 29 Mar 2024 23:59:15 +0300 (MSK) Received: from CAB-WSD-L081021.sberdevices.ru (100.64.160.123) by p-i-exch-sc-m02.sberdevices.ru (172.16.192.103) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1118.40; Fri, 29 Mar 2024 23:59:14 +0300 From: Dmitry Rokosov To: , , , , , , , CC: , , , , , , , Dmitry Rokosov Subject: [PATCH v1 2/6] clk: meson: a1: pll: support 'syspll' general-purpose PLL for CPU clock Date: Fri, 29 Mar 2024 23:58:42 +0300 Message-ID: <20240329205904.25002-3-ddrokosov@salutedevices.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20240329205904.25002-1-ddrokosov@salutedevices.com> References: <20240329205904.25002-1-ddrokosov@salutedevices.com> MIME-Version: 1.0 X-Originating-IP: [100.64.160.123] X-ClientProxiedBy: p-i-exch-sc-m02.sberdevices.ru (172.16.192.103) To p-i-exch-sc-m02.sberdevices.ru (172.16.192.103) X-KSMG-Rule-ID: 10 X-KSMG-Message-Action: clean X-KSMG-AntiSpam-Lua-Profiles: 184500 [Mar 29 2024] X-KSMG-AntiSpam-Version: 6.1.0.4 X-KSMG-AntiSpam-Envelope-From: ddrokosov@salutedevices.com X-KSMG-AntiSpam-Rate: 0 X-KSMG-AntiSpam-Status: not_detected X-KSMG-AntiSpam-Method: none X-KSMG-AntiSpam-Auth: dkim=none X-KSMG-AntiSpam-Info: LuaCore: 14 0.3.14 5a0c43d8a1c3c0e5b0916cc02a90d4b950c01f96, {Tracking_from_domain_doesnt_match_to}, salutedevices.com:7.1.1;127.0.0.199:7.1.2;d41d8cd98f00b204e9800998ecf8427e.com:7.1.1;100.64.160.123:7.1.2;smtp.sberdevices.ru:7.1.1,5.0.1, FromAlignment: s, ApMailHostAddress: 100.64.160.123 X-MS-Exchange-Organization-SCL: -1 X-KSMG-AntiSpam-Interceptor-Info: scan successful X-KSMG-AntiPhishing: Clean X-KSMG-LinksScanning: Clean X-KSMG-AntiVirus: Kaspersky Secure Mail Gateway, version 2.0.1.6960, bases: 2024/03/29 16:52:00 #24511844 X-KSMG-AntiVirus-Status: Clean, skipped X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20240329_135920_956069_533BF48E X-CRM114-Status: GOOD ( 18.10 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org The 'syspll' PLL, also known as the system PLL, is a general and essential PLL responsible for generating the CPU clock frequency. With its wide-ranging capabilities, it is designed to accommodate frequencies within the range of 768MHz to 1536MHz. Signed-off-by: Dmitry Rokosov --- drivers/clk/meson/a1-pll.c | 78 ++++++++++++++++++++++++++++++++++++++ drivers/clk/meson/a1-pll.h | 6 +++ 2 files changed, 84 insertions(+) diff --git a/drivers/clk/meson/a1-pll.c b/drivers/clk/meson/a1-pll.c index 60b2e53e7e51..02fd2d325cc6 100644 --- a/drivers/clk/meson/a1-pll.c +++ b/drivers/clk/meson/a1-pll.c @@ -138,6 +138,81 @@ static struct clk_regmap hifi_pll = { }, }; +static const struct pll_mult_range sys_pll_mult_range = { + .min = 32, + .max = 64, +}; + +/* + * We assume that the sys_pll_clk has already been set up by the low-level + * bootloaders as the main CPU PLL source. Therefore, it is not necessary to + * run the initialization sequence. + */ +static struct clk_regmap sys_pll = { + .data = &(struct meson_clk_pll_data){ + .en = { + .reg_off = ANACTRL_SYSPLL_CTRL0, + .shift = 28, + .width = 1, + }, + .m = { + .reg_off = ANACTRL_SYSPLL_CTRL0, + .shift = 0, + .width = 8, + }, + .n = { + .reg_off = ANACTRL_SYSPLL_CTRL0, + .shift = 10, + .width = 5, + }, + .frac = { + .reg_off = ANACTRL_SYSPLL_CTRL1, + .shift = 0, + .width = 19, + }, + .l = { + .reg_off = ANACTRL_SYSPLL_STS, + .shift = 31, + .width = 1, + }, + .current_en = { + .reg_off = ANACTRL_SYSPLL_CTRL0, + .shift = 26, + .width = 1, + }, + .l_detect = { + .reg_off = ANACTRL_SYSPLL_CTRL2, + .shift = 6, + .width = 1, + }, + .range = &sys_pll_mult_range, + }, + .hw.init = &(struct clk_init_data){ + .name = "sys_pll", + .ops = &meson_clk_pll_ops, + .parent_names = (const char *[]){ "syspll_in" }, + .num_parents = 1, + /* + * This clock is used as the main CPU PLL source in low-level + * bootloaders, and it is necessary to mark it as critical. + */ + .flags = CLK_IS_CRITICAL, + }, +}; + +static struct clk_fixed_factor sys_pll_div16 = { + .mult = 1, + .div = 16, + .hw.init = &(struct clk_init_data){ + .name = "sys_pll_div16", + .ops = &clk_fixed_factor_ops, + .parent_hws = (const struct clk_hw *[]) { + &sys_pll.hw + }, + .num_parents = 1, + }, +}; + static struct clk_fixed_factor fclk_div2_div = { .mult = 1, .div = 2, @@ -283,6 +358,8 @@ static struct clk_hw *a1_pll_hw_clks[] = { [CLKID_FCLK_DIV5] = &fclk_div5.hw, [CLKID_FCLK_DIV7] = &fclk_div7.hw, [CLKID_HIFI_PLL] = &hifi_pll.hw, + [CLKID_SYS_PLL] = &sys_pll.hw, + [CLKID_SYS_PLL_DIV16] = &sys_pll_div16.hw, }; static struct clk_regmap *const a1_pll_regmaps[] = { @@ -293,6 +370,7 @@ static struct clk_regmap *const a1_pll_regmaps[] = { &fclk_div5, &fclk_div7, &hifi_pll, + &sys_pll, }; static struct regmap_config a1_pll_regmap_cfg = { diff --git a/drivers/clk/meson/a1-pll.h b/drivers/clk/meson/a1-pll.h index 4be17b2bf383..666d9b2137e9 100644 --- a/drivers/clk/meson/a1-pll.h +++ b/drivers/clk/meson/a1-pll.h @@ -18,6 +18,12 @@ #define ANACTRL_FIXPLL_CTRL0 0x0 #define ANACTRL_FIXPLL_CTRL1 0x4 #define ANACTRL_FIXPLL_STS 0x14 +#define ANACTRL_SYSPLL_CTRL0 0x80 +#define ANACTRL_SYSPLL_CTRL1 0x84 +#define ANACTRL_SYSPLL_CTRL2 0x88 +#define ANACTRL_SYSPLL_CTRL3 0x8c +#define ANACTRL_SYSPLL_CTRL4 0x90 +#define ANACTRL_SYSPLL_STS 0x94 #define ANACTRL_HIFIPLL_CTRL0 0xc0 #define ANACTRL_HIFIPLL_CTRL1 0xc4 #define ANACTRL_HIFIPLL_CTRL2 0xc8 From patchwork Fri Mar 29 20:58:44 2024 Content-Type: text/plain; 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Fri, 29 Mar 2024 23:59:16 +0300 From: Dmitry Rokosov To: , , , , , , , CC: , , , , , , , Dmitry Rokosov Subject: [PATCH v1 4/6] clk: meson: a1: peripherals: support 'sys_pll_div16' clock as GEN input Date: Fri, 29 Mar 2024 23:58:44 +0300 Message-ID: <20240329205904.25002-5-ddrokosov@salutedevices.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20240329205904.25002-1-ddrokosov@salutedevices.com> References: <20240329205904.25002-1-ddrokosov@salutedevices.com> MIME-Version: 1.0 X-Originating-IP: [100.64.160.123] X-ClientProxiedBy: p-i-exch-sc-m02.sberdevices.ru (172.16.192.103) To p-i-exch-sc-m02.sberdevices.ru (172.16.192.103) X-KSMG-Rule-ID: 10 X-KSMG-Message-Action: clean X-KSMG-AntiSpam-Lua-Profiles: 184500 [Mar 29 2024] X-KSMG-AntiSpam-Version: 6.1.0.4 X-KSMG-AntiSpam-Envelope-From: ddrokosov@salutedevices.com X-KSMG-AntiSpam-Rate: 0 X-KSMG-AntiSpam-Status: not_detected X-KSMG-AntiSpam-Method: none X-KSMG-AntiSpam-Auth: dkim=none X-KSMG-AntiSpam-Info: LuaCore: 14 0.3.14 5a0c43d8a1c3c0e5b0916cc02a90d4b950c01f96, {Tracking_from_domain_doesnt_match_to}, salutedevices.com:7.1.1;127.0.0.199:7.1.2;d41d8cd98f00b204e9800998ecf8427e.com:7.1.1;100.64.160.123:7.1.2;smtp.sberdevices.ru:7.1.1,5.0.1, FromAlignment: s, ApMailHostAddress: 100.64.160.123 X-MS-Exchange-Organization-SCL: -1 X-KSMG-AntiSpam-Interceptor-Info: scan successful X-KSMG-AntiPhishing: Clean X-KSMG-LinksScanning: Clean X-KSMG-AntiVirus: Kaspersky Secure Mail Gateway, version 2.0.1.6960, bases: 2024/03/29 16:52:00 #24511844 X-KSMG-AntiVirus-Status: Clean, skipped X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20240329_135920_946257_5EAA9F63 X-CRM114-Status: GOOD ( 14.69 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org The clock 'sys_pll_div16' is one of the parents of the GEN clock. It is generated in the A1 PLL clock controller with a fixed factor. Signed-off-by: Dmitry Rokosov --- drivers/clk/meson/a1-peripherals.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/clk/meson/a1-peripherals.c b/drivers/clk/meson/a1-peripherals.c index 621af1e6e4b2..3c4452f2b146 100644 --- a/drivers/clk/meson/a1-peripherals.c +++ b/drivers/clk/meson/a1-peripherals.c @@ -747,13 +747,13 @@ static struct clk_regmap fclk_div2_divn = { }; /* - * the index 2 is sys_pll_div16, it will be implemented in the CPU clock driver, * the index 4 is the clock measurement source, it's not supported yet */ -static u32 gen_table[] = { 0, 1, 3, 5, 6, 7, 8 }; +static u32 gen_table[] = { 0, 1, 2, 3, 5, 6, 7, 8 }; static const struct clk_parent_data gen_parent_data[] = { { .fw_name = "xtal", }, { .hw = &rtc.hw }, + { .fw_name = "sys_pll_div16", }, { .fw_name = "hifi_pll", }, { .fw_name = "fclk_div2", }, { .fw_name = "fclk_div3", }, From patchwork Fri Mar 29 20:58:46 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dmitry Rokosov X-Patchwork-Id: 13611068 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 68E23C6FD1F for ; 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Fri, 29 Mar 2024 23:59:18 +0300 (MSK) Received: from CAB-WSD-L081021.sberdevices.ru (100.64.160.123) by p-i-exch-sc-m02.sberdevices.ru (172.16.192.103) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1118.40; Fri, 29 Mar 2024 23:59:17 +0300 From: Dmitry Rokosov To: , , , , , , , CC: , , , , , , , Dmitry Rokosov Subject: [PATCH v1 6/6] clk: meson: a1: add Amlogic A1 CPU clock controller driver Date: Fri, 29 Mar 2024 23:58:46 +0300 Message-ID: <20240329205904.25002-7-ddrokosov@salutedevices.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20240329205904.25002-1-ddrokosov@salutedevices.com> References: <20240329205904.25002-1-ddrokosov@salutedevices.com> MIME-Version: 1.0 X-Originating-IP: [100.64.160.123] X-ClientProxiedBy: p-i-exch-sc-m02.sberdevices.ru (172.16.192.103) To p-i-exch-sc-m02.sberdevices.ru (172.16.192.103) X-KSMG-Rule-ID: 10 X-KSMG-Message-Action: clean X-KSMG-AntiSpam-Lua-Profiles: 184500 [Mar 29 2024] X-KSMG-AntiSpam-Version: 6.1.0.4 X-KSMG-AntiSpam-Envelope-From: ddrokosov@salutedevices.com X-KSMG-AntiSpam-Rate: 0 X-KSMG-AntiSpam-Status: not_detected X-KSMG-AntiSpam-Method: none X-KSMG-AntiSpam-Auth: dkim=none X-KSMG-AntiSpam-Info: LuaCore: 14 0.3.14 5a0c43d8a1c3c0e5b0916cc02a90d4b950c01f96, {Tracking_from_domain_doesnt_match_to}, salutedevices.com:7.1.1;127.0.0.199:7.1.2;d41d8cd98f00b204e9800998ecf8427e.com:7.1.1;100.64.160.123:7.1.2;smtp.sberdevices.ru:7.1.1,5.0.1, FromAlignment: s, ApMailHostAddress: 100.64.160.123 X-MS-Exchange-Organization-SCL: -1 X-KSMG-AntiSpam-Interceptor-Info: scan successful X-KSMG-AntiPhishing: Clean X-KSMG-LinksScanning: Clean X-KSMG-AntiVirus: Kaspersky Secure Mail Gateway, version 2.0.1.6960, bases: 2024/03/29 16:52:00 #24511844 X-KSMG-AntiVirus-Status: Clean, skipped X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20240329_135921_801079_12A1D907 X-CRM114-Status: GOOD ( 28.15 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org The CPU clock controller plays a general role in the Amlogic A1 SoC family by generating CPU clocks. As an APB slave module, it offers the capability to inherit the CPU clock from two sources: the internal fixed clock known as 'cpu fixed clock' and the external input provided by the A1 PLL clock controller, referred to as 'syspll'. It is important for the driver to handle cpu_clk rate switching effectively by transitioning to the CPU fixed clock to avoid any potential execution freezes. Signed-off-by: Dmitry Rokosov --- drivers/clk/meson/Kconfig | 10 ++ drivers/clk/meson/Makefile | 1 + drivers/clk/meson/a1-cpu.c | 324 +++++++++++++++++++++++++++++++++++++ drivers/clk/meson/a1-cpu.h | 16 ++ 4 files changed, 351 insertions(+) create mode 100644 drivers/clk/meson/a1-cpu.c create mode 100644 drivers/clk/meson/a1-cpu.h diff --git a/drivers/clk/meson/Kconfig b/drivers/clk/meson/Kconfig index 80c4a18c83d2..148d4495eee3 100644 --- a/drivers/clk/meson/Kconfig +++ b/drivers/clk/meson/Kconfig @@ -111,6 +111,16 @@ config COMMON_CLK_AXG_AUDIO Support for the audio clock controller on AmLogic A113D devices, aka axg, Say Y if you want audio subsystem to work. +config COMMON_CLK_A1_CPU + tristate "Amlogic A1 SoC CPU controller support" + depends on ARM64 + select COMMON_CLK_MESON_REGMAP + select COMMON_CLK_MESON_CLKC_UTILS + help + Support for the CPU clock controller on Amlogic A113L based + device, A1 SoC Family. Say Y if you want A1 CPU clock controller + to work. + config COMMON_CLK_A1_PLL tristate "Amlogic A1 SoC PLL controller support" depends on ARM64 diff --git a/drivers/clk/meson/Makefile b/drivers/clk/meson/Makefile index 4968fc7ad555..2a06eb0303d6 100644 --- a/drivers/clk/meson/Makefile +++ b/drivers/clk/meson/Makefile @@ -18,6 +18,7 @@ obj-$(CONFIG_COMMON_CLK_MESON_AUDIO_RSTC) += meson-audio-rstc.o obj-$(CONFIG_COMMON_CLK_AXG) += axg.o axg-aoclk.o obj-$(CONFIG_COMMON_CLK_AXG_AUDIO) += axg-audio.o +obj-$(CONFIG_COMMON_CLK_A1_CPU) += a1-cpu.o obj-$(CONFIG_COMMON_CLK_A1_PLL) += a1-pll.o obj-$(CONFIG_COMMON_CLK_A1_PERIPHERALS) += a1-peripherals.o obj-$(CONFIG_COMMON_CLK_A1_AUDIO) += a1-audio.o diff --git a/drivers/clk/meson/a1-cpu.c b/drivers/clk/meson/a1-cpu.c new file mode 100644 index 000000000000..5f5d8ae112e5 --- /dev/null +++ b/drivers/clk/meson/a1-cpu.c @@ -0,0 +1,324 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Amlogic A1 SoC family CPU Clock Controller driver. + * + * Copyright (c) 2024, SaluteDevices. All Rights Reserved. + * Author: Dmitry Rokosov + */ + +#include +#include +#include +#include +#include "a1-cpu.h" +#include "clk-regmap.h" +#include "meson-clkc-utils.h" + +#include + +static u32 cpu_fsource_sel_table[] = { 0, 1, 2 }; +static const struct clk_parent_data cpu_fsource_sel_parents[] = { + { .fw_name = "xtal" }, + { .fw_name = "fclk_div2" }, + { .fw_name = "fclk_div3" }, +}; + +static struct clk_regmap cpu_fsource_sel0 = { + .data = &(struct clk_regmap_mux_data) { + .offset = CPUCTRL_CLK_CTRL0, + .mask = 0x3, + .shift = 0, + .table = cpu_fsource_sel_table, + }, + .hw.init = &(struct clk_init_data) { + .name = "cpu_fsource_sel0", + .ops = &clk_regmap_mux_ops, + .parent_data = cpu_fsource_sel_parents, + .num_parents = ARRAY_SIZE(cpu_fsource_sel_parents), + .flags = CLK_SET_RATE_PARENT, + }, +}; + +static struct clk_regmap cpu_fsource_div0 = { + .data = &(struct clk_regmap_div_data) { + .offset = CPUCTRL_CLK_CTRL0, + .shift = 4, + .width = 6, + }, + .hw.init = &(struct clk_init_data) { + .name = "cpu_fsource_div0", + .ops = &clk_regmap_divider_ops, + .parent_hws = (const struct clk_hw *[]) { + &cpu_fsource_sel0.hw + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + }, +}; + +static struct clk_regmap cpu_fsel0 = { + .data = &(struct clk_regmap_mux_data) { + .offset = CPUCTRL_CLK_CTRL0, + .mask = 0x1, + .shift = 2, + }, + .hw.init = &(struct clk_init_data) { + .name = "cpu_fsel0", + .ops = &clk_regmap_mux_ops, + .parent_hws = (const struct clk_hw *[]) { + &cpu_fsource_sel0.hw, + &cpu_fsource_div0.hw, + }, + .num_parents = 2, + .flags = CLK_SET_RATE_PARENT, + }, +}; + +static struct clk_regmap cpu_fsource_sel1 = { + .data = &(struct clk_regmap_mux_data) { + .offset = CPUCTRL_CLK_CTRL0, + .mask = 0x3, + .shift = 16, + .table = cpu_fsource_sel_table, + }, + .hw.init = &(struct clk_init_data) { + .name = "cpu_fsource_sel1", + .ops = &clk_regmap_mux_ops, + .parent_data = cpu_fsource_sel_parents, + .num_parents = ARRAY_SIZE(cpu_fsource_sel_parents), + .flags = CLK_SET_RATE_PARENT, + }, +}; + +static struct clk_regmap cpu_fsource_div1 = { + .data = &(struct clk_regmap_div_data) { + .offset = CPUCTRL_CLK_CTRL0, + .shift = 20, + .width = 6, + }, + .hw.init = &(struct clk_init_data) { + .name = "cpu_fsource_div1", + .ops = &clk_regmap_divider_ops, + .parent_hws = (const struct clk_hw *[]) { + &cpu_fsource_sel1.hw + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + }, +}; + +static struct clk_regmap cpu_fsel1 = { + .data = &(struct clk_regmap_mux_data) { + .offset = CPUCTRL_CLK_CTRL0, + .mask = 0x1, + .shift = 18, + }, + .hw.init = &(struct clk_init_data) { + .name = "cpu_fsel1", + .ops = &clk_regmap_mux_ops, + .parent_hws = (const struct clk_hw *[]) { + &cpu_fsource_sel1.hw, + &cpu_fsource_div1.hw, + }, + .num_parents = 2, + .flags = CLK_SET_RATE_PARENT, + }, +}; + +static struct clk_regmap cpu_fclk = { + .data = &(struct clk_regmap_mux_data) { + .offset = CPUCTRL_CLK_CTRL0, + .mask = 0x1, + .shift = 10, + }, + .hw.init = &(struct clk_init_data) { + .name = "cpu_fclk", + .ops = &clk_regmap_mux_ops, + .parent_hws = (const struct clk_hw *[]) { + &cpu_fsel0.hw, + &cpu_fsel1.hw, + }, + .num_parents = 2, + .flags = CLK_SET_RATE_PARENT, + }, +}; + +static struct clk_regmap cpu_clk = { + .data = &(struct clk_regmap_mux_data) { + .offset = CPUCTRL_CLK_CTRL0, + .mask = 0x1, + .shift = 11, + }, + .hw.init = &(struct clk_init_data) { + .name = "cpu_clk", + .ops = &clk_regmap_mux_ops, + .parent_data = (const struct clk_parent_data []) { + { .hw = &cpu_fclk.hw }, + { .fw_name = "sys_pll", }, + }, + .num_parents = 2, + .flags = CLK_SET_RATE_PARENT | CLK_IS_CRITICAL, + }, +}; + +/* Array of all clocks registered by this provider */ +static struct clk_hw *a1_cpu_hw_clks[] = { + [CLKID_CPU_FSOURCE_SEL0] = &cpu_fsource_sel0.hw, + [CLKID_CPU_FSOURCE_DIV0] = &cpu_fsource_div0.hw, + [CLKID_CPU_FSEL0] = &cpu_fsel0.hw, + [CLKID_CPU_FSOURCE_SEL1] = &cpu_fsource_sel1.hw, + [CLKID_CPU_FSOURCE_DIV1] = &cpu_fsource_div1.hw, + [CLKID_CPU_FSEL1] = &cpu_fsel1.hw, + [CLKID_CPU_FCLK] = &cpu_fclk.hw, + [CLKID_CPU_CLK] = &cpu_clk.hw, +}; + +static struct clk_regmap *const a1_cpu_regmaps[] = { + &cpu_fsource_sel0, + &cpu_fsource_div0, + &cpu_fsel0, + &cpu_fsource_sel1, + &cpu_fsource_div1, + &cpu_fsel1, + &cpu_fclk, + &cpu_clk, +}; + +static struct regmap_config a1_cpu_regmap_cfg = { + .reg_bits = 32, + .val_bits = 32, + .reg_stride = 4, + .max_register = CPUCTRL_CLK_CTRL1, +}; + +static struct meson_clk_hw_data a1_cpu_clks = { + .hws = a1_cpu_hw_clks, + .num = ARRAY_SIZE(a1_cpu_hw_clks), +}; + +struct a1_cpu_clk_nb_data { + const struct clk_ops *mux_ops; + struct clk_hw *cpu_clk; + struct notifier_block nb; + u8 parent; +}; + +#define MESON_A1_CPU_CLK_GET_PARENT(nbd) \ + ((nbd)->mux_ops->get_parent((nbd)->cpu_clk)) +#define MESON_A1_CPU_CLK_SET_PARENT(nbd, index) \ + ((nbd)->mux_ops->set_parent((nbd)->cpu_clk, index)) + +static int meson_a1_cpu_clk_notifier_cb(struct notifier_block *nb, + unsigned long event, void *data) +{ + struct a1_cpu_clk_nb_data *nbd; + int ret = 0; + + nbd = container_of(nb, struct a1_cpu_clk_nb_data, nb); + + switch (event) { + case PRE_RATE_CHANGE: + nbd->parent = MESON_A1_CPU_CLK_GET_PARENT(nbd); + /* Fallback to the CPU fixed clock */ + ret = MESON_A1_CPU_CLK_SET_PARENT(nbd, 0); + /* Wait for clock propagation */ + udelay(100); + break; + + case POST_RATE_CHANGE: + case ABORT_RATE_CHANGE: + /* Back to the original parent clock */ + ret = MESON_A1_CPU_CLK_SET_PARENT(nbd, nbd->parent); + /* Wait for clock propagation */ + udelay(100); + break; + + default: + pr_warn("Unknown event %lu for %s notifier block\n", + event, clk_hw_get_name(nbd->cpu_clk)); + break; + } + + return notifier_from_errno(ret); +} + +static struct a1_cpu_clk_nb_data a1_cpu_clk_nb_data = { + .mux_ops = &clk_regmap_mux_ops, + .cpu_clk = &cpu_clk.hw, + .nb.notifier_call = meson_a1_cpu_clk_notifier_cb, +}; + +static int meson_a1_dvfs_setup(struct platform_device *pdev) +{ + struct device *dev = &pdev->dev; + struct clk *notifier_clk; + int ret; + + /* Setup clock notifier for cpu_clk */ + notifier_clk = devm_clk_hw_get_clk(dev, &cpu_clk.hw, "dvfs"); + if (IS_ERR(notifier_clk)) + return dev_err_probe(dev, PTR_ERR(notifier_clk), + "can't get cpu_clk as notifier clock\n"); + + ret = devm_clk_notifier_register(dev, notifier_clk, + &a1_cpu_clk_nb_data.nb); + if (ret) + return dev_err_probe(dev, ret, + "can't register cpu_clk notifier\n"); + + return ret; +} + +static int meson_a1_cpu_probe(struct platform_device *pdev) +{ + struct device *dev = &pdev->dev; + void __iomem *base; + struct regmap *map; + int clkid, i, err; + + base = devm_platform_ioremap_resource(pdev, 0); + if (IS_ERR(base)) + return dev_err_probe(dev, PTR_ERR(base), + "can't ioremap resource\n"); + + map = devm_regmap_init_mmio(dev, base, &a1_cpu_regmap_cfg); + if (IS_ERR(map)) + return dev_err_probe(dev, PTR_ERR(map), + "can't init regmap mmio region\n"); + + /* Populate regmap for the regmap backed clocks */ + for (i = 0; i < ARRAY_SIZE(a1_cpu_regmaps); i++) + a1_cpu_regmaps[i]->map = map; + + for (clkid = 0; clkid < a1_cpu_clks.num; clkid++) { + err = devm_clk_hw_register(dev, a1_cpu_clks.hws[clkid]); + if (err) + return dev_err_probe(dev, err, + "clock[%d] registration failed\n", + clkid); + } + + err = devm_of_clk_add_hw_provider(dev, meson_clk_hw_get, &a1_cpu_clks); + if (err) + return dev_err_probe(dev, err, "can't add clk hw provider\n"); + + return meson_a1_dvfs_setup(pdev); +} + +static const struct of_device_id a1_cpu_clkc_match_table[] = { + { .compatible = "amlogic,a1-cpu-clkc", }, + {} +}; +MODULE_DEVICE_TABLE(of, a1_cpu_clkc_match_table); + +static struct platform_driver a1_cpu_clkc_driver = { + .probe = meson_a1_cpu_probe, + .driver = { + .name = "a1-cpu-clkc", + .of_match_table = a1_cpu_clkc_match_table, + }, +}; + +module_platform_driver(a1_cpu_clkc_driver); +MODULE_AUTHOR("Dmitry Rokosov "); +MODULE_LICENSE("GPL"); diff --git a/drivers/clk/meson/a1-cpu.h b/drivers/clk/meson/a1-cpu.h new file mode 100644 index 000000000000..e9af4117e26f --- /dev/null +++ b/drivers/clk/meson/a1-cpu.h @@ -0,0 +1,16 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Amlogic A1 CPU Clock Controller internals + * + * Copyright (c) 2024, SaluteDevices. All Rights Reserved. + * Author: Dmitry Rokosov + */ + +#ifndef __A1_CPU_H +#define __A1_CPU_H + +/* cpu clock controller register offset */ +#define CPUCTRL_CLK_CTRL0 0x80 +#define CPUCTRL_CLK_CTRL1 0x84 + +#endif /* __A1_CPU_H */