From patchwork Wed Apr 3 08:04:30 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Atish Kumar Patra X-Patchwork-Id: 13615554 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 587ADCD1294 for ; Wed, 3 Apr 2024 09:19:11 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:MIME-Version:References:In-Reply-To: Message-Id:Date:Subject:Cc:To:From:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; bh=lNehsSTZi9moaj74D7v31T0S23tIywQyShg/HJnLnxo=; b=weHYTB/cmUzzL6 kIpQYfbh4Vq0XkobbWzDw6vIqA9gGRDUPYU+4DkD73U9A1b3fT7zwcLTVujFKnG+O74VPY2otWIuY zyqd0vWuGtEaJ7mgCxhTDS+IaDYX0bqz4LjIQRvfzXN0jn0e/dzwXm91+83sBUaq1nXaOPAVT6kY/ wSrCFc3luGz8nUi2YqL+d5ZOLftrsRNNtIsS8/2h2X02r5lNS0U4VDxRDwCpY9r8cRjaedEzK2B6s aOBYmDQjtB4SABZyk0C//ySFAlddZjd2JEK+LrblRNg84blYiyy4AbinZ7CbIMyX8yYZICsRkehBO k6If9sQu7q7zo33xCpoQ==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.97.1 #2 (Red Hat Linux)) id 1rrwlt-0000000FABI-0Id0; Wed, 03 Apr 2024 09:19:05 +0000 Received: from mail-pl1-x635.google.com ([2607:f8b0:4864:20::635]) by bombadil.infradead.org with esmtps (Exim 4.97.1 #2 (Red Hat Linux)) id 1rrvcR-0000000EiSr-3VVV for linux-riscv@lists.infradead.org; Wed, 03 Apr 2024 08:05:17 +0000 Received: by mail-pl1-x635.google.com with SMTP id d9443c01a7336-1def3340682so52557695ad.1 for ; Wed, 03 Apr 2024 01:05:14 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=rivosinc-com.20230601.gappssmtp.com; s=20230601; t=1712131514; x=1712736314; darn=lists.infradead.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=wk9dPs2pdPMy/ouYyBMSDOPD1OQUOIvovvehkpc98kM=; b=l/XjP9TeO1K8W6Ae4GWTInej9UIotqVE/UjOH+Pm/fXbV4ysmHQM/JOSOBX+bLqRyN 2NXA693+MopfO625QzWYAYqZJguX4G4hl+uUrNuRL1fZ/mJSPzjugeWgOaMvQixnp08E a+dPMOgMeKr400CofT9o+9w25OSGWuJLjSNpMEd8vm8rcgjIlFqlZqN4l5qKIvetDlcB orNull3VmZN0gUA+Y5K4v77z+MJrHB489kBLBxRzGanZHOPaMnTbHytcbxRj0l21Tydc POIzWWnJNmf18reoO+RU0M/GTdepI6Xdd0pfLZhar1847FaJC7RCtWaKbEG772vKz2ye nABA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1712131514; x=1712736314; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=wk9dPs2pdPMy/ouYyBMSDOPD1OQUOIvovvehkpc98kM=; b=D5+GCLPA9HAdWxTGFby/W1DXlBG4gd+k0YwTGzRvtfQgrpB7k3LP93PQmHn4XHdb+o DXiwQRc9vPE2g3E/wNXVLE3aX+LQTFg/x0FFqq0MMcOGd7BFi++UyD6yc0UzuYHw/eb8 3fYA9gQj/hJOEQQFddVoX3CDE/ED0vUv/wRItvm91AtSpvn1VY63LXpsdOTQZbrzt19V E6e5sukAHwvNS04MwJnG/dsWU9PeQ8ZH/9kpmHDy87Y1tycEL4u3KdWk0FwoqQvY89aP EvraYja1vsRVeDd+TTj0+aFSxnwyvsgpxx+3zMfaoiQzWCt2n6S5rnwNspTe00M9ow69 ZVMw== X-Forwarded-Encrypted: i=1; AJvYcCXu6moM+x33k/JEMIhj57LJeZ1z/9h3bGENPpMuHaootd3LQuqlU3H++C9GmlBlMUBP9o2I4hRQbV5/dRES94iUsuLnhg3pmniPRTEH6k6n X-Gm-Message-State: AOJu0Yxkw6GGmeWULz5/AEo4T1gJdZrrtdcaT2PCZV4gDtaBfkebMkS7 58pJDJEy+avYd6nEHZ9OlyioQNpFS5l2hWUl10Q3jbi83maD9hyC7ty+xe0P3Dk= X-Google-Smtp-Source: AGHT+IGJGNXcOyb9YrykwAGNPaYyhw8xhsLdGwuGzUBrwVAzvp1h6eGWJ0tNbKMZggDJyDT4f6wwug== X-Received: by 2002:a17:903:292:b0:1e2:6240:72e7 with SMTP id j18-20020a170903029200b001e2624072e7mr5865569plr.53.1712131513754; Wed, 03 Apr 2024 01:05:13 -0700 (PDT) Received: from atishp.ba.rivosinc.com ([64.71.180.162]) by smtp.gmail.com with ESMTPSA id c12-20020a170902d48c00b001e0b5d49fc7sm12557229plg.161.2024.04.03.01.05.12 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 03 Apr 2024 01:05:13 -0700 (PDT) From: Atish Patra To: linux-kernel@vger.kernel.org Cc: Atish Patra , =?utf-8?b?Q2zDqW1lbnQgTMOpZ2Vy?= , Conor Dooley , Anup Patel , Ajay Kaher , Alexandre Ghiti , Alexey Makhalov , Andrew Jones , Juergen Gross , kvm-riscv@lists.infradead.org, kvm@vger.kernel.org, linux-kselftest@vger.kernel.org, linux-riscv@lists.infradead.org, Mark Rutland , Palmer Dabbelt , Paolo Bonzini , Paul Walmsley , Shuah Khan , virtualization@lists.linux.dev, VMware PV-Drivers Reviewers , Will Deacon , x86@kernel.org Subject: [PATCH v5 01/22] RISC-V: Fix the typo in Scountovf CSR name Date: Wed, 3 Apr 2024 01:04:30 -0700 Message-Id: <20240403080452.1007601-2-atishp@rivosinc.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240403080452.1007601-1-atishp@rivosinc.com> References: <20240403080452.1007601-1-atishp@rivosinc.com> MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20240403_010515_991813_4A80D61A X-CRM114-Status: GOOD ( 11.19 ) X-BeenThere: linux-riscv@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-riscv" Errors-To: linux-riscv-bounces+linux-riscv=archiver.kernel.org@lists.infradead.org The counter overflow CSR name is "scountovf" not "sscountovf". Fix the csr name. Fixes: 4905ec2fb7e6 ("RISC-V: Add sscofpmf extension support") Reviewed-by: Clément Léger Reviewed-by: Conor Dooley Reviewed-by: Anup Patel Signed-off-by: Atish Patra Reviewed-by: Andrew Jones --- arch/riscv/include/asm/csr.h | 2 +- drivers/perf/riscv_pmu_sbi.c | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/arch/riscv/include/asm/csr.h b/arch/riscv/include/asm/csr.h index 2468c55933cd..9d1b07932794 100644 --- a/arch/riscv/include/asm/csr.h +++ b/arch/riscv/include/asm/csr.h @@ -281,7 +281,7 @@ #define CSR_HPMCOUNTER30H 0xc9e #define CSR_HPMCOUNTER31H 0xc9f -#define CSR_SSCOUNTOVF 0xda0 +#define CSR_SCOUNTOVF 0xda0 #define CSR_SSTATUS 0x100 #define CSR_SIE 0x104 diff --git a/drivers/perf/riscv_pmu_sbi.c b/drivers/perf/riscv_pmu_sbi.c index 8cbe6e5f9c39..3e44d2fb8bf8 100644 --- a/drivers/perf/riscv_pmu_sbi.c +++ b/drivers/perf/riscv_pmu_sbi.c @@ -27,7 +27,7 @@ #define ALT_SBI_PMU_OVERFLOW(__ovl) \ asm volatile(ALTERNATIVE_2( \ - "csrr %0, " __stringify(CSR_SSCOUNTOVF), \ + "csrr %0, " __stringify(CSR_SCOUNTOVF), \ "csrr %0, " __stringify(THEAD_C9XX_CSR_SCOUNTEROF), \ THEAD_VENDOR_ID, ERRATA_THEAD_PMU, \ CONFIG_ERRATA_THEAD_PMU, \ From patchwork Wed Apr 3 08:04:31 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Atish Kumar Patra X-Patchwork-Id: 13615556 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id E100BCD1296 for ; Wed, 3 Apr 2024 09:19:11 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:MIME-Version:References:In-Reply-To: Message-Id:Date:Subject:Cc:To:From:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; bh=H1aWHjY3Uo1f+X0HovoUjtD35ls9m8alH1ewJ3R0xr8=; b=Wl9bnoOCLKJmp+ PmQ23H9tmcwZNAuj/voGtUjyxT4PVZ5g2bk/9ZCslTe886n7MY+aUqJK0zZoXrWuoFqyJgz8Bq0R1 zYVk0rh7I5F3b+lsjIMCNnF/ncSYKzAcQXerOuTcR/pgWfpSB0W/juNLi4iUez7qKZ2X5XWXLqgOT 7zYHUXbj5+qD81rd2sq/ZQ2fdwOYhN68jbna10UnXQYa7yy0J5ZbWERvuXf5A8+EMQh2dBeis7O/B sPpQoQmb7cbu4A1XWMaDC4DW10OpcLAn5jvk3OeoJYDqUEgMy+LdGmjxxLw2bi6F07PSr8oVopxah L0HPWKOKQgeMyZSFKoGA==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.97.1 #2 (Red Hat Linux)) id 1rrwlu-0000000FACX-3F7O; Wed, 03 Apr 2024 09:19:06 +0000 Received: from mail-pl1-x633.google.com ([2607:f8b0:4864:20::633]) by bombadil.infradead.org with esmtps (Exim 4.97.1 #2 (Red Hat Linux)) id 1rrvcb-0000000EiUz-3aLh for linux-riscv@lists.infradead.org; Wed, 03 Apr 2024 08:05:27 +0000 Received: by mail-pl1-x633.google.com with SMTP id d9443c01a7336-1e28856ed7aso8286705ad.0 for ; Wed, 03 Apr 2024 01:05:16 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=rivosinc-com.20230601.gappssmtp.com; s=20230601; t=1712131516; x=1712736316; darn=lists.infradead.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=Bc4Qbmx0AoxDu4ditj7xvL7MfGG2VDboL8zvDiTC/bw=; b=OXNwQ7LlRmAl8/ESr5lNv+nu2EJcZwnIZUKFY/Xkie6SYvTwdr3j/wfg9bLh19L4rP OmEFqyBHF46df0qRq2dcsUVO/8oleeZFxplWDxWfwpPpzZsozHvXonTooSgu5nG7hszE ES57Afyqh8tcaaV4CkRjsh05mUqm9L74/fUDmbqHGVIRrUgNysgZFLQGQzOeGyTR/yot j+PHfcaUmeZA9IW9gsoBwJzNyEg5kF6KlDx8viua2juIzXQwXBI4OVNqdfjiUx+eLee/ FVVKh7tMDMcKCx9qWxguUEYThTl8jqL5B2DUEPCZiF5EODPG8oubiI4uDr8eX2pwJjxZ o3Tw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1712131516; x=1712736316; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=Bc4Qbmx0AoxDu4ditj7xvL7MfGG2VDboL8zvDiTC/bw=; b=pzBiyxbF22a4FtVz9blbnQ0VGuJwOWcEZrQsTh7dIQVvgqjcyzY5DGIrOXDkQILhd6 WHEnOxvY7BH7E4UZVDEgvv3doB+SqfL+XKQ6wWJF9DN8ojBLkSCp6/EL35DodGpU2Dr9 8GrOM8foStamCL9wq1p+2LUsxl9mW/mER7sMhnBZIfdD92DU3XidUGecoqHcYceHLSAo 13oL5J1Q/boVtyDSE3l9IBvSo1fXFyr7kaDgcv1wwUaT7V0E2kFiClE0dZs56DxvxZZ0 lkuCtvmhb5OLSRyhIT0I7ZaygtsR4DvvhwuTcAWt5qRyi8sOTGcsvfbqCYQkRB7OsVEr fx2Q== X-Forwarded-Encrypted: i=1; AJvYcCU/TSEACQ5JhXjkl3o5DNYmbvAn8F+GKDxuHq+WYqpoT3ZiiVDhWOy+Rj4kllSoJlEFR3NPVtkvRinpclZQMQuYxad4hqreI9UYif1uoi5Z X-Gm-Message-State: AOJu0YxzgdmDCwNwqtPvCel4wPmHwf7ONttKPwlBRAAIqAAKInw9QmTl m+MPSFtqdo6vquAtbyNlux9h85WrGooUnmOnoctxkFhp2wSFahdmaAGFHHcabfc= X-Google-Smtp-Source: AGHT+IEN9FTCaj0hRotpYu2L3MLNBsnLZyWzCk4MgIL/9u1tPeTTuGgG3qQXqUKuRiVdVxo5cBEIJA== X-Received: by 2002:a17:902:b089:b0:1dd:878d:9dca with SMTP id p9-20020a170902b08900b001dd878d9dcamr1981385plr.48.1712131516075; Wed, 03 Apr 2024 01:05:16 -0700 (PDT) Received: from atishp.ba.rivosinc.com ([64.71.180.162]) by smtp.gmail.com with ESMTPSA id c12-20020a170902d48c00b001e0b5d49fc7sm12557229plg.161.2024.04.03.01.05.13 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 03 Apr 2024 01:05:15 -0700 (PDT) From: Atish Patra To: linux-kernel@vger.kernel.org Cc: Atish Patra , =?utf-8?b?Q2zDqW1lbnQgTMOpZ2Vy?= , Conor Dooley , Anup Patel , Ajay Kaher , Alexandre Ghiti , Alexey Makhalov , Andrew Jones , Juergen Gross , kvm-riscv@lists.infradead.org, kvm@vger.kernel.org, linux-kselftest@vger.kernel.org, linux-riscv@lists.infradead.org, Mark Rutland , Palmer Dabbelt , Paolo Bonzini , Paul Walmsley , Shuah Khan , virtualization@lists.linux.dev, VMware PV-Drivers Reviewers , Will Deacon , x86@kernel.org Subject: [PATCH v5 02/22] RISC-V: Add FIRMWARE_READ_HI definition Date: Wed, 3 Apr 2024 01:04:31 -0700 Message-Id: <20240403080452.1007601-3-atishp@rivosinc.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240403080452.1007601-1-atishp@rivosinc.com> References: <20240403080452.1007601-1-atishp@rivosinc.com> MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20240403_010525_987326_FA0A05C2 X-CRM114-Status: UNSURE ( 9.23 ) X-CRM114-Notice: Please train this message. X-BeenThere: linux-riscv@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-riscv" Errors-To: linux-riscv-bounces+linux-riscv=archiver.kernel.org@lists.infradead.org SBI v2.0 added another function to SBI PMU extension to read the upper bits of a counter with width larger than XLEN. Add the definition for that function. Reviewed-by: Clément Léger Acked-by: Conor Dooley Reviewed-by: Anup Patel Signed-off-by: Atish Patra Reviewed-by: Andrew Jones --- arch/riscv/include/asm/sbi.h | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/riscv/include/asm/sbi.h b/arch/riscv/include/asm/sbi.h index 6e68f8dff76b..ef8311dafb91 100644 --- a/arch/riscv/include/asm/sbi.h +++ b/arch/riscv/include/asm/sbi.h @@ -131,6 +131,7 @@ enum sbi_ext_pmu_fid { SBI_EXT_PMU_COUNTER_START, SBI_EXT_PMU_COUNTER_STOP, SBI_EXT_PMU_COUNTER_FW_READ, + SBI_EXT_PMU_COUNTER_FW_READ_HI, }; union sbi_pmu_ctr_info { From patchwork Wed Apr 3 08:04:32 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Atish Kumar Patra X-Patchwork-Id: 13615557 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 735F7CD1297 for ; Wed, 3 Apr 2024 09:19:12 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:MIME-Version:References:In-Reply-To: Message-Id:Date:Subject:Cc:To:From:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; bh=o59O1CKB6Hrya+YfR9c+c6O1+zfHAbAmnP/TPJRBsYM=; b=3LWZH5og5oam83 rdIqgrgYAqumWUrkC6vRYY4pwkfYu9jk1UC/66e9lWkyBa9U0p/02z7KZtYLli1UdsPysoVn+axWq iWpCU1lPXESBm6dVy8hfiNfQop4Znsgv9CiwgkNjmB1m6OhN+A4jgt2/PNA5YzBbJNo/PHSxmzJ5v uKcZZVDi+NVjKJ8EvGlVseTV6AM6dkZ47z7ZZK2XavScyIEbY1yxfoeSgx6NW6yl7pgvnBbyJlD+L gSekYnDxMhmNkG6HDyDMbjhVTIRvhN/xWs146mKFJ1d/ayhlvha21EirA1qbFDx/HKUvMZs7wscws 7LCN0hfT32BiDOz5fgpw==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.97.1 #2 (Red Hat Linux)) id 1rrwlv-0000000FADA-2i61; Wed, 03 Apr 2024 09:19:07 +0000 Received: from desiato.infradead.org ([2001:8b0:10b:1:d65d:64ff:fe57:4e05]) by bombadil.infradead.org with esmtps (Exim 4.97.1 #2 (Red Hat Linux)) id 1rrvci-0000000EieL-07a7 for linux-riscv@bombadil.infradead.org; Wed, 03 Apr 2024 08:05:32 +0000 DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=infradead.org; s=desiato.20200630; h=Content-Transfer-Encoding:MIME-Version :References:In-Reply-To:Message-Id:Date:Subject:Cc:To:From:Sender:Reply-To: Content-Type:Content-ID:Content-Description; bh=2ukUdwvkRaeQmBPwRJpu6uMxNPU93zNWp+RJiBVsFw4=; b=iyCeihnHE6l9/YvAqSjEPi3YWw qvbUEVURjXo9VN95Ve5FIekXahhbaeO923ClVMBMxW5aEt/4QSaq/zHz/T4g4ASGLFkRNLXGyi00n bDseD9zf83iGS5T5tIa4droFF2jwqNtlhsZklsZ9Mn5OfpxKa5yFcNHM7GA/Sl0IVw1MhhhQ1rAET HL7feresSKqHt4DIs0Y/1nzDUrdJWpUmyluJSQElbnQOBYW+DAZ6CFrBK4mk8SqmNtL+lZjj9fiZd e3zZ2VKgAFjk8DpsuBEadrZAGF5MHoLihmx0vBeAReDWnHd52hMm94+Hu56xltOmvfHFmY7IJ0y0C 7L2TEODg==; Received: from mail-pl1-x62b.google.com ([2607:f8b0:4864:20::62b]) by desiato.infradead.org with esmtps (Exim 4.97.1 #2 (Red Hat Linux)) id 1rrvcX-000000044jz-0uHb for linux-riscv@lists.infradead.org; Wed, 03 Apr 2024 08:05:30 +0000 Received: by mail-pl1-x62b.google.com with SMTP id d9443c01a7336-1e29328289eso2500865ad.0 for ; Wed, 03 Apr 2024 01:05:19 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=rivosinc-com.20230601.gappssmtp.com; s=20230601; t=1712131518; x=1712736318; darn=lists.infradead.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=2ukUdwvkRaeQmBPwRJpu6uMxNPU93zNWp+RJiBVsFw4=; b=o1s3h3XfZDwP3TZfKsxI9qRup2EDYQLh/pBQxocq6GRVpHHcMfMzCG8vtT3tjQAJyS hwkoT5AG5C2fpfZBlogKiB+v0v/RkylF0f2w3HAzzEsPJxfovUCNy3vjT4HZ2Q5Yn3pU ttC0LCJh1RI5erkwQBEQI2CZnIKKiF3gAaY5bcCWVXCMtSCx2vjQCsytSXu1Reflg2iQ TKxRGw/wVoMjWW02+iPWOQh/BjQJk2qTAR8QaOlm+3i9G11x3jBHE/vMRf7IHB77Rx2N XOY+ZLXJPSQeWvklZWx5IDwV3lnjQGKZ61Xyfs24E7tsLA61Opg5grmmeQI8Quc1DoKf 8qKw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1712131518; x=1712736318; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=2ukUdwvkRaeQmBPwRJpu6uMxNPU93zNWp+RJiBVsFw4=; b=mUQQMa1HECqGL5DjNx7f2OGf0GEVkZNOa8v4Iv0i5gcrnmzj67x0t9zGrnJgOiV/IO obVVLTizLl5+t6+X+TEYzvdvVfkUnd5NN1T27p5ufU7vrVyMEWNjJPqJcokk7Ao2vA2O APeoMlRFNgCc3L0UpRPwfV7m0Pr2w0y9oH2+keNhh5xKrVZ+0S/OqtlQ1GQDGU8x0eql HZq9/fa4CbNu6Dmv1YZ8mVejVlP1AYV3pCeoMbGh18UXKameqGil23bLB/hNJ67KKcFY zy/BJYsofEXyT3pbt3V2lT4QJd04cmqeaxnodEzII+8oIPfljdoEB5tfpQ1To2ysY9OH 0yCg== X-Forwarded-Encrypted: i=1; AJvYcCW0UVuL7K8wLvnrSgsY7ex6IGfrjYY+rMoLoxhKxWn53CTgsK3IllnHX6xU94QTgxEbDRg2yhSCwgjFzC936QULTl4hfluUfiHYkM81veN/ X-Gm-Message-State: AOJu0YxieBSW2InK16a7uqE0+nr8h2j+Dyp4uRUUCDQH++mQIlkMyTfB p5WKQvfImnmoJU2dw61vyiGZrvcTJigNgJZGmPx/wA2erPWGhj0mjJLTKoT6ayI= X-Google-Smtp-Source: AGHT+IGzCaqR/FZVf4jG8/W5aRGI+FZChKgtdmsu22b2KjgU9hzL33Vhb0robWHwzAUPtLmResHVWQ== X-Received: by 2002:a17:902:e741:b0:1dc:a605:5435 with SMTP id p1-20020a170902e74100b001dca6055435mr16071106plf.31.1712131518213; Wed, 03 Apr 2024 01:05:18 -0700 (PDT) Received: from atishp.ba.rivosinc.com ([64.71.180.162]) by smtp.gmail.com with ESMTPSA id c12-20020a170902d48c00b001e0b5d49fc7sm12557229plg.161.2024.04.03.01.05.16 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 03 Apr 2024 01:05:17 -0700 (PDT) From: Atish Patra To: linux-kernel@vger.kernel.org Cc: Atish Patra , Andrew Jones , Palmer Dabbelt , Conor Dooley , Anup Patel , Ajay Kaher , Alexandre Ghiti , Alexey Makhalov , Juergen Gross , kvm-riscv@lists.infradead.org, kvm@vger.kernel.org, linux-kselftest@vger.kernel.org, linux-riscv@lists.infradead.org, Mark Rutland , Palmer Dabbelt , Paolo Bonzini , Paul Walmsley , Shuah Khan , virtualization@lists.linux.dev, VMware PV-Drivers Reviewers , Will Deacon , x86@kernel.org Subject: [PATCH v5 03/22] drivers/perf: riscv: Read upper bits of a firmware counter Date: Wed, 3 Apr 2024 01:04:32 -0700 Message-Id: <20240403080452.1007601-4-atishp@rivosinc.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240403080452.1007601-1-atishp@rivosinc.com> References: <20240403080452.1007601-1-atishp@rivosinc.com> MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20240403_090521_565115_7E5DB753 X-CRM114-Status: GOOD ( 15.97 ) X-BeenThere: linux-riscv@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-riscv" Errors-To: linux-riscv-bounces+linux-riscv=archiver.kernel.org@lists.infradead.org SBI v2.0 introduced a explicit function to read the upper 32 bits for any firmware counter width that is longer than 32bits. This is only applicable for RV32 where firmware counter can be 64 bit. Reviewed-by: Andrew Jones Acked-by: Palmer Dabbelt Reviewed-by: Conor Dooley Reviewed-by: Anup Patel Signed-off-by: Atish Patra --- drivers/perf/riscv_pmu_sbi.c | 25 ++++++++++++++++++++----- 1 file changed, 20 insertions(+), 5 deletions(-) diff --git a/drivers/perf/riscv_pmu_sbi.c b/drivers/perf/riscv_pmu_sbi.c index 3e44d2fb8bf8..babf1b9a4dbe 100644 --- a/drivers/perf/riscv_pmu_sbi.c +++ b/drivers/perf/riscv_pmu_sbi.c @@ -57,6 +57,8 @@ asm volatile(ALTERNATIVE( \ PMU_FORMAT_ATTR(event, "config:0-47"); PMU_FORMAT_ATTR(firmware, "config:63"); +static bool sbi_v2_available; + static struct attribute *riscv_arch_formats_attr[] = { &format_attr_event.attr, &format_attr_firmware.attr, @@ -511,19 +513,29 @@ static u64 pmu_sbi_ctr_read(struct perf_event *event) struct hw_perf_event *hwc = &event->hw; int idx = hwc->idx; struct sbiret ret; - union sbi_pmu_ctr_info info; u64 val = 0; + union sbi_pmu_ctr_info info = pmu_ctr_list[idx]; if (pmu_sbi_is_fw_event(event)) { ret = sbi_ecall(SBI_EXT_PMU, SBI_EXT_PMU_COUNTER_FW_READ, hwc->idx, 0, 0, 0, 0, 0); - if (!ret.error) - val = ret.value; + if (ret.error) + return 0; + + val = ret.value; + if (IS_ENABLED(CONFIG_32BIT) && sbi_v2_available && info.width >= 32) { + ret = sbi_ecall(SBI_EXT_PMU, SBI_EXT_PMU_COUNTER_FW_READ_HI, + hwc->idx, 0, 0, 0, 0, 0); + if (!ret.error) + val |= ((u64)ret.value << 32); + else + WARN_ONCE(1, "Unable to read upper 32 bits of firmware counter error: %d\n", + sbi_err_map_linux_errno(ret.error)); + } } else { - info = pmu_ctr_list[idx]; val = riscv_pmu_ctr_read_csr(info.csr); if (IS_ENABLED(CONFIG_32BIT)) - val = ((u64)riscv_pmu_ctr_read_csr(info.csr + 0x80)) << 31 | val; + val |= ((u64)riscv_pmu_ctr_read_csr(info.csr + 0x80)) << 32; } return val; @@ -1135,6 +1147,9 @@ static int __init pmu_sbi_devinit(void) return 0; } + if (sbi_spec_version >= sbi_mk_version(2, 0)) + sbi_v2_available = true; + ret = cpuhp_setup_state_multi(CPUHP_AP_PERF_RISCV_STARTING, "perf/riscv/pmu:starting", pmu_sbi_starting_cpu, pmu_sbi_dying_cpu); From patchwork Wed Apr 3 08:04:33 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Atish Kumar Patra X-Patchwork-Id: 13615558 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 265FACD1288 for ; Wed, 3 Apr 2024 09:19:15 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:MIME-Version:References:In-Reply-To: Message-Id:Date:Subject:Cc:To:From:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; bh=UMOyXlQdfo4kNo5W6gjoJ8FxXZ1boH+L+DghlcLkgJM=; b=TeLcOtZL+wzuY7 cW2I8NMbqqm5+e934iOSUCst42Qk8vguxg+8Ecym/2I7S6VeUycnwWH4eHb67qFCySsxQnCRMpLDD /OinNlnhcJMudEf3pO6wvyhvAaKVLsWaJL7FLqZWv/J1fKxYZ1FZ4cVMu2syo++utYdSLmPpMFjhg 2MWcxgRaQnms08VYvZWeM7M9D7aLqdGf9FlM80Rvjpa/cYs6y/4KZnyABklVXQnm1VynN6hJUrJen no6pgxCwGWK9pz9H2jLfNg2Zp3l8/e1rSQx30Ze7yDx8Ymg6G7gfitvaxqTMOm9gfp98t8LaPL2nd wP9SD7U3cm8xQS4op0PA==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.97.1 #2 (Red Hat Linux)) id 1rrwlx-0000000FAEA-1Pz2; Wed, 03 Apr 2024 09:19:09 +0000 Received: from casper.infradead.org ([2001:8b0:10b:1236::1]) by bombadil.infradead.org with esmtps (Exim 4.97.1 #2 (Red Hat Linux)) id 1rrvci-0000000Eief-3aqx for linux-riscv@bombadil.infradead.org; Wed, 03 Apr 2024 08:05:32 +0000 DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=infradead.org; s=casper.20170209; h=Content-Transfer-Encoding:MIME-Version: References:In-Reply-To:Message-Id:Date:Subject:Cc:To:From:Sender:Reply-To: Content-Type:Content-ID:Content-Description; bh=Ixjc/2duOe8tMNsDFapztE6WZpMRR0IqMx2Riyo3ljE=; b=M7K05KuRjuFwVS2jErIyv7IfaV l9hET2zsPs/BYeb9R90b7e5fRLv8pXKBK/J9HIqJyT25kVsNp9DDZIwBxIkH+FmGdrb3Kpa7eFU8O J0VMMgXhQ7NrzWTGO/Q9433XKjzN8IqXxCuXipFvfqIg8ECxHnB8enEjk+bWiqaC2OPmIkZP0wkCs XFATFcVMJYVKeHtg72NyklUTRbD7c1FefdhpG9QG21sGyhjeUaE5KsmuIAxN77PzTNsQ2PyEjYBjq ZUsVecL7c+qSECD664xhxhshoE3G6SKZYx3EY+e70bDPZKY8/FY2mGQpfO+rO+ZD9Rz/pHTrY5JQW GMG1WWSw==; Received: from mail-pl1-x62d.google.com ([2607:f8b0:4864:20::62d]) by casper.infradead.org with esmtps (Exim 4.97.1 #2 (Red Hat Linux)) id 1rrvcc-000000055aU-1vJ1 for linux-riscv@lists.infradead.org; Wed, 03 Apr 2024 08:05:31 +0000 Received: by mail-pl1-x62d.google.com with SMTP id d9443c01a7336-1e0bfc42783so51159635ad.0 for ; Wed, 03 Apr 2024 01:05:24 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=rivosinc-com.20230601.gappssmtp.com; s=20230601; t=1712131520; x=1712736320; darn=lists.infradead.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=Ixjc/2duOe8tMNsDFapztE6WZpMRR0IqMx2Riyo3ljE=; b=G0ohviLEEgf8tDNO3f33IBySIf0w76rtSPWvnlkaIKHUn3CGMSFjPS8cdkkpBp4guZ qFeGXxnZlamNA5r9nHpviI0WWSRRpEBBdA9Z50iH8YHENNfbFGDRNoydV8f9Fm1pNUoh INJfR4kpHcHF24yfG9xU/T03TzycQFb+uCfqu7hkUgdQ65U5WXy5iFYucvG9LjvPoQKc T7wvwVwYc4tu7GyNI2uxIOHCNk+tpEneEa6+IFHhz2U63fHQKqwpZNfnhXhZll9iHCF7 4q9lP0FVtZyE5Wn9fsaBsVlkHZCqbb+cLd5HmCp0IyIXyHAyMkkRiSWAd9coedKVPAJq W+tQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1712131520; x=1712736320; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=Ixjc/2duOe8tMNsDFapztE6WZpMRR0IqMx2Riyo3ljE=; b=kdJAeFDhYZ1nFe3oiy/6n+4HJpH+DfDnXqgr34cK8HpPAZ+aZdMJU0aurelSO85mHr WgEmLpbwRd4X4VxsaJitNSLH4teiW+dLXigNhzbgucS4no6OmwT/PfyN7CyacVbFYAhV V4p1hWe9pNgOO3K/Au5bA1EGYVoRzlKaa1WAtpwc/g2sWHiRdS8kXFQbVukfOr65X2zc xE3T8FYlfWDu5Im6FoV0kI2b+n1yK74Ebs+oMz6OLE4GrtkZAaWtsw7ApC1fW/tCbQOC YQVSx+XWiH1cz5Tg5oBNH7BmZo16V7E5Hkroh5m+yj5H2799iBFj+1CBIWtld+HtY7Gt KmGA== X-Forwarded-Encrypted: i=1; AJvYcCVaz35TAcbJsTUFJJgfcfCgxBbEq7od+SbGuhjrBAFYnm88jM2L0JSO3PwUCgD1Z3V3RoMM6GF3hFixKZYvxRIBeKxTufCOo8N578iyZTfw X-Gm-Message-State: AOJu0YysweAxAI2iLJUW4wuRQOVaeAfKUj8IRLa8VBk3pw06Wwkg4Zq8 aBBkDuq24apKvvNoiLM3SihVvqj7Vz6tSDID7WnYq9sPatYsKnXx6t+dBg461n4= X-Google-Smtp-Source: AGHT+IFNP2TORKh7//FzhNMEZN9MBNitQSqhLOnah919WVqeHY+e2MYv0jsRIRUc8mtVSGHiLEDhcg== X-Received: by 2002:a17:902:b701:b0:1e0:a1c7:56fd with SMTP id d1-20020a170902b70100b001e0a1c756fdmr13300312pls.61.1712131520248; Wed, 03 Apr 2024 01:05:20 -0700 (PDT) Received: from atishp.ba.rivosinc.com ([64.71.180.162]) by smtp.gmail.com with ESMTPSA id c12-20020a170902d48c00b001e0b5d49fc7sm12557229plg.161.2024.04.03.01.05.18 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 03 Apr 2024 01:05:19 -0700 (PDT) From: Atish Patra To: linux-kernel@vger.kernel.org Cc: Atish Patra , Ajay Kaher , Alexandre Ghiti , Alexey Makhalov , Andrew Jones , Anup Patel , Conor Dooley , Juergen Gross , kvm-riscv@lists.infradead.org, kvm@vger.kernel.org, linux-kselftest@vger.kernel.org, linux-riscv@lists.infradead.org, Mark Rutland , Palmer Dabbelt , Paolo Bonzini , Paul Walmsley , Shuah Khan , virtualization@lists.linux.dev, VMware PV-Drivers Reviewers , Will Deacon , x86@kernel.org Subject: [PATCH v5 04/22] drivers/perf: riscv: Use BIT macro for shifting operations Date: Wed, 3 Apr 2024 01:04:33 -0700 Message-Id: <20240403080452.1007601-5-atishp@rivosinc.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240403080452.1007601-1-atishp@rivosinc.com> References: <20240403080452.1007601-1-atishp@rivosinc.com> MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20240403_090526_550237_8B0D3CD6 X-CRM114-Status: UNSURE ( 9.78 ) X-CRM114-Notice: Please train this message. X-BeenThere: linux-riscv@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-riscv" Errors-To: linux-riscv-bounces+linux-riscv=archiver.kernel.org@lists.infradead.org It is a good practice to use BIT() instead of (1UL << x). Replace the current usages with BIT(). Signed-off-by: Atish Patra Reviewed-by: Andrew Jones --- arch/riscv/include/asm/sbi.h | 20 ++++++++++---------- drivers/perf/riscv_pmu_sbi.c | 2 +- 2 files changed, 11 insertions(+), 11 deletions(-) diff --git a/arch/riscv/include/asm/sbi.h b/arch/riscv/include/asm/sbi.h index ef8311dafb91..4afa2cd01bae 100644 --- a/arch/riscv/include/asm/sbi.h +++ b/arch/riscv/include/asm/sbi.h @@ -233,20 +233,20 @@ enum sbi_pmu_ctr_type { #define SBI_PMU_EVENT_IDX_INVALID 0xFFFFFFFF /* Flags defined for config matching function */ -#define SBI_PMU_CFG_FLAG_SKIP_MATCH (1 << 0) -#define SBI_PMU_CFG_FLAG_CLEAR_VALUE (1 << 1) -#define SBI_PMU_CFG_FLAG_AUTO_START (1 << 2) -#define SBI_PMU_CFG_FLAG_SET_VUINH (1 << 3) -#define SBI_PMU_CFG_FLAG_SET_VSINH (1 << 4) -#define SBI_PMU_CFG_FLAG_SET_UINH (1 << 5) -#define SBI_PMU_CFG_FLAG_SET_SINH (1 << 6) -#define SBI_PMU_CFG_FLAG_SET_MINH (1 << 7) +#define SBI_PMU_CFG_FLAG_SKIP_MATCH BIT(0) +#define SBI_PMU_CFG_FLAG_CLEAR_VALUE BIT(1) +#define SBI_PMU_CFG_FLAG_AUTO_START BIT(2) +#define SBI_PMU_CFG_FLAG_SET_VUINH BIT(3) +#define SBI_PMU_CFG_FLAG_SET_VSINH BIT(4) +#define SBI_PMU_CFG_FLAG_SET_UINH BIT(5) +#define SBI_PMU_CFG_FLAG_SET_SINH BIT(6) +#define SBI_PMU_CFG_FLAG_SET_MINH BIT(7) /* Flags defined for counter start function */ -#define SBI_PMU_START_FLAG_SET_INIT_VALUE (1 << 0) +#define SBI_PMU_START_FLAG_SET_INIT_VALUE BIT(0) /* Flags defined for counter stop function */ -#define SBI_PMU_STOP_FLAG_RESET (1 << 0) +#define SBI_PMU_STOP_FLAG_RESET BIT(0) enum sbi_ext_dbcn_fid { SBI_EXT_DBCN_CONSOLE_WRITE = 0, diff --git a/drivers/perf/riscv_pmu_sbi.c b/drivers/perf/riscv_pmu_sbi.c index babf1b9a4dbe..a83ae82301e3 100644 --- a/drivers/perf/riscv_pmu_sbi.c +++ b/drivers/perf/riscv_pmu_sbi.c @@ -386,7 +386,7 @@ static int pmu_sbi_ctr_get_idx(struct perf_event *event) cmask = 1; } else if (event->attr.config == PERF_COUNT_HW_INSTRUCTIONS) { cflags |= SBI_PMU_CFG_FLAG_SKIP_MATCH; - cmask = 1UL << (CSR_INSTRET - CSR_CYCLE); + cmask = BIT(CSR_INSTRET - CSR_CYCLE); } } From patchwork Wed Apr 3 08:04:34 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Atish Kumar Patra X-Patchwork-Id: 13615251 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 4A08FC6FD1F for ; Wed, 3 Apr 2024 08:05:39 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:MIME-Version:References:In-Reply-To: Message-Id:Date:Subject:Cc:To:From:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; bh=taAv8F01lunIW/cYAq+3ujz36MHueuWelu8fFu0Vgp4=; b=x9slT7QvV5FevM yGBTnjDYfJ9UVpLAx7nni/d+HZ9u8cd/gYQ1Y2eunqUWZbPFL/koBhlTf3rdxi0UyhpmL9jRcXidm 3qXYaZkjKqzKTygMiXkE3yFRkaMFzkihNePvEH2hJR7r1ijpVqgcdrP4i6vCQNW62B25h5e3UZMBQ jFi05rbO+tXR/LVe884KknLkRqz47Qj2CzN0KB0Cvsjxd4oE5Cr5bKtvXlFycIIb40kOEepkKkjxZ OmxZDoaz2dyyYUOSy3c6s1Ngb93v99wjSXuBsVDRVG7iZgvDQ+6R+eZqhKp9YM+tDxfNiz8thoG1f uls6JaKqfZX/8a1am5wA==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.97.1 #2 (Red Hat Linux)) id 1rrvcj-0000000Eifh-27VN; Wed, 03 Apr 2024 08:05:33 +0000 Received: from mail-pl1-x62c.google.com ([2607:f8b0:4864:20::62c]) by bombadil.infradead.org with esmtps (Exim 4.97.1 #2 (Red Hat Linux)) id 1rrvcc-0000000EiXn-2hTC for linux-riscv@lists.infradead.org; Wed, 03 Apr 2024 08:05:31 +0000 Received: by mail-pl1-x62c.google.com with SMTP id d9443c01a7336-1e267238375so5039175ad.1 for ; Wed, 03 Apr 2024 01:05:24 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=rivosinc-com.20230601.gappssmtp.com; s=20230601; t=1712131524; x=1712736324; darn=lists.infradead.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=2cY+c1Et8e4Cu0t4snI2MWrn2141KaT0UNrXkfFbuJA=; b=upLhoxyZIdpIf4Ctum6bUwXyk+NSnE+fk3ldx6H73jCLymigLCvmOanSrzaiZSbICj YcmqkLKhgt6H8BRmnK11NJmOnj0L05VKSnyuDYu7eD8YPiTPMpmBU2TGWjCZ1aIomQPs 7PrW5GyjB8Xiu01fYpkn5MA3uKc4j4JBV+GHCNU4OrxebPygUx1D4XtmRhHJ2l8ZpGae id/gRNSurTVOvsn2cuecgy4DGHiuCugZBYcPxSTf5rg9YqNOwVjei1re9svMiKenqfZp TUuBEtlj7fpIUQbv/y2QIX1FS1JGrh9lUFtTNjfv3ctfm74K/upwiNO0zLjk3LxZbMPV OarA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1712131524; x=1712736324; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=2cY+c1Et8e4Cu0t4snI2MWrn2141KaT0UNrXkfFbuJA=; b=ogPSJUrh9K68iabLbIYJEquj8HHIJ9A4bXx4zFcTKJjwbDxeMI/tCugxRUcoe5CBo9 BFT4REr38rYQWkliTrMN2NnViRBiGcmsGSGADye3ysK5xdTD/oXVr7vKFthAKKAdaXpl phDniQ07Gy5/vyz8/Z9g9fVhmN5iornLrjBdgKUxUMQTQI2yLwmRY9kv8oFlZIaspIi4 TM67Iu3QF+d7UJCkLjLlxaWPTkBa33O4a+7CjSktTOHJhN/D59Yq0jTiAjuyPiq+MyQK JN1hTHx5maeFaImpaDfoD/rWlk01gBTbYH7A4ygZIPH/keIwVr7nHvi6KrTvbfJLi/4O Kfug== X-Forwarded-Encrypted: i=1; AJvYcCXoTN3zSuzhTn88FuvfCKZ1GlTHBpaJgk9gk4Om7XIvowK/zk9rvy2qjS5YX2TOnjcMz21xUlLQPXByO05xAcds59M6q0JfBi946+ke1O85 X-Gm-Message-State: AOJu0YzypZfQ5/2sXhIuqNOlY4APm7i5CDBGvr63eszuYbOw6zpKqx+/ j6X1kYFh/yVpfYGM9CL9N1rlcxNgH6vC/914A3xNWuIbYIVaDO0Rk1NNi7lA40Y= X-Google-Smtp-Source: AGHT+IFKoJgtWxPYCEvG4otnYA6GehE6Ju467AMTWra/Y4iLfyYQ+vCfm0Zt2yPKMvFR+PhSvC1EhQ== X-Received: by 2002:a17:902:c412:b0:1de:fdf2:b483 with SMTP id k18-20020a170902c41200b001defdf2b483mr2836035plk.8.1712131524245; Wed, 03 Apr 2024 01:05:24 -0700 (PDT) Received: from atishp.ba.rivosinc.com ([64.71.180.162]) by smtp.gmail.com with ESMTPSA id c12-20020a170902d48c00b001e0b5d49fc7sm12557229plg.161.2024.04.03.01.05.20 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 03 Apr 2024 01:05:22 -0700 (PDT) From: Atish Patra To: linux-kernel@vger.kernel.org Cc: Atish Patra , Anup Patel , Palmer Dabbelt , Ajay Kaher , Alexandre Ghiti , Alexey Makhalov , Andrew Jones , Conor Dooley , Juergen Gross , kvm-riscv@lists.infradead.org, kvm@vger.kernel.org, linux-kselftest@vger.kernel.org, linux-riscv@lists.infradead.org, Mark Rutland , Palmer Dabbelt , Paolo Bonzini , Paul Walmsley , Shuah Khan , virtualization@lists.linux.dev, VMware PV-Drivers Reviewers , Will Deacon , x86@kernel.org Subject: [PATCH v5 05/22] RISC-V: Add SBI PMU snapshot definitions Date: Wed, 3 Apr 2024 01:04:34 -0700 Message-Id: <20240403080452.1007601-6-atishp@rivosinc.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240403080452.1007601-1-atishp@rivosinc.com> References: <20240403080452.1007601-1-atishp@rivosinc.com> MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20240403_010527_947498_B3826EEC X-CRM114-Status: GOOD ( 11.63 ) X-BeenThere: linux-riscv@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-riscv" Errors-To: linux-riscv-bounces+linux-riscv=archiver.kernel.org@lists.infradead.org SBI PMU Snapshot function optimizes the number of traps to higher privilege mode by leveraging a shared memory between the S/VS-mode and the M/HS mode. Add the definitions for that extension and new error codes. Reviewed-by: Anup Patel Acked-by: Palmer Dabbelt Signed-off-by: Atish Patra Reviewed-by: Andrew Jones --- arch/riscv/include/asm/sbi.h | 11 +++++++++++ 1 file changed, 11 insertions(+) diff --git a/arch/riscv/include/asm/sbi.h b/arch/riscv/include/asm/sbi.h index 4afa2cd01bae..9aada4b9f7b5 100644 --- a/arch/riscv/include/asm/sbi.h +++ b/arch/riscv/include/asm/sbi.h @@ -132,6 +132,7 @@ enum sbi_ext_pmu_fid { SBI_EXT_PMU_COUNTER_STOP, SBI_EXT_PMU_COUNTER_FW_READ, SBI_EXT_PMU_COUNTER_FW_READ_HI, + SBI_EXT_PMU_SNAPSHOT_SET_SHMEM, }; union sbi_pmu_ctr_info { @@ -148,6 +149,13 @@ union sbi_pmu_ctr_info { }; }; +/* Data structure to contain the pmu snapshot data */ +struct riscv_pmu_snapshot_data { + u64 ctr_overflow_mask; + u64 ctr_values[64]; + u64 reserved[447]; +}; + #define RISCV_PMU_RAW_EVENT_MASK GENMASK_ULL(47, 0) #define RISCV_PMU_RAW_EVENT_IDX 0x20000 @@ -244,9 +252,11 @@ enum sbi_pmu_ctr_type { /* Flags defined for counter start function */ #define SBI_PMU_START_FLAG_SET_INIT_VALUE BIT(0) +#define SBI_PMU_START_FLAG_INIT_SNAPSHOT BIT(1) /* Flags defined for counter stop function */ #define SBI_PMU_STOP_FLAG_RESET BIT(0) +#define SBI_PMU_STOP_FLAG_TAKE_SNAPSHOT BIT(1) enum sbi_ext_dbcn_fid { SBI_EXT_DBCN_CONSOLE_WRITE = 0, @@ -285,6 +295,7 @@ struct sbi_sta_struct { #define SBI_ERR_ALREADY_AVAILABLE -6 #define SBI_ERR_ALREADY_STARTED -7 #define SBI_ERR_ALREADY_STOPPED -8 +#define SBI_ERR_NO_SHMEM -9 extern unsigned long sbi_spec_version; struct sbiret { From patchwork Wed Apr 3 08:04:35 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Atish Kumar Patra X-Patchwork-Id: 13615774 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 2CE45CD128A for ; Wed, 3 Apr 2024 10:34:12 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:MIME-Version:References:In-Reply-To: Message-Id:Date:Subject:Cc:To:From:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; bh=/2XrmMQEkeh+D2HKFkjKIWNemUR7Ni6ThrChS0MfbG4=; b=FTK1vaLSPykEk7 4bGg4cqf/+Ux2GBkpTczKi1nz3oJoBh4hMlVUJhF0tYoMYzQ7ozxeBiFTZUZQYIFBG7BjduFQSusF fM2+Qeuna6AwsYIhbuQqt62rfuf+fTlLrryG30D/otXPJtdkG3MJox/u+tYZHRTRPdNfPS+HOK7Ew qgsuQh4e0h8yvdcwHdKQWq9hY5FARFKTr0BB4F6MYftDfoOvu4veelOe/wftgrY9b6PdjYhdRRL6d M3m1asUtssqXHfYpGoflRFH78nWttLVg2w7/3xGn9cxoLcLvPO/aM1UfaMJWTa2RiT3hl35AC+g/u s8nEN0rh/nRgYFtsoQlw==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.97.1 #2 (Red Hat Linux)) id 1rrxwU-0000000FYKw-0MKP; Wed, 03 Apr 2024 10:34:06 +0000 Received: from casper.infradead.org ([2001:8b0:10b:1236::1]) by bombadil.infradead.org with esmtps (Exim 4.97.1 #2 (Red Hat Linux)) id 1rrvcn-0000000EiiO-0HNh for linux-riscv@bombadil.infradead.org; Wed, 03 Apr 2024 08:05:37 +0000 DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=infradead.org; s=casper.20170209; h=Content-Transfer-Encoding:MIME-Version: References:In-Reply-To:Message-Id:Date:Subject:Cc:To:From:Sender:Reply-To: Content-Type:Content-ID:Content-Description; bh=fy/HVfkL9/BXnOczniC04Qwl03af3PzLwP7P+h0XO80=; b=RqavgaL3uFTukxDgAEnNvfcDtB 0MOGAAyH94i5W3999a52wjhLaxgpLoEvnvSO49fG/zS3FpBbJHpTqzG3lrITRPB+mmhLnc54eJvlt b81O6U6TQ044qlaS6Yz4HRha3J7nUVk/dOu9/6ua1edgQxMSTyakC+O5ABwgN3PdC/fXcRrNtGpgk zzB55bLQneGM9HKM75KNzgiG9eRh0su7VsqGO1NefnTWbVLEVonxSIik4bzbKBi77l/GXar/uV+9/ HNo7ZVafEitCT3ddddlpWsRdVQQ7qnZFrot9XP/8HIdfVmaZUaxYUDGOsIvGcDXerRkyvodnqxMPm xyHXdqXg==; Received: from mail-pl1-x629.google.com ([2607:f8b0:4864:20::629]) by casper.infradead.org with esmtps (Exim 4.97.1 #2 (Red Hat Linux)) id 1rrvcf-000000055bE-2UZX for linux-riscv@lists.infradead.org; Wed, 03 Apr 2024 08:05:35 +0000 Received: by mail-pl1-x629.google.com with SMTP id d9443c01a7336-1e27c303573so11560355ad.3 for ; Wed, 03 Apr 2024 01:05:29 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=rivosinc-com.20230601.gappssmtp.com; s=20230601; t=1712131526; x=1712736326; darn=lists.infradead.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=fy/HVfkL9/BXnOczniC04Qwl03af3PzLwP7P+h0XO80=; b=uvYOVb8fXjgor08bnqXz7QscK9O5SKgCAVQMZonRBWitOU9rNp+YxtnzuCTBv2DUiC e9Ab6BUMAVIt8gnNJbbNZO9b3BZBL3lkfIHVyKM85AJYQeivBbyHLxgh6MVSVT8BX1ov DALLGQlt1TINtBKC4tIuPw2tkC8dFScTMtRExn6uanVImzluAtIJtjO7M3hxm8rUJeWH dNQwmtUlBOmr6ucnS5UvqXaUh3LI/BOt8uaFe698FFEVJdvXpGcftEHFHmDK+OTHABgF JVnHr6ypazBwvh0McQHeaAYrlQFxvxTPmckhEcQDQMh4znVMmttnpW2PzNN/LJbHdeEU cjaA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1712131526; x=1712736326; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=fy/HVfkL9/BXnOczniC04Qwl03af3PzLwP7P+h0XO80=; b=jAtfc/9soAqCgqmi69jcy/K+DcN6bO/VKYgBXVn7voURALv1CA3sMap7WT/r7zYWFv 2mkCCfQcwTv9iTY+bp80zERWoMUks5I11GcVA9xLRseypvh2KKFYHHhpA5YmWDTDwcho b7oQd59tGFZ0JTTPcty8IMRx2jwiDC7VUKnai5fja29zY43FbpMens0lNXuB//s11bxG MFmWVWxcwvqcSItmYbuNWiH+5b/ws9KgHz/6IrPgtcGGjXa3MjuK87hzyjtv8FojYV45 SqpCQTpjTJJ/D/aXP6rZE+/SgkINz8ZNRRpwDD5E4FQm6tMWtyJkYEhFGkGS0CaRKTrM hOpQ== X-Forwarded-Encrypted: i=1; AJvYcCVNR9p6Ou7k46tVTTFDiPTDWJaZTI30LagmrhvNuaNtTxAyBG8McNefdVz3bZTELDatN+iaqiSKkv4nwXFf0NpONg3Y0/P2wMHmUrNLF2ZL X-Gm-Message-State: AOJu0YyvKl+yVlOmXR1mOG2zREoA94P0xe/a9YZHvDclBV15AK047y2P BGTTPjXakImsS5nW9A8hIjXpy2YSmgOonpIdyOl+aCWG8B15GDIkxgx/b+yXhJc= X-Google-Smtp-Source: AGHT+IHx7Qx+ILTKaOpBzWSewlWwQIWzzEUfidMKA5sGbjy/wjDwFOC4pIF0Hh3Hy6z59AOf6brM7A== X-Received: by 2002:a17:902:c94e:b0:1e2:9945:dff with SMTP id i14-20020a170902c94e00b001e299450dffmr364388pla.2.1712131525791; Wed, 03 Apr 2024 01:05:25 -0700 (PDT) Received: from atishp.ba.rivosinc.com ([64.71.180.162]) by smtp.gmail.com with ESMTPSA id c12-20020a170902d48c00b001e0b5d49fc7sm12557229plg.161.2024.04.03.01.05.24 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 03 Apr 2024 01:05:25 -0700 (PDT) From: Atish Patra To: linux-kernel@vger.kernel.org Cc: Atish Patra , Palmer Dabbelt , Anup Patel , Conor Dooley , Ajay Kaher , Alexandre Ghiti , Alexey Makhalov , Andrew Jones , Juergen Gross , kvm-riscv@lists.infradead.org, kvm@vger.kernel.org, linux-kselftest@vger.kernel.org, linux-riscv@lists.infradead.org, Mark Rutland , Palmer Dabbelt , Paolo Bonzini , Paul Walmsley , Shuah Khan , virtualization@lists.linux.dev, VMware PV-Drivers Reviewers , Will Deacon , x86@kernel.org Subject: [PATCH v5 06/22] drivers/perf: riscv: Implement SBI PMU snapshot function Date: Wed, 3 Apr 2024 01:04:35 -0700 Message-Id: <20240403080452.1007601-7-atishp@rivosinc.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240403080452.1007601-1-atishp@rivosinc.com> References: <20240403080452.1007601-1-atishp@rivosinc.com> MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20240403_090529_677448_8A085494 X-CRM114-Status: GOOD ( 28.89 ) X-BeenThere: linux-riscv@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-riscv" Errors-To: linux-riscv-bounces+linux-riscv=archiver.kernel.org@lists.infradead.org SBI v2.0 SBI introduced PMU snapshot feature which adds the following features. 1. Read counter values directly from the shared memory instead of csr read. 2. Start multiple counters with initial values with one SBI call. These functionalities optimizes the number of traps to the higher privilege mode. If the kernel is in VS mode while the hypervisor deploy trap & emulate method, this would minimize all the hpmcounter CSR read traps. If the kernel is running in S-mode, the benefits reduced to CSR latency vs DRAM/cache latency as there is no trap involved while accessing the hpmcounter CSRs. In both modes, it does saves the number of ecalls while starting multiple counter together with an initial values. This is a likely scenario if multiple counters overflow at the same time. Acked-by: Palmer Dabbelt Reviewed-by: Anup Patel Reviewed-by: Conor Dooley Signed-off-by: Atish Patra --- drivers/perf/riscv_pmu.c | 1 + drivers/perf/riscv_pmu_sbi.c | 216 +++++++++++++++++++++++++++++++-- include/linux/perf/riscv_pmu.h | 6 + 3 files changed, 211 insertions(+), 12 deletions(-) diff --git a/drivers/perf/riscv_pmu.c b/drivers/perf/riscv_pmu.c index c78a6fd6c57f..3a941b2c3888 100644 --- a/drivers/perf/riscv_pmu.c +++ b/drivers/perf/riscv_pmu.c @@ -404,6 +404,7 @@ struct riscv_pmu *riscv_pmu_alloc(void) cpuc->n_events = 0; for (i = 0; i < RISCV_MAX_COUNTERS; i++) cpuc->events[i] = NULL; + cpuc->snapshot_addr = NULL; } pmu->pmu = (struct pmu) { .event_init = riscv_pmu_event_init, diff --git a/drivers/perf/riscv_pmu_sbi.c b/drivers/perf/riscv_pmu_sbi.c index a83ae82301e3..8c3475d55433 100644 --- a/drivers/perf/riscv_pmu_sbi.c +++ b/drivers/perf/riscv_pmu_sbi.c @@ -58,6 +58,9 @@ PMU_FORMAT_ATTR(event, "config:0-47"); PMU_FORMAT_ATTR(firmware, "config:63"); static bool sbi_v2_available; +static DEFINE_STATIC_KEY_FALSE(sbi_pmu_snapshot_available); +#define sbi_pmu_snapshot_available() \ + static_branch_unlikely(&sbi_pmu_snapshot_available) static struct attribute *riscv_arch_formats_attr[] = { &format_attr_event.attr, @@ -508,14 +511,108 @@ static int pmu_sbi_event_map(struct perf_event *event, u64 *econfig) return ret; } +static void pmu_sbi_snapshot_free(struct riscv_pmu *pmu) +{ + int cpu; + + for_each_possible_cpu(cpu) { + struct cpu_hw_events *cpu_hw_evt = per_cpu_ptr(pmu->hw_events, cpu); + + if (!cpu_hw_evt->snapshot_addr) + continue; + + free_page((unsigned long)cpu_hw_evt->snapshot_addr); + cpu_hw_evt->snapshot_addr = NULL; + cpu_hw_evt->snapshot_addr_phys = 0; + } +} + +static int pmu_sbi_snapshot_alloc(struct riscv_pmu *pmu) +{ + int cpu; + struct page *snapshot_page; + + for_each_possible_cpu(cpu) { + struct cpu_hw_events *cpu_hw_evt = per_cpu_ptr(pmu->hw_events, cpu); + + if (cpu_hw_evt->snapshot_addr) + continue; + + snapshot_page = alloc_page(GFP_ATOMIC | __GFP_ZERO); + if (!snapshot_page) { + pmu_sbi_snapshot_free(pmu); + return -ENOMEM; + } + cpu_hw_evt->snapshot_addr = page_to_virt(snapshot_page); + cpu_hw_evt->snapshot_addr_phys = page_to_phys(snapshot_page); + } + + return 0; +} + +static int pmu_sbi_snapshot_disable(void) +{ + struct sbiret ret; + + ret = sbi_ecall(SBI_EXT_PMU, SBI_EXT_PMU_SNAPSHOT_SET_SHMEM, -1, + -1, 0, 0, 0, 0); + if (ret.error) { + pr_warn("failed to disable snapshot shared memory\n"); + return sbi_err_map_linux_errno(ret.error); + } + + return 0; +} + +static int pmu_sbi_snapshot_setup(struct riscv_pmu *pmu, int cpu) +{ + struct cpu_hw_events *cpu_hw_evt; + struct sbiret ret = {0}; + + cpu_hw_evt = per_cpu_ptr(pmu->hw_events, cpu); + if (!cpu_hw_evt->snapshot_addr_phys) + return -EINVAL; + + if (cpu_hw_evt->snapshot_set_done) + return 0; + + if (IS_ENABLED(CONFIG_32BIT)) + ret = sbi_ecall(SBI_EXT_PMU, SBI_EXT_PMU_SNAPSHOT_SET_SHMEM, + cpu_hw_evt->snapshot_addr_phys, + (u64)(cpu_hw_evt->snapshot_addr_phys) >> 32, 0, 0, 0, 0); + else + ret = sbi_ecall(SBI_EXT_PMU, SBI_EXT_PMU_SNAPSHOT_SET_SHMEM, + cpu_hw_evt->snapshot_addr_phys, 0, 0, 0, 0, 0); + + /* Free up the snapshot area memory and fall back to SBI PMU calls without snapshot */ + if (ret.error) { + if (ret.error != SBI_ERR_NOT_SUPPORTED) + pr_warn("pmu snapshot setup failed with error %ld\n", ret.error); + return sbi_err_map_linux_errno(ret.error); + } + + cpu_hw_evt->snapshot_set_done = true; + + return 0; +} + static u64 pmu_sbi_ctr_read(struct perf_event *event) { struct hw_perf_event *hwc = &event->hw; int idx = hwc->idx; struct sbiret ret; u64 val = 0; + struct riscv_pmu *pmu = to_riscv_pmu(event->pmu); + struct cpu_hw_events *cpu_hw_evt = this_cpu_ptr(pmu->hw_events); + struct riscv_pmu_snapshot_data *sdata = cpu_hw_evt->snapshot_addr; union sbi_pmu_ctr_info info = pmu_ctr_list[idx]; + /* Read the value from the shared memory directly */ + if (sbi_pmu_snapshot_available()) { + val = sdata->ctr_values[idx]; + return val; + } + if (pmu_sbi_is_fw_event(event)) { ret = sbi_ecall(SBI_EXT_PMU, SBI_EXT_PMU_COUNTER_FW_READ, hwc->idx, 0, 0, 0, 0, 0); @@ -565,6 +662,7 @@ static void pmu_sbi_ctr_start(struct perf_event *event, u64 ival) struct hw_perf_event *hwc = &event->hw; unsigned long flag = SBI_PMU_START_FLAG_SET_INIT_VALUE; + /* There is no benefit setting SNAPSHOT FLAG for a single counter */ #if defined(CONFIG_32BIT) ret = sbi_ecall(SBI_EXT_PMU, SBI_EXT_PMU_COUNTER_START, hwc->idx, 1, flag, ival, ival >> 32, 0); @@ -585,16 +683,36 @@ static void pmu_sbi_ctr_stop(struct perf_event *event, unsigned long flag) { struct sbiret ret; struct hw_perf_event *hwc = &event->hw; + struct riscv_pmu *pmu = to_riscv_pmu(event->pmu); + struct cpu_hw_events *cpu_hw_evt = this_cpu_ptr(pmu->hw_events); + struct riscv_pmu_snapshot_data *sdata = cpu_hw_evt->snapshot_addr; if ((hwc->flags & PERF_EVENT_FLAG_USER_ACCESS) && (hwc->flags & PERF_EVENT_FLAG_USER_READ_CNT)) pmu_sbi_reset_scounteren((void *)event); + if (sbi_pmu_snapshot_available()) + flag |= SBI_PMU_STOP_FLAG_TAKE_SNAPSHOT; + ret = sbi_ecall(SBI_EXT_PMU, SBI_EXT_PMU_COUNTER_STOP, hwc->idx, 1, flag, 0, 0, 0); - if (ret.error && (ret.error != SBI_ERR_ALREADY_STOPPED) && - flag != SBI_PMU_STOP_FLAG_RESET) + if (!ret.error && sbi_pmu_snapshot_available()) { + /* + * The counter snapshot is based on the index base specified by hwc->idx. + * The actual counter value is updated in shared memory at index 0 when counter + * mask is 0x01. To ensure accurate counter values, it's necessary to transfer + * the counter value to shared memory. However, if hwc->idx is zero, the counter + * value is already correctly updated in shared memory, requiring no further + * adjustment. + */ + if (hwc->idx > 0) { + sdata->ctr_values[hwc->idx] = sdata->ctr_values[0]; + sdata->ctr_values[0] = 0; + } + } else if (ret.error && (ret.error != SBI_ERR_ALREADY_STOPPED) && + flag != SBI_PMU_STOP_FLAG_RESET) { pr_err("Stopping counter idx %d failed with error %d\n", hwc->idx, sbi_err_map_linux_errno(ret.error)); + } } static int pmu_sbi_find_num_ctrs(void) @@ -652,10 +770,14 @@ static inline void pmu_sbi_stop_all(struct riscv_pmu *pmu) static inline void pmu_sbi_stop_hw_ctrs(struct riscv_pmu *pmu) { struct cpu_hw_events *cpu_hw_evt = this_cpu_ptr(pmu->hw_events); + unsigned long flag = 0; + + if (sbi_pmu_snapshot_available()) + flag = SBI_PMU_STOP_FLAG_TAKE_SNAPSHOT; /* No need to check the error here as we can't do anything about the error */ sbi_ecall(SBI_EXT_PMU, SBI_EXT_PMU_COUNTER_STOP, 0, - cpu_hw_evt->used_hw_ctrs[0], 0, 0, 0, 0); + cpu_hw_evt->used_hw_ctrs[0], flag, 0, 0, 0); } /* @@ -664,11 +786,10 @@ static inline void pmu_sbi_stop_hw_ctrs(struct riscv_pmu *pmu) * while the overflowed counters need to be started with updated initialization * value. */ -static inline void pmu_sbi_start_overflow_mask(struct riscv_pmu *pmu, - unsigned long ctr_ovf_mask) +static noinline void pmu_sbi_start_ovf_ctrs_sbi(struct cpu_hw_events *cpu_hw_evt, + unsigned long ctr_ovf_mask) { int idx = 0; - struct cpu_hw_events *cpu_hw_evt = this_cpu_ptr(pmu->hw_events); struct perf_event *event; unsigned long flag = SBI_PMU_START_FLAG_SET_INIT_VALUE; unsigned long ctr_start_mask = 0; @@ -703,6 +824,48 @@ static inline void pmu_sbi_start_overflow_mask(struct riscv_pmu *pmu, } } +static noinline void pmu_sbi_start_ovf_ctrs_snapshot(struct cpu_hw_events *cpu_hw_evt, + unsigned long ctr_ovf_mask) +{ + int idx = 0; + struct perf_event *event; + unsigned long flag = SBI_PMU_START_FLAG_INIT_SNAPSHOT; + u64 max_period, init_val = 0; + struct hw_perf_event *hwc; + struct riscv_pmu_snapshot_data *sdata = cpu_hw_evt->snapshot_addr; + + for_each_set_bit(idx, cpu_hw_evt->used_hw_ctrs, RISCV_MAX_COUNTERS) { + if (ctr_ovf_mask & (BIT(idx))) { + event = cpu_hw_evt->events[idx]; + hwc = &event->hw; + max_period = riscv_pmu_ctr_get_width_mask(event); + init_val = local64_read(&hwc->prev_count) & max_period; + sdata->ctr_values[idx] = init_val; + } + /* + * We do not need to update the non-overflow counters the previous + * value should have been there already. + */ + } + + for (idx = 0; idx < BITS_TO_LONGS(RISCV_MAX_COUNTERS); idx++) { + /* Start all the counters in a single shot */ + sbi_ecall(SBI_EXT_PMU, SBI_EXT_PMU_COUNTER_START, idx * BITS_PER_LONG, + cpu_hw_evt->used_hw_ctrs[idx], flag, 0, 0, 0); + } +} + +static void pmu_sbi_start_overflow_mask(struct riscv_pmu *pmu, + unsigned long ctr_ovf_mask) +{ + struct cpu_hw_events *cpu_hw_evt = this_cpu_ptr(pmu->hw_events); + + if (sbi_pmu_snapshot_available()) + pmu_sbi_start_ovf_ctrs_snapshot(cpu_hw_evt, ctr_ovf_mask); + else + pmu_sbi_start_ovf_ctrs_sbi(cpu_hw_evt, ctr_ovf_mask); +} + static irqreturn_t pmu_sbi_ovf_handler(int irq, void *dev) { struct perf_sample_data data; @@ -716,6 +879,7 @@ static irqreturn_t pmu_sbi_ovf_handler(int irq, void *dev) unsigned long overflowed_ctrs = 0; struct cpu_hw_events *cpu_hw_evt = dev; u64 start_clock = sched_clock(); + struct riscv_pmu_snapshot_data *sdata = cpu_hw_evt->snapshot_addr; if (WARN_ON_ONCE(!cpu_hw_evt)) return IRQ_NONE; @@ -737,8 +901,10 @@ static irqreturn_t pmu_sbi_ovf_handler(int irq, void *dev) pmu_sbi_stop_hw_ctrs(pmu); /* Overflow status register should only be read after counter are stopped */ - ALT_SBI_PMU_OVERFLOW(overflow); - + if (sbi_pmu_snapshot_available()) + overflow = sdata->ctr_overflow_mask; + else + ALT_SBI_PMU_OVERFLOW(overflow); /* * Overflow interrupt pending bit should only be cleared after stopping * all the counters to avoid any race condition. @@ -819,6 +985,9 @@ static int pmu_sbi_starting_cpu(unsigned int cpu, struct hlist_node *node) enable_percpu_irq(riscv_pmu_irq, IRQ_TYPE_NONE); } + if (sbi_pmu_snapshot_available()) + return pmu_sbi_snapshot_setup(pmu, cpu); + return 0; } @@ -831,6 +1000,9 @@ static int pmu_sbi_dying_cpu(unsigned int cpu, struct hlist_node *node) /* Disable all counters access for user mode now */ csr_write(CSR_SCOUNTEREN, 0x0); + if (sbi_pmu_snapshot_available()) + return pmu_sbi_snapshot_disable(); + return 0; } @@ -1106,10 +1278,6 @@ static int pmu_sbi_device_probe(struct platform_device *pdev) pmu->event_unmapped = pmu_sbi_event_unmapped; pmu->csr_index = pmu_sbi_csr_index; - ret = cpuhp_state_add_instance(CPUHP_AP_PERF_RISCV_STARTING, &pmu->node); - if (ret) - return ret; - ret = riscv_pm_pmu_register(pmu); if (ret) goto out_unregister; @@ -1118,8 +1286,32 @@ static int pmu_sbi_device_probe(struct platform_device *pdev) if (ret) goto out_unregister; + /* SBI PMU Snapsphot is only available in SBI v2.0 */ + if (sbi_v2_available) { + ret = pmu_sbi_snapshot_alloc(pmu); + if (ret) + goto out_unregister; + + ret = pmu_sbi_snapshot_setup(pmu, smp_processor_id()); + if (!ret) { + pr_info("SBI PMU snapshot detected\n"); + /* + * We enable it once here for the boot cpu. If snapshot shmem setup + * fails during cpu hotplug process, it will fail to start the cpu + * as we can not handle hetergenous PMUs with different snapshot + * capability. + */ + static_branch_enable(&sbi_pmu_snapshot_available); + } + /* Snapshot is an optional feature. Continue if not available */ + } + register_sysctl("kernel", sbi_pmu_sysctl_table); + ret = cpuhp_state_add_instance(CPUHP_AP_PERF_RISCV_STARTING, &pmu->node); + if (ret) + return ret; + return 0; out_unregister: diff --git a/include/linux/perf/riscv_pmu.h b/include/linux/perf/riscv_pmu.h index 43282e22ebe1..c3fa90970042 100644 --- a/include/linux/perf/riscv_pmu.h +++ b/include/linux/perf/riscv_pmu.h @@ -39,6 +39,12 @@ struct cpu_hw_events { DECLARE_BITMAP(used_hw_ctrs, RISCV_MAX_COUNTERS); /* currently enabled firmware counters */ DECLARE_BITMAP(used_fw_ctrs, RISCV_MAX_COUNTERS); + /* The virtual address of the shared memory where counter snapshot will be taken */ + void *snapshot_addr; + /* The physical address of the shared memory where counter snapshot will be taken */ + phys_addr_t snapshot_addr_phys; + /* Boolean flag to indicate setup is already done */ + bool snapshot_set_done; }; struct riscv_pmu { From patchwork Wed Apr 3 08:04:36 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Atish Kumar Patra X-Patchwork-Id: 13615559 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 95CBCCD1294 for ; Wed, 3 Apr 2024 09:19:19 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:MIME-Version:References:In-Reply-To: Message-Id:Date:Subject:Cc:To:From:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; bh=BFT7JLsQmOpa4gTVV77RKkotkTl91TQyL0Rtuw12fEw=; b=XzW+XeX9U/NJpE AHbw3rtXSgVtArkFznJuT00QcJt9NiiJzHJELa1jZOoPBDaIhn8ZKOhxKBRvM479flME6GQC3hgbo x9QrKNxyPbyx51OvnVPtEMB/spYFCm2pm8iAmkV0Z2tBx8I5oJhCG82owUMmO8tgomIyjRKXjwZ3x j97BV5yd+Ur2CQ/3Y2zXWH7u310WeN5bPVPOUHny2UGoZD0CMd4OL2EIQSaHP8z+0kCqFUEjykmAn Mzq6j4yQlXz3l8OetpwbcdG9dL8T6Y4Tju4b1cS6L99CKF3GbmDMf/VhXvhi3N8ytIJO2gp8s8sDZ hiPBq1X/sp+SnMUWSXVA==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.97.1 #2 (Red Hat Linux)) id 1rrwm2-0000000FAHr-39fu; Wed, 03 Apr 2024 09:19:14 +0000 Received: from desiato.infradead.org ([2001:8b0:10b:1:d65d:64ff:fe57:4e05]) by bombadil.infradead.org with esmtps (Exim 4.97.1 #2 (Red Hat Linux)) id 1rrvcp-0000000Eikf-0EV7 for linux-riscv@bombadil.infradead.org; Wed, 03 Apr 2024 08:05:39 +0000 DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=infradead.org; s=desiato.20200630; h=Content-Transfer-Encoding:MIME-Version :References:In-Reply-To:Message-Id:Date:Subject:Cc:To:From:Sender:Reply-To: Content-Type:Content-ID:Content-Description; bh=4rw21DNPDWpaXnd5Gs3cWE2qTmUGGOZ0JnLHhYLDMiI=; b=aeDn/GHj/KD6GzzoqqFBDjM7NU BDvsrNW668L4b7YivpxEl4TF6ibzjuaGYAKWKFl7yL6o4erR/eV2nNfQiIU6QLeoSvNNS7qQyPkyP 8Tv34ACStvHO1/xHRJTeCA+TuxfUSKDxOQwTKZt4dYycvtyNB+VAgpNHbq4xMQUsot4RW7Zjz6T/0 Azxao+nBQR4/KJoU29LR+9v2+M4Ijm+lzECc1wLFVrxvcJBFbU7+cHyOMGzG8RbVL/UW0nw1BQG51 q3OZd4a7FqOlvI3920/IHFk7MS+eXqumwOEXqO+H+265e8N3Av5G9iLKi4HF/ay4mnWJTDzBG2/sL PXM1ARDA==; Received: from mail-pg1-x534.google.com ([2607:f8b0:4864:20::534]) by desiato.infradead.org with esmtps (Exim 4.97.1 #2 (Red Hat Linux)) id 1rrvch-000000044ky-1LRg for linux-riscv@lists.infradead.org; Wed, 03 Apr 2024 08:05:37 +0000 Received: by mail-pg1-x534.google.com with SMTP id 41be03b00d2f7-517ab9a4a13so4589844a12.1 for ; Wed, 03 Apr 2024 01:05:30 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=rivosinc-com.20230601.gappssmtp.com; s=20230601; t=1712131527; x=1712736327; darn=lists.infradead.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=4rw21DNPDWpaXnd5Gs3cWE2qTmUGGOZ0JnLHhYLDMiI=; b=Kw37MUE7HEv/oJAV9q1Jhakkv0IZnbSiYDkqUunyxXd7961bWzWxdEZEqH1AT3kOVv W2RZIz4O7FjPbXAi31ggfW8h6muF6uDOqbGoYVzlEZAPkac5woA6fYfD/h4KYyxPMemF wEvv7BAeOCs+/NbHfxoWYXmzJGfp6j39hlB1hvynUT/sIVRc9ZJSHuYxTOWv8aj5Jkoc 9i8cjUW8zh0AcHCramSkFvHtt6fN2FD0SMIQgOZCBwOILzhzfDd7ejpVLKbldQvEPrHI PzrogL+LY64RBYCRnH0U6uSwAxgg/P+iWbgPPgtXlBAoDGEdOgSLOx0TSlzhsoIY2qzJ HjqA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1712131527; x=1712736327; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=4rw21DNPDWpaXnd5Gs3cWE2qTmUGGOZ0JnLHhYLDMiI=; b=cZRJBccinIeWjNJzrJUyM+4noaqXfpqNLC1d5ea07T4lq//YeP6fECu0n0bpR3OF2c xY1cA84RQttOVndgW/gbI3/agcJUtmdGQAlLqhxIZGc6y48/mNavNvXmPQIyvG/JG3hn XKS7hx8x/Od+Q3pTZFjv4zO/92Nw2AJBl6ORfp8l1uYScJttEdzs8Xp/MsaxsogSywHT WrVPqkBegRX3DUAjqTs1Yaw7yPpgvRfLnnuxeeCcX9EaqMHLVZi+mnuwlwFzSs8oQ2EG 9Ahm6zBrAOPOizUSQhPSOMEUrS+/gbIZww7vvL9YqvTE7BkJwaZd5RsaRYQpONcUkaby qMCw== X-Forwarded-Encrypted: i=1; AJvYcCW5z+4Dx6RtlJp9bbSvai/qkq569XJMgzn0PCh7zFYMQClgYSjx50FfwkmnUGrcDbkEPCvhhRA8ef9NdMGJtqFuUOTZNPwKA7jsO5xmqcd9 X-Gm-Message-State: AOJu0Yxw/ix6vpCked/1x9hagDGzgNUx4CD5Vg1MGr7RoUbiWjJAc7xH koyQFIfUPfOFy20PAUBQV+pbKJ2tctMZNfVxmtgx+SR5iDpBmYb6hsiSWgMPxE4= X-Google-Smtp-Source: AGHT+IHZeguUWEErPiWxvNkeVU9lmGoRHX/48aTBnxr2DMrqRPKV9Qdy9c2zpt6UamZ4tC6ZYgwGwA== X-Received: by 2002:a05:6a20:17a7:b0:1a3:34c4:b184 with SMTP id bl39-20020a056a2017a700b001a334c4b184mr13823636pzb.19.1712131527654; Wed, 03 Apr 2024 01:05:27 -0700 (PDT) Received: from atishp.ba.rivosinc.com ([64.71.180.162]) by smtp.gmail.com with ESMTPSA id c12-20020a170902d48c00b001e0b5d49fc7sm12557229plg.161.2024.04.03.01.05.25 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 03 Apr 2024 01:05:26 -0700 (PDT) From: Atish Patra To: linux-kernel@vger.kernel.org Cc: Atish Patra , Ajay Kaher , Alexandre Ghiti , Alexey Makhalov , Andrew Jones , Anup Patel , Conor Dooley , Juergen Gross , kvm-riscv@lists.infradead.org, kvm@vger.kernel.org, linux-kselftest@vger.kernel.org, linux-riscv@lists.infradead.org, Mark Rutland , Palmer Dabbelt , Paolo Bonzini , Paul Walmsley , Shuah Khan , virtualization@lists.linux.dev, VMware PV-Drivers Reviewers , Will Deacon , x86@kernel.org Subject: [PATCH v5 07/22] drivers/perf: riscv: Fix counter mask iteration for RV32 Date: Wed, 3 Apr 2024 01:04:36 -0700 Message-Id: <20240403080452.1007601-8-atishp@rivosinc.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240403080452.1007601-1-atishp@rivosinc.com> References: <20240403080452.1007601-1-atishp@rivosinc.com> MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20240403_090531_629377_FF10ED8E X-CRM114-Status: GOOD ( 15.00 ) X-BeenThere: linux-riscv@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-riscv" Errors-To: linux-riscv-bounces+linux-riscv=archiver.kernel.org@lists.infradead.org For RV32, used_hw_ctrs can have more than 1 word if the firmware chooses to interleave firmware/hardware counters indicies. Even though it's a unlikely scenario, handle that case by iterating over all the words instead of just using the first word. Signed-off-by: Atish Patra Reviewed-by: Andrew Jones --- drivers/perf/riscv_pmu_sbi.c | 21 ++++++++++++--------- 1 file changed, 12 insertions(+), 9 deletions(-) diff --git a/drivers/perf/riscv_pmu_sbi.c b/drivers/perf/riscv_pmu_sbi.c index 8c3475d55433..82336fec82b8 100644 --- a/drivers/perf/riscv_pmu_sbi.c +++ b/drivers/perf/riscv_pmu_sbi.c @@ -771,13 +771,15 @@ static inline void pmu_sbi_stop_hw_ctrs(struct riscv_pmu *pmu) { struct cpu_hw_events *cpu_hw_evt = this_cpu_ptr(pmu->hw_events); unsigned long flag = 0; + int i; if (sbi_pmu_snapshot_available()) flag = SBI_PMU_STOP_FLAG_TAKE_SNAPSHOT; - /* No need to check the error here as we can't do anything about the error */ - sbi_ecall(SBI_EXT_PMU, SBI_EXT_PMU_COUNTER_STOP, 0, - cpu_hw_evt->used_hw_ctrs[0], flag, 0, 0, 0); + for (i = 0; i < BITS_TO_LONGS(RISCV_MAX_COUNTERS); i++) + /* No need to check the error here as we can't do anything about the error */ + sbi_ecall(SBI_EXT_PMU, SBI_EXT_PMU_COUNTER_STOP, i * BITS_PER_LONG, + cpu_hw_evt->used_hw_ctrs[i], flag, 0, 0, 0); } /* @@ -789,7 +791,7 @@ static inline void pmu_sbi_stop_hw_ctrs(struct riscv_pmu *pmu) static noinline void pmu_sbi_start_ovf_ctrs_sbi(struct cpu_hw_events *cpu_hw_evt, unsigned long ctr_ovf_mask) { - int idx = 0; + int idx = 0, i; struct perf_event *event; unsigned long flag = SBI_PMU_START_FLAG_SET_INIT_VALUE; unsigned long ctr_start_mask = 0; @@ -797,11 +799,12 @@ static noinline void pmu_sbi_start_ovf_ctrs_sbi(struct cpu_hw_events *cpu_hw_evt struct hw_perf_event *hwc; u64 init_val = 0; - ctr_start_mask = cpu_hw_evt->used_hw_ctrs[0] & ~ctr_ovf_mask; - - /* Start all the counters that did not overflow in a single shot */ - sbi_ecall(SBI_EXT_PMU, SBI_EXT_PMU_COUNTER_START, 0, ctr_start_mask, - 0, 0, 0, 0); + for (i = 0; i < BITS_TO_LONGS(RISCV_MAX_COUNTERS); i++) { + ctr_start_mask = cpu_hw_evt->used_hw_ctrs[i] & ~ctr_ovf_mask; + /* Start all the counters that did not overflow in a single shot */ + sbi_ecall(SBI_EXT_PMU, SBI_EXT_PMU_COUNTER_START, i * BITS_PER_LONG, ctr_start_mask, + 0, 0, 0, 0); + } /* Reinitialize and start all the counter that overflowed */ while (ctr_ovf_mask) { From patchwork Wed Apr 3 08:04:37 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Atish Kumar Patra X-Patchwork-Id: 13615560 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id A6849CD1288 for ; Wed, 3 Apr 2024 09:19:22 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:MIME-Version:References:In-Reply-To: Message-Id:Date:Subject:Cc:To:From:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; bh=yvjmevGKovP+Vdbn5swKS7900TPrJkQK/5LhFT59nuk=; b=BkjIIP9vQXzw0D OGysgKon7Ar3YYc7le3/ecJp2BA3zaUoGYhkKJDiV9/jMy0aRoVCjnnllp1jrCpZYOeshbiIa5W6D eAiaz16P460gnF6eekfqGfYevrARI+08j6cgx4cAeFtGSSIpY/fz2AEdDG2dWZ7gydGY3kLPXPyJL n02eJB66+YMzikFgnmkT+XL+PceIJ5/Nem7K/1kiCcowC4/YsatNY4gzQjEO7SI5f7IajobTyHaIk /qqq5Z57+uRlNiunEbiXKNgd7hFBMo3kCXeBqtwy94k7xIVPaUixVcFXvCPCfSuvRsHx88D5XSprD thf1iKiofi0EkSJe9VmA==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.97.1 #2 (Red Hat Linux)) id 1rrwm5-0000000FAKH-24Mt; Wed, 03 Apr 2024 09:19:17 +0000 Received: from casper.infradead.org ([2001:8b0:10b:1236::1]) by bombadil.infradead.org with esmtps (Exim 4.97.1 #2 (Red Hat Linux)) id 1rrvct-0000000Eiml-072q for linux-riscv@bombadil.infradead.org; Wed, 03 Apr 2024 08:05:43 +0000 DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=infradead.org; s=casper.20170209; h=Content-Transfer-Encoding:MIME-Version: References:In-Reply-To:Message-Id:Date:Subject:Cc:To:From:Sender:Reply-To: Content-Type:Content-ID:Content-Description; bh=2HMUEh/ouJpwrjadx4E8ELJ1oGZIEAqlVNHNOiveHPA=; b=nGBDO9hTg6Lx6QgE2Q4r2AFIfT 3EG4JRJLSBedDVCyTlWl7zOJFFzJMfN31CqKBQuTJufubDkmhKeXjPliOCBHm9myR5ZtzbAyng8QI GWVgtW4wt/7wrq3qkYh8tB0LsWOY9iz2mwdeq6sYzzLdRjkIbrqOzZUbRPqv+KX3AyEvmwRSkoV05 p4seF39oZ+4eHC75XgWRgVwY7zopnLxzlT41kuSbokyyh87hO47w0DAudLvfoRr/Bg+EERQHXWgRc JXrtVEug9zINzanABrtVxAeetnc1vWZ7NgZf1NXjQcxrsQyGmYGvByQlumboeqp3rGG5XZ5mg1f3Q GETReWWA==; Received: from mail-pl1-x631.google.com ([2607:f8b0:4864:20::631]) by casper.infradead.org with esmtps (Exim 4.97.1 #2 (Red Hat Linux)) id 1rrvci-000000055dH-0fb2 for linux-riscv@lists.infradead.org; Wed, 03 Apr 2024 08:05:41 +0000 Received: by mail-pl1-x631.google.com with SMTP id d9443c01a7336-1e0411c0a52so51648225ad.0 for ; Wed, 03 Apr 2024 01:05:31 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=rivosinc-com.20230601.gappssmtp.com; s=20230601; t=1712131529; x=1712736329; darn=lists.infradead.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=2HMUEh/ouJpwrjadx4E8ELJ1oGZIEAqlVNHNOiveHPA=; b=AGja0JDHb+PNzXZODDRPqG5FIm2XrBOYXLGctDm3UGzTAgXY7uJH7qd9YpLlLZtNUK q3X0gUaHoVt1mCR4p9LVPqa1wystQDN9j9I6Y8lNMwr59QsLTFQd6Yhq82oPF0TRE+gZ rcFzwg6/8dCJsRbyaPwxsh4qlfzA+7gWg5/1wJ61N0OmFFHvslA2F2/8Yn8w6iP3FrqA l2vfX5LM6SYKP6V7btS7IbuFRzfFlSuOpNffoUnpPPb3AHOrPNm+MOwKJkIYxlBh7PqE WwLNH+tD1Wuwe1ni+TdQ+tr8Hh6yTRrL9PHqX/PtXMNwA+qmozrE1e3Zw1cbmKykg7fn PZ0Q== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1712131529; x=1712736329; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=2HMUEh/ouJpwrjadx4E8ELJ1oGZIEAqlVNHNOiveHPA=; b=gM8KItk5vwrhX/uy3JN9bimMXxW5KhNMat70hy6XqdiC1J+03UrZgM3bIj4Or8HLXd 5KvDxCXFOOU8rWQRuQgkFCFvxyffbZUFTZj27TQZ+puDAt0IBN+8RjVUfhXiOzq+QdYS 1Y94uRVQiNiO9mhzbQqifLaNANmITHQxFu6UfEj+47AYBuFWiwXxw4od3lBTSTIjJmoj 7Ny0LduHHiFJTnyEFL3811PHJTDtCut7b5Wv+fhXLNVPCFwFfArBesbz6Afb+fAz1w3c vjlp9EoOWFY6nzYqmIWOi+Ousaxb4Xoj9vXD9BYntuERaXg8iusoNI495/CxbmntMAOO i1fA== X-Forwarded-Encrypted: i=1; AJvYcCX814UNPh1hp6sTjO9YOV9OqylegFF35ygu1iLGCr/QF+zhnBrUTZpeiEgr5VcL4JkQAwX7GcjoBoXoVVpcvu8leQH8wzpu56FjGpBjEvSL X-Gm-Message-State: AOJu0YzFBqZde9jy1h6WRkdluw2de0MPH48M/PBx8FRbCVzVUH5Zs2k6 V1h6gWHfF6n5GRyL6lFJMFfiwEE15AJqjP2RUG5GeJ8EG5k5CWPgdIDKSeAi9I8= X-Google-Smtp-Source: AGHT+IF30gBaFjuZamH6gB+fLa8VQAOCDXL32p+FdETcNWyCBYGk0g9s0A7zOmyK2RvO8zqC4rEDCA== X-Received: by 2002:a17:902:aa04:b0:1e2:23b8:98dd with SMTP id be4-20020a170902aa0400b001e223b898ddmr14090965plb.69.1712131529484; Wed, 03 Apr 2024 01:05:29 -0700 (PDT) Received: from atishp.ba.rivosinc.com ([64.71.180.162]) by smtp.gmail.com with ESMTPSA id c12-20020a170902d48c00b001e0b5d49fc7sm12557229plg.161.2024.04.03.01.05.27 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 03 Apr 2024 01:05:28 -0700 (PDT) From: Atish Patra To: linux-kernel@vger.kernel.org Cc: Atish Patra , Ajay Kaher , Alexandre Ghiti , Alexey Makhalov , Andrew Jones , Anup Patel , Conor Dooley , Juergen Gross , kvm-riscv@lists.infradead.org, kvm@vger.kernel.org, linux-kselftest@vger.kernel.org, linux-riscv@lists.infradead.org, Mark Rutland , Palmer Dabbelt , Paolo Bonzini , Paul Walmsley , Shuah Khan , virtualization@lists.linux.dev, VMware PV-Drivers Reviewers , Will Deacon , x86@kernel.org Subject: [PATCH v5 08/22] RISC-V: KVM: Fix the initial sample period value Date: Wed, 3 Apr 2024 01:04:37 -0700 Message-Id: <20240403080452.1007601-9-atishp@rivosinc.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240403080452.1007601-1-atishp@rivosinc.com> References: <20240403080452.1007601-1-atishp@rivosinc.com> MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20240403_090532_239461_82C841F9 X-CRM114-Status: GOOD ( 11.10 ) X-BeenThere: linux-riscv@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-riscv" Errors-To: linux-riscv-bounces+linux-riscv=archiver.kernel.org@lists.infradead.org The initial sample period value when counter value is not assigned should be set to maximum value supported by the counter width. Otherwise, it may result in spurious interrupts. Signed-off-by: Atish Patra Reviewed-by: Andrew Jones --- arch/riscv/kvm/vcpu_pmu.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/riscv/kvm/vcpu_pmu.c b/arch/riscv/kvm/vcpu_pmu.c index 86391a5061dd..cee1b9ca4ec4 100644 --- a/arch/riscv/kvm/vcpu_pmu.c +++ b/arch/riscv/kvm/vcpu_pmu.c @@ -39,7 +39,7 @@ static u64 kvm_pmu_get_sample_period(struct kvm_pmc *pmc) u64 sample_period; if (!pmc->counter_val) - sample_period = counter_val_mask + 1; + sample_period = counter_val_mask; else sample_period = (-pmc->counter_val) & counter_val_mask; From patchwork Wed Apr 3 08:04:38 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Atish Kumar Patra X-Patchwork-Id: 13615252 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 87793C6FD1F for ; Wed, 3 Apr 2024 08:05:53 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:MIME-Version:References:In-Reply-To: Message-Id:Date:Subject:Cc:To:From:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; bh=qWnQOdRT3ySCM1eQZFGnxvmDjg8JccnZdtgt+Im9OFg=; b=fD7m0TzqKjjjRR A7cjz40DTH31Qpt7FfWr3LSVPOUuwX+WPOcwuUKlPOgkVWde/sS706hooEhNncG04n2cJ4zgcJ4as ZZPeJVAY3i2zkkLvcnjhu1XNMkS3Jpuy7gG1bTLKhDhgDQNOO4HFT7/8Px+OnaZyeH81vQk9skhwI mTnRaGOrRxjRP5xtTb+OQd6emFez77/+lcImbi+RH3817JYZRCZWZznrjBbIHyqmJE8u17sCIfCxw idKoCQWkszK2gn5fTvtYLSVgt970hZHkka6wPGchE9QPeiG0rHbU5rNJCsPuRJORzL2vKelQOaG0r 7OPwuU5qpxW/kSqqOavQ==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.97.1 #2 (Red Hat Linux)) id 1rrvcz-0000000EitX-10a6; Wed, 03 Apr 2024 08:05:49 +0000 Received: from mail-pl1-x636.google.com ([2607:f8b0:4864:20::636]) by bombadil.infradead.org with esmtps (Exim 4.97.1 #2 (Red Hat Linux)) id 1rrvcu-0000000EieZ-3bRP for linux-riscv@lists.infradead.org; Wed, 03 Apr 2024 08:05:46 +0000 Received: by mail-pl1-x636.google.com with SMTP id d9443c01a7336-1e0d82d441bso54645185ad.3 for ; Wed, 03 Apr 2024 01:05:31 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=rivosinc-com.20230601.gappssmtp.com; s=20230601; t=1712131531; x=1712736331; darn=lists.infradead.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=+MJsU2/1DVF77yTSQMrmRq+eYVFGn04LSwUVmAHv4W8=; b=TIbVwok+meVnUaOnr3UaR9blFEh/RmDidZ3Kq2p5YKyw0R70BI8vCzUKCfwNaGoV/w LKpYN8LrvtkQX6q7S91nz7afHfFnrjtuk3p13V+4EKYmNx0E+hK5EJyUGBLCmpPnC4fy GCl24h9R4Lm4u+D1Falc3Ss3DrXepftDarg2PdD7Re+W54rks35Ap3Ucljnza5k+Hiu8 KgoxVjzgGcprvXz+PikVdkE8JnefaMBa/SJ7I+WHwlQLo6zY9hcOMRXr8ieuysc0GQeE NxSfgqGc38Y2FTHSf9YML4kKImFL7nV1/ZAVCzpdZugqqARJjFVZQVpFf6qYvbcxkkJm iDNw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1712131531; x=1712736331; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=+MJsU2/1DVF77yTSQMrmRq+eYVFGn04LSwUVmAHv4W8=; b=SOw+1m7KrsTpflNWnKoqQr7AW6A12wS2pYbxXUQo47zgTA6I/ClXFDE+xieci/iLZ4 PkKnbtJaz+DuZgQKR8tkNgozw2s2qEixEzPFZsuwuXSpCtr7xsrEebJIfWsEbZaZKvUt PLXR74rKgPK7pbOYzRIlcnnCoa+OYPvysrLRlb9zva5M6e01XDoF0JDW8gBhcSSJFDrx XyyEe/8akrA39D9/GYuCM8BfbLidRhpy9qBvAHriFTOWwJF6eTS4FEv+q+55AznYrdQU 9dZ5PLorpmymTIu/3dmf0+Tjv4jSy30Fyb50IS19nRJsO0uvqM96Ybpl+56V6ZBYYyVk G9+Q== X-Forwarded-Encrypted: i=1; AJvYcCXY6uaHuCEAZYhGDdS6Q/Kvn3sjXTBgBNADD/IMgbDrejHgyFcdElY/h7vrfbo5lWd5rlzUwYh2yOrUD1PhG0FrzdNV5nRoMYGV8YR9E96m X-Gm-Message-State: AOJu0YyA/KdbNHy5i6CEcIfeE5VLVIiEy3db1Z3wrasW3zkbsFK+Y4Cb R8Sl+Vyo2g4jsNQYE+MzAOBMWNOvhz4Qt3qiCt95eWOZmekMc4ASfRn1xKrXmHA= X-Google-Smtp-Source: AGHT+IE6hcM+iluLyfs2xAMwl4nidxEf2cHLsogRdu+mNxI8DxtzYjnOXL+jL/8fbjTuoDpYxOz/uQ== X-Received: by 2002:a17:903:244c:b0:1e2:6191:f6ae with SMTP id l12-20020a170903244c00b001e26191f6aemr2389190pls.0.1712131531142; Wed, 03 Apr 2024 01:05:31 -0700 (PDT) Received: from atishp.ba.rivosinc.com ([64.71.180.162]) by smtp.gmail.com with ESMTPSA id c12-20020a170902d48c00b001e0b5d49fc7sm12557229plg.161.2024.04.03.01.05.29 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 03 Apr 2024 01:05:30 -0700 (PDT) From: Atish Patra To: linux-kernel@vger.kernel.org Cc: Atish Patra , Ajay Kaher , Alexandre Ghiti , Alexey Makhalov , Andrew Jones , Anup Patel , Conor Dooley , Juergen Gross , kvm-riscv@lists.infradead.org, kvm@vger.kernel.org, linux-kselftest@vger.kernel.org, linux-riscv@lists.infradead.org, Mark Rutland , Palmer Dabbelt , Paolo Bonzini , Paul Walmsley , Shuah Khan , virtualization@lists.linux.dev, VMware PV-Drivers Reviewers , Will Deacon , x86@kernel.org Subject: [PATCH v5 09/22] RISC-V: KVM: Rename the SBI_STA_SHMEM_DISABLE to a generic name Date: Wed, 3 Apr 2024 01:04:38 -0700 Message-Id: <20240403080452.1007601-10-atishp@rivosinc.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240403080452.1007601-1-atishp@rivosinc.com> References: <20240403080452.1007601-1-atishp@rivosinc.com> MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20240403_010544_915898_50443E2C X-CRM114-Status: GOOD ( 15.15 ) X-BeenThere: linux-riscv@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-riscv" Errors-To: linux-riscv-bounces+linux-riscv=archiver.kernel.org@lists.infradead.org SBI_STA_SHMEM_DISABLE is a macro to invoke disable shared memory commands. As this can be invoked from other SBI extension context as well, rename it to more generic name as SBI_SHMEM_DISABLE. Signed-off-by: Atish Patra Reviewed-by: Andrew Jones --- arch/riscv/include/asm/sbi.h | 2 +- arch/riscv/kernel/paravirt.c | 6 +++--- arch/riscv/kvm/vcpu_sbi_sta.c | 4 ++-- 3 files changed, 6 insertions(+), 6 deletions(-) diff --git a/arch/riscv/include/asm/sbi.h b/arch/riscv/include/asm/sbi.h index 9aada4b9f7b5..f31650b10899 100644 --- a/arch/riscv/include/asm/sbi.h +++ b/arch/riscv/include/asm/sbi.h @@ -277,7 +277,7 @@ struct sbi_sta_struct { u8 pad[47]; } __packed; -#define SBI_STA_SHMEM_DISABLE -1 +#define SBI_SHMEM_DISABLE -1 /* SBI spec version fields */ #define SBI_SPEC_VERSION_DEFAULT 0x1 diff --git a/arch/riscv/kernel/paravirt.c b/arch/riscv/kernel/paravirt.c index 0d6225fd3194..fa6b0339a65d 100644 --- a/arch/riscv/kernel/paravirt.c +++ b/arch/riscv/kernel/paravirt.c @@ -62,7 +62,7 @@ static int sbi_sta_steal_time_set_shmem(unsigned long lo, unsigned long hi, ret = sbi_ecall(SBI_EXT_STA, SBI_EXT_STA_STEAL_TIME_SET_SHMEM, lo, hi, flags, 0, 0, 0); if (ret.error) { - if (lo == SBI_STA_SHMEM_DISABLE && hi == SBI_STA_SHMEM_DISABLE) + if (lo == SBI_SHMEM_DISABLE && hi == SBI_SHMEM_DISABLE) pr_warn("Failed to disable steal-time shmem"); else pr_warn("Failed to set steal-time shmem"); @@ -84,8 +84,8 @@ static int pv_time_cpu_online(unsigned int cpu) static int pv_time_cpu_down_prepare(unsigned int cpu) { - return sbi_sta_steal_time_set_shmem(SBI_STA_SHMEM_DISABLE, - SBI_STA_SHMEM_DISABLE, 0); + return sbi_sta_steal_time_set_shmem(SBI_SHMEM_DISABLE, + SBI_SHMEM_DISABLE, 0); } static u64 pv_time_steal_clock(int cpu) diff --git a/arch/riscv/kvm/vcpu_sbi_sta.c b/arch/riscv/kvm/vcpu_sbi_sta.c index d8cf9ca28c61..5f35427114c1 100644 --- a/arch/riscv/kvm/vcpu_sbi_sta.c +++ b/arch/riscv/kvm/vcpu_sbi_sta.c @@ -93,8 +93,8 @@ static int kvm_sbi_sta_steal_time_set_shmem(struct kvm_vcpu *vcpu) if (flags != 0) return SBI_ERR_INVALID_PARAM; - if (shmem_phys_lo == SBI_STA_SHMEM_DISABLE && - shmem_phys_hi == SBI_STA_SHMEM_DISABLE) { + if (shmem_phys_lo == SBI_SHMEM_DISABLE && + shmem_phys_hi == SBI_SHMEM_DISABLE) { vcpu->arch.sta.shmem = INVALID_GPA; return 0; } From patchwork Wed Apr 3 08:04:39 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Atish Kumar Patra X-Patchwork-Id: 13615255 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id D4F9DC6FD1F for ; Wed, 3 Apr 2024 08:06:05 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:MIME-Version:References:In-Reply-To: Message-Id:Date:Subject:Cc:To:From:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; bh=hhZG+X1m/xT3fV3wxBo/yNrUgHsEMisv0loVYZ8KvQk=; b=0/uLwRiiCrTSrS MuvXydpRil058q5U3sJ5jgik36fUidHB7cn6/nZAsWX3NzNsVyHlIWiaZa7LG8PAbwPKjYpUC9D47 UX2mumeTvs5fTSEppORrl+RyeawWo4SL9fViuYUW24o1VDi8Oo4Eqy3+rjs4nzQPM1zX/+MqGfb4I xTb+AWnmVTG2b+cfVcS6KzMyheJH6Rq9CeNtHigTZvtafmto7b5LvFzrqCZU0MkVaXbOVl+hWJW5m schAF3YqWwmZIBgeCjIaqdxUlgKdm2ImewizsNeJmkTFtc/j2Z6CqbSojySbfdT6ccdXEIYXHLziJ 4zZlG9A9V98rPHGY0ILQ==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.97.1 #2 (Red Hat Linux)) id 1rrvdA-0000000Ej31-0tme; Wed, 03 Apr 2024 08:06:00 +0000 Received: from mail-pg1-x52a.google.com ([2607:f8b0:4864:20::52a]) by bombadil.infradead.org with esmtps (Exim 4.97.1 #2 (Red Hat Linux)) id 1rrvcw-0000000EigB-1cyn for linux-riscv@lists.infradead.org; Wed, 03 Apr 2024 08:05:48 +0000 Received: by mail-pg1-x52a.google.com with SMTP id 41be03b00d2f7-5dca1efad59so4381204a12.2 for ; Wed, 03 Apr 2024 01:05:33 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=rivosinc-com.20230601.gappssmtp.com; s=20230601; t=1712131533; x=1712736333; darn=lists.infradead.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=oLadZMY/1E+aj61iqE390ie32fUnJXqsMN5cFXtebck=; b=v/84nTXuOlbtGb6cTg6yIxvolwTS9ec7zNrknC5EQj2ABaQrkK659DDDfCkvKRbTwc WowaJ/q/CfnLV/PkaiKwP+S/XnplCiRXPJQr5JWvm1QEkZ9MYQz7FDU35YCw1YhkqZG/ aMqIC2l3/uV+tZiJdnt8x2kK3sVPuwCZzf7tJ9YMNFsdVSsYl3WJ3HzlL17QekUWUiYJ g555zuAlIUXaELhqR7Hp9Uoawj1FFMybF/w/3OWXXIOj3/uC7u/K6HININ0cpGxJVjpZ nancgIqtesEg3x8bF4JZlxrZzlkI1CkVsDBNC4UfkPk+eVPxnjIKmpPVU4wL1RtNDrHG eeSQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1712131533; x=1712736333; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=oLadZMY/1E+aj61iqE390ie32fUnJXqsMN5cFXtebck=; b=tpVDCNnD9MVk2JHso3HX5VLCFnFs6QxekajCtJRG7oCTIU3RVUYAaOhOFI4NoHHiVH 1vR5bmdbnl8s6Uc3Y+e39V916pAXYuNdUYv6xAt0rjXm1EvoJGK7HraD3Bl9PjQ1n2Lw l62fzjOqwP+Czd6UHwL1rfsvEJkWHnmhvCr318wVzN257S7mwIxZ46431F7Hl4xTDv0K jzc/82/ZfUzkh+a2vMVMUWdWW0m8Ns9eSPUThp7unyquLsik+1NbLbhIbOA/cIznY/Ps Az9Xarlz0eC8vjHNOB9tmu7JOPm3nJRoCAPgyV8ZTnXYWP6i5+AVty/Qesw3S/jZSul0 jNHw== X-Forwarded-Encrypted: i=1; AJvYcCXC6HFROQiu57EOKxrjLTeisw9S/bnkzcl4u3nMnBdhq0dm+XJ3td9fNlrfLohxl086T7kSuz+OL5R0nOgLI+b6hL2RSJUHi7U2qt4dkZqU X-Gm-Message-State: AOJu0YwALC9i/tOQZB9pdmIfAX1rH5jvyGJNwlzUfxmb15sKyH9DGpoF vGWsj8dn0LGMDPduyL+Y3IfhJ1TaurNfPSxrax16WSAl06OFC0BiPctRdExqXYY= X-Google-Smtp-Source: AGHT+IHYBgMwEeWVbd4P9PNDRXwi0PIWRTlB15cj+AGKTpxTy9q1IU7RrYP0KIGaFYPVod/3S9sbOg== X-Received: by 2002:a05:6a21:3294:b0:1a5:6a85:8ce9 with SMTP id yt20-20020a056a21329400b001a56a858ce9mr2619252pzb.12.1712131533285; Wed, 03 Apr 2024 01:05:33 -0700 (PDT) Received: from atishp.ba.rivosinc.com ([64.71.180.162]) by smtp.gmail.com with ESMTPSA id c12-20020a170902d48c00b001e0b5d49fc7sm12557229plg.161.2024.04.03.01.05.31 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 03 Apr 2024 01:05:32 -0700 (PDT) From: Atish Patra To: linux-kernel@vger.kernel.org Cc: Atish Patra , Anup Patel , Andrew Jones , Ajay Kaher , Alexandre Ghiti , Alexey Makhalov , Conor Dooley , Juergen Gross , kvm-riscv@lists.infradead.org, kvm@vger.kernel.org, linux-kselftest@vger.kernel.org, linux-riscv@lists.infradead.org, Mark Rutland , Palmer Dabbelt , Paolo Bonzini , Paul Walmsley , Shuah Khan , virtualization@lists.linux.dev, VMware PV-Drivers Reviewers , Will Deacon , x86@kernel.org Subject: [PATCH v5 10/22] RISC-V: KVM: No need to update the counter value during reset Date: Wed, 3 Apr 2024 01:04:39 -0700 Message-Id: <20240403080452.1007601-11-atishp@rivosinc.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240403080452.1007601-1-atishp@rivosinc.com> References: <20240403080452.1007601-1-atishp@rivosinc.com> MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20240403_010546_601992_86A5A287 X-CRM114-Status: GOOD ( 13.12 ) X-BeenThere: linux-riscv@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-riscv" Errors-To: linux-riscv-bounces+linux-riscv=archiver.kernel.org@lists.infradead.org The virtual counter value is updated during pmu_ctr_read. There is no need to update it in reset case. Otherwise, it will be counted twice which is incorrect. Fixes: 0cb74b65d2e5 ("RISC-V: KVM: Implement perf support without sampling") Reviewed-by: Anup Patel Reviewed-by: Andrew Jones Signed-off-by: Atish Patra --- arch/riscv/kvm/vcpu_pmu.c | 8 ++------ 1 file changed, 2 insertions(+), 6 deletions(-) diff --git a/arch/riscv/kvm/vcpu_pmu.c b/arch/riscv/kvm/vcpu_pmu.c index cee1b9ca4ec4..b5159ce4592d 100644 --- a/arch/riscv/kvm/vcpu_pmu.c +++ b/arch/riscv/kvm/vcpu_pmu.c @@ -397,7 +397,6 @@ int kvm_riscv_vcpu_pmu_ctr_stop(struct kvm_vcpu *vcpu, unsigned long ctr_base, { struct kvm_pmu *kvpmu = vcpu_to_pmu(vcpu); int i, pmc_index, sbiret = 0; - u64 enabled, running; struct kvm_pmc *pmc; int fevent_code; @@ -432,12 +431,9 @@ int kvm_riscv_vcpu_pmu_ctr_stop(struct kvm_vcpu *vcpu, unsigned long ctr_base, sbiret = SBI_ERR_ALREADY_STOPPED; } - if (flags & SBI_PMU_STOP_FLAG_RESET) { - /* Relase the counter if this is a reset request */ - pmc->counter_val += perf_event_read_value(pmc->perf_event, - &enabled, &running); + if (flags & SBI_PMU_STOP_FLAG_RESET) + /* Release the counter if this is a reset request */ kvm_pmu_release_perf_event(pmc); - } } else { sbiret = SBI_ERR_INVALID_PARAM; } From patchwork Wed Apr 3 08:04:40 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Atish Kumar Patra X-Patchwork-Id: 13615563 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id DE4A1CD1288 for ; Wed, 3 Apr 2024 09:19:33 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:MIME-Version:References:In-Reply-To: Message-Id:Date:Subject:Cc:To:From:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; bh=qeIh27JZGNzAEdL49duZ0LdbHS+Th+7LVg+92kk1D84=; b=NM6SDgCx86PWDZ 1IXEWoSuYlPIEgyfAJnwELIhV7U17XcYM59Z4yB8r7nNXtGTnyW5WsI/3vd36uXnSlxG0SEuuUTE7 fkhV+HtBcylSBvJGaqTTVhCisvhbKyGMVFlMPDdebtO9/xACAcJ2DEVdQj4H9xy8SzDP9Aur9Ek0L xqgipbn2VpDZT4fyFH0Z9FZ5wiqf7Gm7quvJf9MFPcf5hRm5JRcf0TzZolB2fkGDU7qP40aZXFyO0 roGFTtsEpJxwK/mZNIwfEn9BDjE+i0/3qoj7hrCYDWL8nsgOijoouL7JcRdaosz0egtfWlHcX3KxM o9iBzw0yLVJvJwTX0EmQ==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.97.1 #2 (Red Hat Linux)) id 1rrwmB-0000000FAPE-1Hyh; Wed, 03 Apr 2024 09:19:23 +0000 Received: from casper.infradead.org ([2001:8b0:10b:1236::1]) by bombadil.infradead.org with esmtps (Exim 4.97.1 #2 (Red Hat Linux)) id 1rrvcw-0000000Eipo-2cer for linux-riscv@bombadil.infradead.org; Wed, 03 Apr 2024 08:05:46 +0000 DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=infradead.org; s=casper.20170209; h=Content-Transfer-Encoding:MIME-Version: References:In-Reply-To:Message-Id:Date:Subject:Cc:To:From:Sender:Reply-To: Content-Type:Content-ID:Content-Description; bh=QIyaUvQe1Xat3Gv2wtXts1DoFv5C5UbopqhCGzslRuw=; b=NuN5yo5BjpkkKH8gBlZNTZrq7Q YZplOstlNBlGGFFvpp/pkS/0MPcJTIWlXylEMAZieQzI/wtvNfzYetlY36ALDXiuqpsKVA3lhgpLU oh+67JE2zq0Ra9EOJ676dLsThUEtv7i13Rcq6n22XTWnYTzRQdLunGaSXg0sdzMJDY9umtyCN+u6i 7lJCHpapnth2v8/rGGX6CyCd4/WWAQgwRznrDG6vPjorjwf8uHJuj5XMT8zaUrhFZnmXXeb25b/C4 jJmYRy4/OHAzo912AOaU3pcxJaS5m/3iEtn+7P+PkeqIRMR3FBqkt/sw8Ys5wKPMpAIZu8ItXBeFV kSK+Nigw==; Received: from mail-pl1-x636.google.com ([2607:f8b0:4864:20::636]) by casper.infradead.org with esmtps (Exim 4.97.1 #2 (Red Hat Linux)) id 1rrvco-000000055eg-0Dmb for linux-riscv@lists.infradead.org; Wed, 03 Apr 2024 08:05:45 +0000 Received: by mail-pl1-x636.google.com with SMTP id d9443c01a7336-1e0d8403257so47314405ad.1 for ; Wed, 03 Apr 2024 01:05:37 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=rivosinc-com.20230601.gappssmtp.com; s=20230601; t=1712131535; x=1712736335; darn=lists.infradead.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=QIyaUvQe1Xat3Gv2wtXts1DoFv5C5UbopqhCGzslRuw=; b=yxBnGYWwFLVcCGwsUOeYON77Yw8urPO0VbVfe41tILZQcfbPtXblogTOWK4CX4hmBR Z6e+mETvGcktfhpXvkd+2TGa2xCw3VcUq0e5ZgOwDfz6ip/07blnvVSa5RLMGL6IzJxC KTeuo8xEtlxjEzwDmNklAuJa4vyfbWZV7En+5ftbeUWOhjGm9hvxI1HvnGVBS8Se+y2S 5gT2g3fjZSbHSvP7Qa8NtjMHjlNtaceZdTBR1GQOPTKVIxUV6Vpf493tjZj4F+w0pl3y QDpINhZklY5SczCLYmlpNt2cg2jzBqwIhj+fqTuQY+WeuhS4aa4LCe5KvHMVTPfl6PIM jhdQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1712131535; x=1712736335; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=QIyaUvQe1Xat3Gv2wtXts1DoFv5C5UbopqhCGzslRuw=; b=Q1ZET3qoIYw7fJllUH5iGebYS2f53XUsDQnbNLaWhmS6KydeWwAN2KNiXBgpZxY6G0 61DSBUxnaEAwbEc+7bFP87A6jjTPkQdwqKIoOci3nMxpsxwEaqV+u2kOcM2VAaOPrtnW VbzQnbvBPo4TInueZ+tkiQP0cJ/33C51V+Tlet8yYAFYy1Bs5G25+XyeQCtI6gGAlpE0 QsOxJ96FnZO4Eo7cZrGRdX77inoKl6qSR3YhTyLpkE9jWr8Pz/bs8HaCKPY5JU9rfa5X wL32h+SpzO1Q33rbM94DxxnyTnvKgjY0te3hT/cHN8Yt60fJ6WnqLmTpQl0OqSjjO++b ZuSA== X-Forwarded-Encrypted: i=1; AJvYcCWbBpTbaq0R0C5Boh1aQoWvyZpWrL4HX+d5Ou3V2Sze9kt3iU+iLkcxn9uB206jn5p0YxrjIXj16xAZ/b0RgJwXNKKdKyFRHfbDmOVgtHLV X-Gm-Message-State: AOJu0YyJZAaNX76HSbTd9POl1U97FzWdMZ1uBXsHA0fmw6ZLMSP0bCny tkw3mUk3u3QwWXwIi3TGWXeLcvW5Ai15b+zDHcIxBxA34/feitjk9l3MhSuClqI= X-Google-Smtp-Source: AGHT+IEWaMwJlilOpjjtAd3ogSZtQYb7+W8r4UBVM9U3DF3iIMbLdC4POqTiOnAm6aIo/b0Y3UPrBw== X-Received: by 2002:a17:902:7881:b0:1e0:cd01:9fd with SMTP id q1-20020a170902788100b001e0cd0109fdmr11915195pll.26.1712131535324; Wed, 03 Apr 2024 01:05:35 -0700 (PDT) Received: from atishp.ba.rivosinc.com ([64.71.180.162]) by smtp.gmail.com with ESMTPSA id c12-20020a170902d48c00b001e0b5d49fc7sm12557229plg.161.2024.04.03.01.05.33 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 03 Apr 2024 01:05:34 -0700 (PDT) From: Atish Patra To: linux-kernel@vger.kernel.org Cc: Atish Patra , Anup Patel , Ajay Kaher , Alexandre Ghiti , Alexey Makhalov , Andrew Jones , Conor Dooley , Juergen Gross , kvm-riscv@lists.infradead.org, kvm@vger.kernel.org, linux-kselftest@vger.kernel.org, linux-riscv@lists.infradead.org, Mark Rutland , Palmer Dabbelt , Paolo Bonzini , Paul Walmsley , Shuah Khan , virtualization@lists.linux.dev, VMware PV-Drivers Reviewers , Will Deacon , x86@kernel.org Subject: [PATCH v5 11/22] RISC-V: KVM: No need to exit to the user space if perf event failed Date: Wed, 3 Apr 2024 01:04:40 -0700 Message-Id: <20240403080452.1007601-12-atishp@rivosinc.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240403080452.1007601-1-atishp@rivosinc.com> References: <20240403080452.1007601-1-atishp@rivosinc.com> MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20240403_090538_158902_1CC93439 X-CRM114-Status: GOOD ( 16.53 ) X-BeenThere: linux-riscv@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-riscv" Errors-To: linux-riscv-bounces+linux-riscv=archiver.kernel.org@lists.infradead.org Currently, we return a linux error code if creating a perf event failed in kvm. That shouldn't be necessary as guest can continue to operate without perf profiling or profiling with firmware counters. Return appropriate SBI error code to indicate that PMU configuration failed. An error message in kvm already describes the reason for failure. Fixes: 0cb74b65d2e5 ("RISC-V: KVM: Implement perf support without sampling") Reviewed-by: Anup Patel Signed-off-by: Atish Patra --- arch/riscv/kvm/vcpu_pmu.c | 14 +++++++++----- arch/riscv/kvm/vcpu_sbi_pmu.c | 6 +++--- 2 files changed, 12 insertions(+), 8 deletions(-) diff --git a/arch/riscv/kvm/vcpu_pmu.c b/arch/riscv/kvm/vcpu_pmu.c index b5159ce4592d..2d9929bbc2c8 100644 --- a/arch/riscv/kvm/vcpu_pmu.c +++ b/arch/riscv/kvm/vcpu_pmu.c @@ -229,8 +229,9 @@ static int kvm_pmu_validate_counter_mask(struct kvm_pmu *kvpmu, unsigned long ct return 0; } -static int kvm_pmu_create_perf_event(struct kvm_pmc *pmc, struct perf_event_attr *attr, - unsigned long flags, unsigned long eidx, unsigned long evtdata) +static long kvm_pmu_create_perf_event(struct kvm_pmc *pmc, struct perf_event_attr *attr, + unsigned long flags, unsigned long eidx, + unsigned long evtdata) { struct perf_event *event; @@ -454,7 +455,8 @@ int kvm_riscv_vcpu_pmu_ctr_cfg_match(struct kvm_vcpu *vcpu, unsigned long ctr_ba unsigned long eidx, u64 evtdata, struct kvm_vcpu_sbi_return *retdata) { - int ctr_idx, ret, sbiret = 0; + int ctr_idx, sbiret = 0; + long ret; bool is_fevent; unsigned long event_code; u32 etype = kvm_pmu_get_perf_event_type(eidx); @@ -513,8 +515,10 @@ int kvm_riscv_vcpu_pmu_ctr_cfg_match(struct kvm_vcpu *vcpu, unsigned long ctr_ba kvpmu->fw_event[event_code].started = true; } else { ret = kvm_pmu_create_perf_event(pmc, &attr, flags, eidx, evtdata); - if (ret) - return ret; + if (ret) { + sbiret = SBI_ERR_NOT_SUPPORTED; + goto out; + } } set_bit(ctr_idx, kvpmu->pmc_in_use); diff --git a/arch/riscv/kvm/vcpu_sbi_pmu.c b/arch/riscv/kvm/vcpu_sbi_pmu.c index 7eca72df2cbd..e1633606c98b 100644 --- a/arch/riscv/kvm/vcpu_sbi_pmu.c +++ b/arch/riscv/kvm/vcpu_sbi_pmu.c @@ -42,9 +42,9 @@ static int kvm_sbi_ext_pmu_handler(struct kvm_vcpu *vcpu, struct kvm_run *run, #endif /* * This can fail if perf core framework fails to create an event. - * Forward the error to userspace because it's an error which - * happened within the host kernel. The other option would be - * to convert to an SBI error and forward to the guest. + * No need to forward the error to userspace and exit the guest. + * The operation can continue without profiling. Forward the + * appropriate SBI error to the guest. */ ret = kvm_riscv_vcpu_pmu_ctr_cfg_match(vcpu, cp->a0, cp->a1, cp->a2, cp->a3, temp, retdata); From patchwork Wed Apr 3 08:04:41 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Atish Kumar Patra X-Patchwork-Id: 13615561 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 774F5CD1288 for ; Wed, 3 Apr 2024 09:19:26 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:MIME-Version:References:In-Reply-To: Message-Id:Date:Subject:Cc:To:From:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; bh=Z1kxVzhrzTkt8A5z8PtmQaxXMoxAhtYRs7bzZ6T1zgg=; b=1D2iNb9OcYmBvw csmdOpvIMtUJiymPlXC47C9zB9AeiTH6TNgjWe3Hyv7PH4iXsO38ADPpGc61ArkvVxQqZQKd0wUwD qTtaETRZufWTrmCG+W9PYXqNdK8L/CsOB1gn+mW864CI5mmBS1PqRV/73QcCRg2iY3Iiyqzx4YcgF X9EoHh3PbDczgh8L2nafa80aNfb3dM/0z7eNKLEGuL5Gu/DCg+/vPx65PObVkqOxxlI0ymozGKhoB 0LJKws3PXYAHpnbQeU6iPYh24hwwI1wEL/IMC8A0qfpVXqX5M151ksk2ZVhr65l6Z8a8Ds1dQjQLL S6HqmPbAxoNthPBwai4Q==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.97.1 #2 (Red Hat Linux)) id 1rrwm9-0000000FANe-2uAU; Wed, 03 Apr 2024 09:19:21 +0000 Received: from desiato.infradead.org ([2001:8b0:10b:1:d65d:64ff:fe57:4e05]) by bombadil.infradead.org with esmtps (Exim 4.97.1 #2 (Red Hat Linux)) id 1rrvcv-0000000EioM-10zY for linux-riscv@bombadil.infradead.org; Wed, 03 Apr 2024 08:05:45 +0000 DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=infradead.org; s=desiato.20200630; h=Content-Transfer-Encoding:MIME-Version :References:In-Reply-To:Message-Id:Date:Subject:Cc:To:From:Sender:Reply-To: Content-Type:Content-ID:Content-Description; bh=DuA34i2i05BdrpKVxBo9U52t2zQUfVSke6lRxCYCo/Y=; b=OUehZ/0t3GPyU+luWwuyzgls0Q 4Zx1ucIiqQbCNxijz7j2JQeZu2aT9Zqpb+oubFdl1OY4i8hAdLErfw/Oixv9WbC8gsUYONnKt88XQ jRr0fCZDMvfAoya9QiSVvzdDEWHDfu0QNPJxE2R135L4Z5R2rRIk+6ZJpzZOcyI9nf5zmWFY3nWWT tC1yhGCXWCHYnRmp16gs13EOc1OL703cfbapsm5dPCZT0tyr/T1f9jAL6TY8lpS0iL3AMeg62Ed6H ypgN258YkbZ5U8fy7xNkRsJfwLxMrk/n7czLeYAkHYSaZsIj4+MsLzwzgInpPWdtl3WA0N9k8kDgZ 67FcyEiQ==; Received: from mail-pl1-x62e.google.com ([2607:f8b0:4864:20::62e]) by desiato.infradead.org with esmtps (Exim 4.97.1 #2 (Red Hat Linux)) id 1rrvcp-000000044nt-3MLl for linux-riscv@lists.infradead.org; Wed, 03 Apr 2024 08:05:43 +0000 Received: by mail-pl1-x62e.google.com with SMTP id d9443c01a7336-1def89f0cfdso5306825ad.0 for ; Wed, 03 Apr 2024 01:05:39 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=rivosinc-com.20230601.gappssmtp.com; s=20230601; t=1712131537; x=1712736337; darn=lists.infradead.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=DuA34i2i05BdrpKVxBo9U52t2zQUfVSke6lRxCYCo/Y=; b=f1MX+7fVpAPuaxZSPl/lc6jNDAAO+MtmWv6zyZc4kp/vHlW22kgSWdjuU56jeGj8Ni wKcFx+vJdN1b97kaeZ7er1xxGB9Ko0GytTe8N/JTaXRywwvzvtlP3Gwb+QTG52qzkWvn u+CnGiUYu+Nji9OfrXqbLrYUMz/YLZZ5PRg/AEO8zhuP6KLPiyUnpqa7FsEVMyFgZa9z hlE+hM++TEy/Z0Thk4oUPX+95CNgVPyqMXK7zsaFEXk+z36jsSv6vTB4g/7MTIIH28U6 k4WkgAEwyARi2tYG6sfeCkCdFtwbJgq8UQD/Cg8B8kRYWl27rkoOpGa9JkafXYZWuNOk UU4g== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1712131537; x=1712736337; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=DuA34i2i05BdrpKVxBo9U52t2zQUfVSke6lRxCYCo/Y=; b=tFPsBSGJbgNgOOJciTYAr316hJSbKX5zCVXsbpCvyxyijz0bXlF47UgEl9sA0OO4XV f45tzZmL1ghpjrxF7yGAOSuwF0KvLXJhQw+jJi69GQfDbQLcYES7mAoup3i+rn6KrxmQ F+sX+8WgQkfj2vV9mUg30KW0JGxakPoYpvB8vXkDsLVYrTBf/UkqYgHTGIv3+zk67BVn mZZuZLnekCXjHJUsiA5oyT9l/avNE5S6HyFE5mkCHniAMks/4STLOv6E0L4Wc/0bAJ9E QrQu+KslZZLO6FAFwgJIF1xjBhLt+v58mwJr3s9WaAOnBVZEZWGkb02MCPumC+ciidfg 6/Mw== X-Forwarded-Encrypted: i=1; AJvYcCVmJ9SMrhHi9NmZNhAj2brK5rl5R/8AOYdtJlIsdxj5k/21O7jDsVmxhQLPgUFPnQJb6Y+CG/1zvFFGwPCH7doJmFuh0RAKoya/8ffbizXX X-Gm-Message-State: AOJu0YxDI0qz7SZk4HofLq8ZnQbVa48dpihdNJaKkR7y1pVDyt9YeYFl sgGM1FqW1vzTjNuoqCa71onHU6TCjNYyvxw94MkH9oEA76EnMwcjJYJyWcD1EaQ= X-Google-Smtp-Source: AGHT+IFBrDynPtuhgjL+hZ1dZyV0Uqc7RiuyZWbbuSRb3GyHkug7a6buerfzOAosBHqmfYwR+/IA1w== X-Received: by 2002:a17:902:a984:b0:1e0:dc6e:45ed with SMTP id bh4-20020a170902a98400b001e0dc6e45edmr2249678plb.15.1712131537573; Wed, 03 Apr 2024 01:05:37 -0700 (PDT) Received: from atishp.ba.rivosinc.com ([64.71.180.162]) by smtp.gmail.com with ESMTPSA id c12-20020a170902d48c00b001e0b5d49fc7sm12557229plg.161.2024.04.03.01.05.35 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 03 Apr 2024 01:05:36 -0700 (PDT) From: Atish Patra To: linux-kernel@vger.kernel.org Cc: Atish Patra , Anup Patel , Ajay Kaher , Alexandre Ghiti , Alexey Makhalov , Andrew Jones , Conor Dooley , Juergen Gross , kvm-riscv@lists.infradead.org, kvm@vger.kernel.org, linux-kselftest@vger.kernel.org, linux-riscv@lists.infradead.org, Mark Rutland , Palmer Dabbelt , Paolo Bonzini , Paul Walmsley , Shuah Khan , virtualization@lists.linux.dev, VMware PV-Drivers Reviewers , Will Deacon , x86@kernel.org Subject: [PATCH v5 12/22] RISC-V: KVM: Implement SBI PMU Snapshot feature Date: Wed, 3 Apr 2024 01:04:41 -0700 Message-Id: <20240403080452.1007601-13-atishp@rivosinc.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240403080452.1007601-1-atishp@rivosinc.com> References: <20240403080452.1007601-1-atishp@rivosinc.com> MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20240403_090541_052915_4F7E5BBB X-CRM114-Status: GOOD ( 25.73 ) X-BeenThere: linux-riscv@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-riscv" Errors-To: linux-riscv-bounces+linux-riscv=archiver.kernel.org@lists.infradead.org PMU Snapshot function allows to minimize the number of traps when the guest access configures/access the hpmcounters. If the snapshot feature is enabled, the hypervisor updates the shared memory with counter data and state of overflown counters. The guest can just read the shared memory instead of trap & emulate done by the hypervisor. This patch doesn't implement the counter overflow yet. Reviewed-by: Anup Patel Signed-off-by: Atish Patra --- arch/riscv/include/asm/kvm_vcpu_pmu.h | 7 ++ arch/riscv/kvm/vcpu_pmu.c | 121 +++++++++++++++++++++++++- arch/riscv/kvm/vcpu_sbi_pmu.c | 3 + 3 files changed, 130 insertions(+), 1 deletion(-) diff --git a/arch/riscv/include/asm/kvm_vcpu_pmu.h b/arch/riscv/include/asm/kvm_vcpu_pmu.h index 395518a1664e..77a1fc4d203d 100644 --- a/arch/riscv/include/asm/kvm_vcpu_pmu.h +++ b/arch/riscv/include/asm/kvm_vcpu_pmu.h @@ -50,6 +50,10 @@ struct kvm_pmu { bool init_done; /* Bit map of all the virtual counter used */ DECLARE_BITMAP(pmc_in_use, RISCV_KVM_MAX_COUNTERS); + /* The address of the counter snapshot area (guest physical address) */ + gpa_t snapshot_addr; + /* The actual data of the snapshot */ + struct riscv_pmu_snapshot_data *sdata; }; #define vcpu_to_pmu(vcpu) (&(vcpu)->arch.pmu_context) @@ -85,6 +89,9 @@ int kvm_riscv_vcpu_pmu_ctr_cfg_match(struct kvm_vcpu *vcpu, unsigned long ctr_ba int kvm_riscv_vcpu_pmu_ctr_read(struct kvm_vcpu *vcpu, unsigned long cidx, struct kvm_vcpu_sbi_return *retdata); void kvm_riscv_vcpu_pmu_init(struct kvm_vcpu *vcpu); +int kvm_riscv_vcpu_pmu_snapshot_set_shmem(struct kvm_vcpu *vcpu, unsigned long saddr_low, + unsigned long saddr_high, unsigned long flags, + struct kvm_vcpu_sbi_return *retdata); void kvm_riscv_vcpu_pmu_deinit(struct kvm_vcpu *vcpu); void kvm_riscv_vcpu_pmu_reset(struct kvm_vcpu *vcpu); diff --git a/arch/riscv/kvm/vcpu_pmu.c b/arch/riscv/kvm/vcpu_pmu.c index 2d9929bbc2c8..f706c688b338 100644 --- a/arch/riscv/kvm/vcpu_pmu.c +++ b/arch/riscv/kvm/vcpu_pmu.c @@ -14,6 +14,7 @@ #include #include #include +#include #include #define kvm_pmu_num_counters(pmu) ((pmu)->num_hw_ctrs + (pmu)->num_fw_ctrs) @@ -311,6 +312,80 @@ int kvm_riscv_vcpu_pmu_read_hpm(struct kvm_vcpu *vcpu, unsigned int csr_num, return ret; } +static void kvm_pmu_clear_snapshot_area(struct kvm_vcpu *vcpu) +{ + struct kvm_pmu *kvpmu = vcpu_to_pmu(vcpu); + int snapshot_area_size = sizeof(struct riscv_pmu_snapshot_data); + + if (kvpmu->sdata) { + if (kvpmu->snapshot_addr != INVALID_GPA) { + memset(kvpmu->sdata, 0, snapshot_area_size); + kvm_vcpu_write_guest(vcpu, kvpmu->snapshot_addr, + kvpmu->sdata, snapshot_area_size); + } else { + pr_warn("snapshot address invalid\n"); + } + kfree(kvpmu->sdata); + kvpmu->sdata = NULL; + } + kvpmu->snapshot_addr = INVALID_GPA; +} + +int kvm_riscv_vcpu_pmu_snapshot_set_shmem(struct kvm_vcpu *vcpu, unsigned long saddr_low, + unsigned long saddr_high, unsigned long flags, + struct kvm_vcpu_sbi_return *retdata) +{ + struct kvm_pmu *kvpmu = vcpu_to_pmu(vcpu); + int snapshot_area_size = sizeof(struct riscv_pmu_snapshot_data); + int sbiret = 0; + gpa_t saddr; + unsigned long hva; + bool writable; + + if (!kvpmu || flags) { + sbiret = SBI_ERR_INVALID_PARAM; + goto out; + } + + if (saddr_low == SBI_SHMEM_DISABLE && saddr_high == SBI_SHMEM_DISABLE) { + kvm_pmu_clear_snapshot_area(vcpu); + return 0; + } + + saddr = saddr_low; + + if (saddr_high != 0) { + if (IS_ENABLED(CONFIG_32BIT)) + saddr |= ((gpa_t)saddr << 32); + else + sbiret = SBI_ERR_INVALID_ADDRESS; + goto out; + } + + hva = kvm_vcpu_gfn_to_hva_prot(vcpu, saddr >> PAGE_SHIFT, &writable); + if (kvm_is_error_hva(hva) || !writable) { + sbiret = SBI_ERR_INVALID_ADDRESS; + goto out; + } + + kvpmu->sdata = kzalloc(snapshot_area_size, GFP_ATOMIC); + if (!kvpmu->sdata) + return -ENOMEM; + + if (kvm_vcpu_write_guest(vcpu, saddr, kvpmu->sdata, snapshot_area_size)) { + kfree(kvpmu->sdata); + sbiret = SBI_ERR_FAILURE; + goto out; + } + + kvpmu->snapshot_addr = saddr; + +out: + retdata->err_val = sbiret; + + return 0; +} + int kvm_riscv_vcpu_pmu_num_ctrs(struct kvm_vcpu *vcpu, struct kvm_vcpu_sbi_return *retdata) { @@ -344,20 +419,38 @@ int kvm_riscv_vcpu_pmu_ctr_start(struct kvm_vcpu *vcpu, unsigned long ctr_base, int i, pmc_index, sbiret = 0; struct kvm_pmc *pmc; int fevent_code; + bool snap_flag_set = flags & SBI_PMU_START_FLAG_INIT_SNAPSHOT; if (kvm_pmu_validate_counter_mask(kvpmu, ctr_base, ctr_mask) < 0) { sbiret = SBI_ERR_INVALID_PARAM; goto out; } + if (snap_flag_set) { + if (kvpmu->snapshot_addr == INVALID_GPA) { + sbiret = SBI_ERR_NO_SHMEM; + goto out; + } + if (kvm_vcpu_read_guest(vcpu, kvpmu->snapshot_addr, kvpmu->sdata, + sizeof(struct riscv_pmu_snapshot_data))) { + pr_warn("Unable to read snapshot shared memory while starting counters\n"); + sbiret = SBI_ERR_FAILURE; + goto out; + } + } /* Start the counters that have been configured and requested by the guest */ for_each_set_bit(i, &ctr_mask, RISCV_MAX_COUNTERS) { pmc_index = i + ctr_base; if (!test_bit(pmc_index, kvpmu->pmc_in_use)) continue; pmc = &kvpmu->pmc[pmc_index]; - if (flags & SBI_PMU_START_FLAG_SET_INIT_VALUE) + if (flags & SBI_PMU_START_FLAG_SET_INIT_VALUE) { pmc->counter_val = ival; + } else if (snap_flag_set) { + /* The counter index in the snapshot are relative to the counter base */ + pmc->counter_val = kvpmu->sdata->ctr_values[i]; + } + if (pmc->cinfo.type == SBI_PMU_CTR_TYPE_FW) { fevent_code = get_event_code(pmc->event_idx); if (fevent_code >= SBI_PMU_FW_MAX) { @@ -398,14 +491,22 @@ int kvm_riscv_vcpu_pmu_ctr_stop(struct kvm_vcpu *vcpu, unsigned long ctr_base, { struct kvm_pmu *kvpmu = vcpu_to_pmu(vcpu); int i, pmc_index, sbiret = 0; + u64 enabled, running; struct kvm_pmc *pmc; int fevent_code; + bool snap_flag_set = flags & SBI_PMU_STOP_FLAG_TAKE_SNAPSHOT; + bool shmem_needs_update = false; if (kvm_pmu_validate_counter_mask(kvpmu, ctr_base, ctr_mask) < 0) { sbiret = SBI_ERR_INVALID_PARAM; goto out; } + if (snap_flag_set && kvpmu->snapshot_addr == INVALID_GPA) { + sbiret = SBI_ERR_NO_SHMEM; + goto out; + } + /* Stop the counters that have been configured and requested by the guest */ for_each_set_bit(i, &ctr_mask, RISCV_MAX_COUNTERS) { pmc_index = i + ctr_base; @@ -438,12 +539,28 @@ int kvm_riscv_vcpu_pmu_ctr_stop(struct kvm_vcpu *vcpu, unsigned long ctr_base, } else { sbiret = SBI_ERR_INVALID_PARAM; } + + if (snap_flag_set && !sbiret) { + if (pmc->cinfo.type == SBI_PMU_CTR_TYPE_FW) + pmc->counter_val = kvpmu->fw_event[fevent_code].value; + else if (pmc->perf_event) + pmc->counter_val += perf_event_read_value(pmc->perf_event, + &enabled, &running); + /* TODO: Add counter overflow support when sscofpmf support is added */ + kvpmu->sdata->ctr_values[i] = pmc->counter_val; + shmem_needs_update = true; + } + if (flags & SBI_PMU_STOP_FLAG_RESET) { pmc->event_idx = SBI_PMU_EVENT_IDX_INVALID; clear_bit(pmc_index, kvpmu->pmc_in_use); } } + if (shmem_needs_update) + kvm_vcpu_write_guest(vcpu, kvpmu->snapshot_addr, kvpmu->sdata, + sizeof(struct riscv_pmu_snapshot_data)); + out: retdata->err_val = sbiret; @@ -566,6 +683,7 @@ void kvm_riscv_vcpu_pmu_init(struct kvm_vcpu *vcpu) kvpmu->num_hw_ctrs = num_hw_ctrs + 1; kvpmu->num_fw_ctrs = SBI_PMU_FW_MAX; memset(&kvpmu->fw_event, 0, SBI_PMU_FW_MAX * sizeof(struct kvm_fw_event)); + kvpmu->snapshot_addr = INVALID_GPA; if (kvpmu->num_hw_ctrs > RISCV_KVM_MAX_HW_CTRS) { pr_warn_once("Limiting the hardware counters to 32 as specified by the ISA"); @@ -625,6 +743,7 @@ void kvm_riscv_vcpu_pmu_deinit(struct kvm_vcpu *vcpu) } bitmap_zero(kvpmu->pmc_in_use, RISCV_MAX_COUNTERS); memset(&kvpmu->fw_event, 0, SBI_PMU_FW_MAX * sizeof(struct kvm_fw_event)); + kvm_pmu_clear_snapshot_area(vcpu); } void kvm_riscv_vcpu_pmu_reset(struct kvm_vcpu *vcpu) diff --git a/arch/riscv/kvm/vcpu_sbi_pmu.c b/arch/riscv/kvm/vcpu_sbi_pmu.c index e1633606c98b..d3e7625fb2d2 100644 --- a/arch/riscv/kvm/vcpu_sbi_pmu.c +++ b/arch/riscv/kvm/vcpu_sbi_pmu.c @@ -64,6 +64,9 @@ static int kvm_sbi_ext_pmu_handler(struct kvm_vcpu *vcpu, struct kvm_run *run, case SBI_EXT_PMU_COUNTER_FW_READ: ret = kvm_riscv_vcpu_pmu_ctr_read(vcpu, cp->a0, retdata); break; + case SBI_EXT_PMU_SNAPSHOT_SET_SHMEM: + ret = kvm_riscv_vcpu_pmu_snapshot_set_shmem(vcpu, cp->a0, cp->a1, cp->a2, retdata); + break; default: retdata->err_val = SBI_ERR_NOT_SUPPORTED; } From patchwork Wed Apr 3 08:04:42 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Atish Kumar Patra X-Patchwork-Id: 13615253 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id A5F61CD1288 for ; Wed, 3 Apr 2024 08:05:59 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:MIME-Version:References:In-Reply-To: Message-Id:Date:Subject:Cc:To:From:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; bh=5X/gF5luUqfhhZJ8pF0k7pIJCf+dFbiZyWscLXpjRDM=; b=vuF4Pg2ZJRpcUB cHcymPhx82KU2zHR4Y+UAAkHBXBNn5AAUHmX5srWR/ujyItyPJyVdfqoihe3IHanPbQXr62DIvce3 6GlXNt1QhNHbnDlQEi6+wI2NjpDd3AcgYTcOZsB/B8wg0ulaiLZjKLB3XwkHEkpmOiaYhrxP9di63 fPqoNs5N2a323wXFXOUgPLFujtwNPT+2phAuwAjutGaLFsEO+v1LoFsjp/aYTLn5SguS9ldeAgg2h OvJ6vrPemm6V5CS658jc+hbz2JJUTKi5G4gUvU6DJaGqI3e/EQ0NYz9QwkVV3UT+D6vlsOHOq7rhi jnSlMugBLp5t3Y3K5t/A==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.97.1 #2 (Red Hat Linux)) id 1rrvd4-0000000Eixk-2IgE; Wed, 03 Apr 2024 08:05:54 +0000 Received: from casper.infradead.org ([2001:8b0:10b:1236::1]) by bombadil.infradead.org with esmtps (Exim 4.97.1 #2 (Red Hat Linux)) id 1rrvcx-0000000EirC-1klJ for linux-riscv@bombadil.infradead.org; Wed, 03 Apr 2024 08:05:47 +0000 DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=infradead.org; s=casper.20170209; h=Content-Transfer-Encoding:MIME-Version: References:In-Reply-To:Message-Id:Date:Subject:Cc:To:From:Sender:Reply-To: Content-Type:Content-ID:Content-Description; bh=rXnCfEQr49seHP/FSHmxz/iFr1Wo4k3zkXIMwp9jdU8=; b=AhgZRbyV+6+WxIw6MPNTnf1LUq skj51Y7qOHcb6eeCAyT68geQqT1eGIwm7pyr1dO2iine1VbQbpG9jCLHEV4puzbKva8+0Pq2SRWKq QK90/uDZ8dUW61FFZyf4SQN0VRxLWEZF9rC/fQkyWEYKOzR8GhhdX1/puQuYyUkUu09gnvepzB4Eu PEB8XqFr1exuwgAz9Mlo0hLr+C4HhwocO0BSlm5pj4ZMkEaeg5FW1WA1nIS2N/EDW+7DWTjabeU8T C4HXz/xyNgpS94qPatUYtFHQpKzt67eD6MZfJr0avFYYWM+Nd6Me+G4xMv59F7+f5MkIwdroTPeIR PrhPXpCQ==; Received: from mail-pl1-x635.google.com ([2607:f8b0:4864:20::635]) by casper.infradead.org with esmtps (Exim 4.97.1 #2 (Red Hat Linux)) id 1rrvcr-000000055fv-3ZIt for linux-riscv@lists.infradead.org; Wed, 03 Apr 2024 08:05:46 +0000 Received: by mail-pl1-x635.google.com with SMTP id d9443c01a7336-1e0f3052145so57208425ad.2 for ; Wed, 03 Apr 2024 01:05:41 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=rivosinc-com.20230601.gappssmtp.com; s=20230601; t=1712131539; x=1712736339; darn=lists.infradead.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=rXnCfEQr49seHP/FSHmxz/iFr1Wo4k3zkXIMwp9jdU8=; b=HCfgy2AUpwuG0dwuGq7okKSabNXeqzgaDLk162+TAbnFDxh7wyP7w8V7F3o0vj3A+j QjY2bcweQEE57dmFGk87kqHUHgSBaVA7/AJ1ETMyZsJYG7QK29HF9HJMvY5CYYAKdHwQ RFlFLZBLZ1CYQXdRrH/DFP/Yubv6vogIi/RYfPs5aliBNX2Ctu6rlnWlKZObivaNGi3J GXimQD0LxDyX3k3j9FhMn27Xv2bYFtUfAhi3AQ3TEXQlAk1tW2NF/G4FEQxEFSNB8Ke0 G6Mbn+LyO6EC52PdkJ2ziOmzkyKQCLx4HFvnak+fOiyBOD0gymFT33m1o98x59DXckr8 lX6g== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1712131539; x=1712736339; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=rXnCfEQr49seHP/FSHmxz/iFr1Wo4k3zkXIMwp9jdU8=; b=aU7HYOs4A5WtTOJxHh1jGGgUpVMM7h7+JROL3bfki4fQxMgsRvkCmICXm5PnhNgqF+ AQpfguLGc3gAqNm7rTyr8pEBsBRK7rUjN95wDW3bGB+qlTUi41MS/QpdYWXWK6gwIpXZ dRNEhzq1JHcqRuLSWADXULj1VGCn5jpVpxlmokJKyOZnpuEaB8EC4/Oa53l0M8AIyqP4 yHbGGte/hQ12LblELS0HhBtTPol3PRmuqJa2Bg/ehsvK5P9laPzUIyVTLDdK3IG8ZCwS W3p3ZfoBih9tiUNLEdmJNLCqTg3rIF7GbGZenr88ZLln2fHrxaSxD9Bhz2y7vE970+x4 /TDg== X-Forwarded-Encrypted: i=1; AJvYcCWEm5w0cRLBu8ReD2QdxOxD6vMPh08DTT4QL5AX8GiS7m+nPwM7ejQfGtkvs5KL/T6JssuZYlqbHUi6gx5LjPf5BLAr3sUHCLkiapvWjsHI X-Gm-Message-State: AOJu0Yx3HNy7FZMGeXBCwb4vZGw4URWwV9X5tVmKh4H9fmIk+bTv7L/X VdcOXcri5KNLSIZYOQ0hkmjjIs94HCxAmhcUDCeH2rnT9n7frC2+BrCgHeqUkN4= X-Google-Smtp-Source: AGHT+IEKAQtLJdG29phCvANRsKDlhQNvytpbUBwT9LiLceHxJiumwFb6nYVGbmAmgyUeS4Et5t4rgw== X-Received: by 2002:a17:902:eac2:b0:1e2:9ddc:f620 with SMTP id p2-20020a170902eac200b001e29ddcf620mr7808pld.23.1712131539180; Wed, 03 Apr 2024 01:05:39 -0700 (PDT) Received: from atishp.ba.rivosinc.com ([64.71.180.162]) by smtp.gmail.com with ESMTPSA id c12-20020a170902d48c00b001e0b5d49fc7sm12557229plg.161.2024.04.03.01.05.37 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 03 Apr 2024 01:05:38 -0700 (PDT) From: Atish Patra To: linux-kernel@vger.kernel.org Cc: Atish Patra , Anup Patel , Ajay Kaher , Alexandre Ghiti , Alexey Makhalov , Andrew Jones , Conor Dooley , Juergen Gross , kvm-riscv@lists.infradead.org, kvm@vger.kernel.org, linux-kselftest@vger.kernel.org, linux-riscv@lists.infradead.org, Mark Rutland , Palmer Dabbelt , Paolo Bonzini , Paul Walmsley , Shuah Khan , virtualization@lists.linux.dev, VMware PV-Drivers Reviewers , Will Deacon , x86@kernel.org Subject: [PATCH v5 13/22] RISC-V: KVM: Add perf sampling support for guests Date: Wed, 3 Apr 2024 01:04:42 -0700 Message-Id: <20240403080452.1007601-14-atishp@rivosinc.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240403080452.1007601-1-atishp@rivosinc.com> References: <20240403080452.1007601-1-atishp@rivosinc.com> MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20240403_090541_956884_F28C80AE X-CRM114-Status: GOOD ( 24.32 ) X-BeenThere: linux-riscv@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-riscv" Errors-To: linux-riscv-bounces+linux-riscv=archiver.kernel.org@lists.infradead.org KVM enables perf for guest via counter virtualization. However, the sampling can not be supported as there is no mechanism to enabled trap/emulate scountovf in ISA yet. Rely on the SBI PMU snapshot to provide the counter overflow data via the shared memory. In case of sampling event, the host first sets the guest's LCOFI interrupt and injects to the guest via irq filtering mechanism defined in AIA specification. Thus, ssaia must be enabled in the host in order to use perf sampling in the guest. No other AIA dependency w.r.t kernel is required. Reviewed-by: Anup Patel Signed-off-by: Atish Patra --- arch/riscv/include/asm/csr.h | 3 +- arch/riscv/include/asm/kvm_vcpu_pmu.h | 3 ++ arch/riscv/include/uapi/asm/kvm.h | 1 + arch/riscv/kvm/aia.c | 5 ++ arch/riscv/kvm/vcpu.c | 15 ++++-- arch/riscv/kvm/vcpu_onereg.c | 5 ++ arch/riscv/kvm/vcpu_pmu.c | 68 +++++++++++++++++++++++++-- 7 files changed, 92 insertions(+), 8 deletions(-) diff --git a/arch/riscv/include/asm/csr.h b/arch/riscv/include/asm/csr.h index 9d1b07932794..25966995da04 100644 --- a/arch/riscv/include/asm/csr.h +++ b/arch/riscv/include/asm/csr.h @@ -168,7 +168,8 @@ #define VSIP_TO_HVIP_SHIFT (IRQ_VS_SOFT - IRQ_S_SOFT) #define VSIP_VALID_MASK ((_AC(1, UL) << IRQ_S_SOFT) | \ (_AC(1, UL) << IRQ_S_TIMER) | \ - (_AC(1, UL) << IRQ_S_EXT)) + (_AC(1, UL) << IRQ_S_EXT) | \ + (_AC(1, UL) << IRQ_PMU_OVF)) /* AIA CSR bits */ #define TOPI_IID_SHIFT 16 diff --git a/arch/riscv/include/asm/kvm_vcpu_pmu.h b/arch/riscv/include/asm/kvm_vcpu_pmu.h index 77a1fc4d203d..257f17641e00 100644 --- a/arch/riscv/include/asm/kvm_vcpu_pmu.h +++ b/arch/riscv/include/asm/kvm_vcpu_pmu.h @@ -36,6 +36,7 @@ struct kvm_pmc { bool started; /* Monitoring event ID */ unsigned long event_idx; + struct kvm_vcpu *vcpu; }; /* PMU data structure per vcpu */ @@ -50,6 +51,8 @@ struct kvm_pmu { bool init_done; /* Bit map of all the virtual counter used */ DECLARE_BITMAP(pmc_in_use, RISCV_KVM_MAX_COUNTERS); + /* Bit map of all the virtual counter overflown */ + DECLARE_BITMAP(pmc_overflown, RISCV_KVM_MAX_COUNTERS); /* The address of the counter snapshot area (guest physical address) */ gpa_t snapshot_addr; /* The actual data of the snapshot */ diff --git a/arch/riscv/include/uapi/asm/kvm.h b/arch/riscv/include/uapi/asm/kvm.h index b1c503c2959c..e878e7cc3978 100644 --- a/arch/riscv/include/uapi/asm/kvm.h +++ b/arch/riscv/include/uapi/asm/kvm.h @@ -167,6 +167,7 @@ enum KVM_RISCV_ISA_EXT_ID { KVM_RISCV_ISA_EXT_ZFA, KVM_RISCV_ISA_EXT_ZTSO, KVM_RISCV_ISA_EXT_ZACAS, + KVM_RISCV_ISA_EXT_SSCOFPMF, KVM_RISCV_ISA_EXT_MAX, }; diff --git a/arch/riscv/kvm/aia.c b/arch/riscv/kvm/aia.c index a944294f6f23..0f0a9d11bb5f 100644 --- a/arch/riscv/kvm/aia.c +++ b/arch/riscv/kvm/aia.c @@ -545,6 +545,9 @@ void kvm_riscv_aia_enable(void) enable_percpu_irq(hgei_parent_irq, irq_get_trigger_type(hgei_parent_irq)); csr_set(CSR_HIE, BIT(IRQ_S_GEXT)); + /* Enable IRQ filtering for overflow interrupt only if sscofpmf is present */ + if (__riscv_isa_extension_available(NULL, RISCV_ISA_EXT_SSCOFPMF)) + csr_write(CSR_HVIEN, BIT(IRQ_PMU_OVF)); } void kvm_riscv_aia_disable(void) @@ -558,6 +561,8 @@ void kvm_riscv_aia_disable(void) return; hgctrl = get_cpu_ptr(&aia_hgei); + if (__riscv_isa_extension_available(NULL, RISCV_ISA_EXT_SSCOFPMF)) + csr_clear(CSR_HVIEN, BIT(IRQ_PMU_OVF)); /* Disable per-CPU SGEI interrupt */ csr_clear(CSR_HIE, BIT(IRQ_S_GEXT)); disable_percpu_irq(hgei_parent_irq); diff --git a/arch/riscv/kvm/vcpu.c b/arch/riscv/kvm/vcpu.c index b5ca9f2e98ac..bb10771b2b18 100644 --- a/arch/riscv/kvm/vcpu.c +++ b/arch/riscv/kvm/vcpu.c @@ -365,6 +365,13 @@ void kvm_riscv_vcpu_sync_interrupts(struct kvm_vcpu *vcpu) } } + /* Sync up the HVIP.LCOFIP bit changes (only clear) by the guest */ + if ((csr->hvip ^ hvip) & (1UL << IRQ_PMU_OVF)) { + if (!(hvip & (1UL << IRQ_PMU_OVF)) && + !test_and_set_bit(IRQ_PMU_OVF, v->irqs_pending_mask)) + clear_bit(IRQ_PMU_OVF, v->irqs_pending); + } + /* Sync-up AIA high interrupts */ kvm_riscv_vcpu_aia_sync_interrupts(vcpu); @@ -382,7 +389,8 @@ int kvm_riscv_vcpu_set_interrupt(struct kvm_vcpu *vcpu, unsigned int irq) if (irq < IRQ_LOCAL_MAX && irq != IRQ_VS_SOFT && irq != IRQ_VS_TIMER && - irq != IRQ_VS_EXT) + irq != IRQ_VS_EXT && + irq != IRQ_PMU_OVF) return -EINVAL; set_bit(irq, vcpu->arch.irqs_pending); @@ -397,14 +405,15 @@ int kvm_riscv_vcpu_set_interrupt(struct kvm_vcpu *vcpu, unsigned int irq) int kvm_riscv_vcpu_unset_interrupt(struct kvm_vcpu *vcpu, unsigned int irq) { /* - * We only allow VS-mode software, timer, and external + * We only allow VS-mode software, timer, counter overflow and external * interrupts when irq is one of the local interrupts * defined by RISC-V privilege specification. */ if (irq < IRQ_LOCAL_MAX && irq != IRQ_VS_SOFT && irq != IRQ_VS_TIMER && - irq != IRQ_VS_EXT) + irq != IRQ_VS_EXT && + irq != IRQ_PMU_OVF) return -EINVAL; clear_bit(irq, vcpu->arch.irqs_pending); diff --git a/arch/riscv/kvm/vcpu_onereg.c b/arch/riscv/kvm/vcpu_onereg.c index f4a6124d25c9..4da4ed899104 100644 --- a/arch/riscv/kvm/vcpu_onereg.c +++ b/arch/riscv/kvm/vcpu_onereg.c @@ -36,6 +36,7 @@ static const unsigned long kvm_isa_ext_arr[] = { /* Multi letter extensions (alphabetically sorted) */ KVM_ISA_EXT_ARR(SMSTATEEN), KVM_ISA_EXT_ARR(SSAIA), + KVM_ISA_EXT_ARR(SSCOFPMF), KVM_ISA_EXT_ARR(SSTC), KVM_ISA_EXT_ARR(SVINVAL), KVM_ISA_EXT_ARR(SVNAPOT), @@ -101,6 +102,9 @@ static bool kvm_riscv_vcpu_isa_enable_allowed(unsigned long ext) return false; case KVM_RISCV_ISA_EXT_V: return riscv_v_vstate_ctrl_user_allowed(); + case KVM_RISCV_ISA_EXT_SSCOFPMF: + /* Sscofpmf depends on interrupt filtering defined in ssaia */ + return __riscv_isa_extension_available(NULL, RISCV_ISA_EXT_SSAIA); default: break; } @@ -116,6 +120,7 @@ static bool kvm_riscv_vcpu_isa_disable_allowed(unsigned long ext) case KVM_RISCV_ISA_EXT_C: case KVM_RISCV_ISA_EXT_I: case KVM_RISCV_ISA_EXT_M: + case KVM_RISCV_ISA_EXT_SSCOFPMF: case KVM_RISCV_ISA_EXT_SSTC: case KVM_RISCV_ISA_EXT_SVINVAL: case KVM_RISCV_ISA_EXT_SVNAPOT: diff --git a/arch/riscv/kvm/vcpu_pmu.c b/arch/riscv/kvm/vcpu_pmu.c index f706c688b338..9fedf9dc498b 100644 --- a/arch/riscv/kvm/vcpu_pmu.c +++ b/arch/riscv/kvm/vcpu_pmu.c @@ -230,6 +230,47 @@ static int kvm_pmu_validate_counter_mask(struct kvm_pmu *kvpmu, unsigned long ct return 0; } +static void kvm_riscv_pmu_overflow(struct perf_event *perf_event, + struct perf_sample_data *data, + struct pt_regs *regs) +{ + struct kvm_pmc *pmc = perf_event->overflow_handler_context; + struct kvm_vcpu *vcpu = pmc->vcpu; + struct kvm_pmu *kvpmu = vcpu_to_pmu(vcpu); + struct riscv_pmu *rpmu = to_riscv_pmu(perf_event->pmu); + u64 period; + + /* + * Stop the event counting by directly accessing the perf_event. + * Otherwise, this needs to deferred via a workqueue. + * That will introduce skew in the counter value because the actual + * physical counter would start after returning from this function. + * It will be stopped again once the workqueue is scheduled + */ + rpmu->pmu.stop(perf_event, PERF_EF_UPDATE); + + /* + * The hw counter would start automatically when this function returns. + * Thus, the host may continue to interrupt and inject it to the guest + * even without the guest configuring the next event. Depending on the hardware + * the host may have some sluggishness only if privilege mode filtering is not + * available. In an ideal world, where qemu is not the only capable hardware, + * this can be removed. + * FYI: ARM64 does this way while x86 doesn't do anything as such. + * TODO: Should we keep it for RISC-V ? + */ + period = -(local64_read(&perf_event->count)); + + local64_set(&perf_event->hw.period_left, 0); + perf_event->attr.sample_period = period; + perf_event->hw.sample_period = period; + + set_bit(pmc->idx, kvpmu->pmc_overflown); + kvm_riscv_vcpu_set_interrupt(vcpu, IRQ_PMU_OVF); + + rpmu->pmu.start(perf_event, PERF_EF_RELOAD); +} + static long kvm_pmu_create_perf_event(struct kvm_pmc *pmc, struct perf_event_attr *attr, unsigned long flags, unsigned long eidx, unsigned long evtdata) @@ -249,7 +290,7 @@ static long kvm_pmu_create_perf_event(struct kvm_pmc *pmc, struct perf_event_att */ attr->sample_period = kvm_pmu_get_sample_period(pmc); - event = perf_event_create_kernel_counter(attr, -1, current, NULL, pmc); + event = perf_event_create_kernel_counter(attr, -1, current, kvm_riscv_pmu_overflow, pmc); if (IS_ERR(event)) { pr_err("kvm pmu event creation failed for eidx %lx: %ld\n", eidx, PTR_ERR(event)); return PTR_ERR(event); @@ -443,6 +484,8 @@ int kvm_riscv_vcpu_pmu_ctr_start(struct kvm_vcpu *vcpu, unsigned long ctr_base, pmc_index = i + ctr_base; if (!test_bit(pmc_index, kvpmu->pmc_in_use)) continue; + /* The guest started the counter again. Reset the overflow status */ + clear_bit(pmc_index, kvpmu->pmc_overflown); pmc = &kvpmu->pmc[pmc_index]; if (flags & SBI_PMU_START_FLAG_SET_INIT_VALUE) { pmc->counter_val = ival; @@ -546,7 +589,13 @@ int kvm_riscv_vcpu_pmu_ctr_stop(struct kvm_vcpu *vcpu, unsigned long ctr_base, else if (pmc->perf_event) pmc->counter_val += perf_event_read_value(pmc->perf_event, &enabled, &running); - /* TODO: Add counter overflow support when sscofpmf support is added */ + /* + * The counter and overflow indicies in the snapshot region are w.r.to + * cbase. Modify the set bit in the counter mask instead of the pmc_index + * which indicates the absolute counter index. + */ + if (test_bit(pmc_index, kvpmu->pmc_overflown)) + kvpmu->sdata->ctr_overflow_mask |= BIT(i); kvpmu->sdata->ctr_values[i] = pmc->counter_val; shmem_needs_update = true; } @@ -554,6 +603,15 @@ int kvm_riscv_vcpu_pmu_ctr_stop(struct kvm_vcpu *vcpu, unsigned long ctr_base, if (flags & SBI_PMU_STOP_FLAG_RESET) { pmc->event_idx = SBI_PMU_EVENT_IDX_INVALID; clear_bit(pmc_index, kvpmu->pmc_in_use); + clear_bit(pmc_index, kvpmu->pmc_overflown); + if (snap_flag_set) { + /* + * Only clear the given counter as the caller is responsible to + * validate both the overflow mask and configured counters. + */ + kvpmu->sdata->ctr_overflow_mask &= ~BIT(i); + shmem_needs_update = true; + } } } @@ -703,6 +761,7 @@ void kvm_riscv_vcpu_pmu_init(struct kvm_vcpu *vcpu) pmc = &kvpmu->pmc[i]; pmc->idx = i; pmc->event_idx = SBI_PMU_EVENT_IDX_INVALID; + pmc->vcpu = vcpu; if (i < kvpmu->num_hw_ctrs) { pmc->cinfo.type = SBI_PMU_CTR_TYPE_HW; if (i < 3) @@ -735,13 +794,14 @@ void kvm_riscv_vcpu_pmu_deinit(struct kvm_vcpu *vcpu) if (!kvpmu) return; - for_each_set_bit(i, kvpmu->pmc_in_use, RISCV_MAX_COUNTERS) { + for_each_set_bit(i, kvpmu->pmc_in_use, RISCV_KVM_MAX_COUNTERS) { pmc = &kvpmu->pmc[i]; pmc->counter_val = 0; kvm_pmu_release_perf_event(pmc); pmc->event_idx = SBI_PMU_EVENT_IDX_INVALID; } - bitmap_zero(kvpmu->pmc_in_use, RISCV_MAX_COUNTERS); + bitmap_zero(kvpmu->pmc_in_use, RISCV_KVM_MAX_COUNTERS); + bitmap_zero(kvpmu->pmc_overflown, RISCV_KVM_MAX_COUNTERS); memset(&kvpmu->fw_event, 0, SBI_PMU_FW_MAX * sizeof(struct kvm_fw_event)); kvm_pmu_clear_snapshot_area(vcpu); } From patchwork Wed Apr 3 08:04:43 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Atish Kumar Patra X-Patchwork-Id: 13615257 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id C3A7BCD1288 for ; Wed, 3 Apr 2024 08:06:16 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:MIME-Version:References:In-Reply-To: Message-Id:Date:Subject:Cc:To:From:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; bh=bCcf8jb+pVHZlTUTHJDCfnIhosxjSv/OP3jkJ5ocQv4=; b=SEELAnLqh+xfTv JGN6TDo5YCG1TTSHXGzGwl+fN2W0rEG8U7cgg1rKMW30ejlyTC/HM6THbYQY9wdBZY2wem+BqFI4F XxUkdw0t0TC8m0zPdBwVB7EwQACQdRxjckEog7vwO81RE/qF81i/UdobeHsdbcjE7CUzuE8lmhRUQ Iqaui4z8Gm7qg14Rn5bckRt1FZhr8Ngo66vAFU5gmVHDtWveZ11gQycJ+LlbcA46deg03Jay9DZbF R60ze30YX8WBFhthfTyTC4KwPd2+4x8fFpj3rXLHX+8k6vgUDkKoEnk0wxtDxSMmsvVX6TjRjTLfs oD414bGR9oCPcPwQHb1A==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.97.1 #2 (Red Hat Linux)) id 1rrvdL-0000000EjDr-0DvI; Wed, 03 Apr 2024 08:06:11 +0000 Received: from mail-pf1-x42a.google.com ([2607:f8b0:4864:20::42a]) by bombadil.infradead.org with esmtps (Exim 4.97.1 #2 (Red Hat Linux)) id 1rrvcw-0000000EimT-1cJT for linux-riscv@lists.infradead.org; Wed, 03 Apr 2024 08:05:51 +0000 Received: by mail-pf1-x42a.google.com with SMTP id d2e1a72fcca58-6e7425a6714so4993774b3a.0 for ; Wed, 03 Apr 2024 01:05:41 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=rivosinc-com.20230601.gappssmtp.com; s=20230601; t=1712131541; x=1712736341; darn=lists.infradead.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=aZ3FkBLSpZeB7lcfW0sTr11VliYr1a02KCqdXY16nx8=; b=YnHHAEss1uxFuDWlxAd0Q8xkO/BeGHd22i+8BkEKTUowuQItBxOVqOi2S5c/UPsfy+ VJ/zZC3fG5p3SMgzhQHhAiXexHZg+0rNkpcx7OSyFz3GME0JAivoIdO+FTO3+i3SRppc KqTUgsRXoo/cZmflvBgVPvRoZHjGVUyqSy7kdFpj0qLJXYGzLwV1uDQFu+EH6J3+yWB6 gjnj0ALHNUVmcaEMzwX3fFc4GvwHLNs5HQ1QgMRg2VAR6xrrGnJgIk41e5t4cF0G1d3U 2yP/USgQFQSan06LvnAnLSNtWm0D6ICK+aD41Mcl8HsXiZ86JdANTSq6Zz/Du4YYQ4+S OLdw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1712131541; x=1712736341; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=aZ3FkBLSpZeB7lcfW0sTr11VliYr1a02KCqdXY16nx8=; b=MF+4AcJWdQXf14xZTXVUDCa0jddck434/hDa8VOkrStHZ0oXbIhO2Mxz+/WPCIFGX1 CsDZBwi0E3zs6QLu86dRAbS9V7UrbsqeQEYkKRO4YyNPeftfblS5BpDKZrAXf+hEblr2 H/OcAlY6nlRYI6pFcaqaHhmDwXC7EFdaNqXb4SGdqClE97NURTPsHd3qa4Dx4CAP4/gp PJkrgLtZz8EbVjpYZZRg9IKffDMZ32gbTuyuPTbhsTk87HZuqzlWHfRNtmK0cLpcW1yD qe3zE87eOvcdMGXaCD6JpqkMhSRo+VoCcP6T94eC/zZ8B6Ei1SZyPUSAzmAeOWu3CsTi JXdQ== X-Forwarded-Encrypted: i=1; AJvYcCUflZffF9aQcuKcbucMOBXeeMK4mhNvW0PxHsIt+THR1WWgWgABP+60kHseZDKnr7XRoySb25eh01iBfcw2uqnHFEdZwSJ1SBOPM327UZHC X-Gm-Message-State: AOJu0YxkKWWlHuUehtI41gQSCsnelWzSnSpf5l6Dx5Q+8vbLTEJj0fP7 taG7Uu1AofF5sjbGuBbQwXUxinTwr+0OVLSStyLPNKUPDkRGJOWpEAZ/OiP4Ekw= X-Google-Smtp-Source: AGHT+IEAq+anA/aMtiO8arRrh2Jnm92J1PBH5kUlEvdhS5op/jw7hZzAqhRtuwLXN5Zk3guWOTaagw== X-Received: by 2002:a05:6a20:9e4c:b0:1a3:ca3c:c62b with SMTP id mt12-20020a056a209e4c00b001a3ca3cc62bmr17369882pzb.19.1712131541148; Wed, 03 Apr 2024 01:05:41 -0700 (PDT) Received: from atishp.ba.rivosinc.com ([64.71.180.162]) by smtp.gmail.com with ESMTPSA id c12-20020a170902d48c00b001e0b5d49fc7sm12557229plg.161.2024.04.03.01.05.39 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 03 Apr 2024 01:05:40 -0700 (PDT) From: Atish Patra To: linux-kernel@vger.kernel.org Cc: Atish Patra , Anup Patel , Ajay Kaher , Alexandre Ghiti , Alexey Makhalov , Andrew Jones , Conor Dooley , Juergen Gross , kvm-riscv@lists.infradead.org, kvm@vger.kernel.org, linux-kselftest@vger.kernel.org, linux-riscv@lists.infradead.org, Mark Rutland , Palmer Dabbelt , Paolo Bonzini , Paul Walmsley , Shuah Khan , virtualization@lists.linux.dev, VMware PV-Drivers Reviewers , Will Deacon , x86@kernel.org Subject: [PATCH v5 14/22] RISC-V: KVM: Support 64 bit firmware counters on RV32 Date: Wed, 3 Apr 2024 01:04:43 -0700 Message-Id: <20240403080452.1007601-15-atishp@rivosinc.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240403080452.1007601-1-atishp@rivosinc.com> References: <20240403080452.1007601-1-atishp@rivosinc.com> MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20240403_010546_593505_8F2636CC X-CRM114-Status: GOOD ( 16.97 ) X-BeenThere: linux-riscv@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-riscv" Errors-To: linux-riscv-bounces+linux-riscv=archiver.kernel.org@lists.infradead.org The SBI v2.0 introduced a fw_read_hi function to read 64 bit firmware counters for RV32 based systems. Add infrastructure to support that. Reviewed-by: Anup Patel Signed-off-by: Atish Patra Reviewed-by: Andrew Jones --- arch/riscv/include/asm/kvm_vcpu_pmu.h | 4 ++- arch/riscv/kvm/vcpu_pmu.c | 44 ++++++++++++++++++++++++++- arch/riscv/kvm/vcpu_sbi_pmu.c | 6 ++++ 3 files changed, 52 insertions(+), 2 deletions(-) diff --git a/arch/riscv/include/asm/kvm_vcpu_pmu.h b/arch/riscv/include/asm/kvm_vcpu_pmu.h index 257f17641e00..55861b5d3382 100644 --- a/arch/riscv/include/asm/kvm_vcpu_pmu.h +++ b/arch/riscv/include/asm/kvm_vcpu_pmu.h @@ -20,7 +20,7 @@ static_assert(RISCV_KVM_MAX_COUNTERS <= 64); struct kvm_fw_event { /* Current value of the event */ - unsigned long value; + u64 value; /* Event monitoring status */ bool started; @@ -91,6 +91,8 @@ int kvm_riscv_vcpu_pmu_ctr_cfg_match(struct kvm_vcpu *vcpu, unsigned long ctr_ba struct kvm_vcpu_sbi_return *retdata); int kvm_riscv_vcpu_pmu_ctr_read(struct kvm_vcpu *vcpu, unsigned long cidx, struct kvm_vcpu_sbi_return *retdata); +int kvm_riscv_vcpu_pmu_fw_ctr_read_hi(struct kvm_vcpu *vcpu, unsigned long cidx, + struct kvm_vcpu_sbi_return *retdata); void kvm_riscv_vcpu_pmu_init(struct kvm_vcpu *vcpu); int kvm_riscv_vcpu_pmu_snapshot_set_shmem(struct kvm_vcpu *vcpu, unsigned long saddr_low, unsigned long saddr_high, unsigned long flags, diff --git a/arch/riscv/kvm/vcpu_pmu.c b/arch/riscv/kvm/vcpu_pmu.c index 9fedf9dc498b..ff326152eeff 100644 --- a/arch/riscv/kvm/vcpu_pmu.c +++ b/arch/riscv/kvm/vcpu_pmu.c @@ -197,6 +197,36 @@ static int pmu_get_pmc_index(struct kvm_pmu *pmu, unsigned long eidx, return kvm_pmu_get_programmable_pmc_index(pmu, eidx, cbase, cmask); } +static int pmu_fw_ctr_read_hi(struct kvm_vcpu *vcpu, unsigned long cidx, + unsigned long *out_val) +{ + struct kvm_pmu *kvpmu = vcpu_to_pmu(vcpu); + struct kvm_pmc *pmc; + int fevent_code; + + if (!IS_ENABLED(CONFIG_32BIT)) { + pr_warn("%s: should be invoked for only RV32\n", __func__); + return -EINVAL; + } + + if (cidx >= kvm_pmu_num_counters(kvpmu) || cidx == 1) { + pr_warn("Invalid counter id [%ld]during read\n", cidx); + return -EINVAL; + } + + pmc = &kvpmu->pmc[cidx]; + + if (pmc->cinfo.type != SBI_PMU_CTR_TYPE_FW) + return -EINVAL; + + fevent_code = get_event_code(pmc->event_idx); + pmc->counter_val = kvpmu->fw_event[fevent_code].value; + + *out_val = pmc->counter_val >> 32; + + return 0; +} + static int pmu_ctr_read(struct kvm_vcpu *vcpu, unsigned long cidx, unsigned long *out_val) { @@ -705,6 +735,18 @@ int kvm_riscv_vcpu_pmu_ctr_cfg_match(struct kvm_vcpu *vcpu, unsigned long ctr_ba return 0; } +int kvm_riscv_vcpu_pmu_fw_ctr_read_hi(struct kvm_vcpu *vcpu, unsigned long cidx, + struct kvm_vcpu_sbi_return *retdata) +{ + int ret; + + ret = pmu_fw_ctr_read_hi(vcpu, cidx, &retdata->out_val); + if (ret == -EINVAL) + retdata->err_val = SBI_ERR_INVALID_PARAM; + + return 0; +} + int kvm_riscv_vcpu_pmu_ctr_read(struct kvm_vcpu *vcpu, unsigned long cidx, struct kvm_vcpu_sbi_return *retdata) { @@ -778,7 +820,7 @@ void kvm_riscv_vcpu_pmu_init(struct kvm_vcpu *vcpu) pmc->cinfo.csr = CSR_CYCLE + i; } else { pmc->cinfo.type = SBI_PMU_CTR_TYPE_FW; - pmc->cinfo.width = BITS_PER_LONG - 1; + pmc->cinfo.width = 63; } } diff --git a/arch/riscv/kvm/vcpu_sbi_pmu.c b/arch/riscv/kvm/vcpu_sbi_pmu.c index d3e7625fb2d2..cf111de51bdb 100644 --- a/arch/riscv/kvm/vcpu_sbi_pmu.c +++ b/arch/riscv/kvm/vcpu_sbi_pmu.c @@ -64,6 +64,12 @@ static int kvm_sbi_ext_pmu_handler(struct kvm_vcpu *vcpu, struct kvm_run *run, case SBI_EXT_PMU_COUNTER_FW_READ: ret = kvm_riscv_vcpu_pmu_ctr_read(vcpu, cp->a0, retdata); break; + case SBI_EXT_PMU_COUNTER_FW_READ_HI: + if (IS_ENABLED(CONFIG_32BIT)) + ret = kvm_riscv_vcpu_pmu_fw_ctr_read_hi(vcpu, cp->a0, retdata); + else + retdata->out_val = 0; + break; case SBI_EXT_PMU_SNAPSHOT_SET_SHMEM: ret = kvm_riscv_vcpu_pmu_snapshot_set_shmem(vcpu, cp->a0, cp->a1, cp->a2, retdata); break; From patchwork Wed Apr 3 08:04:44 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Atish Kumar Patra X-Patchwork-Id: 13615254 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 04EADCD1288 for ; Wed, 3 Apr 2024 08:06:05 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:MIME-Version:References:In-Reply-To: Message-Id:Date:Subject:Cc:To:From:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; bh=TepjqFiB/wiOebsiHhAuP8NVGwi7FX73QEkvT+3KLYY=; b=QlpIN2X0Lk1lY0 KJpgUEiXQZ8JhHlo02tbLWW5k/4qMHUAKfxIneyzbcKK6nqrXH3GUJQg5jqlUbnU8JQfSpKmpAIW3 mF8hLOXkAfY/JjzZjlU3s/VW5tmTA4JQ8tOBN48OM8m89EY2OX4mmc9bDN6WGmRTNIyTpK1ptCusc ryz/JbNuphDu3AKKI0b6yStKcZ+joqXCpsmaYQUrwGC6eecrFWIlxpLZNZzEEWI7Gz9sJDUapnHQW DLd9MPewU2afdC5GiKKfb/unxfRHr3Rv7+n6lmYgnfrwqFiIHOB6WFKDWFVmK5mr7ttRvHRvMi/JG +fmb0sUXE/aBMsSRyXRQ==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.97.1 #2 (Red Hat Linux)) id 1rrvd8-0000000Ej1n-2YQY; Wed, 03 Apr 2024 08:05:58 +0000 Received: from mail-pl1-x636.google.com ([2607:f8b0:4864:20::636]) by bombadil.infradead.org with esmtps (Exim 4.97.1 #2 (Red Hat Linux)) id 1rrvcv-0000000EinU-2SAu for linux-riscv@lists.infradead.org; Wed, 03 Apr 2024 08:05:48 +0000 Received: by mail-pl1-x636.google.com with SMTP id d9443c01a7336-1e252f2bf23so24491185ad.2 for ; Wed, 03 Apr 2024 01:05:43 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=rivosinc-com.20230601.gappssmtp.com; s=20230601; t=1712131543; x=1712736343; darn=lists.infradead.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=qwALXHKqCD9Iy5mIzImMbfILjpXmZkM44DIWXWIBe7w=; b=sD7UeOVLa771f4kLZcyhcrwrabBOL+pGjbTi6M6Jtfhrwxb8uIsyniif9OjhUVRkpZ jkaa8h05Ly43DbA+UPwO3cAJTc1wsxeL7yWQylctcrdSZsIPqlwY81SeoSbbZjsvWozz rEd6k0qFsnBf75cix6Xms92oPCEwNvFW+mzaMoLYKkNd2iTwis9c9qnJ6KKNsTmqg5mj Fh9Wq0qMN1ahct+pTFS9f5eeF1NIokpXL4bq3QESiIDn97ZIS3gYZ0GOOevcUmKI5sW7 0YdDzmO821U4NmBH+ECFE/1wmTCI5MOth3v5EHfmk6mNIAlcwLdvzGBb2WacHUhio2fL w/ZA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1712131543; x=1712736343; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=qwALXHKqCD9Iy5mIzImMbfILjpXmZkM44DIWXWIBe7w=; b=vqcx5Xg0RCs2kv1G4ex/sfBZz9/ui9EGiT6/UJYOFi4EyQkVM3dcHW31lUjst5dpy2 3/gv/8ExnEZNo9HiX0vVATZpmtIXZGf48T8Wwll/Ec42UFYpHsAIM/xKbpQSRfa1IkJv rPiB7dGg51hegMtHOD7+R00EzHpevfqRPYorR9ure2MhoazFczwcZDgZqpmgn8fL5jat gwztx6YXW8ld+xoccRN99wnDRetHbVKdcBqt0SV3fABj8ah5Vl1mLnvr/KMTF0637ifm xxbGsyTsvLDhCHg4bqKLgVxHyQKQKVkm4RkRZ1dk5/EveGvZtEV5Ke4P2QcTf2kPN4R+ pm2w== X-Forwarded-Encrypted: i=1; AJvYcCVSPGE0qGQJ2DP6gtBsurSwpeTB26oijJKbhNRPC2fE7WSvk6CdSiZRm7Ii/v+87ik6iH8uEmfW9/LnT99KbaYJZY68HqhCmPSBoW3oK9t8 X-Gm-Message-State: AOJu0Yxw1STgX85A8rsKi8TQjZ8aUv8TCfQ87y/l5hd5rz8vsjbRV5YJ bQYskDEWYN55ZN22mWPbMWjj7tLftKbKS9x7tP4zh4GlsYC1D/FHQw00pRWpT/Q= X-Google-Smtp-Source: AGHT+IFqbJuXOQnG+Kx5BB+hJvgv/ZybZvtn14tS9BuaWyH/U/F2Vi2RSE0rwqy3IKMxLYQ7u8QtTQ== X-Received: by 2002:a17:903:2283:b0:1e0:b60e:1a33 with SMTP id b3-20020a170903228300b001e0b60e1a33mr2264737plh.31.1712131543069; Wed, 03 Apr 2024 01:05:43 -0700 (PDT) Received: from atishp.ba.rivosinc.com ([64.71.180.162]) by smtp.gmail.com with ESMTPSA id c12-20020a170902d48c00b001e0b5d49fc7sm12557229plg.161.2024.04.03.01.05.41 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 03 Apr 2024 01:05:42 -0700 (PDT) From: Atish Patra To: linux-kernel@vger.kernel.org Cc: Atish Patra , Ajay Kaher , Alexandre Ghiti , Alexey Makhalov , Andrew Jones , Anup Patel , Conor Dooley , Juergen Gross , kvm-riscv@lists.infradead.org, kvm@vger.kernel.org, linux-kselftest@vger.kernel.org, linux-riscv@lists.infradead.org, Mark Rutland , Palmer Dabbelt , Paolo Bonzini , Paul Walmsley , Shuah Khan , virtualization@lists.linux.dev, VMware PV-Drivers Reviewers , Will Deacon , x86@kernel.org Subject: [PATCH v5 15/22] RISC-V: KVM: Improve firmware counter read function Date: Wed, 3 Apr 2024 01:04:44 -0700 Message-Id: <20240403080452.1007601-16-atishp@rivosinc.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240403080452.1007601-1-atishp@rivosinc.com> References: <20240403080452.1007601-1-atishp@rivosinc.com> MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20240403_010545_704650_130FC105 X-CRM114-Status: GOOD ( 12.43 ) X-BeenThere: linux-riscv@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-riscv" Errors-To: linux-riscv-bounces+linux-riscv=archiver.kernel.org@lists.infradead.org Rename the function to indicate that it is meant for firmware counter read. While at it, add a range sanity check for it as well. Signed-off-by: Atish Patra Reviewed-by: Andrew Jones --- arch/riscv/include/asm/kvm_vcpu_pmu.h | 2 +- arch/riscv/kvm/vcpu_pmu.c | 7 ++++++- arch/riscv/kvm/vcpu_sbi_pmu.c | 2 +- 3 files changed, 8 insertions(+), 3 deletions(-) diff --git a/arch/riscv/include/asm/kvm_vcpu_pmu.h b/arch/riscv/include/asm/kvm_vcpu_pmu.h index 55861b5d3382..fa0f535bbbf0 100644 --- a/arch/riscv/include/asm/kvm_vcpu_pmu.h +++ b/arch/riscv/include/asm/kvm_vcpu_pmu.h @@ -89,7 +89,7 @@ int kvm_riscv_vcpu_pmu_ctr_cfg_match(struct kvm_vcpu *vcpu, unsigned long ctr_ba unsigned long ctr_mask, unsigned long flags, unsigned long eidx, u64 evtdata, struct kvm_vcpu_sbi_return *retdata); -int kvm_riscv_vcpu_pmu_ctr_read(struct kvm_vcpu *vcpu, unsigned long cidx, +int kvm_riscv_vcpu_pmu_fw_ctr_read(struct kvm_vcpu *vcpu, unsigned long cidx, struct kvm_vcpu_sbi_return *retdata); int kvm_riscv_vcpu_pmu_fw_ctr_read_hi(struct kvm_vcpu *vcpu, unsigned long cidx, struct kvm_vcpu_sbi_return *retdata); diff --git a/arch/riscv/kvm/vcpu_pmu.c b/arch/riscv/kvm/vcpu_pmu.c index ff326152eeff..94efa88d054d 100644 --- a/arch/riscv/kvm/vcpu_pmu.c +++ b/arch/riscv/kvm/vcpu_pmu.c @@ -235,6 +235,11 @@ static int pmu_ctr_read(struct kvm_vcpu *vcpu, unsigned long cidx, u64 enabled, running; int fevent_code; + if (cidx >= kvm_pmu_num_counters(kvpmu) || cidx == 1) { + pr_warn("Invalid counter id [%ld] during read\n", cidx); + return -EINVAL; + } + pmc = &kvpmu->pmc[cidx]; if (pmc->cinfo.type == SBI_PMU_CTR_TYPE_FW) { @@ -747,7 +752,7 @@ int kvm_riscv_vcpu_pmu_fw_ctr_read_hi(struct kvm_vcpu *vcpu, unsigned long cidx, return 0; } -int kvm_riscv_vcpu_pmu_ctr_read(struct kvm_vcpu *vcpu, unsigned long cidx, +int kvm_riscv_vcpu_pmu_fw_ctr_read(struct kvm_vcpu *vcpu, unsigned long cidx, struct kvm_vcpu_sbi_return *retdata) { int ret; diff --git a/arch/riscv/kvm/vcpu_sbi_pmu.c b/arch/riscv/kvm/vcpu_sbi_pmu.c index cf111de51bdb..e4be34e03e83 100644 --- a/arch/riscv/kvm/vcpu_sbi_pmu.c +++ b/arch/riscv/kvm/vcpu_sbi_pmu.c @@ -62,7 +62,7 @@ static int kvm_sbi_ext_pmu_handler(struct kvm_vcpu *vcpu, struct kvm_run *run, ret = kvm_riscv_vcpu_pmu_ctr_stop(vcpu, cp->a0, cp->a1, cp->a2, retdata); break; case SBI_EXT_PMU_COUNTER_FW_READ: - ret = kvm_riscv_vcpu_pmu_ctr_read(vcpu, cp->a0, retdata); + ret = kvm_riscv_vcpu_pmu_fw_ctr_read(vcpu, cp->a0, retdata); break; case SBI_EXT_PMU_COUNTER_FW_READ_HI: if (IS_ENABLED(CONFIG_32BIT)) From patchwork Wed Apr 3 08:04:45 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Atish Kumar Patra X-Patchwork-Id: 13615256 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 128EDC6FD1F for ; Wed, 3 Apr 2024 08:06:10 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:MIME-Version:References:In-Reply-To: Message-Id:Date:Subject:Cc:To:From:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; bh=Bj0IvKZKgGwXgbp/XQyK3DQ4DDhVBfHt2s4J99jy9mA=; b=zZDTE7QI3kOPUc e92FLc8xq/UO0KV609m/9cUDyR2y72Cw5EmrFBitW//VVTfTWf+sR72jrlg15YoxIOF90AXn9ryRk iKHzFtdGpR2LFMc9FSG8Zmj0u9uXcu/AIDKdjTKOhRqWXStBGhpFl+nfU15IsB6ydRi8iRQzpTtG4 T0lxvkutrGZf9jO37xQfia4+QiQA9CAei/qm+Yesxs0jWBPzVm9XqtY3C/lhHKBls/l2f2ff+lUKg 7+9LNU9lzzkoDlKl6pk6ne3/TH66oz5JSxzlPbSHWp1fgOz6QLbd/pzpDnSACNL+T6r9nZ2EcI1qY CTCampBKUIQowD5hSiMg==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.97.1 #2 (Red Hat Linux)) id 1rrvdD-0000000Ej5d-0D4L; Wed, 03 Apr 2024 08:06:03 +0000 Received: from desiato.infradead.org ([2001:8b0:10b:1:d65d:64ff:fe57:4e05]) by bombadil.infradead.org with esmtps (Exim 4.97.1 #2 (Red Hat Linux)) id 1rrvd0-0000000EiuR-3NSr for linux-riscv@bombadil.infradead.org; Wed, 03 Apr 2024 08:05:50 +0000 DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=infradead.org; s=desiato.20200630; h=Content-Transfer-Encoding:MIME-Version :References:In-Reply-To:Message-Id:Date:Subject:Cc:To:From:Sender:Reply-To: Content-Type:Content-ID:Content-Description; bh=UKKIkxhVPzlR31GWSQWSWFD216hXiUzA8utaOE+u8sQ=; b=GuAQUzw1FZ3ka9KiIOf4rLgX1o 9eS6VflZNhRRr35X8j0khrMLIWxZWTgjO6J/x0sD0cNHSysU/UfZRE2Z4c4yc+EoO9UzcH5JoPfX1 a0x8q+Wu5mC1cs6mIRe9R1TxKdFWGywsGBfh6KYtGI9MIxOd7raY9ebmpxOBX2MPapvCNwE8BUIQf DTEMXuyr8zpUexB2NF+HMOtEncFl+TJEcIRLqlASRboART4YH4hgGyocFM45lgLG+tI6yDJPYsgxt t8EBjsVGmjg32iPuue9HZ9UYo1/Q7R/ADoIMF50K+Y9MCcC1OW1fWTtV/YXHEoQvVeOt6CJ+fJGls JH26t4CA==; Received: from mail-pl1-x631.google.com ([2607:f8b0:4864:20::631]) by desiato.infradead.org with esmtps (Exim 4.97.1 #2 (Red Hat Linux)) id 1rrvcx-000000044q8-0F0J for linux-riscv@lists.infradead.org; Wed, 03 Apr 2024 08:05:49 +0000 Received: by mail-pl1-x631.google.com with SMTP id d9443c01a7336-1e0ae065d24so51513715ad.1 for ; Wed, 03 Apr 2024 01:05:46 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=rivosinc-com.20230601.gappssmtp.com; s=20230601; t=1712131545; x=1712736345; darn=lists.infradead.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=UKKIkxhVPzlR31GWSQWSWFD216hXiUzA8utaOE+u8sQ=; b=rVgY2YG5YWhFOfVZ3Nu1BpCVnlYfPYjjKo0ekFs+BH8DAsH0je8PJL/dgYFhd1DOiZ PJjwy1Cp2s6vCjrbUjintu7eA6srWgQ19Wjlb9X8jdFPHspyAHv4/486MQeSsi7WXARQ b9JEnT8uoWQKuJBg5CC1QgHqXBPZ5aafVO3Oi713+Ny2qusO9M0F3bpHqIwq4rPMQzzX 9XkJJv/iGTd9hkYWwsmMNKwDgTVP0Hmi48rhxlo9hHmMbrALYrz3BrDofdqEkJDpx4Fo kQ2F5xywHXlyoA4VoqmFV6UKysbkZa9XU9JJRRbNHqvfIJvEcc2r89/vCgKf9Q2mX7fi cAMQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1712131545; x=1712736345; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=UKKIkxhVPzlR31GWSQWSWFD216hXiUzA8utaOE+u8sQ=; b=mRORiO8zD4iE4zoplm2W3fItPeaYE0KueGbJnkNcsk6710JuCOzf35R8RdDYUBolcg Wmnag34KFnJO9TAoIajDioDKf5mqag5ophxTxDi3JaCt2l0dd2xCrs3UCJYIgkCWvBJW FnGsVr4fe2QREUCc67w2qn+RKxMfLI72nc1RCyBBsNIVGoW78dL6tec1gfeDWefTLh29 HhvaV6Vw9KlPQBnwgB21zerq3LPbSsjSFat0gtBPTbQ9EkY3BSoaU5pZZKpr5Gr3zw/B HfVwMA5XFNBkq3Liifiz9RP06t8vX57OgmBIY07ZOR3k8YZpB3W05EZ7Z8Fz7Vu9flbs ZiDA== X-Forwarded-Encrypted: i=1; AJvYcCWAi5JgfvfQa2T9iVa5/PC5TRyCPvkjYUPAbuOuToKtvl23uI5ti8sd2RKP5lKXjlNINtmNhb54eOvIqfbcju1LbcorNPfIh20wLTdx+iei X-Gm-Message-State: AOJu0YwrfDLG6h5/pfncmj9LrDlWgp4+h+ou3xq0sAvEyDZhlubhmywv zuWtsO6fFjCz1i58qnsJ79jbm8YebWLxmpXC7q3cCJ7T7T/kzK6+vhV1vZxhZ18= X-Google-Smtp-Source: AGHT+IEHII7tSGtUqO5wpO59JDooIKUZaJc45tvRQjDzAvEN2jSXssf4AqTMGpJ/lHoLRFAsmkx1xA== X-Received: by 2002:a17:902:bf04:b0:1e0:115c:e03c with SMTP id bi4-20020a170902bf0400b001e0115ce03cmr11696876plb.53.1712131545155; Wed, 03 Apr 2024 01:05:45 -0700 (PDT) Received: from atishp.ba.rivosinc.com ([64.71.180.162]) by smtp.gmail.com with ESMTPSA id c12-20020a170902d48c00b001e0b5d49fc7sm12557229plg.161.2024.04.03.01.05.43 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 03 Apr 2024 01:05:44 -0700 (PDT) From: Atish Patra To: linux-kernel@vger.kernel.org Cc: Atish Patra , Andrew Jones , Ajay Kaher , Alexandre Ghiti , Alexey Makhalov , Anup Patel , Conor Dooley , Juergen Gross , kvm-riscv@lists.infradead.org, kvm@vger.kernel.org, linux-kselftest@vger.kernel.org, linux-riscv@lists.infradead.org, Mark Rutland , Palmer Dabbelt , Paolo Bonzini , Paul Walmsley , Shuah Khan , virtualization@lists.linux.dev, VMware PV-Drivers Reviewers , Will Deacon , x86@kernel.org Subject: [PATCH v5 16/22] KVM: riscv: selftests: Move sbi definitions to its own header file Date: Wed, 3 Apr 2024 01:04:45 -0700 Message-Id: <20240403080452.1007601-17-atishp@rivosinc.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240403080452.1007601-1-atishp@rivosinc.com> References: <20240403080452.1007601-1-atishp@rivosinc.com> MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20240403_090547_413086_4CB5C269 X-CRM114-Status: GOOD ( 15.05 ) X-BeenThere: linux-riscv@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-riscv" Errors-To: linux-riscv-bounces+linux-riscv=archiver.kernel.org@lists.infradead.org The SBI definitions will continue to grow. Move the sbi related definitions to its own header file from processor.h Suggested-by: Andrew Jones Signed-off-by: Atish Patra Reviewed-by: Andrew Jones --- .../selftests/kvm/include/riscv/processor.h | 39 --------------- .../testing/selftests/kvm/include/riscv/sbi.h | 50 +++++++++++++++++++ .../selftests/kvm/include/riscv/ucall.h | 1 + tools/testing/selftests/kvm/steal_time.c | 4 +- 4 files changed, 54 insertions(+), 40 deletions(-) create mode 100644 tools/testing/selftests/kvm/include/riscv/sbi.h diff --git a/tools/testing/selftests/kvm/include/riscv/processor.h b/tools/testing/selftests/kvm/include/riscv/processor.h index ce473fe251dd..3b9cb39327ff 100644 --- a/tools/testing/selftests/kvm/include/riscv/processor.h +++ b/tools/testing/selftests/kvm/include/riscv/processor.h @@ -154,45 +154,6 @@ void vm_install_interrupt_handler(struct kvm_vm *vm, exception_handler_fn handle #define PGTBL_PAGE_SIZE PGTBL_L0_BLOCK_SIZE #define PGTBL_PAGE_SIZE_SHIFT PGTBL_L0_BLOCK_SHIFT -/* SBI return error codes */ -#define SBI_SUCCESS 0 -#define SBI_ERR_FAILURE -1 -#define SBI_ERR_NOT_SUPPORTED -2 -#define SBI_ERR_INVALID_PARAM -3 -#define SBI_ERR_DENIED -4 -#define SBI_ERR_INVALID_ADDRESS -5 -#define SBI_ERR_ALREADY_AVAILABLE -6 -#define SBI_ERR_ALREADY_STARTED -7 -#define SBI_ERR_ALREADY_STOPPED -8 - -#define SBI_EXT_EXPERIMENTAL_START 0x08000000 -#define SBI_EXT_EXPERIMENTAL_END 0x08FFFFFF - -#define KVM_RISCV_SELFTESTS_SBI_EXT SBI_EXT_EXPERIMENTAL_END -#define KVM_RISCV_SELFTESTS_SBI_UCALL 0 -#define KVM_RISCV_SELFTESTS_SBI_UNEXP 1 - -enum sbi_ext_id { - SBI_EXT_BASE = 0x10, - SBI_EXT_STA = 0x535441, -}; - -enum sbi_ext_base_fid { - SBI_EXT_BASE_PROBE_EXT = 3, -}; - -struct sbiret { - long error; - long value; -}; - -struct sbiret sbi_ecall(int ext, int fid, unsigned long arg0, - unsigned long arg1, unsigned long arg2, - unsigned long arg3, unsigned long arg4, - unsigned long arg5); - -bool guest_sbi_probe_extension(int extid, long *out_val); - static inline void local_irq_enable(void) { csr_set(CSR_SSTATUS, SR_SIE); diff --git a/tools/testing/selftests/kvm/include/riscv/sbi.h b/tools/testing/selftests/kvm/include/riscv/sbi.h new file mode 100644 index 000000000000..ba04f2dec7b5 --- /dev/null +++ b/tools/testing/selftests/kvm/include/riscv/sbi.h @@ -0,0 +1,50 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * RISC-V SBI specific definitions + * + * Copyright (C) 2024 Rivos Inc. + */ + +#ifndef SELFTEST_KVM_SBI_H +#define SELFTEST_KVM_SBI_H + +/* SBI return error codes */ +#define SBI_SUCCESS 0 +#define SBI_ERR_FAILURE -1 +#define SBI_ERR_NOT_SUPPORTED -2 +#define SBI_ERR_INVALID_PARAM -3 +#define SBI_ERR_DENIED -4 +#define SBI_ERR_INVALID_ADDRESS -5 +#define SBI_ERR_ALREADY_AVAILABLE -6 +#define SBI_ERR_ALREADY_STARTED -7 +#define SBI_ERR_ALREADY_STOPPED -8 + +#define SBI_EXT_EXPERIMENTAL_START 0x08000000 +#define SBI_EXT_EXPERIMENTAL_END 0x08FFFFFF + +#define KVM_RISCV_SELFTESTS_SBI_EXT SBI_EXT_EXPERIMENTAL_END +#define KVM_RISCV_SELFTESTS_SBI_UCALL 0 +#define KVM_RISCV_SELFTESTS_SBI_UNEXP 1 + +enum sbi_ext_id { + SBI_EXT_BASE = 0x10, + SBI_EXT_STA = 0x535441, +}; + +enum sbi_ext_base_fid { + SBI_EXT_BASE_PROBE_EXT = 3, +}; + +struct sbiret { + long error; + long value; +}; + +struct sbiret sbi_ecall(int ext, int fid, unsigned long arg0, + unsigned long arg1, unsigned long arg2, + unsigned long arg3, unsigned long arg4, + unsigned long arg5); + +bool guest_sbi_probe_extension(int extid, long *out_val); + +#endif /* SELFTEST_KVM_SBI_H */ diff --git a/tools/testing/selftests/kvm/include/riscv/ucall.h b/tools/testing/selftests/kvm/include/riscv/ucall.h index be46eb32ec27..a695ae36f3e0 100644 --- a/tools/testing/selftests/kvm/include/riscv/ucall.h +++ b/tools/testing/selftests/kvm/include/riscv/ucall.h @@ -3,6 +3,7 @@ #define SELFTEST_KVM_UCALL_H #include "processor.h" +#include "sbi.h" #define UCALL_EXIT_REASON KVM_EXIT_RISCV_SBI diff --git a/tools/testing/selftests/kvm/steal_time.c b/tools/testing/selftests/kvm/steal_time.c index bae0c5026f82..2ff82c7fd926 100644 --- a/tools/testing/selftests/kvm/steal_time.c +++ b/tools/testing/selftests/kvm/steal_time.c @@ -11,7 +11,9 @@ #include #include #include -#ifndef __riscv +#ifdef __riscv +#include "sbi.h" +#else #include #endif From patchwork Wed Apr 3 08:04:46 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Atish Kumar Patra X-Patchwork-Id: 13615258 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id F3714CD1288 for ; Wed, 3 Apr 2024 08:06:22 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:MIME-Version:References:In-Reply-To: Message-Id:Date:Subject:Cc:To:From:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; bh=NaE60lYbe6wqexLzWeavEF8Z0W8xrku10qmqnLecF34=; b=ZehUc7n6g5lvZx YBreisaLmy36uzA644tLOMVuuxrBDJoldyRze+/tZLV9e+nuRuznjwDh1uZFmvp4jW0HQ0ropFmYv SPMUw5uz6Pqge4PIYnm1/ux/61YxWbuCIxLKjvDn0MR2UQrRfV7uWC78nnrYVQqAzeriHsEev9GxK jYxHu8K+gGsV3sVgaDxuhr2MLN3tFd/HtZOTbpD0tt1YoGsBnCKE0rjRvAWr+16SlIPcQJGYwTqq5 lOm/QJJc5jJ/Texvp0rL2G0KFfRmjaisYGQOG6PeSnKEAVT/JXdl2ROVwCdggUiPscn39dRkb8LjW 9acwgAnFsxoQx/ECDjlQ==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.97.1 #2 (Red Hat Linux)) id 1rrvdR-0000000EjK8-2od9; Wed, 03 Apr 2024 08:06:17 +0000 Received: from mail-pl1-f176.google.com ([209.85.214.176]) by bombadil.infradead.org with esmtps (Exim 4.97.1 #2 (Red Hat Linux)) id 1rrvd0-0000000EitY-3I5W for linux-riscv@lists.infradead.org; Wed, 03 Apr 2024 08:05:54 +0000 Received: by mail-pl1-f176.google.com with SMTP id d9443c01a7336-1e2987e9d67so1071595ad.1 for ; Wed, 03 Apr 2024 01:05:49 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=rivosinc-com.20230601.gappssmtp.com; s=20230601; t=1712131548; x=1712736348; darn=lists.infradead.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=iiceCABnvA1jknfstt9FkxftBmpWokdNdmMlEhNsfyg=; b=dqhchlchGWWxja0yyzYQXd/0BPsRbWquZwjgtUMEoa7h1vxD+xj5ic/N2Lav4PoK6N 98E7JTTXf2CxRdcsh/4wS2hOAzhsMlfrszQv8ugpqvudh1FmyQ0HjbQDRWHTKpVflL5V HzH2+W2HvUYX3EBHGmG6J1ZchwJr8ZN4oN8+GnMHQPhgc6Zsmy/jRQaAinaV42A2AhmV 0dINMVAvetK07KCbmhkzaM+cWVBldZfyJ06eZI8ezNDez4jsJLYL62BZxvXjGTFqlWEe DHO0giMZfPwFvTJNmoRuWvHn4adresKq0gvekKSO+efMn+PaGKXKzCZ89k/5mscIHb9J el2A== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1712131548; x=1712736348; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=iiceCABnvA1jknfstt9FkxftBmpWokdNdmMlEhNsfyg=; b=Ts24RmqyHbWPMSemHu3gXA2tp+DUQO1Pbp/MzodShjvUmSVDZlPTKrrNKaCMzXSFSM HoDyiNTHkKADOugDFSn3D2fZeSpRLAFAcRfrEhbGQ+z06DTsVO4AIFXTvKEy63lOoZ1w AhnuyHU/jwOOzKAZmlQQzHsRVQcvJjOGh38meyBnAYU70ba9tHjEEnSz+41KXIfl5Z1f 8HZkMNdsFgT18VGD/RipbJbajwx5L5HxsRxQkRxA7a5f+uqz1dh8tv/7itlqrShFSvS5 4GVFqxRpMjTB/tAEaDyPqtCPPfi3cbddQN1t6vRN0aviK69eVPNMhwVo2/bspQxdGm5Z YPlQ== X-Forwarded-Encrypted: i=1; AJvYcCX0K4xRjnKXEVa01gVEwj38bxDtuq/LMBnb+U7S5LSbTVv94ryX/x6j8/e5mOtreR+HTbm4dOwNzFWtldZ3tLGowrGGqqZ7IVFk4vhyaZPK X-Gm-Message-State: AOJu0YxGR+ck0oPUuXWGNKPBd8sJxw5r1RuqEPryVQLzIxON+3ek4HvJ Q7SEJwGfsYhKJK+WYEw8UI/AVG/CnMkYHu4sDNs8g2qPpCtrSF8l+IA0QU/pYgU= X-Google-Smtp-Source: AGHT+IEPeMI0z43MjvlBXsAsUdkQGTsWnPaqF+QUoQ1JhMqwDtA7d+BW/HuEGoVFyjEvifPOaGIfHg== X-Received: by 2002:a17:903:181:b0:1e0:e85c:72dc with SMTP id z1-20020a170903018100b001e0e85c72dcmr2464037plg.19.1712131548509; Wed, 03 Apr 2024 01:05:48 -0700 (PDT) Received: from atishp.ba.rivosinc.com ([64.71.180.162]) by smtp.gmail.com with ESMTPSA id c12-20020a170902d48c00b001e0b5d49fc7sm12557229plg.161.2024.04.03.01.05.45 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 03 Apr 2024 01:05:46 -0700 (PDT) From: Atish Patra To: linux-kernel@vger.kernel.org Cc: Atish Patra , Ajay Kaher , Alexandre Ghiti , Alexey Makhalov , Andrew Jones , Anup Patel , Conor Dooley , Juergen Gross , kvm-riscv@lists.infradead.org, kvm@vger.kernel.org, linux-kselftest@vger.kernel.org, linux-riscv@lists.infradead.org, Mark Rutland , Palmer Dabbelt , Paolo Bonzini , Paul Walmsley , Shuah Khan , virtualization@lists.linux.dev, VMware PV-Drivers Reviewers , Will Deacon , x86@kernel.org Subject: [PATCH v5 17/22] KVM: riscv: selftests: Add helper functions for extension checks Date: Wed, 3 Apr 2024 01:04:46 -0700 Message-Id: <20240403080452.1007601-18-atishp@rivosinc.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240403080452.1007601-1-atishp@rivosinc.com> References: <20240403080452.1007601-1-atishp@rivosinc.com> MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20240403_010550_916382_88738343 X-CRM114-Status: GOOD ( 12.61 ) X-BeenThere: linux-riscv@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-riscv" Errors-To: linux-riscv-bounces+linux-riscv=archiver.kernel.org@lists.infradead.org __vcpu_has_ext can check both SBI and ISA extensions when the first argument is properly converted to SBI/ISA extension IDs. Introduce two helper functions to make life easier for developers so they don't have to worry about the conversions. Replace the current usages as well with new helpers. Signed-off-by: Atish Patra Reviewed-by: Andrew Jones --- tools/testing/selftests/kvm/include/riscv/processor.h | 10 ++++++++++ tools/testing/selftests/kvm/riscv/arch_timer.c | 2 +- 2 files changed, 11 insertions(+), 1 deletion(-) diff --git a/tools/testing/selftests/kvm/include/riscv/processor.h b/tools/testing/selftests/kvm/include/riscv/processor.h index 3b9cb39327ff..5f389166338c 100644 --- a/tools/testing/selftests/kvm/include/riscv/processor.h +++ b/tools/testing/selftests/kvm/include/riscv/processor.h @@ -50,6 +50,16 @@ static inline uint64_t __kvm_reg_id(uint64_t type, uint64_t subtype, bool __vcpu_has_ext(struct kvm_vcpu *vcpu, uint64_t ext); +static inline bool __vcpu_has_isa_ext(struct kvm_vcpu *vcpu, uint64_t isa_ext) +{ + return __vcpu_has_ext(vcpu, RISCV_ISA_EXT_REG(isa_ext)); +} + +static inline bool __vcpu_has_sbi_ext(struct kvm_vcpu *vcpu, uint64_t sbi_ext) +{ + return __vcpu_has_ext(vcpu, RISCV_SBI_EXT_REG(sbi_ext)); +} + struct ex_regs { unsigned long ra; unsigned long sp; diff --git a/tools/testing/selftests/kvm/riscv/arch_timer.c b/tools/testing/selftests/kvm/riscv/arch_timer.c index e22848f747c0..6a3e97ead824 100644 --- a/tools/testing/selftests/kvm/riscv/arch_timer.c +++ b/tools/testing/selftests/kvm/riscv/arch_timer.c @@ -85,7 +85,7 @@ struct kvm_vm *test_vm_create(void) int nr_vcpus = test_args.nr_vcpus; vm = vm_create_with_vcpus(nr_vcpus, guest_code, vcpus); - __TEST_REQUIRE(__vcpu_has_ext(vcpus[0], RISCV_ISA_EXT_REG(KVM_RISCV_ISA_EXT_SSTC)), + __TEST_REQUIRE(__vcpu_has_isa_ext(vcpus[0], KVM_RISCV_ISA_EXT_SSTC), "SSTC not available, skipping test\n"); vm_init_vector_tables(vm); From patchwork Wed Apr 3 08:04:47 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Atish Kumar Patra X-Patchwork-Id: 13615261 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 5A5C0CD1288 for ; Wed, 3 Apr 2024 08:06:37 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:MIME-Version:References:In-Reply-To: Message-Id:Date:Subject:Cc:To:From:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; bh=O/6kcOGhQC8OEgf93/u5AXhghbPIAArA4ygly40MBYk=; b=Nfv/7Rq3IPWozd bYnIs2Zn3/jbFezhxr6XoQ1eOtfEXD5vpvO7UusXlH1Oqsm7tEpQ1UbDUCReOcccIPV2WM7V1ahkE mfYUTJD5wJIrdDRuXE2GgQpM3ZtbWeJdQXJZj++MH7fvKEqAoAp/B/9ZbU2RmDxFvNJZReoOGSPMJ 8R8Miu74bAQ29qHosDoupW+EB1Ps6kIa6uAqHi05iWSCE8SWrwVAsCH1ObvB5ao7PHLDljLDqISVY lpAwokDIRryJUgfAzq6G5jrOBXb72L7/yPY8MDr+QcB/WZkRawlJ08qsFGeVdHEBTodTZij4ZevEh KjlEWYo7hUwBcD5DXqyA==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.97.1 #2 (Red Hat Linux)) id 1rrvdg-0000000EjZN-0rTB; Wed, 03 Apr 2024 08:06:32 +0000 Received: from desiato.infradead.org ([2001:8b0:10b:1:d65d:64ff:fe57:4e05]) by bombadil.infradead.org with esmtps (Exim 4.97.1 #2 (Red Hat Linux)) id 1rrvdD-0000000Ej5e-20bE for linux-riscv@bombadil.infradead.org; Wed, 03 Apr 2024 08:06:03 +0000 DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=infradead.org; s=desiato.20200630; h=Content-Transfer-Encoding:MIME-Version :References:In-Reply-To:Message-Id:Date:Subject:Cc:To:From:Sender:Reply-To: Content-Type:Content-ID:Content-Description; bh=xZMdAGbGUb3Pn/mM6S9aCTNbs+MKWuMa25SVPrHMqxo=; b=dKDmxsMmPMZlS33TB0h0ea2HqN YKRqAJzkhoTEADadz6VquwKAWo+8sDaA9VsYc86klG5JTqq2J6gJr1T0qG/ex2RWqXr6BO2jJ9yqC 6sIRLlkny8SNbBnA5jC4DahYFCQc9wUg1TREvCkvReqG9A6vsC0KOlyRUSCMBc5rF9M+0yaznyy0g XE9Nyq8QajY4rs8KsZpsrXa9nVISkb/FPTyy8rVYKTQQfZfAW1wsH1mMBs+gp69Ca5FD2q+lfZ157 CLRU0uvHMhnBSly2vjua/3UcgunBlWatmDvo8egNZuipvTR0eoFMBztN4gAIdWs2wlra+MBijJxis rH/CBl/w==; Received: from mail-pg1-x535.google.com ([2607:f8b0:4864:20::535]) by desiato.infradead.org with esmtps (Exim 4.97.1 #2 (Red Hat Linux)) id 1rrvd3-000000044rj-0By5 for linux-riscv@lists.infradead.org; Wed, 03 Apr 2024 08:05:59 +0000 Received: by mail-pg1-x535.google.com with SMTP id 41be03b00d2f7-5dbf7b74402so3367182a12.0 for ; Wed, 03 Apr 2024 01:05:52 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=rivosinc-com.20230601.gappssmtp.com; s=20230601; t=1712131551; x=1712736351; darn=lists.infradead.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=xZMdAGbGUb3Pn/mM6S9aCTNbs+MKWuMa25SVPrHMqxo=; b=kkcwaxHnOpogsiW2YpMqXrxdCI6CTZ2jLCorhmaUK+qUK0KCvMZw20OSHttaiBj3z+ WiUItEv78gq/VP1ZrfjeiWlKWsulS0tyoJVpY333/uQzv3MIuQLf6YUu7FZ6VDbcdECD GSfeL0jAunLxAkxHRWrYlm7YaO+J40uK7cavtEcrW4kOK8cWOMb0VsV+iadz9e+ClOHL mly+lsKItut8+OHBZ/uGWF7VSZeqmKznZiDrU8G8Ur7fYMxkrr0yvuKDCU3RE87x4Clo P/eIu0u2o8xO/UlOKfmhbMaFHwjBMFK0zoZG/nhSaPlb8jfxPZ+F6G+cDeEuanHXf4BR Ovew== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1712131551; x=1712736351; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=xZMdAGbGUb3Pn/mM6S9aCTNbs+MKWuMa25SVPrHMqxo=; b=nn2SP84Hl1fuR5SyIrawTGsiQPG0PZ9R/O3YrnNn0BdjpG9xawd10Ocsf4zndHGu5J h99+AdjhgQHg+/Q6asHpQzAsGKJ3uW8CvQ5K0qJ1BwDz+zLfbCL+b+tuADIaTIgTX+ig x7vLYr+GELFsjAakKeKMhLISh+aaRuNv58jtOX331jTK4m0oV0MxxlCxZ+yXym297tqC q5BRguZV4ElsrN7BzOBPO3tkAO/oHxxCIh6CXW34TXn06MQR+RHRQrsFLt7BrLqAMRd1 B7pZ9eTNJTpmjO+FG62A/IbBriuOiuNkcaYWP4yBKiBr3Q37hpIt/WimasN3G7SUabkv deKg== X-Forwarded-Encrypted: i=1; AJvYcCWt+MBUpi7LboSBpSAEwDf8DV73xQizgrlIZ5bRFqitjEPHt4ifUNTTZ+kfRgk7CEiE0EkUkXkJthp8H/L/0mILKZZ9xgdAYK1QId+aaq3L X-Gm-Message-State: AOJu0YxC5S0DXI1RZk57l0NSNgeQBI89GP9+ZCTrgUVifi0cBEuKUngs GjRHejgSQmI1UN14TdmSNrAYNjW5w+2tIC7rIP/BRYfa1Wtu3VqbtTQ3vJMyKS8= X-Google-Smtp-Source: AGHT+IFHku/sICvAenYJFC+cS7PaObyEd64lSbck4sFkQiPnTcMjwhsfqy4pdW/5l9uIy4qG4AZ0Fg== X-Received: by 2002:a05:6a20:94cf:b0:1a7:377:b867 with SMTP id ht15-20020a056a2094cf00b001a70377b867mr11062652pzb.57.1712131551038; Wed, 03 Apr 2024 01:05:51 -0700 (PDT) Received: from atishp.ba.rivosinc.com ([64.71.180.162]) by smtp.gmail.com with ESMTPSA id c12-20020a170902d48c00b001e0b5d49fc7sm12557229plg.161.2024.04.03.01.05.48 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 03 Apr 2024 01:05:49 -0700 (PDT) From: Atish Patra To: linux-kernel@vger.kernel.org Cc: Atish Patra , Anup Patel , Andrew Jones , Ajay Kaher , Alexandre Ghiti , Alexey Makhalov , Conor Dooley , Juergen Gross , kvm-riscv@lists.infradead.org, kvm@vger.kernel.org, linux-kselftest@vger.kernel.org, linux-riscv@lists.infradead.org, Mark Rutland , Palmer Dabbelt , Paolo Bonzini , Paul Walmsley , Shuah Khan , virtualization@lists.linux.dev, VMware PV-Drivers Reviewers , Will Deacon , x86@kernel.org Subject: [PATCH v5 18/22] KVM: riscv: selftests: Add Sscofpmf to get-reg-list test Date: Wed, 3 Apr 2024 01:04:47 -0700 Message-Id: <20240403080452.1007601-19-atishp@rivosinc.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240403080452.1007601-1-atishp@rivosinc.com> References: <20240403080452.1007601-1-atishp@rivosinc.com> MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20240403_090553_748043_BF037D9C X-CRM114-Status: UNSURE ( 9.05 ) X-CRM114-Notice: Please train this message. X-BeenThere: linux-riscv@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-riscv" Errors-To: linux-riscv-bounces+linux-riscv=archiver.kernel.org@lists.infradead.org The KVM RISC-V allows Sscofpmf extension for Guest/VM so let us add this extension to get-reg-list test. Reviewed-by: Anup Patel Reviewed-by: Andrew Jones Signed-off-by: Atish Patra --- tools/testing/selftests/kvm/riscv/get-reg-list.c | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/tools/testing/selftests/kvm/riscv/get-reg-list.c b/tools/testing/selftests/kvm/riscv/get-reg-list.c index b882b7b9b785..222198dd6d04 100644 --- a/tools/testing/selftests/kvm/riscv/get-reg-list.c +++ b/tools/testing/selftests/kvm/riscv/get-reg-list.c @@ -43,6 +43,7 @@ bool filter_reg(__u64 reg) case KVM_REG_RISCV_ISA_EXT | KVM_REG_RISCV_ISA_SINGLE | KVM_RISCV_ISA_EXT_V: case KVM_REG_RISCV_ISA_EXT | KVM_REG_RISCV_ISA_SINGLE | KVM_RISCV_ISA_EXT_SMSTATEEN: case KVM_REG_RISCV_ISA_EXT | KVM_REG_RISCV_ISA_SINGLE | KVM_RISCV_ISA_EXT_SSAIA: + case KVM_REG_RISCV_ISA_EXT | KVM_REG_RISCV_ISA_SINGLE | KVM_RISCV_ISA_EXT_SSCOFPMF: case KVM_REG_RISCV_ISA_EXT | KVM_REG_RISCV_ISA_SINGLE | KVM_RISCV_ISA_EXT_SSTC: case KVM_REG_RISCV_ISA_EXT | KVM_REG_RISCV_ISA_SINGLE | KVM_RISCV_ISA_EXT_SVINVAL: case KVM_REG_RISCV_ISA_EXT | KVM_REG_RISCV_ISA_SINGLE | KVM_RISCV_ISA_EXT_SVNAPOT: @@ -408,6 +409,7 @@ static const char *isa_ext_single_id_to_str(__u64 reg_off) KVM_ISA_EXT_ARR(V), KVM_ISA_EXT_ARR(SMSTATEEN), KVM_ISA_EXT_ARR(SSAIA), + KVM_ISA_EXT_ARR(SSCOFPMF), KVM_ISA_EXT_ARR(SSTC), KVM_ISA_EXT_ARR(SVINVAL), KVM_ISA_EXT_ARR(SVNAPOT), @@ -931,6 +933,7 @@ KVM_ISA_EXT_SUBLIST_CONFIG(fp_f, FP_F); KVM_ISA_EXT_SUBLIST_CONFIG(fp_d, FP_D); KVM_ISA_EXT_SIMPLE_CONFIG(h, H); KVM_ISA_EXT_SUBLIST_CONFIG(smstateen, SMSTATEEN); +KVM_ISA_EXT_SIMPLE_CONFIG(sscofpmf, SSCOFPMF); KVM_ISA_EXT_SIMPLE_CONFIG(sstc, SSTC); KVM_ISA_EXT_SIMPLE_CONFIG(svinval, SVINVAL); KVM_ISA_EXT_SIMPLE_CONFIG(svnapot, SVNAPOT); @@ -986,6 +989,7 @@ struct vcpu_reg_list *vcpu_configs[] = { &config_fp_d, &config_h, &config_smstateen, + &config_sscofpmf, &config_sstc, &config_svinval, &config_svnapot, From patchwork Wed Apr 3 08:04:48 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Atish Kumar Patra X-Patchwork-Id: 13615259 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 42B17CD1288 for ; Wed, 3 Apr 2024 08:06:26 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:MIME-Version:References:In-Reply-To: Message-Id:Date:Subject:Cc:To:From:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; bh=qqcj090InE7sXuBAszIuWv5N09djmfIeolCLabVW28g=; b=R0nrTl7kw/UDUA QjlXB+Yq9EssFmQJQ9o4sWpDgSoV1vYF69X5di1/lIruL+9EiT1JpMfZJhbxrb83MiCFxtFpd4BHf Jc6aWHZsr75/08+NS8Fk42MLcb8mADnVrasnUVGrXy63htfMnc2WhqAJFJQS0O1RMAEjfs/fXRAr3 pQxMZDx2ETcE0K5DHvuqfllyq2+CMVZLZ3/9fF+pGws5VWtGggI+gw/yK5Vb6YKT6nzLmJlo/K0XQ 8X8d5reLVT7RRKXygnwtTFY3mV4FkwCCwU8rzjzW3VBrW4Js5CpsKDCMKEmshvW1Rj66y0yQdAUkP UZ3mDqNACdhqE5wt4tWg==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.97.1 #2 (Red Hat Linux)) id 1rrvdW-0000000EjOX-0Gmy; Wed, 03 Apr 2024 08:06:22 +0000 Received: from mail-pl1-x632.google.com ([2607:f8b0:4864:20::632]) by bombadil.infradead.org with esmtps (Exim 4.97.1 #2 (Red Hat Linux)) id 1rrvd4-0000000Eixn-346O for linux-riscv@lists.infradead.org; Wed, 03 Apr 2024 08:05:56 +0000 Received: by mail-pl1-x632.google.com with SMTP id d9443c01a7336-1e034607879so48832315ad.0 for ; Wed, 03 Apr 2024 01:05:54 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=rivosinc-com.20230601.gappssmtp.com; s=20230601; t=1712131554; x=1712736354; darn=lists.infradead.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=GkhEh3Kwi0UVSPm+lxEXp9oZg2L7eBy2zYGiPlgLtso=; b=w1Q4Ps8CwnL8lBPSRfaepyOAK4J5tCdhrkC3O0ApCO2z2G7ckEOOH/HxCFZFQMQrCr 2MCGVeMTB8ePP662P3wCoc9xzUu4HBrPJC/kPjngYU6ZNE2rhiQniYpkz91gODF5ruJu KEH5LBsAWUEA/PRlO0hU3HiOxo8Cl9x2KvkpKwY7GwA8JV+0mJnt9/JX2npNA3WTcXNb pkiPoQleJtGmSHbBho6eb59Lv54qrSlH+ykkJvym95WFojwyleBFjMhJVrWwACfRyFE1 daCvvt3q5PdDEd7FhdOKInN8zTAvTuEimhBaCJ51tttmEIAVhnSyJIueE9Ek+yES1wMs ultA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1712131554; x=1712736354; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=GkhEh3Kwi0UVSPm+lxEXp9oZg2L7eBy2zYGiPlgLtso=; b=N8as1FSfoRuoHOD4DYwjmEWJyqiSIaCNva/uGjwWJ7JHlFeNXe4dF3djcf70h9uV6z UuLbsOdnHj+xtkxenoyIK4WbTwvvBZ954GREyylqz26J9i+WnxWNO37/XhR8RwhNL/fG kFNqWU52BCANR5kPP4GEYumc5y3JRhWymT0p3kMWJqqlCCjJ+sB8Jno8mJzniqPtBTAz dbTS8CNEqIzoDbx/2+MZnrOS7t+BD+GQDM4tfY+ipid8hVPCcCyMx/Hy1qmFg4q2hb3+ HVMqd1GMZcQKmMMgHmOKNy55YAvek1X/Sxr6yTUdoPO0VW5cquFLwAlNGVMixCNuqiwn 2DCw== X-Forwarded-Encrypted: i=1; AJvYcCXbdk3TE/MEbslTiLq4jJR+DsI00p12OLOxfeZsxYp0vVM6GX2KmcXY1wZ66MLwkAnHXbygmCZZMHhUK7gAspBbyZDvj1+ju4BfA2NCYAOA X-Gm-Message-State: AOJu0YzLobBHbLxQyProMghL02Hv3HB39XOwKe1INysbAnbYfuSwDVr3 eXnmoz/I/3f8Hpz2KZSTDL90kOc2QX+8nNJEzLO9XweUaJgCrOKR00Db4uWU/JM= X-Google-Smtp-Source: AGHT+IHXyVuhd2UN6DaFS3pRiDjXF6BBqw4nhkvMX8+6lolbeavqTSelxKMWeizm1rfTvMdNdGFtWA== X-Received: by 2002:a17:903:292:b0:1e2:6240:72e7 with SMTP id j18-20020a170903029200b001e2624072e7mr5867168plr.53.1712131554171; Wed, 03 Apr 2024 01:05:54 -0700 (PDT) Received: from atishp.ba.rivosinc.com ([64.71.180.162]) by smtp.gmail.com with ESMTPSA id c12-20020a170902d48c00b001e0b5d49fc7sm12557229plg.161.2024.04.03.01.05.51 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 03 Apr 2024 01:05:52 -0700 (PDT) From: Atish Patra To: linux-kernel@vger.kernel.org Cc: Atish Patra , Anup Patel , Ajay Kaher , Alexandre Ghiti , Alexey Makhalov , Andrew Jones , Conor Dooley , Juergen Gross , kvm-riscv@lists.infradead.org, kvm@vger.kernel.org, linux-kselftest@vger.kernel.org, linux-riscv@lists.infradead.org, Mark Rutland , Palmer Dabbelt , Paolo Bonzini , Paul Walmsley , Shuah Khan , virtualization@lists.linux.dev, VMware PV-Drivers Reviewers , Will Deacon , x86@kernel.org Subject: [PATCH v5 19/22] KVM: riscv: selftests: Add SBI PMU extension definitions Date: Wed, 3 Apr 2024 01:04:48 -0700 Message-Id: <20240403080452.1007601-20-atishp@rivosinc.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240403080452.1007601-1-atishp@rivosinc.com> References: <20240403080452.1007601-1-atishp@rivosinc.com> MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20240403_010554_881620_81876DC9 X-CRM114-Status: UNSURE ( 9.68 ) X-CRM114-Notice: Please train this message. X-BeenThere: linux-riscv@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-riscv" Errors-To: linux-riscv-bounces+linux-riscv=archiver.kernel.org@lists.infradead.org The SBI PMU extension definition is required for upcoming SBI PMU selftests. Reviewed-by: Anup Patel Signed-off-by: Atish Patra Reviewed-by: Andrew Jones --- .../testing/selftests/kvm/include/riscv/sbi.h | 66 +++++++++++++++++++ 1 file changed, 66 insertions(+) diff --git a/tools/testing/selftests/kvm/include/riscv/sbi.h b/tools/testing/selftests/kvm/include/riscv/sbi.h index ba04f2dec7b5..6675ca673c77 100644 --- a/tools/testing/selftests/kvm/include/riscv/sbi.h +++ b/tools/testing/selftests/kvm/include/riscv/sbi.h @@ -29,17 +29,83 @@ enum sbi_ext_id { SBI_EXT_BASE = 0x10, SBI_EXT_STA = 0x535441, + SBI_EXT_PMU = 0x504D55, }; enum sbi_ext_base_fid { SBI_EXT_BASE_PROBE_EXT = 3, }; +enum sbi_ext_pmu_fid { + SBI_EXT_PMU_NUM_COUNTERS = 0, + SBI_EXT_PMU_COUNTER_GET_INFO, + SBI_EXT_PMU_COUNTER_CFG_MATCH, + SBI_EXT_PMU_COUNTER_START, + SBI_EXT_PMU_COUNTER_STOP, + SBI_EXT_PMU_COUNTER_FW_READ, + SBI_EXT_PMU_COUNTER_FW_READ_HI, + SBI_EXT_PMU_SNAPSHOT_SET_SHMEM, +}; + +union sbi_pmu_ctr_info { + unsigned long value; + struct { + unsigned long csr:12; + unsigned long width:6; +#if __riscv_xlen == 32 + unsigned long reserved:13; +#else + unsigned long reserved:45; +#endif + unsigned long type:1; + }; +}; struct sbiret { long error; long value; }; +/** General pmu event codes specified in SBI PMU extension */ +enum sbi_pmu_hw_generic_events_t { + SBI_PMU_HW_NO_EVENT = 0, + SBI_PMU_HW_CPU_CYCLES = 1, + SBI_PMU_HW_INSTRUCTIONS = 2, + SBI_PMU_HW_CACHE_REFERENCES = 3, + SBI_PMU_HW_CACHE_MISSES = 4, + SBI_PMU_HW_BRANCH_INSTRUCTIONS = 5, + SBI_PMU_HW_BRANCH_MISSES = 6, + SBI_PMU_HW_BUS_CYCLES = 7, + SBI_PMU_HW_STALLED_CYCLES_FRONTEND = 8, + SBI_PMU_HW_STALLED_CYCLES_BACKEND = 9, + SBI_PMU_HW_REF_CPU_CYCLES = 10, + + SBI_PMU_HW_GENERAL_MAX, +}; + +/* SBI PMU counter types */ +enum sbi_pmu_ctr_type { + SBI_PMU_CTR_TYPE_HW = 0x0, + SBI_PMU_CTR_TYPE_FW, +}; + +/* Flags defined for config matching function */ +#define SBI_PMU_CFG_FLAG_SKIP_MATCH BIT(0) +#define SBI_PMU_CFG_FLAG_CLEAR_VALUE BIT(1) +#define SBI_PMU_CFG_FLAG_AUTO_START BIT(2) +#define SBI_PMU_CFG_FLAG_SET_VUINH BIT(3) +#define SBI_PMU_CFG_FLAG_SET_VSINH BIT(4) +#define SBI_PMU_CFG_FLAG_SET_UINH BIT(5) +#define SBI_PMU_CFG_FLAG_SET_SINH BIT(6) +#define SBI_PMU_CFG_FLAG_SET_MINH BIT(7) + +/* Flags defined for counter start function */ +#define SBI_PMU_START_FLAG_SET_INIT_VALUE BIT(0) +#define SBI_PMU_START_FLAG_INIT_SNAPSHOT BIT(1) + +/* Flags defined for counter stop function */ +#define SBI_PMU_STOP_FLAG_RESET BIT(0) +#define SBI_PMU_STOP_FLAG_TAKE_SNAPSHOT BIT(1) + struct sbiret sbi_ecall(int ext, int fid, unsigned long arg0, unsigned long arg1, unsigned long arg2, unsigned long arg3, unsigned long arg4, From patchwork Wed Apr 3 08:04:49 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Atish Kumar Patra X-Patchwork-Id: 13615260 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 7337ACD1288 for ; Wed, 3 Apr 2024 08:06:33 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:MIME-Version:References:In-Reply-To: Message-Id:Date:Subject:Cc:To:From:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; bh=u5E7vy5FCQHFKyu6tJoV6wJC83nXHT4AJvUAk2PKT8I=; b=rsDQ1vVowVUAz/ JejtFPEo54U6aZluGVPoXpyL2111+wr+6btCzSI+n+J6ambr+pHdUVxSWYoAKam82KUvILWeyZO5J VEfcrLHQ9bq5vfVeWob5KvYK2sfzOZ37tUtTpU7f7QL7RBY4na2vcPWYiTQ21zri26bnqrx7RH+VB v9TZ31wPmRRrtB1KOZtV3n691Bxz2WQWJNS8+afuxizrZnetdl60bAqgl6ZmBSwKwqCmGpM1fyRwv nBEPBM9qu0sjD1h8nFPGTtdMTmXsSrUZX3/OxOx98v5cmXLWb2O6o6nE1tzuR0dB3fsK//xKec7io Yx3KnyRqL/+gRxoLLfIw==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.97.1 #2 (Red Hat Linux)) id 1rrvdb-0000000EjUW-3Dt9; Wed, 03 Apr 2024 08:06:27 +0000 Received: from mail-pl1-x632.google.com ([2607:f8b0:4864:20::632]) by bombadil.infradead.org with esmtps (Exim 4.97.1 #2 (Red Hat Linux)) id 1rrvd7-0000000Ej0X-1dbU for linux-riscv@lists.infradead.org; Wed, 03 Apr 2024 08:06:01 +0000 Received: by mail-pl1-x632.google.com with SMTP id d9443c01a7336-1e2987e9d67so1072315ad.1 for ; Wed, 03 Apr 2024 01:05:57 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=rivosinc-com.20230601.gappssmtp.com; s=20230601; t=1712131557; x=1712736357; darn=lists.infradead.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=LCMipi4iMwcecw5jkK7vSbrK4Smr7cw1nRJDkHi5YgY=; b=t5P892YEV8FnTiXMI9YwNqZMgp085n93dzQKXP3PDos6Kl/2wEKGIbSW8pxMru296p uDPwKALxRahcC2Ik6V98Edz+AaeLVTJg5SpdTFQkYVuVMrYfAFlajvKSegjreCXrYHsU Uer2UedIvKXgPqiDJ2dYO2MMd8RkdqRI4WFcLIWxpyxNRTYV3SaeEGB7gg4m6VMFFOCW GzIsAxgbW6s2FNZElvLXMw1Ak4dM4cl4HVvHieUElVvuzSr35MxKFRpgwJXiqQmMtJ7b Xokxkar6HoVhx8AGJaeBm81F/2LtLjn8JKCDJc7ipPXdBC2sJXBmbw4vgAqDhe6Q54Od wIuA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1712131557; x=1712736357; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=LCMipi4iMwcecw5jkK7vSbrK4Smr7cw1nRJDkHi5YgY=; b=Twgh2og+fJScOKP8AwMr16gg/Nsg5vBbqqjeLKEolUBz9QC/AAutMHd2u6KI3wovSf SPFh2+5sUMqMNj4HT1Wdo3RwhAqwgmWSdzNm158g3Z3K8F34nOQnoYb3YwkEieg7lEoD pFgsOsSzYPDhF6fDxhI8fVUEF/2sX0ucUukula+U8aUNLk2w+C9Ahhq1LVn9n07soUDL K+rHJrGOBjTynA/n3a1EpQ2nE1K82FihqjEdQ9szQtHUaAE3V+cwaMPUm3tRjlzo3kH4 wQYa6VAaodPwazzFDdzOstSHo1bu8e37uiruKbTV2mPa8+srxV9ZRCwD1UadhOLBmvyH mmog== X-Forwarded-Encrypted: i=1; AJvYcCUxX/RD1PR8TX5srfImuMLxvxhlZLu0QzmfhwI1MVumZIvMN9POCupBNUQxU8bo0BOrSE4qEE9iezItsNj6uamXAU8J/zRj/xpYNN5vU3VR X-Gm-Message-State: AOJu0YwvcHLTkL2xy87zqPKbEe5uLoEG+oknVWH7x2vf01IXWPEcQ42T 2J3RMiFWKUKBwXEyfKPbmSekLsP1AMBj+hR15l++C9xQXTcEa/WIgI6/yb4VswM= X-Google-Smtp-Source: AGHT+IHpyx5a6XqGmtOIk6bFUng2qDzlcvAJJ7ibWLTxJ0Xo8UDyEPRszXuJnMno9PGr0QMK56dlfw== X-Received: by 2002:a17:902:d4d1:b0:1e0:ab65:85e5 with SMTP id o17-20020a170902d4d100b001e0ab6585e5mr2774053plg.1.1712131556762; Wed, 03 Apr 2024 01:05:56 -0700 (PDT) Received: from atishp.ba.rivosinc.com ([64.71.180.162]) by smtp.gmail.com with ESMTPSA id c12-20020a170902d48c00b001e0b5d49fc7sm12557229plg.161.2024.04.03.01.05.54 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 03 Apr 2024 01:05:55 -0700 (PDT) From: Atish Patra To: linux-kernel@vger.kernel.org Cc: Atish Patra , Anup Patel , Ajay Kaher , Alexandre Ghiti , Alexey Makhalov , Andrew Jones , Conor Dooley , Juergen Gross , kvm-riscv@lists.infradead.org, kvm@vger.kernel.org, linux-kselftest@vger.kernel.org, linux-riscv@lists.infradead.org, Mark Rutland , Palmer Dabbelt , Paolo Bonzini , Paul Walmsley , Shuah Khan , virtualization@lists.linux.dev, VMware PV-Drivers Reviewers , Will Deacon , x86@kernel.org Subject: [PATCH v5 20/22] KVM: riscv: selftests: Add SBI PMU selftest Date: Wed, 3 Apr 2024 01:04:49 -0700 Message-Id: <20240403080452.1007601-21-atishp@rivosinc.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240403080452.1007601-1-atishp@rivosinc.com> References: <20240403080452.1007601-1-atishp@rivosinc.com> MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20240403_010557_683743_5FCAEA17 X-CRM114-Status: GOOD ( 21.99 ) X-BeenThere: linux-riscv@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-riscv" Errors-To: linux-riscv-bounces+linux-riscv=archiver.kernel.org@lists.infradead.org This test implements basic sanity test and cycle/instret event counting tests. Reviewed-by: Anup Patel Signed-off-by: Atish Patra --- tools/testing/selftests/kvm/Makefile | 1 + .../selftests/kvm/riscv/sbi_pmu_test.c | 340 ++++++++++++++++++ 2 files changed, 341 insertions(+) create mode 100644 tools/testing/selftests/kvm/riscv/sbi_pmu_test.c diff --git a/tools/testing/selftests/kvm/Makefile b/tools/testing/selftests/kvm/Makefile index 741c7dc16afc..1cfcd2797ee4 100644 --- a/tools/testing/selftests/kvm/Makefile +++ b/tools/testing/selftests/kvm/Makefile @@ -189,6 +189,7 @@ TEST_GEN_PROGS_s390x += rseq_test TEST_GEN_PROGS_s390x += set_memory_region_test TEST_GEN_PROGS_s390x += kvm_binary_stats_test +TEST_GEN_PROGS_riscv += riscv/sbi_pmu_test TEST_GEN_PROGS_riscv += arch_timer TEST_GEN_PROGS_riscv += demand_paging_test TEST_GEN_PROGS_riscv += dirty_log_test diff --git a/tools/testing/selftests/kvm/riscv/sbi_pmu_test.c b/tools/testing/selftests/kvm/riscv/sbi_pmu_test.c new file mode 100644 index 000000000000..8e7c7a3172d8 --- /dev/null +++ b/tools/testing/selftests/kvm/riscv/sbi_pmu_test.c @@ -0,0 +1,340 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * sbi_pmu_test.c - Tests the riscv64 SBI PMU functionality. + * + * Copyright (c) 2024, Rivos Inc. + */ + +#include +#include +#include +#include +#include +#include "kvm_util.h" +#include "test_util.h" +#include "processor.h" +#include "sbi.h" + +/* Maximum counters(firmware + hardware) */ +#define RISCV_MAX_PMU_COUNTERS 64 +union sbi_pmu_ctr_info ctrinfo_arr[RISCV_MAX_PMU_COUNTERS]; + +/* Cache the available counters in a bitmask */ +static unsigned long counter_mask_available; + +unsigned long pmu_csr_read_num(int csr_num) +{ +#define switchcase_csr_read(__csr_num, __val) {\ + case __csr_num: \ + __val = csr_read(__csr_num); \ + break; } +#define switchcase_csr_read_2(__csr_num, __val) {\ + switchcase_csr_read(__csr_num + 0, __val) \ + switchcase_csr_read(__csr_num + 1, __val)} +#define switchcase_csr_read_4(__csr_num, __val) {\ + switchcase_csr_read_2(__csr_num + 0, __val) \ + switchcase_csr_read_2(__csr_num + 2, __val)} +#define switchcase_csr_read_8(__csr_num, __val) {\ + switchcase_csr_read_4(__csr_num + 0, __val) \ + switchcase_csr_read_4(__csr_num + 4, __val)} +#define switchcase_csr_read_16(__csr_num, __val) {\ + switchcase_csr_read_8(__csr_num + 0, __val) \ + switchcase_csr_read_8(__csr_num + 8, __val)} +#define switchcase_csr_read_32(__csr_num, __val) {\ + switchcase_csr_read_16(__csr_num + 0, __val) \ + switchcase_csr_read_16(__csr_num + 16, __val)} + + unsigned long ret = 0; + + switch (csr_num) { + switchcase_csr_read_32(CSR_CYCLE, ret) + switchcase_csr_read_32(CSR_CYCLEH, ret) + default : + break; + } + + return ret; +#undef switchcase_csr_read_32 +#undef switchcase_csr_read_16 +#undef switchcase_csr_read_8 +#undef switchcase_csr_read_4 +#undef switchcase_csr_read_2 +#undef switchcase_csr_read +} + +static inline void dummy_func_loop(uint64_t iter) +{ + int i = 0; + + while (i < iter) { + asm volatile("nop"); + i++; + } +} + +static void start_counter(unsigned long counter, unsigned long start_flags, + unsigned long ival) +{ + struct sbiret ret; + + ret = sbi_ecall(SBI_EXT_PMU, SBI_EXT_PMU_COUNTER_START, counter, 1, start_flags, + ival, 0, 0); + __GUEST_ASSERT(ret.error == 0, "Unable to start counter %ld\n", counter); +} + +/* This should be invoked only for reset counter use case */ +static void stop_reset_counter(unsigned long counter, unsigned long stop_flags) +{ + struct sbiret ret; + + ret = sbi_ecall(SBI_EXT_PMU, SBI_EXT_PMU_COUNTER_STOP, counter, 1, + stop_flags | SBI_PMU_STOP_FLAG_RESET, 0, 0, 0); + __GUEST_ASSERT(ret.error == SBI_ERR_ALREADY_STOPPED, + "Unable to stop counter %ld\n", counter); +} + +static void stop_counter(unsigned long counter, unsigned long stop_flags) +{ + struct sbiret ret; + + ret = sbi_ecall(SBI_EXT_PMU, SBI_EXT_PMU_COUNTER_STOP, counter, 1, stop_flags, + 0, 0, 0); + __GUEST_ASSERT(ret.error == 0, "Unable to stop counter %ld error %ld\n", + counter, ret.error); +} + +static void guest_illegal_exception_handler(struct ex_regs *regs) +{ + __GUEST_ASSERT(regs->cause == EXC_INST_ILLEGAL, + "Unexpected exception handler %lx\n", regs->cause); + + /* skip the trapping instruction */ + regs->epc += 4; +} + +static unsigned long get_counter_index(unsigned long cbase, unsigned long cmask, + unsigned long cflags, + unsigned long event) +{ + struct sbiret ret; + + ret = sbi_ecall(SBI_EXT_PMU, SBI_EXT_PMU_COUNTER_CFG_MATCH, cbase, cmask, + cflags, event, 0, 0); + __GUEST_ASSERT(ret.error == 0, "config matching failed %ld\n", ret.error); + GUEST_ASSERT(ret.value < RISCV_MAX_PMU_COUNTERS); + GUEST_ASSERT(BIT(ret.value) & counter_mask_available); + + return ret.value; +} + +static unsigned long get_num_counters(void) +{ + struct sbiret ret; + + ret = sbi_ecall(SBI_EXT_PMU, SBI_EXT_PMU_NUM_COUNTERS, 0, 0, 0, 0, 0, 0); + + __GUEST_ASSERT(ret.error == 0, "Unable to retrieve number of counters from SBI PMU"); + __GUEST_ASSERT(ret.value < RISCV_MAX_PMU_COUNTERS, + "Invalid number of counters %ld\n", ret.value); + + return ret.value; +} + +static void update_counter_info(int num_counters) +{ + int i = 0; + struct sbiret ret; + + for (i = 0; i < num_counters; i++) { + ret = sbi_ecall(SBI_EXT_PMU, SBI_EXT_PMU_COUNTER_GET_INFO, i, 0, 0, 0, 0, 0); + + /* There can be gaps in logical counter indicies*/ + if (ret.error) + continue; + GUEST_ASSERT_NE(ret.value, 0); + + ctrinfo_arr[i].value = ret.value; + counter_mask_available |= BIT(i); + } + + GUEST_ASSERT(counter_mask_available > 0); +} + +static unsigned long read_counter(int idx, union sbi_pmu_ctr_info ctrinfo) +{ + unsigned long counter_val = 0; + struct sbiret ret; + + __GUEST_ASSERT(ctrinfo.type < 2, "Invalid counter type %d", ctrinfo.type); + + if (ctrinfo.type == SBI_PMU_CTR_TYPE_HW) { + counter_val = pmu_csr_read_num(ctrinfo.csr); + } else if (ctrinfo.type == SBI_PMU_CTR_TYPE_FW) { + ret = sbi_ecall(SBI_EXT_PMU, SBI_EXT_PMU_COUNTER_FW_READ, idx, 0, 0, 0, 0, 0); + GUEST_ASSERT(ret.error == 0); + counter_val = ret.value; + } + + return counter_val; +} + +static void test_pmu_event(unsigned long event) +{ + unsigned long counter; + unsigned long counter_value_pre, counter_value_post; + unsigned long counter_init_value = 100; + + counter = get_counter_index(0, counter_mask_available, 0, event); + counter_value_pre = read_counter(counter, ctrinfo_arr[counter]); + + /* Do not set the initial value */ + start_counter(counter, 0, counter_init_value); + dummy_func_loop(10000); + stop_counter(counter, 0); + + counter_value_post = read_counter(counter, ctrinfo_arr[counter]); + __GUEST_ASSERT(counter_value_post > counter_value_pre, + "counter_value_post %lx counter_value_pre %lx\n", + counter_value_post, counter_value_pre); + + /* Now set the initial value and compare */ + start_counter(counter, SBI_PMU_START_FLAG_SET_INIT_VALUE, counter_init_value); + dummy_func_loop(10000); + stop_counter(counter, 0); + + counter_value_post = read_counter(counter, ctrinfo_arr[counter]); + __GUEST_ASSERT(counter_value_post > counter_init_value, + "counter_value_post %lx counter_init_value %lx\n", + counter_value_post, counter_init_value); + + stop_reset_counter(counter, 0); +} + +static void test_invalid_event(void) +{ + struct sbiret ret; + unsigned long event = 0x1234; /* A random event */ + + ret = sbi_ecall(SBI_EXT_PMU, SBI_EXT_PMU_COUNTER_CFG_MATCH, 0, + counter_mask_available, 0, event, 0, 0); + GUEST_ASSERT_EQ(ret.error, SBI_ERR_NOT_SUPPORTED); +} + +static void test_pmu_events(void) +{ + int num_counters = 0; + + /* Get the counter details */ + num_counters = get_num_counters(); + update_counter_info(num_counters); + + /* Sanity testing for any random invalid event */ + test_invalid_event(); + + /* Only these two events are guaranteed to be present */ + test_pmu_event(SBI_PMU_HW_CPU_CYCLES); + test_pmu_event(SBI_PMU_HW_INSTRUCTIONS); + + GUEST_DONE(); +} + +static void test_pmu_basic_sanity(void) +{ + long out_val = 0; + bool probe; + struct sbiret ret; + int num_counters = 0, i; + union sbi_pmu_ctr_info ctrinfo; + + probe = guest_sbi_probe_extension(SBI_EXT_PMU, &out_val); + GUEST_ASSERT(probe && out_val == 1); + + num_counters = get_num_counters(); + + for (i = 0; i < num_counters; i++) { + ret = sbi_ecall(SBI_EXT_PMU, SBI_EXT_PMU_COUNTER_GET_INFO, i, + 0, 0, 0, 0, 0); + + /* There can be gaps in logical counter indicies*/ + if (ret.error) + continue; + GUEST_ASSERT_NE(ret.value, 0); + + ctrinfo.value = ret.value; + + /** + * Accesibillity check of hardware and read capability of firmware counters. + * The spec doesn't mandate any initial value. No need to check any value. + */ + read_counter(i, ctrinfo); + } + + GUEST_DONE(); +} + +static void run_vcpu(struct kvm_vcpu *vcpu) +{ + struct ucall uc; + + vcpu_run(vcpu); + switch (get_ucall(vcpu, &uc)) { + case UCALL_ABORT: + REPORT_GUEST_ASSERT(uc); + break; + case UCALL_DONE: + case UCALL_SYNC: + break; + default: + TEST_FAIL("Unknown ucall %lu", uc.cmd); + break; + } +} + +void test_vm_destroy(struct kvm_vm *vm) +{ + memset(ctrinfo_arr, 0, sizeof(union sbi_pmu_ctr_info) * RISCV_MAX_PMU_COUNTERS); + counter_mask_available = 0; + kvm_vm_free(vm); +} + +static void test_vm_basic_test(void *guest_code) +{ + struct kvm_vm *vm; + struct kvm_vcpu *vcpu; + + vm = vm_create_with_one_vcpu(&vcpu, guest_code); + __TEST_REQUIRE(__vcpu_has_sbi_ext(vcpu, KVM_RISCV_SBI_EXT_PMU), + "SBI PMU not available, skipping test"); + vm_init_vector_tables(vm); + /* Illegal instruction handler is required to verify read access without configuration */ + vm_install_exception_handler(vm, EXC_INST_ILLEGAL, guest_illegal_exception_handler); + + vcpu_init_vector_tables(vcpu); + run_vcpu(vcpu); + + test_vm_destroy(vm); +} + +static void test_vm_events_test(void *guest_code) +{ + struct kvm_vm *vm = NULL; + struct kvm_vcpu *vcpu = NULL; + + vm = vm_create_with_one_vcpu(&vcpu, guest_code); + __TEST_REQUIRE(__vcpu_has_sbi_ext(vcpu, KVM_RISCV_SBI_EXT_PMU), + "SBI PMU not available, skipping test"); + run_vcpu(vcpu); + + test_vm_destroy(vm); +} + +int main(void) +{ + test_vm_basic_test(test_pmu_basic_sanity); + pr_info("SBI PMU basic test : PASS\n"); + + test_vm_events_test(test_pmu_events); + pr_info("SBI PMU event verification test : PASS\n"); + + return 0; +} From patchwork Wed Apr 3 08:04:50 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Atish Kumar Patra X-Patchwork-Id: 13615562 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id A21A9CD1294 for ; Wed, 3 Apr 2024 09:19:29 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:MIME-Version:References:In-Reply-To: Message-Id:Date:Subject:Cc:To:From:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; bh=I/jbKOHoSq25COYa6MKxHHI0QZpi6AE+bbMxd8v5pns=; b=DuMGN/gZiJj8pU x3X8M5jfROiLKjQ44/zLomWC+ot8qC7W2QQLQ2dJz4nQSYrisb33PKM7/P0Tn9Lv+0w9eTc5rUPTA OTDQqBwX+p2QCrvJeaVTOFfZXfKxOEQX5CSKti4q0YiXmmqM/oOrCfwu/1H/g0WX5V1gV+g/O6e+3 +Dv1/F4SqalftxHjQ832hpVaMyJKjDPyX58fD1iwdI5alJpkUHEKpQuqfgR3xyAAmS30p3CD5npx+ rl/UvShN2uweEA9ptC2RYXdnzb0mBkKap5gMB881QO706ILotoGLV2rmpxwENT5NEprfv7K6tfTb4 MObJN16SjHbKrCo/Un9w==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.97.1 #2 (Red Hat Linux)) id 1rrwmC-0000000FAQ6-15gO; Wed, 03 Apr 2024 09:19:24 +0000 Received: from mail-pl1-x636.google.com ([2607:f8b0:4864:20::636]) by bombadil.infradead.org with esmtps (Exim 4.97.1 #2 (Red Hat Linux)) id 1rrvd9-0000000Ej2c-3WIO for linux-riscv@lists.infradead.org; Wed, 03 Apr 2024 08:06:03 +0000 Received: by mail-pl1-x636.google.com with SMTP id d9443c01a7336-1def89f0cfdso5308465ad.0 for ; Wed, 03 Apr 2024 01:05:59 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=rivosinc-com.20230601.gappssmtp.com; s=20230601; t=1712131559; x=1712736359; darn=lists.infradead.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=QiRGaFoKeEXKkn+uQbOU1j6rVkfyQcqx7Ktuzq541sw=; b=upZYHqex1TwG/jByuqXOjxUygY/dyf1b6KmWACIBh5x7a+VG8wWHiJ8W30HZyF2xAq o0XaE1wMAGLa4T3IKpNn5xcqmcmkHHccs+Os7fVkkzVCugWP/nxxrT4ocvraw5Ma7+cB iKYHsP5tOBGrv1Ru7qyvlHYg2L36mYUGpUX05JxZ79l+ZVTQtJdr81sY10ii9sgttHZn QMt0nr0rkihJtqkH9sodeByRHxTl+aTG9J6L3FvlP7SyfNHjsFJACOxxwS3k9he7IYRl rygpqSMtSQ4nBMkMezHF9y7H9gtAuSuAV0GqgJzSSfVx+5MeAhKcTifzgz6okGxrxKMm ZEoA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1712131559; x=1712736359; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=QiRGaFoKeEXKkn+uQbOU1j6rVkfyQcqx7Ktuzq541sw=; b=df8jdp6SWdF+rDifYVKVFBunVjd86NhTTJxgyk9r51Ecbfz2UNA0dMTeDlqDfx1hkm aqrcpz3Oh4zjQWxQelEASJJnfc0FGeo8gEg967fVICBa+hK9FAaKvhZ0dYgDftpXu8G1 J2pdNzWKS8d/wiZGusH7F/YWgkEOFrFrejsTz5fdeIZKxHPBc1ol20Tif0DQCHt6QxWZ JOtnuGo2oWlM8aDys/O9Wq0xm82SOqGydyA99m0G3yWdG+m/GPKtj40gwgWK/nmZhNik ZbOQKKKb/m6oLFR81ePl59vqawZVTUDd2B+BjJuBs0gL7nFswadHenV/mjl/sTHH0NDr ojiw== X-Forwarded-Encrypted: i=1; AJvYcCWlyMf9w8kOmDdu0hQ6T1DkVLHjifsq52XTbCOLD3o8tpZZQk2goA/2BqzKeUASbEJnc60nH2P4B0ZLhfCqJcnRBjnK0VeEPo/tjYr0hluQ X-Gm-Message-State: AOJu0YxX/JPdgAdQy5AiGt92WGK65Ois3ZUolx60qvQcdPbfiVGQgGgI JOxtFuBu/Fn6k9urioM5cvkRq0ZmV8/Xc0lV/NqE1Y/v8ApQyD6wT6VjnqTfaPE= X-Google-Smtp-Source: AGHT+IFXXTLLFkv43kYTnbNPYdO7OcKcoIWVKkiXhLEEPUmEqBIkqvXfcIj5Q46ZbmbSydNL7e6NQg== X-Received: by 2002:a17:902:e747:b0:1e0:e8b5:3225 with SMTP id p7-20020a170902e74700b001e0e8b53225mr3012611plf.12.1712131559154; Wed, 03 Apr 2024 01:05:59 -0700 (PDT) Received: from atishp.ba.rivosinc.com ([64.71.180.162]) by smtp.gmail.com with ESMTPSA id c12-20020a170902d48c00b001e0b5d49fc7sm12557229plg.161.2024.04.03.01.05.56 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 03 Apr 2024 01:05:57 -0700 (PDT) From: Atish Patra To: linux-kernel@vger.kernel.org Cc: Atish Patra , Anup Patel , Ajay Kaher , Alexandre Ghiti , Alexey Makhalov , Andrew Jones , Conor Dooley , Juergen Gross , kvm-riscv@lists.infradead.org, kvm@vger.kernel.org, linux-kselftest@vger.kernel.org, linux-riscv@lists.infradead.org, Mark Rutland , Palmer Dabbelt , Paolo Bonzini , Paul Walmsley , Shuah Khan , virtualization@lists.linux.dev, VMware PV-Drivers Reviewers , Will Deacon , x86@kernel.org Subject: [PATCH v5 21/22] KVM: riscv: selftests: Add a test for PMU snapshot functionality Date: Wed, 3 Apr 2024 01:04:50 -0700 Message-Id: <20240403080452.1007601-22-atishp@rivosinc.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240403080452.1007601-1-atishp@rivosinc.com> References: <20240403080452.1007601-1-atishp@rivosinc.com> MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20240403_010600_104508_CD150EEF X-CRM114-Status: GOOD ( 21.52 ) X-BeenThere: linux-riscv@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-riscv" Errors-To: linux-riscv-bounces+linux-riscv=archiver.kernel.org@lists.infradead.org Verify PMU snapshot functionality by setting up the shared memory correctly and reading the counter values from the shared memory instead of the CSR. Reviewed-by: Anup Patel Signed-off-by: Atish Patra Reviewed-by: Andrew Jones --- .../testing/selftests/kvm/include/riscv/sbi.h | 25 ++++ .../selftests/kvm/lib/riscv/processor.c | 12 ++ .../selftests/kvm/riscv/sbi_pmu_test.c | 127 ++++++++++++++++++ 3 files changed, 164 insertions(+) diff --git a/tools/testing/selftests/kvm/include/riscv/sbi.h b/tools/testing/selftests/kvm/include/riscv/sbi.h index 6675ca673c77..8c98bd99d450 100644 --- a/tools/testing/selftests/kvm/include/riscv/sbi.h +++ b/tools/testing/selftests/kvm/include/riscv/sbi.h @@ -8,6 +8,12 @@ #ifndef SELFTEST_KVM_SBI_H #define SELFTEST_KVM_SBI_H +/* SBI spec version fields */ +#define SBI_SPEC_VERSION_DEFAULT 0x1 +#define SBI_SPEC_VERSION_MAJOR_SHIFT 24 +#define SBI_SPEC_VERSION_MAJOR_MASK 0x7f +#define SBI_SPEC_VERSION_MINOR_MASK 0xffffff + /* SBI return error codes */ #define SBI_SUCCESS 0 #define SBI_ERR_FAILURE -1 @@ -33,6 +39,9 @@ enum sbi_ext_id { }; enum sbi_ext_base_fid { + SBI_EXT_BASE_GET_SPEC_VERSION = 0, + SBI_EXT_BASE_GET_IMP_ID, + SBI_EXT_BASE_GET_IMP_VERSION, SBI_EXT_BASE_PROBE_EXT = 3, }; enum sbi_ext_pmu_fid { @@ -60,6 +69,12 @@ union sbi_pmu_ctr_info { }; }; +struct riscv_pmu_snapshot_data { + u64 ctr_overflow_mask; + u64 ctr_values[64]; + u64 reserved[447]; +}; + struct sbiret { long error; long value; @@ -113,4 +128,14 @@ struct sbiret sbi_ecall(int ext, int fid, unsigned long arg0, bool guest_sbi_probe_extension(int extid, long *out_val); +/* Make SBI version */ +static inline unsigned long sbi_mk_version(unsigned long major, + unsigned long minor) +{ + return ((major & SBI_SPEC_VERSION_MAJOR_MASK) << + SBI_SPEC_VERSION_MAJOR_SHIFT) | minor; +} + +unsigned long get_host_sbi_spec_version(void); + #endif /* SELFTEST_KVM_SBI_H */ diff --git a/tools/testing/selftests/kvm/lib/riscv/processor.c b/tools/testing/selftests/kvm/lib/riscv/processor.c index e8211f5d6863..ccb35573749c 100644 --- a/tools/testing/selftests/kvm/lib/riscv/processor.c +++ b/tools/testing/selftests/kvm/lib/riscv/processor.c @@ -502,3 +502,15 @@ bool guest_sbi_probe_extension(int extid, long *out_val) return true; } + +unsigned long get_host_sbi_spec_version(void) +{ + struct sbiret ret; + + ret = sbi_ecall(SBI_EXT_BASE, SBI_EXT_BASE_GET_SPEC_VERSION, 0, + 0, 0, 0, 0, 0); + + GUEST_ASSERT(!ret.error); + + return ret.value; +} diff --git a/tools/testing/selftests/kvm/riscv/sbi_pmu_test.c b/tools/testing/selftests/kvm/riscv/sbi_pmu_test.c index 8e7c7a3172d8..7d195be5c3d9 100644 --- a/tools/testing/selftests/kvm/riscv/sbi_pmu_test.c +++ b/tools/testing/selftests/kvm/riscv/sbi_pmu_test.c @@ -19,6 +19,11 @@ #define RISCV_MAX_PMU_COUNTERS 64 union sbi_pmu_ctr_info ctrinfo_arr[RISCV_MAX_PMU_COUNTERS]; +/* Snapshot shared memory data */ +#define PMU_SNAPSHOT_GPA_BASE BIT(30) +static void *snapshot_gva; +static vm_paddr_t snapshot_gpa; + /* Cache the available counters in a bitmask */ static unsigned long counter_mask_available; @@ -178,6 +183,32 @@ static unsigned long read_counter(int idx, union sbi_pmu_ctr_info ctrinfo) return counter_val; } +static inline void verify_sbi_requirement_assert(void) +{ + long out_val = 0; + bool probe; + + probe = guest_sbi_probe_extension(SBI_EXT_PMU, &out_val); + GUEST_ASSERT(probe && out_val == 1); + + if (get_host_sbi_spec_version() < sbi_mk_version(2, 0)) + __GUEST_ASSERT(0, "SBI implementation version doesn't support PMU Snapshot"); +} + +static void snapshot_set_shmem(vm_paddr_t gpa, unsigned long flags) +{ + unsigned long lo = (unsigned long)gpa; +#if __riscv_xlen == 32 + unsigned long hi = (unsigned long)(gpa >> 32); +#else + unsigned long hi = gpa == -1 ? -1 : 0; +#endif + struct sbiret ret = sbi_ecall(SBI_EXT_PMU, SBI_EXT_PMU_SNAPSHOT_SET_SHMEM, + lo, hi, flags, 0, 0, 0); + + GUEST_ASSERT(ret.value == 0 && ret.error == 0); +} + static void test_pmu_event(unsigned long event) { unsigned long counter; @@ -210,6 +241,41 @@ static void test_pmu_event(unsigned long event) stop_reset_counter(counter, 0); } +static void test_pmu_event_snapshot(unsigned long event) +{ + unsigned long counter; + unsigned long counter_value_pre, counter_value_post; + unsigned long counter_init_value = 100; + struct riscv_pmu_snapshot_data *snapshot_data = snapshot_gva; + + counter = get_counter_index(0, counter_mask_available, 0, event); + counter_value_pre = read_counter(counter, ctrinfo_arr[counter]); + + /* Do not set the initial value */ + start_counter(counter, 0, 0); + dummy_func_loop(10000); + stop_counter(counter, SBI_PMU_STOP_FLAG_TAKE_SNAPSHOT); + + /* The counter value is updated w.r.t relative index of cbase */ + counter_value_post = READ_ONCE(snapshot_data->ctr_values[0]); + __GUEST_ASSERT(counter_value_post > counter_value_pre, + "counter_value_post %lx counter_value_pre %lx\n", + counter_value_post, counter_value_pre); + + /* Now set the initial value and compare */ + WRITE_ONCE(snapshot_data->ctr_values[0], counter_init_value); + start_counter(counter, SBI_PMU_START_FLAG_INIT_SNAPSHOT, 0); + dummy_func_loop(10000); + stop_counter(counter, SBI_PMU_STOP_FLAG_TAKE_SNAPSHOT); + + counter_value_post = READ_ONCE(snapshot_data->ctr_values[0]); + __GUEST_ASSERT(counter_value_post > counter_init_value, + "counter_value_post %lx counter_init_value %lx for counter\n", + counter_value_post, counter_init_value); + + stop_reset_counter(counter, 0); +} + static void test_invalid_event(void) { struct sbiret ret; @@ -272,6 +338,34 @@ static void test_pmu_basic_sanity(void) GUEST_DONE(); } +static void test_pmu_events_snaphost(void) +{ + int num_counters = 0; + struct riscv_pmu_snapshot_data *snapshot_data = snapshot_gva; + int i; + + /* Verify presence of SBI PMU and minimum requrired SBI version */ + verify_sbi_requirement_assert(); + + snapshot_set_shmem(snapshot_gpa, 0); + + /* Get the counter details */ + num_counters = get_num_counters(); + update_counter_info(num_counters); + + /* Validate shared memory access */ + GUEST_ASSERT_EQ(READ_ONCE(snapshot_data->ctr_overflow_mask), 0); + for (i = 0; i < num_counters; i++) { + if (counter_mask_available & (BIT(i))) + GUEST_ASSERT_EQ(READ_ONCE(snapshot_data->ctr_values[i]), 0); + } + /* Only these two events are guranteed to be present */ + test_pmu_event_snapshot(SBI_PMU_HW_CPU_CYCLES); + test_pmu_event_snapshot(SBI_PMU_HW_INSTRUCTIONS); + + GUEST_DONE(); +} + static void run_vcpu(struct kvm_vcpu *vcpu) { struct ucall uc; @@ -328,13 +422,46 @@ static void test_vm_events_test(void *guest_code) test_vm_destroy(vm); } +static void test_vm_setup_snapshot_mem(struct kvm_vm *vm, struct kvm_vcpu *vcpu) +{ + /* PMU Snapshot requires single page only */ + vm_userspace_mem_region_add(vm, VM_MEM_SRC_ANONYMOUS, PMU_SNAPSHOT_GPA_BASE, 1, 1, 0); + /* PMU_SNAPSHOT_GPA_BASE is identity mapped */ + virt_map(vm, PMU_SNAPSHOT_GPA_BASE, PMU_SNAPSHOT_GPA_BASE, 1); + + snapshot_gva = (void *)(PMU_SNAPSHOT_GPA_BASE); + snapshot_gpa = addr_gva2gpa(vcpu->vm, (vm_vaddr_t)snapshot_gva); + sync_global_to_guest(vcpu->vm, snapshot_gva); + sync_global_to_guest(vcpu->vm, snapshot_gpa); +} + +static void test_vm_events_snapshot_test(void *guest_code) +{ + struct kvm_vm *vm = NULL; + struct kvm_vcpu *vcpu; + + vm = vm_create_with_one_vcpu(&vcpu, guest_code); + __TEST_REQUIRE(__vcpu_has_sbi_ext(vcpu, KVM_RISCV_SBI_EXT_PMU), + "SBI PMU not available, skipping test"); + + test_vm_setup_snapshot_mem(vm, vcpu); + + run_vcpu(vcpu); + + test_vm_destroy(vm); +} + int main(void) { + pr_info("SBI PMU basic test : starting\n"); test_vm_basic_test(test_pmu_basic_sanity); pr_info("SBI PMU basic test : PASS\n"); test_vm_events_test(test_pmu_events); pr_info("SBI PMU event verification test : PASS\n"); + test_vm_events_snapshot_test(test_pmu_events_snaphost); + pr_info("SBI PMU event verification with snapshot test : PASS\n"); + return 0; } From patchwork Wed Apr 3 08:04:51 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Atish Kumar Patra X-Patchwork-Id: 13615564 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 61CECCD1294 for ; Wed, 3 Apr 2024 09:19:39 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:MIME-Version:References:In-Reply-To: Message-Id:Date:Subject:Cc:To:From:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; bh=oa9cDIpDax/yKTzMQfgKN3xjx86nTZZ1X0SE4uCUPZ4=; b=uZQ1d2g6s/aEVH 4bPijnKhZRAoR5JtnomKAcwtEOafxtFZnl2AW4vJNlIbXI5QRle6Qo91F27ayUsqIA964yAUtOTtW 97M3itZPsV39mnAVD8+4pBampyhpPoUbgCUI040CJNu1boJInRHM+M0F3DDyQDI73lM/P/gxtApZQ wprLLQMpEt65771fW1NwwPEIu0VHrAyAJI5GGtVRxzEdZhoCwjn9dRZTNfBwhjARAENBuJ6em7JVE jfFrB3tRxYo8brb2r1yyZqOOeFQ6Ct0MA7RsHEyLQ031615Fv0thjBFx0sDL8rJ0E6rGvELkkG82t RqnI4MrnN6ooINmz3bBw==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.97.1 #2 (Red Hat Linux)) id 1rrwmL-0000000FAY5-0gBQ; Wed, 03 Apr 2024 09:19:33 +0000 Received: from mail-pl1-x62e.google.com ([2607:f8b0:4864:20::62e]) by bombadil.infradead.org with esmtps (Exim 4.97.1 #2 (Red Hat Linux)) id 1rrvdE-0000000Ej5f-2TtU for linux-riscv@lists.infradead.org; Wed, 03 Apr 2024 08:06:11 +0000 Received: by mail-pl1-x62e.google.com with SMTP id d9443c01a7336-1e0411c0a52so51652095ad.0 for ; Wed, 03 Apr 2024 01:06:02 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=rivosinc-com.20230601.gappssmtp.com; s=20230601; t=1712131562; x=1712736362; darn=lists.infradead.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=08Ow0qzJAlLAfVOdK6hW39Nfp7LW+caK9DtQyZhdmmU=; b=E0rmXj/QuULAtN9xBEWRUMXfy2U3vjkqn5buK1rMeJNoWEgSLTWyd7uY7BxEBANkdW lC2n5vZoru5d0fZV6fiRu/i+ZxJ46eR5dMVN84E7sswj4qsMxv8G9UPyg9gzBO9Uvhvy FWsZLBHwl8/67NjWJmKBeWiHr/5e2h+E4OeRYclmL4zJ3wQrAfwU211HGLOpFQ3T71H3 dbEW13shJQMn5jIKS3Y9OE0NBnBel6W8RpBhWi1jQ0OAA1/Tnl0Eul9LRa565/SURV63 /ZmetZkK+qIKv5UBkB6oEZETm1g5AxlRDS0sVcL0o76q3UnwX9LKcP+l19G7OOAT3ikO SIRg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1712131562; x=1712736362; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=08Ow0qzJAlLAfVOdK6hW39Nfp7LW+caK9DtQyZhdmmU=; b=mr9xnxLXJYFtTAcxrYVsPbLqnKXtVYeECPK2D2XkQCUub7zKlERU3AKERoSzupgpmr vb1gFBRa0uQb0AvhYrIIioH+Hr4YxN8zUZYEoihofJ6yaqNxpzKrxQHU97V62PkaI8SI bRiuhWxc52yXGSrnNo+op1dbv77UQ2j8yuUH697slanDM5/kZ8/gOyNNxwRGCn0Pm11D V4W5oK5OpuIWuh474y4+pKRqmt5xmsQtjqPqX65R6DiioiKji1i/QyGzJRItwv0TD1PS 8W/IKpuIS8H5KuUK+Twqve1UGE+KDutfoFhuRa5veWK768p7y/Z1ea+Vlv/cZDlIuKkz yQ/w== X-Forwarded-Encrypted: i=1; AJvYcCUByefNmiVLfeBaDFlnMmTKVOpIGJpiwpVe2ceDtQozHt7s2hTgBfVrJ3/GOPE8QjZX45jgmTk4wYisZbELahSgsfNXpVCqOSK6eMDxbqIh X-Gm-Message-State: AOJu0YzO+Jzov9W1D87OuT/KZeETSIiQfhMf+PTH/EYKJHB7ZZYSmfV6 3iTTFWsK11qe0X20S4MHrYj9bHXueI7Y8vIyOFiwrZccXxz0xNxDrDDZlZYoCTk= X-Google-Smtp-Source: AGHT+IE72ENkNXFbTzbhg6SzqOY0byxQCRn9OXM0YoFZNh+Y8OZZcNtpF6ZIM4eDWD3GUsrp+79BKw== X-Received: by 2002:a17:902:ea10:b0:1e0:e6b0:2364 with SMTP id s16-20020a170902ea1000b001e0e6b02364mr14335253plg.64.1712131562243; Wed, 03 Apr 2024 01:06:02 -0700 (PDT) Received: from atishp.ba.rivosinc.com ([64.71.180.162]) by smtp.gmail.com with ESMTPSA id c12-20020a170902d48c00b001e0b5d49fc7sm12557229plg.161.2024.04.03.01.05.59 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 03 Apr 2024 01:06:00 -0700 (PDT) From: Atish Patra To: linux-kernel@vger.kernel.org Cc: Atish Patra , Anup Patel , Ajay Kaher , Alexandre Ghiti , Alexey Makhalov , Andrew Jones , Conor Dooley , Juergen Gross , kvm-riscv@lists.infradead.org, kvm@vger.kernel.org, linux-kselftest@vger.kernel.org, linux-riscv@lists.infradead.org, Mark Rutland , Palmer Dabbelt , Paolo Bonzini , Paul Walmsley , Shuah Khan , virtualization@lists.linux.dev, VMware PV-Drivers Reviewers , Will Deacon , x86@kernel.org Subject: [PATCH v5 22/22] KVM: riscv: selftests: Add a test for counter overflow Date: Wed, 3 Apr 2024 01:04:51 -0700 Message-Id: <20240403080452.1007601-23-atishp@rivosinc.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240403080452.1007601-1-atishp@rivosinc.com> References: <20240403080452.1007601-1-atishp@rivosinc.com> MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20240403_010605_301052_AA17147D X-CRM114-Status: GOOD ( 17.80 ) X-BeenThere: linux-riscv@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-riscv" Errors-To: linux-riscv-bounces+linux-riscv=archiver.kernel.org@lists.infradead.org Add a test for verifying overflow interrupt. Currently, it relies on overflow support on cycle/instret events. This test works for cycle/ instret events which support sampling via hpmcounters on the platform. There are no ISA extensions to detect if a platform supports that. Thus, this test will fail on platform with virtualization but doesn't support overflow on these two events. Reviewed-by: Anup Patel Signed-off-by: Atish Patra Reviewed-by: Andrew Jones --- .../selftests/kvm/riscv/sbi_pmu_test.c | 114 ++++++++++++++++++ 1 file changed, 114 insertions(+) diff --git a/tools/testing/selftests/kvm/riscv/sbi_pmu_test.c b/tools/testing/selftests/kvm/riscv/sbi_pmu_test.c index 7d195be5c3d9..451db956b885 100644 --- a/tools/testing/selftests/kvm/riscv/sbi_pmu_test.c +++ b/tools/testing/selftests/kvm/riscv/sbi_pmu_test.c @@ -14,6 +14,7 @@ #include "test_util.h" #include "processor.h" #include "sbi.h" +#include "arch_timer.h" /* Maximum counters(firmware + hardware) */ #define RISCV_MAX_PMU_COUNTERS 64 @@ -24,6 +25,9 @@ union sbi_pmu_ctr_info ctrinfo_arr[RISCV_MAX_PMU_COUNTERS]; static void *snapshot_gva; static vm_paddr_t snapshot_gpa; +static int vcpu_shared_irq_count; +static int counter_in_use; + /* Cache the available counters in a bitmask */ static unsigned long counter_mask_available; @@ -117,6 +121,31 @@ static void guest_illegal_exception_handler(struct ex_regs *regs) regs->epc += 4; } +static void guest_irq_handler(struct ex_regs *regs) +{ + unsigned int irq_num = regs->cause & ~CAUSE_IRQ_FLAG; + struct riscv_pmu_snapshot_data *snapshot_data = snapshot_gva; + unsigned long overflown_mask; + unsigned long counter_val = 0; + + /* Validate that we are in the correct irq handler */ + GUEST_ASSERT_EQ(irq_num, IRQ_PMU_OVF); + + /* Stop all counters first to avoid further interrupts */ + stop_counter(counter_in_use, SBI_PMU_STOP_FLAG_TAKE_SNAPSHOT); + + csr_clear(CSR_SIP, BIT(IRQ_PMU_OVF)); + + overflown_mask = READ_ONCE(snapshot_data->ctr_overflow_mask); + GUEST_ASSERT(overflown_mask & 0x01); + + WRITE_ONCE(vcpu_shared_irq_count, vcpu_shared_irq_count+1); + + counter_val = READ_ONCE(snapshot_data->ctr_values[0]); + /* Now start the counter to mimick the real driver behavior */ + start_counter(counter_in_use, SBI_PMU_START_FLAG_SET_INIT_VALUE, counter_val); +} + static unsigned long get_counter_index(unsigned long cbase, unsigned long cmask, unsigned long cflags, unsigned long event) @@ -276,6 +305,33 @@ static void test_pmu_event_snapshot(unsigned long event) stop_reset_counter(counter, 0); } +static void test_pmu_event_overflow(unsigned long event) +{ + unsigned long counter; + unsigned long counter_value_post; + unsigned long counter_init_value = ULONG_MAX - 10000; + struct riscv_pmu_snapshot_data *snapshot_data = snapshot_gva; + + counter = get_counter_index(0, counter_mask_available, 0, event); + counter_in_use = counter; + + /* The counter value is updated w.r.t relative index of cbase passed to start/stop */ + WRITE_ONCE(snapshot_data->ctr_values[0], counter_init_value); + start_counter(counter, SBI_PMU_START_FLAG_INIT_SNAPSHOT, 0); + dummy_func_loop(10000); + udelay(msecs_to_usecs(2000)); + /* irq handler should have stopped the counter */ + stop_counter(counter, SBI_PMU_STOP_FLAG_TAKE_SNAPSHOT); + + counter_value_post = READ_ONCE(snapshot_data->ctr_values[0]); + /* The counter value after stopping should be less the init value due to overflow */ + __GUEST_ASSERT(counter_value_post < counter_init_value, + "counter_value_post %lx counter_init_value %lx for counter\n", + counter_value_post, counter_init_value); + + stop_reset_counter(counter, 0); +} + static void test_invalid_event(void) { struct sbiret ret; @@ -366,6 +422,34 @@ static void test_pmu_events_snaphost(void) GUEST_DONE(); } +static void test_pmu_events_overflow(void) +{ + int num_counters = 0; + + /* Verify presence of SBI PMU and minimum requrired SBI version */ + verify_sbi_requirement_assert(); + + snapshot_set_shmem(snapshot_gpa, 0); + csr_set(CSR_IE, BIT(IRQ_PMU_OVF)); + local_irq_enable(); + + /* Get the counter details */ + num_counters = get_num_counters(); + update_counter_info(num_counters); + + /* + * Qemu supports overflow for cycle/instruction. + * This test may fail on any platform that do not support overflow for these two events. + */ + test_pmu_event_overflow(SBI_PMU_HW_CPU_CYCLES); + GUEST_ASSERT_EQ(vcpu_shared_irq_count, 1); + + test_pmu_event_overflow(SBI_PMU_HW_INSTRUCTIONS); + GUEST_ASSERT_EQ(vcpu_shared_irq_count, 2); + + GUEST_DONE(); +} + static void run_vcpu(struct kvm_vcpu *vcpu) { struct ucall uc; @@ -451,6 +535,33 @@ static void test_vm_events_snapshot_test(void *guest_code) test_vm_destroy(vm); } +static void test_vm_events_overflow(void *guest_code) +{ + struct kvm_vm *vm = NULL; + struct kvm_vcpu *vcpu; + + vm = vm_create_with_one_vcpu(&vcpu, guest_code); + __TEST_REQUIRE(__vcpu_has_sbi_ext(vcpu, KVM_RISCV_SBI_EXT_PMU), + "SBI PMU not available, skipping test"); + + __TEST_REQUIRE(__vcpu_has_isa_ext(vcpu, KVM_RISCV_ISA_EXT_SSCOFPMF), + "Sscofpmf is not available, skipping overflow test"); + + + test_vm_setup_snapshot_mem(vm, vcpu); + vm_init_vector_tables(vm); + vm_install_interrupt_handler(vm, guest_irq_handler); + + vcpu_init_vector_tables(vcpu); + /* Initialize guest timer frequency. */ + vcpu_get_reg(vcpu, RISCV_TIMER_REG(frequency), &timer_freq); + sync_global_to_guest(vm, timer_freq); + + run_vcpu(vcpu); + + test_vm_destroy(vm); +} + int main(void) { pr_info("SBI PMU basic test : starting\n"); @@ -463,5 +574,8 @@ int main(void) test_vm_events_snapshot_test(test_pmu_events_snaphost); pr_info("SBI PMU event verification with snapshot test : PASS\n"); + test_vm_events_overflow(test_pmu_events_overflow); + pr_info("SBI PMU event verification with overflow test : PASS\n"); + return 0; }