From patchwork Wed Apr 3 10:52:04 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Peter Ujfalusi X-Patchwork-Id: 13615864 Received: from mgamail.intel.com (mgamail.intel.com [192.198.163.18]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 017761DFCE for ; Wed, 3 Apr 2024 10:52:09 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=192.198.163.18 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1712141531; cv=none; b=nS2ohzw4M0+OhxcEoaW/YWvC/0hPPlstlyBuo4OdWh5SHxLCRYn3FzE2Xquy+qERQU0knOtpyoNm6iNR6tAdKnKxrdsQcMDB9sYEIekHAT3APLqimFyL6W26aUP+ylxxf91xALKESp6uyS89RgTB5GqdGfSqIINB4VqG98DnZ/8= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1712141531; c=relaxed/simple; bh=G6G69kKaVR6Ff3xOyjllVLYIfO5HVjDwgECuLWhpX+s=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=JbZgZhMCblrZXIvVcC2Keqiq2zrxDMEbcR4vLyhMVqPno42JHj8mhkptIuyLGZ9+lV85SKtPq0YoyMLFQ4Dwpjcy8y/90egKoMzymq75pt5dc4t3o+ryqdShyQHrxCHhWLfj8foNl8bFAizDcPrw+Vp/uDxsUe4RwekrJ/Nuh/M= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linux.intel.com; spf=none smtp.mailfrom=linux.intel.com; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b=EXxHcOg/; arc=none smtp.client-ip=192.198.163.18 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linux.intel.com Authentication-Results: smtp.subspace.kernel.org; spf=none smtp.mailfrom=linux.intel.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b="EXxHcOg/" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1712141530; x=1743677530; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=G6G69kKaVR6Ff3xOyjllVLYIfO5HVjDwgECuLWhpX+s=; b=EXxHcOg/YDtbEZHknNPIbAib3oBu/BWyk685t2JyV9iCao2+JhHLrDeJ 8i18gyaIjmm/FasUcNuO84MCKvZ5DUPiSRyaoLofZ5jYANZ4uIKrbI+qQ XN+wJ7Zop2YulFdTnjIfTtM6R1cD0X5wC68wR2/Kl8/dU2Dm2jjjFGZYT xpzMM+hXs78XV4qKz82J9Q8X0EIatIAQEQKll91Zr4o6lHO5etG6Tuw+L IiBhaeM3nWoO8isUxNqqsY7hVyDMqcZHeR4Kun/PsnO/aokEHPzxJu754 Zs88F5Hw5xPDC7Rl4/0H4f+sZU7vUl2Rd4rr19yuHOopfUsor9c5vJ0Dm w==; X-CSE-ConnectionGUID: Kf6OA2vHRGqzdRLTvVbzeg== X-CSE-MsgGUID: iaucNxoSRNyeQ3/XpAAHVQ== X-IronPort-AV: E=McAfee;i="6600,9927,11032"; a="7212187" X-IronPort-AV: E=Sophos;i="6.07,177,1708416000"; d="scan'208";a="7212187" Received: from orviesa002.jf.intel.com ([10.64.159.142]) by fmvoesa112.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 03 Apr 2024 03:51:44 -0700 X-CSE-ConnectionGUID: oJvvTn5USfKFG/Ho1ZItSg== X-CSE-MsgGUID: 9HTFLHQ9RVO3lClMRU3/Pw== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.07,177,1708416000"; d="scan'208";a="49374777" Received: from aelgham-mobl2.ger.corp.intel.com (HELO pujfalus-desk.ger.corp.intel.com) ([10.249.35.133]) by orviesa002-auth.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 03 Apr 2024 03:51:42 -0700 From: Peter Ujfalusi To: lgirdwood@gmail.com, broonie@kernel.org Cc: linux-sound@vger.kernel.org, pierre-louis.bossart@linux.intel.com, kai.vehmanen@linux.intel.com, ranjani.sridharan@linux.intel.com, rander.wang@intel.com, liam.r.girdwood@intel.com Subject: [PATCH 1/7] ASoC: SOF: Intel: hda: Create debugfs file to force a clean DSP boot Date: Wed, 3 Apr 2024 13:52:04 +0300 Message-ID: <20240403105210.17949-2-peter.ujfalusi@linux.intel.com> X-Mailer: git-send-email 2.44.0 In-Reply-To: <20240403105210.17949-1-peter.ujfalusi@linux.intel.com> References: <20240403105210.17949-1-peter.ujfalusi@linux.intel.com> Precedence: bulk X-Mailing-List: linux-sound@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 When IMR boot is supported on a platform it is always going to be used to boot the DSP unless some catastrophic event happens. There is no way for a developer to force a clean DSP boot without removing and re-inserting the modules. Create a 'skip_imr_boot' debugfs file which can be used to force the next DSP boot as clean (prune) boot. Signed-off-by: Peter Ujfalusi Reviewed-by: Ranjani Sridharan Reviewed-by: Pierre-Louis Bossart --- sound/soc/sof/intel/hda-loader.c | 7 ++++++- sound/soc/sof/intel/hda.c | 1 + sound/soc/sof/intel/lnl.c | 7 ++++++- sound/soc/sof/intel/mtl.c | 7 ++++++- 4 files changed, 19 insertions(+), 3 deletions(-) diff --git a/sound/soc/sof/intel/hda-loader.c b/sound/soc/sof/intel/hda-loader.c index b81f231abee3..d5b9209beb5a 100644 --- a/sound/soc/sof/intel/hda-loader.c +++ b/sound/soc/sof/intel/hda-loader.c @@ -15,6 +15,7 @@ * Hardware interface for HDA DSP code loader */ +#include #include #include #include @@ -643,8 +644,12 @@ int hda_dsp_post_fw_run(struct snd_sof_dev *sdev) /* Check if IMR boot is usable */ if (!sof_debug_check_flag(SOF_DBG_IGNORE_D3_PERSISTENT) && (sdev->fw_ready.flags & SOF_IPC_INFO_D3_PERSISTENT || - sdev->pdata->ipc_type == SOF_IPC_TYPE_4)) + sdev->pdata->ipc_type == SOF_IPC_TYPE_4)) { hdev->imrboot_supported = true; + debugfs_create_bool("skip_imr_boot", + 0644, sdev->debugfs_root, + &hdev->skip_imr_boot); + } } hda_sdw_int_enable(sdev, true); diff --git a/sound/soc/sof/intel/hda.c b/sound/soc/sof/intel/hda.c index d38dc43c2f1c..33721e817ef4 100644 --- a/sound/soc/sof/intel/hda.c +++ b/sound/soc/sof/intel/hda.c @@ -19,6 +19,7 @@ #include #include +#include #include #include #include diff --git a/sound/soc/sof/intel/lnl.c b/sound/soc/sof/intel/lnl.c index d1c73d407e68..5114411f1e36 100644 --- a/sound/soc/sof/intel/lnl.c +++ b/sound/soc/sof/intel/lnl.c @@ -6,6 +6,7 @@ * Hardware interface for audio DSP on LunarLake. */ +#include #include #include #include @@ -83,8 +84,12 @@ static int lnl_dsp_post_fw_run(struct snd_sof_dev *sdev) struct sof_intel_hda_dev *hda = sdev->pdata->hw_pdata; /* Check if IMR boot is usable */ - if (!sof_debug_check_flag(SOF_DBG_IGNORE_D3_PERSISTENT)) + if (!sof_debug_check_flag(SOF_DBG_IGNORE_D3_PERSISTENT)) { hda->imrboot_supported = true; + debugfs_create_bool("skip_imr_boot", + 0644, sdev->debugfs_root, + &hda->skip_imr_boot); + } } return 0; diff --git a/sound/soc/sof/intel/mtl.c b/sound/soc/sof/intel/mtl.c index 060c34988e90..c640fbf6615a 100644 --- a/sound/soc/sof/intel/mtl.c +++ b/sound/soc/sof/intel/mtl.c @@ -9,6 +9,7 @@ * Hardware interface for audio DSP on Meteorlake. */ +#include #include #include #include @@ -294,8 +295,12 @@ int mtl_dsp_post_fw_run(struct snd_sof_dev *sdev) } /* Check if IMR boot is usable */ - if (!sof_debug_check_flag(SOF_DBG_IGNORE_D3_PERSISTENT)) + if (!sof_debug_check_flag(SOF_DBG_IGNORE_D3_PERSISTENT)) { hdev->imrboot_supported = true; + debugfs_create_bool("skip_imr_boot", + 0644, sdev->debugfs_root, + &hdev->skip_imr_boot); + } } hda_sdw_int_enable(sdev, true); From patchwork Wed Apr 3 10:52:05 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Peter Ujfalusi X-Patchwork-Id: 13615865 Received: from mgamail.intel.com (mgamail.intel.com [192.198.163.18]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id B77951350EC for ; Wed, 3 Apr 2024 10:52:10 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=192.198.163.18 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1712141532; cv=none; b=hS1DzJizTIWPjfM8ddgJxCP7QxeY/s70izuM08DBY8DicFNwsq/7R20CFvzTMWLQbhJDReTU1sNo3CVrL5YzNJGYAe4MZBxnENSD9xiBReHhnq+q7sRz/KwwbHdgkKOhADguwV5+aUesFvzJfLsINnP4u7XTElEO2BOBhccgtqw= ARC-Message-Signature: i=1; a=rsa-sha256; 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d="scan'208";a="49374785" Received: from aelgham-mobl2.ger.corp.intel.com (HELO pujfalus-desk.ger.corp.intel.com) ([10.249.35.133]) by orviesa002-auth.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 03 Apr 2024 03:51:45 -0700 From: Peter Ujfalusi To: lgirdwood@gmail.com, broonie@kernel.org Cc: linux-sound@vger.kernel.org, pierre-louis.bossart@linux.intel.com, kai.vehmanen@linux.intel.com, ranjani.sridharan@linux.intel.com, rander.wang@intel.com, liam.r.girdwood@intel.com Subject: [PATCH 2/7] ASoC: SOF: Intel: mtl: Correct rom_status_reg Date: Wed, 3 Apr 2024 13:52:05 +0300 Message-ID: <20240403105210.17949-3-peter.ujfalusi@linux.intel.com> X-Mailer: git-send-email 2.44.0 In-Reply-To: <20240403105210.17949-1-peter.ujfalusi@linux.intel.com> References: <20240403105210.17949-1-peter.ujfalusi@linux.intel.com> Precedence: bulk X-Mailing-List: linux-sound@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 ACE1 architecture changed the place where the ROM updates the status code from the shared SRAM window to HFFLGP1QW0 register for the status and HFFLGP1QW0 + 4 for the error code. The rom_status_reg is not used on MTL because it was wrongly assigned based on older platform convention (SRAM window) and it was giving inconsistent readings. Fixes: 064520e8aeaa ("ASoC: SOF: Intel: Add support for MeteorLake (MTL)") Signed-off-by: Peter Ujfalusi Reviewed-by: Rander Wang Reviewed-by: Kai Vehmanen Reviewed-by: Pierre-Louis Bossart Reviewed-by: Liam Girdwood --- sound/soc/sof/intel/mtl.c | 4 ++-- sound/soc/sof/intel/mtl.h | 4 ++-- 2 files changed, 4 insertions(+), 4 deletions(-) diff --git a/sound/soc/sof/intel/mtl.c b/sound/soc/sof/intel/mtl.c index c640fbf6615a..a27ce8debe91 100644 --- a/sound/soc/sof/intel/mtl.c +++ b/sound/soc/sof/intel/mtl.c @@ -732,7 +732,7 @@ const struct sof_intel_dsp_desc mtl_chip_info = { .ipc_ack = MTL_DSP_REG_HFIPCXIDA, .ipc_ack_mask = MTL_DSP_REG_HFIPCXIDA_DONE, .ipc_ctl = MTL_DSP_REG_HFIPCXCTL, - .rom_status_reg = MTL_DSP_ROM_STS, + .rom_status_reg = MTL_DSP_REG_HFFLGPXQWY, .rom_init_timeout = 300, .ssp_count = MTL_SSP_COUNT, .ssp_base_offset = CNL_SSP_BASE_OFFSET, @@ -760,7 +760,7 @@ const struct sof_intel_dsp_desc arl_s_chip_info = { .ipc_ack = MTL_DSP_REG_HFIPCXIDA, .ipc_ack_mask = MTL_DSP_REG_HFIPCXIDA_DONE, .ipc_ctl = MTL_DSP_REG_HFIPCXCTL, - .rom_status_reg = MTL_DSP_ROM_STS, + .rom_status_reg = MTL_DSP_REG_HFFLGPXQWY, .rom_init_timeout = 300, .ssp_count = MTL_SSP_COUNT, .ssp_base_offset = CNL_SSP_BASE_OFFSET, diff --git a/sound/soc/sof/intel/mtl.h b/sound/soc/sof/intel/mtl.h index ea8c1b83f712..3c56427a966b 100644 --- a/sound/soc/sof/intel/mtl.h +++ b/sound/soc/sof/intel/mtl.h @@ -70,8 +70,8 @@ #define MTL_DSP_ROM_STS MTL_SRAM_WINDOW_OFFSET(0) /* ROM status */ #define MTL_DSP_ROM_ERROR (MTL_SRAM_WINDOW_OFFSET(0) + 0x4) /* ROM error code */ -#define MTL_DSP_REG_HFFLGPXQWY 0x163200 /* ROM debug status */ -#define MTL_DSP_REG_HFFLGPXQWY_ERROR 0x163204 /* ROM debug error code */ +#define MTL_DSP_REG_HFFLGPXQWY 0x163200 /* DSP core0 status */ +#define MTL_DSP_REG_HFFLGPXQWY_ERROR 0x163204 /* DSP core0 error */ #define MTL_DSP_REG_HfIMRIS1 0x162088 #define MTL_DSP_REG_HfIMRIS1_IU_MASK BIT(0) From patchwork Wed Apr 3 10:52:06 2024 Content-Type: text/plain; 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03 Apr 2024 03:51:47 -0700 From: Peter Ujfalusi To: lgirdwood@gmail.com, broonie@kernel.org Cc: linux-sound@vger.kernel.org, pierre-louis.bossart@linux.intel.com, kai.vehmanen@linux.intel.com, ranjani.sridharan@linux.intel.com, rander.wang@intel.com, liam.r.girdwood@intel.com Subject: [PATCH 3/7] ASoC: SOF: Intel: lnl: Correct rom_status_reg Date: Wed, 3 Apr 2024 13:52:06 +0300 Message-ID: <20240403105210.17949-4-peter.ujfalusi@linux.intel.com> X-Mailer: git-send-email 2.44.0 In-Reply-To: <20240403105210.17949-1-peter.ujfalusi@linux.intel.com> References: <20240403105210.17949-1-peter.ujfalusi@linux.intel.com> Precedence: bulk X-Mailing-List: linux-sound@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 ACE2 architecture changed the place where the ROM updates the status code from the shared SRAM window (and HFFLGP1QW0 in ACE1) to HFDSC register for the status and HFDEC (HFDSC + 4) for the error code. The rom_status_reg is not used on LNL because it was wrongly assigned based on older platform convention (SRAM window) and it was giving inconsistent readings. Add new header file for lnl specific register definitions. Fixes: 64a63d9914a5 ("ASoC: SOF: Intel: LNL: Add support for Lunarlake platform") Signed-off-by: Peter Ujfalusi Reviewed-by: Rander Wang Reviewed-by: Kai Vehmanen Reviewed-by: Pierre-Louis Bossart Reviewed-by: Liam Girdwood --- sound/soc/sof/intel/lnl.c | 3 ++- sound/soc/sof/intel/lnl.h | 15 +++++++++++++++ 2 files changed, 17 insertions(+), 1 deletion(-) create mode 100644 sound/soc/sof/intel/lnl.h diff --git a/sound/soc/sof/intel/lnl.c b/sound/soc/sof/intel/lnl.c index 5114411f1e36..8e7193344341 100644 --- a/sound/soc/sof/intel/lnl.c +++ b/sound/soc/sof/intel/lnl.c @@ -17,6 +17,7 @@ #include "hda-ipc.h" #include "../sof-audio.h" #include "mtl.h" +#include "lnl.h" #include /* LunarLake ops */ @@ -197,7 +198,7 @@ const struct sof_intel_dsp_desc lnl_chip_info = { .ipc_ack = MTL_DSP_REG_HFIPCXIDA, .ipc_ack_mask = MTL_DSP_REG_HFIPCXIDA_DONE, .ipc_ctl = MTL_DSP_REG_HFIPCXCTL, - .rom_status_reg = MTL_DSP_ROM_STS, + .rom_status_reg = LNL_DSP_REG_HFDSC, .rom_init_timeout = 300, .ssp_count = MTL_SSP_COUNT, .d0i3_offset = MTL_HDA_VS_D0I3C, diff --git a/sound/soc/sof/intel/lnl.h b/sound/soc/sof/intel/lnl.h new file mode 100644 index 000000000000..4f4734fe7e08 --- /dev/null +++ b/sound/soc/sof/intel/lnl.h @@ -0,0 +1,15 @@ +/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-3-Clause) */ +/* + * This file is provided under a dual BSD/GPLv2 license. When using or + * redistributing this file, you may do so under either license. + * + * Copyright(c) 2024 Intel Corporation. All rights reserved. + */ + +#ifndef __SOF_INTEL_LNL_H +#define __SOF_INTEL_LNL_H + +#define LNL_DSP_REG_HFDSC 0x160200 /* DSP core0 status */ +#define LNL_DSP_REG_HFDEC 0x160204 /* DSP core0 error */ + +#endif /* __SOF_INTEL_LNL_H */ From patchwork Wed Apr 3 10:52:07 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Peter Ujfalusi X-Patchwork-Id: 13615867 Received: from mgamail.intel.com (mgamail.intel.com [192.198.163.18]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 5047A13A25C for ; Wed, 3 Apr 2024 10:52:17 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=192.198.163.18 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1712141539; cv=none; b=j/N7xn8WViQOPu1cg3iYotcAXkV934ogBFP9pAYWkmK9WAaS/LGsmmHosq6CNulzclBemGpzwUIYFaKj7TX0/0SPVbvfLmBajEFukIjOWautYBtWDfVil2WeH8Z3yLOOqXebPym3FHqtoMuIXVsxOpHckPhC4Unhh87s0lOHiCc= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1712141539; c=relaxed/simple; bh=iXXIzp82egDjy9+TYz+ugE62ypHc3SPIS16HEE/JNN4=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=Z7Y69il3JBmR/9DReuVflrtsnKxwxPc523hY1aWy0GxeF7Cr0q1T7gSfG8hgq4W9vVg3+EZZdcLkRVzNzQra7VMrbIn4uSoZBoeXYIiUSOW7gWHvoXmzcrLK3O/2BhXcGSVRSrHWNfUa2uV6Udxga1p4VImR1P0flVg2snMvYtg= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linux.intel.com; spf=none smtp.mailfrom=linux.intel.com; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b=EI5wUAPe; arc=none smtp.client-ip=192.198.163.18 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linux.intel.com Authentication-Results: smtp.subspace.kernel.org; spf=none smtp.mailfrom=linux.intel.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b="EI5wUAPe" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1712141538; x=1743677538; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=iXXIzp82egDjy9+TYz+ugE62ypHc3SPIS16HEE/JNN4=; b=EI5wUAPebkDYX60BzoGiuSPmCdUyLC3lbkm4hg2DNYOECVutWbs45A6y AkpWXPl94IlBKX/aFLhTJZZNLatBFzznyPeovwHrij3hhqBSZyZFef7HJ CbLcmluZ9DwzOHv/8fQ6VmofRjyOVjBlHjd8Bn0gG+hqK8px/RokW+Y3I Tu1yZ4VWHaqCpVk3avRwLRF+3PLufM40IPfcn4jch80bCVahsgBvcbHpq HC7cfpWVk8FnQ+z5h7LQOo8uOiby7QMH9cSp05NVRIIE9TxKYILssZZs/ d7lmo5PwMR+9WaqICpOWB4IdeAHxiZGqacDyR9PJ3ltTDUi8FcBHnm3Pk Q==; X-CSE-ConnectionGUID: CKFoBe7fQ0qS54JIt0derw== X-CSE-MsgGUID: Nps83ajxT12Zj/hCUefIUg== X-IronPort-AV: E=McAfee;i="6600,9927,11032"; a="7212227" X-IronPort-AV: E=Sophos;i="6.07,177,1708416000"; d="scan'208";a="7212227" Received: from orviesa002.jf.intel.com ([10.64.159.142]) by fmvoesa112.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 03 Apr 2024 03:51:53 -0700 X-CSE-ConnectionGUID: zSjQga8DQHGfWRgQfjrT+g== X-CSE-MsgGUID: SZNEajkJRYez8N917uc81A== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.07,177,1708416000"; d="scan'208";a="49374801" Received: from aelgham-mobl2.ger.corp.intel.com (HELO pujfalus-desk.ger.corp.intel.com) ([10.249.35.133]) by orviesa002-auth.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 03 Apr 2024 03:51:50 -0700 From: Peter Ujfalusi To: lgirdwood@gmail.com, broonie@kernel.org Cc: linux-sound@vger.kernel.org, pierre-louis.bossart@linux.intel.com, kai.vehmanen@linux.intel.com, ranjani.sridharan@linux.intel.com, rander.wang@intel.com, liam.r.girdwood@intel.com Subject: [PATCH 4/7] ASoC: SOF: Intel: mtl: Disable interrupts when firmware boot failed Date: Wed, 3 Apr 2024 13:52:07 +0300 Message-ID: <20240403105210.17949-5-peter.ujfalusi@linux.intel.com> X-Mailer: git-send-email 2.44.0 In-Reply-To: <20240403105210.17949-1-peter.ujfalusi@linux.intel.com> References: <20240403105210.17949-1-peter.ujfalusi@linux.intel.com> Precedence: bulk X-Mailing-List: linux-sound@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 In case of error during the firmware boot we need to disable the interrupts which were enabled as part of the boot sequence. Fixes: 064520e8aeaa ("ASoC: SOF: Intel: Add support for MeteorLake (MTL)") Signed-off-by: Peter Ujfalusi Reviewed-by: Rander Wang Reviewed-by: Kai Vehmanen Reviewed-by: Pierre-Louis Bossart Reviewed-by: Liam Girdwood --- sound/soc/sof/intel/mtl.c | 1 + 1 file changed, 1 insertion(+) diff --git a/sound/soc/sof/intel/mtl.c b/sound/soc/sof/intel/mtl.c index a27ce8debe91..3bc229957365 100644 --- a/sound/soc/sof/intel/mtl.c +++ b/sound/soc/sof/intel/mtl.c @@ -508,6 +508,7 @@ int mtl_dsp_cl_init(struct snd_sof_dev *sdev, int stream_tag, bool imr_boot) dump_msg = kasprintf(GFP_KERNEL, "Boot iteration failed: %d/%d", hda->boot_iteration, HDA_FW_BOOT_ATTEMPTS); snd_sof_dsp_dbg_dump(sdev, dump_msg, flags); + mtl_enable_interrupts(sdev, false); mtl_dsp_core_power_down(sdev, SOF_DSP_PRIMARY_CORE); kfree(dump_msg); From patchwork Wed Apr 3 10:52:08 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Peter Ujfalusi X-Patchwork-Id: 13615869 Received: from mgamail.intel.com (mgamail.intel.com [192.198.163.18]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 24FE5136989 for ; Wed, 3 Apr 2024 10:52:24 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=192.198.163.18 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1712141546; cv=none; b=Ls/bG8dYwi5n0yyRkdYGVJ3Fr9P22ZcnwBXpw+I1hCCKUbTnNutY61NR3hAtvhfIG636NUWoR1fEEp7V/jvRPWqTxqM5600ufB9jHIOINh15M21aQropTjCBuQ9F+J3VTEzDoGjh5cw51qdTawR0EJ8LXkYWLwg8Qj3pru2AbOA= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1712141546; c=relaxed/simple; bh=TB3U5DyFLdiTso/zAIU2seZ9xbyOBOvQxIdi0/CSuTA=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=YDhD7fD1C3I6Fs6R5JzkHNRpJhzDHo3/e68tWrgQx+0l7Kj6yTr7ChdvfJU/J35QoAmxRMQfqwbYtrfd0bbhT5/EpRZNcRwQP9SWcOIXPEgMJvYu3xtRaMD5SM3t0DF2KCGIL9hYUi5D1KAXvs9xdCvEGs0tG9KV3nFRwEHHaEA= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linux.intel.com; spf=none smtp.mailfrom=linux.intel.com; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b=S2A6g711; arc=none smtp.client-ip=192.198.163.18 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linux.intel.com Authentication-Results: smtp.subspace.kernel.org; spf=none smtp.mailfrom=linux.intel.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b="S2A6g711" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1712141545; x=1743677545; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=TB3U5DyFLdiTso/zAIU2seZ9xbyOBOvQxIdi0/CSuTA=; b=S2A6g711d5XzoMWK1zN/juAYd0PkfDugW+nv8r31Ui7qiYx61bURXRa7 MH92adQhSe+48tFnPdB2uvAXE8IEis6tidTlMQSHQJLGWOLnJ4xHpiIP3 WCN6unrgiIij/1X8R/L8gYzLBk9EeN3/N4jlMKnOJmEMecJjzru4jLeW2 ZdmjemXOu6h9jStxMw68VdJwkm6BhISiZwNgQOyVX46aIFjB9mxEbQQOx C7g0P2WvchjHd4pmAn3p2Wdy903chfsxhFU8dZos2T/PvHB2G7rOQi5Il 77GSbW7Yf+bIzUHdYZiNJywGws3h8Ap33O8MgCPbMdIhdQR0gsnNjWVLL Q==; X-CSE-ConnectionGUID: ER2romzKS66BUW/32tZ4nA== X-CSE-MsgGUID: CqeoZV1KSV2KmDaIEeQ++g== X-IronPort-AV: E=McAfee;i="6600,9927,11032"; a="7212243" X-IronPort-AV: E=Sophos;i="6.07,177,1708416000"; d="scan'208";a="7212243" Received: from orviesa002.jf.intel.com ([10.64.159.142]) by fmvoesa112.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 03 Apr 2024 03:51:55 -0700 X-CSE-ConnectionGUID: Pi3C79MdQyenf2UNoamGHw== X-CSE-MsgGUID: EwTRR7+wQQ++Otx6d95dZg== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.07,177,1708416000"; d="scan'208";a="49374809" Received: from aelgham-mobl2.ger.corp.intel.com (HELO pujfalus-desk.ger.corp.intel.com) ([10.249.35.133]) by orviesa002-auth.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 03 Apr 2024 03:51:53 -0700 From: Peter Ujfalusi To: lgirdwood@gmail.com, broonie@kernel.org Cc: linux-sound@vger.kernel.org, pierre-louis.bossart@linux.intel.com, kai.vehmanen@linux.intel.com, ranjani.sridharan@linux.intel.com, rander.wang@intel.com, liam.r.girdwood@intel.com Subject: [PATCH 5/7] ASoC: SOF: Intel: mtl: Implement firmware boot state check Date: Wed, 3 Apr 2024 13:52:08 +0300 Message-ID: <20240403105210.17949-6-peter.ujfalusi@linux.intel.com> X-Mailer: git-send-email 2.44.0 In-Reply-To: <20240403105210.17949-1-peter.ujfalusi@linux.intel.com> References: <20240403105210.17949-1-peter.ujfalusi@linux.intel.com> Precedence: bulk X-Mailing-List: linux-sound@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 With the corrected rom_status_reg values we can now add a check for target boot status for firmware booting. With the check now we can identify failed firmware boots (IMR boots) and we can use the fallback to purge boot the DSP. Fixes: 064520e8aeaa ("ASoC: SOF: Intel: Add support for MeteorLake (MTL)") Signed-off-by: Peter Ujfalusi Reviewed-by: Rander Wang Reviewed-by: Kai Vehmanen Reviewed-by: Pierre-Louis Bossart Reviewed-by: Liam Girdwood --- sound/soc/sof/intel/mtl.c | 37 ++++++++++++++++++++++++++++++++----- 1 file changed, 32 insertions(+), 5 deletions(-) diff --git a/sound/soc/sof/intel/mtl.c b/sound/soc/sof/intel/mtl.c index 3bc229957365..5c9d14e5925d 100644 --- a/sound/soc/sof/intel/mtl.c +++ b/sound/soc/sof/intel/mtl.c @@ -444,7 +444,7 @@ int mtl_dsp_cl_init(struct snd_sof_dev *sdev, int stream_tag, bool imr_boot) { struct sof_intel_hda_dev *hda = sdev->pdata->hw_pdata; const struct sof_intel_dsp_desc *chip = hda->desc; - unsigned int status; + unsigned int status, target_status; u32 ipc_hdr, flags; char *dump_msg; int ret; @@ -490,13 +490,40 @@ int mtl_dsp_cl_init(struct snd_sof_dev *sdev, int stream_tag, bool imr_boot) mtl_enable_ipc_interrupts(sdev); + if (chip->rom_status_reg == MTL_DSP_ROM_STS) { + /* + * Workaround: when the ROM status register is pointing to + * the SRAM window (MTL_DSP_ROM_STS) the platform cannot catch + * ROM_INIT_DONE because of a very short timing window. + * Follow the recommendations and skip target state waiting. + */ + return 0; + } + /* - * ACE workaround: don't wait for ROM INIT. - * The platform cannot catch ROM_INIT_DONE because of a very short - * timing window. Follow the recommendations and skip this part. + * step 7: + * - Cold/Full boot: wait for ROM init to proceed to download the firmware + * - IMR boot: wait for ROM firmware entered (firmware booted up from IMR) */ + if (imr_boot) + target_status = FSR_STATE_FW_ENTERED; + else + target_status = FSR_STATE_INIT_DONE; - return 0; + ret = snd_sof_dsp_read_poll_timeout(sdev, HDA_DSP_BAR, + chip->rom_status_reg, status, + (FSR_TO_STATE_CODE(status) == target_status), + HDA_DSP_REG_POLL_INTERVAL_US, + chip->rom_init_timeout * + USEC_PER_MSEC); + + if (!ret) + return 0; + + if (hda->boot_iteration == HDA_FW_BOOT_ATTEMPTS) + dev_err(sdev->dev, + "%s: timeout with rom_status_reg (%#x) read\n", + __func__, chip->rom_status_reg); err: flags = SOF_DBG_DUMP_PCI | SOF_DBG_DUMP_MBOX | SOF_DBG_DUMP_OPTIONAL; From patchwork Wed Apr 3 10:52:09 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Peter Ujfalusi X-Patchwork-Id: 13615868 Received: from mgamail.intel.com (mgamail.intel.com [192.198.163.18]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 76B9D1DFCE for ; Wed, 3 Apr 2024 10:52:23 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=192.198.163.18 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1712141545; cv=none; b=qL95qWMqckYLhZuurlydZOBktI/mwrg4aD7SUgKyVg3hotnmZIZf77cwWP2TAW+LinWME0uZAntXeM54AJUGczazb2zA49v2QkwYZazX/nOTOWpNykLkwNPEiko6JAu2LEih8LnJKFpiukWX5rR6C9znogRuA3B3HcJRH3PyX50= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1712141545; c=relaxed/simple; bh=EEjCPFmKwcpkjJYT22t7Fl+r38U6rXF1EzqRJkGJMhs=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=cGccsW8LfrNFiV0DnS7ydA1e7n+7yMUN7EOL6RoqeUFOKJ6OVAFomnrP3wPW8e32bqmKYgLCl+Y1LLMnsMJ88l6EEhqeA9gU/gl12cfJOJQE4cDBdkXFSHpE8bh37cjnd9JzC09xkFyvjzocAJgqHpeedRFmYxez9P/L7Pil5l8= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linux.intel.com; spf=none smtp.mailfrom=linux.intel.com; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b=Mz+VHI6g; arc=none smtp.client-ip=192.198.163.18 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linux.intel.com Authentication-Results: smtp.subspace.kernel.org; spf=none smtp.mailfrom=linux.intel.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b="Mz+VHI6g" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1712141544; x=1743677544; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=EEjCPFmKwcpkjJYT22t7Fl+r38U6rXF1EzqRJkGJMhs=; b=Mz+VHI6gzeaBPnKmpaGqER+jwzhGQ+otrDpYDilY+Vr55Q906h5pkjc/ VMTgqzWzYqkIuxZxUhMk2zI5eRM17dD4A1sr/m500HVQnrqoEgGOa43BX RRisxDBPUhNIgiMJTl5fpjp1U9Bv5lv0iHMyYHEpaVT+hwxDpcaI09Vik I/3+XNuSSoBGZkV0RCRORLhS4XHmdm/P+GOza6KZL+a3GuEfU/vPR0TwU swE+83WkBdHvuloYrQPhQwaMCen8CTfGiOwS6K5AgQCKMRDQhEDAtplBd 1M12hi+g8lUzO5oxhd7Xh8VnNcdyDyLS8odl6UIWc/TMB7PZcuZSnmFp1 g==; X-CSE-ConnectionGUID: VXxHD5CGQyiKUvmTkBhXqA== X-CSE-MsgGUID: sGMUxn3BSTuGEYFpptvEsw== X-IronPort-AV: E=McAfee;i="6600,9927,11032"; a="7212257" X-IronPort-AV: E=Sophos;i="6.07,177,1708416000"; d="scan'208";a="7212257" Received: from orviesa002.jf.intel.com ([10.64.159.142]) by fmvoesa112.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 03 Apr 2024 03:51:58 -0700 X-CSE-ConnectionGUID: biHKZu5CSiujHmnAIfLK/A== X-CSE-MsgGUID: W0r+AP1+RsGGFVFk923ElA== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.07,177,1708416000"; d="scan'208";a="49374815" Received: from aelgham-mobl2.ger.corp.intel.com (HELO pujfalus-desk.ger.corp.intel.com) ([10.249.35.133]) by orviesa002-auth.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 03 Apr 2024 03:51:55 -0700 From: Peter Ujfalusi To: lgirdwood@gmail.com, broonie@kernel.org Cc: linux-sound@vger.kernel.org, pierre-louis.bossart@linux.intel.com, kai.vehmanen@linux.intel.com, ranjani.sridharan@linux.intel.com, rander.wang@intel.com, liam.r.girdwood@intel.com Subject: [PATCH 6/7] ASoC: SOF: Intel: hda-dsp/mtl: Add support for ACE ROM state codes Date: Wed, 3 Apr 2024 13:52:09 +0300 Message-ID: <20240403105210.17949-7-peter.ujfalusi@linux.intel.com> X-Mailer: git-send-email 2.44.0 In-Reply-To: <20240403105210.17949-1-peter.ujfalusi@linux.intel.com> References: <20240403105210.17949-1-peter.ujfalusi@linux.intel.com> Precedence: bulk X-Mailing-List: linux-sound@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 The ROM state codes differ between CAVS and ACE architecture, there is a slight overlap. Add the ACE related state defines to mtl.h, introduce new table and use it on case the function is called when running on ACE architecture. Signed-off-by: Peter Ujfalusi Reviewed-by: Rander Wang Reviewed-by: Kai Vehmanen Reviewed-by: Pierre-Louis Bossart Reviewed-by: Liam Girdwood --- sound/soc/sof/intel/hda.c | 72 +++++++++++++++++++++++++++++++++++---- sound/soc/sof/intel/hda.h | 2 ++ sound/soc/sof/intel/mtl.h | 44 ++++++++++++++++++++++++ 3 files changed, 112 insertions(+), 6 deletions(-) diff --git a/sound/soc/sof/intel/hda.c b/sound/soc/sof/intel/hda.c index 33721e817ef4..2fc10bec7331 100644 --- a/sound/soc/sof/intel/hda.c +++ b/sound/soc/sof/intel/hda.c @@ -35,6 +35,7 @@ #include "../ipc4-topology.h" #include "hda.h" #include "telemetry.h" +#include "mtl.h" #define CREATE_TRACE_POINTS #include @@ -597,7 +598,7 @@ static const struct hda_dsp_msg_code hda_dsp_rom_fw_error_texts[] = { }; #define FSR_ROM_STATE_ENTRY(state) {FSR_STATE_ROM_##state, #state} -static const struct hda_dsp_msg_code fsr_rom_state_names[] = { +static const struct hda_dsp_msg_code cavs_fsr_rom_state_names[] = { FSR_ROM_STATE_ENTRY(INIT), FSR_ROM_STATE_ENTRY(INIT_DONE), FSR_ROM_STATE_ENTRY(CSE_MANIFEST_LOADED), @@ -620,6 +621,58 @@ static const struct hda_dsp_msg_code fsr_rom_state_names[] = { FSR_ROM_STATE_ENTRY(CSE_IPC_DOWN), }; +static const struct hda_dsp_msg_code ace_fsr_rom_state_names[] = { + FSR_ROM_STATE_ENTRY(INIT), + FSR_ROM_STATE_ENTRY(INIT_DONE), + FSR_ROM_STATE_ENTRY(CSE_MANIFEST_LOADED), + FSR_ROM_STATE_ENTRY(FW_MANIFEST_LOADED), + FSR_ROM_STATE_ENTRY(FW_FW_LOADED), + FSR_ROM_STATE_ENTRY(FW_ENTERED), + FSR_ROM_STATE_ENTRY(VERIFY_FEATURE_MASK), + FSR_ROM_STATE_ENTRY(GET_LOAD_OFFSET), + FSR_ROM_STATE_ENTRY(RESET_VECTOR_DONE), + FSR_ROM_STATE_ENTRY(PURGE_BOOT), + FSR_ROM_STATE_ENTRY(RESTORE_BOOT), + FSR_ROM_STATE_ENTRY(FW_ENTRY_POINT), + FSR_ROM_STATE_ENTRY(VALIDATE_PUB_KEY), + FSR_ROM_STATE_ENTRY(POWER_DOWN_HPSRAM), + FSR_ROM_STATE_ENTRY(POWER_DOWN_ULPSRAM), + FSR_ROM_STATE_ENTRY(POWER_UP_ULPSRAM_STACK), + FSR_ROM_STATE_ENTRY(POWER_UP_HPSRAM_DMA), + FSR_ROM_STATE_ENTRY(BEFORE_EP_POINTER_READ), + FSR_ROM_STATE_ENTRY(VALIDATE_MANIFEST), + FSR_ROM_STATE_ENTRY(VALIDATE_FW_MODULE), + FSR_ROM_STATE_ENTRY(PROTECT_IMR_REGION), + FSR_ROM_STATE_ENTRY(PUSH_MODEL_ROUTINE), + FSR_ROM_STATE_ENTRY(PULL_MODEL_ROUTINE), + FSR_ROM_STATE_ENTRY(VALIDATE_PKG_DIR), + FSR_ROM_STATE_ENTRY(VALIDATE_CPD), + FSR_ROM_STATE_ENTRY(VALIDATE_CSS_MAN_HEADER), + FSR_ROM_STATE_ENTRY(VALIDATE_BLOB_SVN), + FSR_ROM_STATE_ENTRY(VERIFY_IFWI_PARTITION), + FSR_ROM_STATE_ENTRY(REMOVE_ACCESS_CONTROL), + FSR_ROM_STATE_ENTRY(AUTH_BYPASS), + FSR_ROM_STATE_ENTRY(AUTH_ENABLED), + FSR_ROM_STATE_ENTRY(INIT_DMA), + FSR_ROM_STATE_ENTRY(PURGE_FW_ENTRY), + FSR_ROM_STATE_ENTRY(PURGE_FW_END), + FSR_ROM_STATE_ENTRY(CLEAN_UP_BSS_DONE), + FSR_ROM_STATE_ENTRY(IMR_RESTORE_ENTRY), + FSR_ROM_STATE_ENTRY(IMR_RESTORE_END), + FSR_ROM_STATE_ENTRY(FW_MANIFEST_IN_DMA_BUFF), + FSR_ROM_STATE_ENTRY(LOAD_CSE_MAN_TO_IMR), + FSR_ROM_STATE_ENTRY(LOAD_FW_MAN_TO_IMR), + FSR_ROM_STATE_ENTRY(LOAD_FW_CODE_TO_IMR), + FSR_ROM_STATE_ENTRY(FW_LOADING_DONE), + FSR_ROM_STATE_ENTRY(FW_CODE_LOADED), + FSR_ROM_STATE_ENTRY(VERIFY_IMAGE_TYPE), + FSR_ROM_STATE_ENTRY(AUTH_API_INIT), + FSR_ROM_STATE_ENTRY(AUTH_API_PROC), + FSR_ROM_STATE_ENTRY(AUTH_API_FIRST_BUSY), + FSR_ROM_STATE_ENTRY(AUTH_API_FIRST_RESULT), + FSR_ROM_STATE_ENTRY(AUTH_API_CLEANUP), +}; + #define FSR_BRINGUP_STATE_ENTRY(state) {FSR_STATE_BRINGUP_##state, #state} static const struct hda_dsp_msg_code fsr_bringup_state_names[] = { FSR_BRINGUP_STATE_ENTRY(INIT), @@ -664,7 +717,7 @@ hda_dsp_get_state_text(u32 code, const struct hda_dsp_msg_code *msg_code, return NULL; } -static void hda_dsp_get_state(struct snd_sof_dev *sdev, const char *level) +void hda_dsp_get_state(struct snd_sof_dev *sdev, const char *level) { const struct sof_intel_dsp_desc *chip = get_chip_info(sdev->pdata); const char *state_text, *error_text, *module_text; @@ -680,12 +733,19 @@ static void hda_dsp_get_state(struct snd_sof_dev *sdev, const char *level) else module_text = fsr_module_names[module]; - if (module == FSR_MOD_BRNGUP) + if (module == FSR_MOD_BRNGUP) { state_text = hda_dsp_get_state_text(state, fsr_bringup_state_names, ARRAY_SIZE(fsr_bringup_state_names)); - else - state_text = hda_dsp_get_state_text(state, fsr_rom_state_names, - ARRAY_SIZE(fsr_rom_state_names)); + } else { + if (chip->hw_ip_version < SOF_INTEL_ACE_1_0) + state_text = hda_dsp_get_state_text(state, + cavs_fsr_rom_state_names, + ARRAY_SIZE(cavs_fsr_rom_state_names)); + else + state_text = hda_dsp_get_state_text(state, + ace_fsr_rom_state_names, + ARRAY_SIZE(ace_fsr_rom_state_names)); + } /* not for us, must be generic sof message */ if (!state_text) { diff --git a/sound/soc/sof/intel/hda.h b/sound/soc/sof/intel/hda.h index c939a24d770e..16140ae22c90 100644 --- a/sound/soc/sof/intel/hda.h +++ b/sound/soc/sof/intel/hda.h @@ -695,6 +695,8 @@ int hda_dsp_ipc_get_window_offset(struct snd_sof_dev *sdev, u32 id); irqreturn_t hda_dsp_ipc_irq_thread(int irq, void *context); int hda_dsp_ipc_cmd_done(struct snd_sof_dev *sdev, int dir); +void hda_dsp_get_state(struct snd_sof_dev *sdev, const char *level); + /* * DSP Code loader. */ diff --git a/sound/soc/sof/intel/mtl.h b/sound/soc/sof/intel/mtl.h index 3c56427a966b..d2d709fb4f06 100644 --- a/sound/soc/sof/intel/mtl.h +++ b/sound/soc/sof/intel/mtl.h @@ -72,6 +72,50 @@ #define MTL_DSP_REG_HFFLGPXQWY 0x163200 /* DSP core0 status */ #define MTL_DSP_REG_HFFLGPXQWY_ERROR 0x163204 /* DSP core0 error */ + +/* FSR status codes */ +#define FSR_STATE_ROM_RESET_VECTOR_DONE 0x8 +#define FSR_STATE_ROM_PURGE_BOOT 0x9 +#define FSR_STATE_ROM_RESTORE_BOOT 0xA +#define FSR_STATE_ROM_FW_ENTRY_POINT 0xB +#define FSR_STATE_ROM_VALIDATE_PUB_KEY 0xC +#define FSR_STATE_ROM_POWER_DOWN_HPSRAM 0xD +#define FSR_STATE_ROM_POWER_DOWN_ULPSRAM 0xE +#define FSR_STATE_ROM_POWER_UP_ULPSRAM_STACK 0xF +#define FSR_STATE_ROM_POWER_UP_HPSRAM_DMA 0x10 +#define FSR_STATE_ROM_BEFORE_EP_POINTER_READ 0x11 +#define FSR_STATE_ROM_VALIDATE_MANIFEST 0x12 +#define FSR_STATE_ROM_VALIDATE_FW_MODULE 0x13 +#define FSR_STATE_ROM_PROTECT_IMR_REGION 0x14 +#define FSR_STATE_ROM_PUSH_MODEL_ROUTINE 0x15 +#define FSR_STATE_ROM_PULL_MODEL_ROUTINE 0x16 +#define FSR_STATE_ROM_VALIDATE_PKG_DIR 0x17 +#define FSR_STATE_ROM_VALIDATE_CPD 0x18 +#define FSR_STATE_ROM_VALIDATE_CSS_MAN_HEADER 0x19 +#define FSR_STATE_ROM_VALIDATE_BLOB_SVN 0x1A +#define FSR_STATE_ROM_VERIFY_IFWI_PARTITION 0x1B +#define FSR_STATE_ROM_REMOVE_ACCESS_CONTROL 0x1C +#define FSR_STATE_ROM_AUTH_BYPASS 0x1D +#define FSR_STATE_ROM_AUTH_ENABLED 0x1E +#define FSR_STATE_ROM_INIT_DMA 0x1F +#define FSR_STATE_ROM_PURGE_FW_ENTRY 0x20 +#define FSR_STATE_ROM_PURGE_FW_END 0x21 +#define FSR_STATE_ROM_CLEAN_UP_BSS_DONE 0x22 +#define FSR_STATE_ROM_IMR_RESTORE_ENTRY 0x23 +#define FSR_STATE_ROM_IMR_RESTORE_END 0x24 +#define FSR_STATE_ROM_FW_MANIFEST_IN_DMA_BUFF 0x25 +#define FSR_STATE_ROM_LOAD_CSE_MAN_TO_IMR 0x26 +#define FSR_STATE_ROM_LOAD_FW_MAN_TO_IMR 0x27 +#define FSR_STATE_ROM_LOAD_FW_CODE_TO_IMR 0x28 +#define FSR_STATE_ROM_FW_LOADING_DONE 0x29 +#define FSR_STATE_ROM_FW_CODE_LOADED 0x2A +#define FSR_STATE_ROM_VERIFY_IMAGE_TYPE 0x2B +#define FSR_STATE_ROM_AUTH_API_INIT 0x2C +#define FSR_STATE_ROM_AUTH_API_PROC 0x2D +#define FSR_STATE_ROM_AUTH_API_FIRST_BUSY 0x2E +#define FSR_STATE_ROM_AUTH_API_FIRST_RESULT 0x2F +#define FSR_STATE_ROM_AUTH_API_CLEANUP 0x30 + #define MTL_DSP_REG_HfIMRIS1 0x162088 #define MTL_DSP_REG_HfIMRIS1_IU_MASK BIT(0) From patchwork Wed Apr 3 10:52:10 2024 Content-Type: text/plain; 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03 Apr 2024 03:51:58 -0700 From: Peter Ujfalusi To: lgirdwood@gmail.com, broonie@kernel.org Cc: linux-sound@vger.kernel.org, pierre-louis.bossart@linux.intel.com, kai.vehmanen@linux.intel.com, ranjani.sridharan@linux.intel.com, rander.wang@intel.com, liam.r.girdwood@intel.com Subject: [PATCH 7/7] ASoC: SOF: Intel: mtl: Correct the mtl_dsp_dump output Date: Wed, 3 Apr 2024 13:52:10 +0300 Message-ID: <20240403105210.17949-8-peter.ujfalusi@linux.intel.com> X-Mailer: git-send-email 2.44.0 In-Reply-To: <20240403105210.17949-1-peter.ujfalusi@linux.intel.com> References: <20240403105210.17949-1-peter.ujfalusi@linux.intel.com> Precedence: bulk X-Mailing-List: linux-sound@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 The ROM/firmware state handling has changed between CAVS and ACE architecture: CAVS: ROM and firmware uses the SRAM window for the state and status/error code reporting ACE: ROM code is using two registers to report the state and error while the firmware is using the SRAM window to report states and status/error codes. Use the generic hda_dsp_get_state() to decode ROM state and error codes and print out the firmware state and status/error code only if the SRAM window is accessible - the firmware is booted and the Status readout is not 0xffffffff. Signed-off-by: Peter Ujfalusi Reviewed-by: Rander Wang Reviewed-by: Kai Vehmanen Reviewed-by: Pierre-Louis Bossart Reviewed-by: Liam Girdwood --- sound/soc/sof/intel/mtl.c | 16 +++++----------- 1 file changed, 5 insertions(+), 11 deletions(-) diff --git a/sound/soc/sof/intel/mtl.c b/sound/soc/sof/intel/mtl.c index 5c9d14e5925d..dc203505536c 100644 --- a/sound/soc/sof/intel/mtl.c +++ b/sound/soc/sof/intel/mtl.c @@ -310,22 +310,16 @@ int mtl_dsp_post_fw_run(struct snd_sof_dev *sdev) void mtl_dsp_dump(struct snd_sof_dev *sdev, u32 flags) { char *level = (flags & SOF_DBG_DUMP_OPTIONAL) ? KERN_DEBUG : KERN_ERR; - u32 romdbgsts; - u32 romdbgerr; u32 fwsts; u32 fwlec; + hda_dsp_get_state(sdev, level); fwsts = snd_sof_dsp_read(sdev, HDA_DSP_BAR, MTL_DSP_ROM_STS); fwlec = snd_sof_dsp_read(sdev, HDA_DSP_BAR, MTL_DSP_ROM_ERROR); - romdbgsts = snd_sof_dsp_read(sdev, HDA_DSP_BAR, MTL_DSP_REG_HFFLGPXQWY); - romdbgerr = snd_sof_dsp_read(sdev, HDA_DSP_BAR, MTL_DSP_REG_HFFLGPXQWY_ERROR); - - dev_err(sdev->dev, "ROM status: %#x, ROM error: %#x\n", fwsts, fwlec); - dev_err(sdev->dev, "ROM debug status: %#x, ROM debug error: %#x\n", romdbgsts, - romdbgerr); - romdbgsts = snd_sof_dsp_read(sdev, HDA_DSP_BAR, MTL_DSP_REG_HFFLGPXQWY + 0x8 * 3); - dev_printk(level, sdev->dev, "ROM feature bit%s enabled\n", - romdbgsts & BIT(24) ? "" : " not"); + + if (fwsts != 0xffffffff) + dev_err(sdev->dev, "Firmware state: %#x, status/error code: %#x\n", + fwsts, fwlec); sof_ipc4_intel_dump_telemetry_state(sdev, flags); }