From patchwork Wed Apr 3 11:22:29 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Vivekanandan, Balasubramani" X-Patchwork-Id: 13615965 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 578A0CD1288 for ; Wed, 3 Apr 2024 11:22:52 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 8356B112A0B; Wed, 3 Apr 2024 11:22:51 +0000 (UTC) Authentication-Results: gabe.freedesktop.org; dkim=pass (2048-bit key; unprotected) header.d=intel.com header.i=@intel.com header.b="RKyE3tfz"; dkim-atps=neutral Received: from mgamail.intel.com (mgamail.intel.com [198.175.65.10]) by gabe.freedesktop.org (Postfix) with ESMTPS id DF6C110EF3B; Wed, 3 Apr 2024 11:22:48 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1712143369; x=1743679369; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=CboQQp1pv9ZFmZrda2W5aIS+LzDpsqCiBn7sdOpM8tc=; b=RKyE3tfzF7vzu8VUfNx32/2Mv8T28RzOMVGoag6qyzFDvz+6/DFh8m+c 0oPXxPcCif3KhYemLYF0BBEPJzMaMhjvJv0juALxtgzKbDGR2PUKcG/7Q cVG/yOdzZe4wGND2pgbR89GBXrl+ysBPA3cXu5U9eZoSRHgsvSqDC/MMy 1ZYZ4L8EAyXmkBZKiQBMsKUhcUbs6RD2DR38LJrfiwQppO2qp6WjL1lS0 3NvdaWnemHwXI1IrMzrryuWvYeZ9DyMaTll4Y4n1Ha0kZqQO+7MUoa3U0 IkqpYO8xHeWs7/2ImyMoRUx2onCriv2e3yxMX+se2K1tzTPqKcFZus3VD w==; X-CSE-ConnectionGUID: C6SQZ3hLTS2gs3u46xIQ4g== X-CSE-MsgGUID: m+9WRWppTLOKOaNGWjYpRA== X-IronPort-AV: E=McAfee;i="6600,9927,11032"; a="24823978" X-IronPort-AV: E=Sophos;i="6.07,177,1708416000"; d="scan'208";a="24823978" Received: from orviesa009.jf.intel.com ([10.64.159.149]) by orvoesa102.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 03 Apr 2024 04:22:49 -0700 X-CSE-ConnectionGUID: W/+QsBjoQiSag7XgFqYnEg== X-CSE-MsgGUID: zjBzS+hJSrCufwfrQEBq0g== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.07,177,1708416000"; d="scan'208";a="18358486" Received: from bvivekan-desk.iind.intel.com ([10.190.238.63]) by orviesa009-auth.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 03 Apr 2024 04:22:47 -0700 From: Balasubramani Vivekanandan To: intel-gfx@lists.freedesktop.org, intel-xe@lists.freedesktop.org Cc: Matt Roper , Lucas De Marchi , Balasubramani Vivekanandan , Clint Taylor Subject: [PATCH v2 01/25] drm/i915/display: Prepare to handle new C20 PLL register address Date: Wed, 3 Apr 2024 16:52:29 +0530 Message-Id: <20240403112253.1432390-2-balasubramani.vivekanandan@intel.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20240403112253.1432390-1-balasubramani.vivekanandan@intel.com> References: <20240403112253.1432390-1-balasubramani.vivekanandan@intel.com> MIME-Version: 1.0 X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" New platforms have different addresses for C20 PLL registers. This patch prepares the driver to work with different register addresses. New structure `struct intel_c20pll_reg` is created to hold the register addresses for each platform with different register address. CC: Clint Taylor Signed-off-by: Balasubramani Vivekanandan --- drivers/gpu/drm/i915/display/intel_cx0_phy.c | 53 +++++++++++++------ .../gpu/drm/i915/display/intel_cx0_phy_regs.h | 36 ++++++++++--- 2 files changed, 65 insertions(+), 24 deletions(-) diff --git a/drivers/gpu/drm/i915/display/intel_cx0_phy.c b/drivers/gpu/drm/i915/display/intel_cx0_phy.c index a2c4bf33155f..13a2e3db2812 100644 --- a/drivers/gpu/drm/i915/display/intel_cx0_phy.c +++ b/drivers/gpu/drm/i915/display/intel_cx0_phy.c @@ -759,6 +759,17 @@ static const struct intel_c10pll_state * const mtl_c10_edp_tables[] = { NULL, }; +static struct intel_c20pll_reg mtl_c20_reg = { + .tx_cnt_a = MTL_C20_A_TX_CNTX_CFG_ADDR, + .tx_cnt_b = MTL_C20_B_TX_CNTX_CFG_ADDR, + .cmn_cnt_a = MTL_C20_A_CMN_CNTX_CFG_ADDR, + .cmn_cnt_b = MTL_C20_B_CMN_CNTX_CFG_ADDR, + .mplla_a = MTL_C20_A_MPLLA_CFG_ADDR, + .mplla_b = MTL_C20_B_MPLLA_CFG_ADDR, + .mpllb_a = MTL_C20_A_MPLLB_CFG_ADDR, + .mpllb_b = MTL_C20_B_MPLLB_CFG_ADDR +}; + /* C20 basic DP 1.4 tables */ static const struct intel_c20pll_state mtl_c20_dp_rbr = { .clock = 162000, @@ -2161,6 +2172,7 @@ static void intel_c20pll_readout_hw_state(struct intel_encoder *encoder, bool cntx; intel_wakeref_t wakeref; int i; + struct intel_c20pll_reg *pll_reg = &mtl_c20_reg; wakeref = intel_cx0_phy_transaction_begin(encoder); @@ -2171,20 +2183,20 @@ static void intel_c20pll_readout_hw_state(struct intel_encoder *encoder, for (i = 0; i < ARRAY_SIZE(pll_state->tx); i++) { if (cntx) pll_state->tx[i] = intel_c20_sram_read(encoder, INTEL_CX0_LANE0, - PHY_C20_B_TX_CNTX_CFG(i)); + PHY_C20_B_TX_CNTX_CFG(pll_reg, i)); else pll_state->tx[i] = intel_c20_sram_read(encoder, INTEL_CX0_LANE0, - PHY_C20_A_TX_CNTX_CFG(i)); + PHY_C20_A_TX_CNTX_CFG(pll_reg, i)); } /* Read common configuration */ for (i = 0; i < ARRAY_SIZE(pll_state->cmn); i++) { if (cntx) pll_state->cmn[i] = intel_c20_sram_read(encoder, INTEL_CX0_LANE0, - PHY_C20_B_CMN_CNTX_CFG(i)); + PHY_C20_B_CMN_CNTX_CFG(pll_reg, i)); else pll_state->cmn[i] = intel_c20_sram_read(encoder, INTEL_CX0_LANE0, - PHY_C20_A_CMN_CNTX_CFG(i)); + PHY_C20_A_CMN_CNTX_CFG(pll_reg, i)); } if (intel_c20phy_use_mpllb(pll_state)) { @@ -2192,20 +2204,20 @@ static void intel_c20pll_readout_hw_state(struct intel_encoder *encoder, for (i = 0; i < ARRAY_SIZE(pll_state->mpllb); i++) { if (cntx) pll_state->mpllb[i] = intel_c20_sram_read(encoder, INTEL_CX0_LANE0, - PHY_C20_B_MPLLB_CNTX_CFG(i)); + PHY_C20_B_MPLLB_CNTX_CFG(pll_reg, i)); else pll_state->mpllb[i] = intel_c20_sram_read(encoder, INTEL_CX0_LANE0, - PHY_C20_A_MPLLB_CNTX_CFG(i)); + PHY_C20_A_MPLLB_CNTX_CFG(pll_reg, i)); } } else { /* MPLLA configuration */ for (i = 0; i < ARRAY_SIZE(pll_state->mplla); i++) { if (cntx) pll_state->mplla[i] = intel_c20_sram_read(encoder, INTEL_CX0_LANE0, - PHY_C20_B_MPLLA_CNTX_CFG(i)); + PHY_C20_B_MPLLA_CNTX_CFG(pll_reg, i)); else pll_state->mplla[i] = intel_c20_sram_read(encoder, INTEL_CX0_LANE0, - PHY_C20_A_MPLLA_CNTX_CFG(i)); + PHY_C20_A_MPLLA_CNTX_CFG(pll_reg, i)); } } @@ -2341,6 +2353,7 @@ static void intel_c20_pll_program(struct drm_i915_private *i915, u32 clock = crtc_state->port_clock; bool cntx; int i; + const struct intel_c20pll_reg *pll_reg = &mtl_c20_reg; if (intel_crtc_has_dp_encoder(crtc_state)) dp = true; @@ -2363,17 +2376,25 @@ static void intel_c20_pll_program(struct drm_i915_private *i915, /* 3.1 Tx configuration */ for (i = 0; i < ARRAY_SIZE(pll_state->tx); i++) { if (cntx) - intel_c20_sram_write(encoder, INTEL_CX0_LANE0, PHY_C20_A_TX_CNTX_CFG(i), pll_state->tx[i]); + intel_c20_sram_write(encoder, INTEL_CX0_LANE0, + PHY_C20_A_TX_CNTX_CFG(pll_reg, i), + pll_state->tx[i]); else - intel_c20_sram_write(encoder, INTEL_CX0_LANE0, PHY_C20_B_TX_CNTX_CFG(i), pll_state->tx[i]); + intel_c20_sram_write(encoder, INTEL_CX0_LANE0, + PHY_C20_B_TX_CNTX_CFG(pll_reg, i), + pll_state->tx[i]); } /* 3.2 common configuration */ for (i = 0; i < ARRAY_SIZE(pll_state->cmn); i++) { if (cntx) - intel_c20_sram_write(encoder, INTEL_CX0_LANE0, PHY_C20_A_CMN_CNTX_CFG(i), pll_state->cmn[i]); + intel_c20_sram_write(encoder, INTEL_CX0_LANE0, + PHY_C20_A_CMN_CNTX_CFG(pll_reg, i), + pll_state->cmn[i]); else - intel_c20_sram_write(encoder, INTEL_CX0_LANE0, PHY_C20_B_CMN_CNTX_CFG(i), pll_state->cmn[i]); + intel_c20_sram_write(encoder, INTEL_CX0_LANE0, + PHY_C20_B_CMN_CNTX_CFG(pll_reg, i), + pll_state->cmn[i]); } /* 3.3 mpllb or mplla configuration */ @@ -2381,22 +2402,22 @@ static void intel_c20_pll_program(struct drm_i915_private *i915, for (i = 0; i < ARRAY_SIZE(pll_state->mpllb); i++) { if (cntx) intel_c20_sram_write(encoder, INTEL_CX0_LANE0, - PHY_C20_A_MPLLB_CNTX_CFG(i), + PHY_C20_A_MPLLB_CNTX_CFG(pll_reg, i), pll_state->mpllb[i]); else intel_c20_sram_write(encoder, INTEL_CX0_LANE0, - PHY_C20_B_MPLLB_CNTX_CFG(i), + PHY_C20_B_MPLLB_CNTX_CFG(pll_reg, i), pll_state->mpllb[i]); } } else { for (i = 0; i < ARRAY_SIZE(pll_state->mplla); i++) { if (cntx) intel_c20_sram_write(encoder, INTEL_CX0_LANE0, - PHY_C20_A_MPLLA_CNTX_CFG(i), + PHY_C20_A_MPLLA_CNTX_CFG(pll_reg, i), pll_state->mplla[i]); else intel_c20_sram_write(encoder, INTEL_CX0_LANE0, - PHY_C20_B_MPLLA_CNTX_CFG(i), + PHY_C20_B_MPLLA_CNTX_CFG(pll_reg, i), pll_state->mplla[i]); } } diff --git a/drivers/gpu/drm/i915/display/intel_cx0_phy_regs.h b/drivers/gpu/drm/i915/display/intel_cx0_phy_regs.h index bdd0c8c4ef97..882b98dc347b 100644 --- a/drivers/gpu/drm/i915/display/intel_cx0_phy_regs.h +++ b/drivers/gpu/drm/i915/display/intel_cx0_phy_regs.h @@ -254,24 +254,44 @@ #define PHY_C20_VDR_CUSTOM_WIDTH 0xD02 #define PHY_C20_CUSTOM_WIDTH_MASK REG_GENMASK(1, 0) #define PHY_C20_CUSTOM_WIDTH(val) REG_FIELD_PREP8(PHY_C20_CUSTOM_WIDTH_MASK, val) -#define PHY_C20_A_TX_CNTX_CFG(idx) (0xCF2E - (idx)) -#define PHY_C20_B_TX_CNTX_CFG(idx) (0xCF2A - (idx)) +#define PHY_C20_A_TX_CNTX_CFG(reg, idx) ((reg)->tx_cnt_a - (idx)) +#define PHY_C20_B_TX_CNTX_CFG(reg, idx) ((reg)->tx_cnt_b - (idx)) #define C20_PHY_TX_RATE REG_GENMASK(2, 0) -#define PHY_C20_A_CMN_CNTX_CFG(idx) (0xCDAA - (idx)) -#define PHY_C20_B_CMN_CNTX_CFG(idx) (0xCDA5 - (idx)) -#define PHY_C20_A_MPLLA_CNTX_CFG(idx) (0xCCF0 - (idx)) -#define PHY_C20_B_MPLLA_CNTX_CFG(idx) (0xCCE5 - (idx)) +#define PHY_C20_A_CMN_CNTX_CFG(reg, idx) ((reg)->cmn_cnt_a - (idx)) +#define PHY_C20_B_CMN_CNTX_CFG(reg, idx) ((reg)->cmn_cnt_b - (idx)) +#define PHY_C20_A_MPLLA_CNTX_CFG(reg, idx) ((reg)->mplla_a - (idx)) +#define PHY_C20_B_MPLLA_CNTX_CFG(reg, idx) ((reg)->mplla_b - (idx)) #define C20_MPLLA_FRACEN REG_BIT(14) #define C20_FB_CLK_DIV4_EN REG_BIT(13) #define C20_MPLLA_TX_CLK_DIV_MASK REG_GENMASK(10, 8) -#define PHY_C20_A_MPLLB_CNTX_CFG(idx) (0xCB5A - (idx)) -#define PHY_C20_B_MPLLB_CNTX_CFG(idx) (0xCB4E - (idx)) +#define PHY_C20_A_MPLLB_CNTX_CFG(reg, idx) ((reg)->mpllb_a - (idx)) +#define PHY_C20_B_MPLLB_CNTX_CFG(reg, idx) ((reg)->mpllb_b - (idx)) #define C20_MPLLB_TX_CLK_DIV_MASK REG_GENMASK(15, 13) #define C20_MPLLB_FRACEN REG_BIT(13) #define C20_REF_CLK_MPLLB_DIV_MASK REG_GENMASK(12, 10) #define C20_MULTIPLIER_MASK REG_GENMASK(11, 0) #define C20_PHY_USE_MPLLB REG_BIT(7) +struct intel_c20pll_reg { + u16 tx_cnt_a; + u16 tx_cnt_b; + u16 cmn_cnt_a; + u16 cmn_cnt_b; + u16 mplla_a; + u16 mplla_b; + u16 mpllb_a; + u16 mpllb_b; +}; + +#define MTL_C20_A_TX_CNTX_CFG_ADDR 0xCF2E +#define MTL_C20_B_TX_CNTX_CFG_ADDR 0xCF2A +#define MTL_C20_A_CMN_CNTX_CFG_ADDR 0xCDAA +#define MTL_C20_B_CMN_CNTX_CFG_ADDR 0xCDA5 +#define MTL_C20_A_MPLLA_CFG_ADDR 0xCCF0 +#define MTL_C20_B_MPLLA_CFG_ADDR 0xCCE5 +#define MTL_C20_A_MPLLB_CFG_ADDR 0xCB5A +#define MTL_C20_B_MPLLB_CFG_ADDR 0xCB4E + /* C20 Phy VSwing Masks */ #define C20_PHY_VSWING_PREEMPH_MASK REG_GENMASK8(5, 0) #define C20_PHY_VSWING_PREEMPH(val) REG_FIELD_PREP8(C20_PHY_VSWING_PREEMPH_MASK, val) From patchwork Wed Apr 3 11:22:30 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Vivekanandan, Balasubramani" X-Patchwork-Id: 13615966 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id D81BBCD1294 for ; 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X-CSE-ConnectionGUID: 0ek16IiLTNWhBBmPMFTXYA== X-CSE-MsgGUID: GckoN95fRl28+zI+7CxAQw== X-IronPort-AV: E=McAfee;i="6600,9927,11032"; a="24823996" X-IronPort-AV: E=Sophos;i="6.07,177,1708416000"; d="scan'208";a="24823996" Received: from orviesa009.jf.intel.com ([10.64.159.149]) by orvoesa102.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 03 Apr 2024 04:22:51 -0700 X-CSE-ConnectionGUID: oeF1KSdRTs++HnnK3YUqTg== X-CSE-MsgGUID: VdzWpvLRRZiNQrmOdL70Ug== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.07,177,1708416000"; d="scan'208";a="18358492" Received: from bvivekan-desk.iind.intel.com ([10.190.238.63]) by orviesa009-auth.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 03 Apr 2024 04:22:50 -0700 From: Balasubramani Vivekanandan To: intel-gfx@lists.freedesktop.org, intel-xe@lists.freedesktop.org Cc: Matt Roper , Lucas De Marchi , Balasubramani Vivekanandan Subject: [PATCH v2 02/25] drm/xe/bmg: Add BMG platform definition Date: Wed, 3 Apr 2024 16:52:30 +0530 Message-Id: <20240403112253.1432390-3-balasubramani.vivekanandan@intel.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20240403112253.1432390-1-balasubramani.vivekanandan@intel.com> References: <20240403112253.1432390-1-balasubramani.vivekanandan@intel.com> MIME-Version: 1.0 X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" From: Matt Roper BMG is a discrete GPU based on the Xe2 architecture. Bspec: 68090 Signed-off-by: Matt Roper Signed-off-by: Balasubramani Vivekanandan --- drivers/gpu/drm/xe/xe_pci.c | 7 +++++++ drivers/gpu/drm/xe/xe_platform_types.h | 1 + include/drm/xe_pciids.h | 7 +++++++ 3 files changed, 15 insertions(+) diff --git a/drivers/gpu/drm/xe/xe_pci.c b/drivers/gpu/drm/xe/xe_pci.c index c47ab4b67467..b3158053baee 100644 --- a/drivers/gpu/drm/xe/xe_pci.c +++ b/drivers/gpu/drm/xe/xe_pci.c @@ -337,6 +337,12 @@ static const struct xe_device_desc lnl_desc = { .require_force_probe = true, }; +static const struct xe_device_desc bmg_desc = { + DGFX_FEATURES, + PLATFORM(XE_BATTLEMAGE), + .require_force_probe = true, +}; + #undef PLATFORM __diag_pop(); @@ -379,6 +385,7 @@ static const struct pci_device_id pciidlist[] = { XE_PVC_IDS(INTEL_VGA_DEVICE, &pvc_desc), XE_MTL_IDS(INTEL_VGA_DEVICE, &mtl_desc), XE_LNL_IDS(INTEL_VGA_DEVICE, &lnl_desc), + XE_BMG_IDS(INTEL_VGA_DEVICE, &bmg_desc), { } }; MODULE_DEVICE_TABLE(pci, pciidlist); diff --git a/drivers/gpu/drm/xe/xe_platform_types.h b/drivers/gpu/drm/xe/xe_platform_types.h index 553f53dbd093..79b7042c4534 100644 --- a/drivers/gpu/drm/xe/xe_platform_types.h +++ b/drivers/gpu/drm/xe/xe_platform_types.h @@ -22,6 +22,7 @@ enum xe_platform { XE_PVC, XE_METEORLAKE, XE_LUNARLAKE, + XE_BATTLEMAGE, }; enum xe_subplatform { diff --git a/include/drm/xe_pciids.h b/include/drm/xe_pciids.h index c7fc288dacee..73d972a8aca1 100644 --- a/include/drm/xe_pciids.h +++ b/include/drm/xe_pciids.h @@ -208,4 +208,11 @@ MACRO__(0x64A0, ## __VA_ARGS__), \ MACRO__(0x64B0, ## __VA_ARGS__) +#define XE_BMG_IDS(MACRO__, ...) \ + MACRO__(0xE202, ## __VA_ARGS__), \ + MACRO__(0xE20B, ## __VA_ARGS__), \ + MACRO__(0xE20C, ## __VA_ARGS__), \ + MACRO__(0xE20D, ## __VA_ARGS__), \ + MACRO__(0xE212, ## __VA_ARGS__) + #endif From patchwork Wed Apr 3 11:22:31 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Vivekanandan, Balasubramani" X-Patchwork-Id: 13615967 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 04B2ECD1288 for ; Wed, 3 Apr 2024 11:22:56 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 6F15810EF3B; Wed, 3 Apr 2024 11:22:55 +0000 (UTC) Authentication-Results: gabe.freedesktop.org; dkim=pass (2048-bit key; unprotected) header.d=intel.com header.i=@intel.com header.b="W8VUHWds"; dkim-atps=neutral Received: from mgamail.intel.com (mgamail.intel.com [198.175.65.10]) by gabe.freedesktop.org (Postfix) with ESMTPS id F18D2112A0F; Wed, 3 Apr 2024 11:22:52 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1712143373; x=1743679373; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=xzrFbXEDQUB8nd70SidKMIXoBJZQIcCHF292AjuMF8Q=; b=W8VUHWdsE6/+JKJNHp/dQJCqNB4zoQ4u3M0J+4aqLxisw/FufVHP4Kmf rfa88vDzH+z/7uUxyDbOikmyZbdG5R9ACUOOjRZzvhDf3cMCuoUE4lA7z mxqlMsPXzTPv61MR+7Nh85VXLhr1ExL3d2sajttPxw5h481uppRhffy7O gUEHFnRTUGSQM8iMQPP8Q6xcDhQjMlRcTqVEVFVpptzVgSDtbYNlqx75i Byws5xF75ppsVNZbLpWZLQ8zzn1sZrQpMdvTKyunjc5nhZHKg3ICVZQtB DvUZaMz008D1T92ryUuSQDDyrGLaxR9Wk43g7sgxUBkWZKfQkhpR7RGYL g==; X-CSE-ConnectionGUID: dgiRcADDSIK19hHbKcrYGg== X-CSE-MsgGUID: e58ghcTRTyCx+ZMflxHELQ== X-IronPort-AV: E=McAfee;i="6600,9927,11032"; a="24824006" X-IronPort-AV: E=Sophos;i="6.07,177,1708416000"; d="scan'208";a="24824006" Received: from orviesa009.jf.intel.com ([10.64.159.149]) by orvoesa102.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 03 Apr 2024 04:22:53 -0700 X-CSE-ConnectionGUID: PA4PbNqkQhK4fHduQu0BCA== X-CSE-MsgGUID: tO2vG1OeS0GMsdtGKqF9qw== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.07,177,1708416000"; d="scan'208";a="18358495" Received: from bvivekan-desk.iind.intel.com ([10.190.238.63]) by orviesa009-auth.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 03 Apr 2024 04:22:52 -0700 From: Balasubramani Vivekanandan To: intel-gfx@lists.freedesktop.org, intel-xe@lists.freedesktop.org Cc: Matt Roper , Lucas De Marchi , Balasubramani Vivekanandan Subject: [PATCH v2 03/25] drm/xe/bmg: Define IS_BATTLEMAGE macro Date: Wed, 3 Apr 2024 16:52:31 +0530 Message-Id: <20240403112253.1432390-4-balasubramani.vivekanandan@intel.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20240403112253.1432390-1-balasubramani.vivekanandan@intel.com> References: <20240403112253.1432390-1-balasubramani.vivekanandan@intel.com> MIME-Version: 1.0 X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" Common display code requires IS_BATTLEMAGE macro. Defined the macro. Signed-off-by: Balasubramani Vivekanandan Reviewed-by: Matt Roper --- drivers/gpu/drm/xe/compat-i915-headers/i915_drv.h | 1 + 1 file changed, 1 insertion(+) diff --git a/drivers/gpu/drm/xe/compat-i915-headers/i915_drv.h b/drivers/gpu/drm/xe/compat-i915-headers/i915_drv.h index a01d1b869c2d..9161d1fdf239 100644 --- a/drivers/gpu/drm/xe/compat-i915-headers/i915_drv.h +++ b/drivers/gpu/drm/xe/compat-i915-headers/i915_drv.h @@ -88,6 +88,7 @@ static inline struct drm_i915_private *kdev_to_i915(struct device *kdev) #define IS_DG2(dev_priv) IS_PLATFORM(dev_priv, XE_DG2) #define IS_METEORLAKE(dev_priv) IS_PLATFORM(dev_priv, XE_METEORLAKE) #define IS_LUNARLAKE(dev_priv) IS_PLATFORM(dev_priv, XE_LUNARLAKE) +#define IS_BATTLEMAGE(dev_priv) IS_PLATFORM(dev_priv, XE_BATTLEMAGE) #define IS_HASWELL_ULT(dev_priv) (dev_priv && 0) #define IS_BROADWELL_ULT(dev_priv) (dev_priv && 0) From patchwork Wed Apr 3 11:22:32 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Vivekanandan, Balasubramani" X-Patchwork-Id: 13615968 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id A5A14CD1297 for ; Wed, 3 Apr 2024 11:22:57 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id D5682112A12; Wed, 3 Apr 2024 11:22:56 +0000 (UTC) Authentication-Results: gabe.freedesktop.org; dkim=pass (2048-bit key; unprotected) header.d=intel.com header.i=@intel.com header.b="LNkMqCE0"; dkim-atps=neutral Received: from mgamail.intel.com (mgamail.intel.com [198.175.65.10]) by gabe.freedesktop.org (Postfix) with ESMTPS id 2F930112A11; Wed, 3 Apr 2024 11:22:55 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1712143376; x=1743679376; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=gdyAvl2ku3TYX1gG2FKpS39C3vPWe9URIlYDj2KKYoE=; b=LNkMqCE0/QIHd/oRB5LNzVcWdNTK7216PVf9UXx9X+TWxZCrnYP8jRd9 BxgtUUBVfPASaN/8OKcCMBdyhvzlLEhDvSwhFtvfmJm/1hsCm+DSGuvfx i7aHRwGDQffJyINS58ELJ2GCBB6U1wS0q36hORYtpUN00sX+hyy/kwcKh RF7NTi18Kd5IX0aCmG+5+Ypu3DbnSsS5CDXO7/YioI/CL8ObRw2N2RWTS vS90qIlx7E3m/pUemdNfY1kkuFaKLb0m4NUhC5CL9oKNbciHGCKMnD+u0 FfoqtjX+aIH6uDS8XdmLhgUxHwTOs/gDO1cfo30wHEWkEBzedCapM5qlx w==; X-CSE-ConnectionGUID: 2bPh/XOmTg6JOS3aahgkPQ== X-CSE-MsgGUID: vnVVAPcOTpahipXxiUEDgA== X-IronPort-AV: E=McAfee;i="6600,9927,11032"; a="24824015" X-IronPort-AV: E=Sophos;i="6.07,177,1708416000"; d="scan'208";a="24824015" Received: from orviesa009.jf.intel.com ([10.64.159.149]) by orvoesa102.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 03 Apr 2024 04:22:55 -0700 X-CSE-ConnectionGUID: vrXGThaoROO45UXZBP9QPQ== X-CSE-MsgGUID: +Hss+hRVTO6ZtnbGfZXvhg== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.07,177,1708416000"; d="scan'208";a="18358499" Received: from bvivekan-desk.iind.intel.com ([10.190.238.63]) by orviesa009-auth.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 03 Apr 2024 04:22:54 -0700 From: Balasubramani Vivekanandan To: intel-gfx@lists.freedesktop.org, intel-xe@lists.freedesktop.org Cc: Matt Roper , Lucas De Marchi , Balasubramani Vivekanandan Subject: [PATCH v2 04/25] drm/i915/bmg: Define IS_BATTLEMAGE macro Date: Wed, 3 Apr 2024 16:52:32 +0530 Message-Id: <20240403112253.1432390-5-balasubramani.vivekanandan@intel.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20240403112253.1432390-1-balasubramani.vivekanandan@intel.com> References: <20240403112253.1432390-1-balasubramani.vivekanandan@intel.com> MIME-Version: 1.0 X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" Display code uses IS_BATTLEMAGE macro but the platform support doesn't still exist in i915. So fake IS_BATTLEMAGE macro defined to enable building i915 code. We should make sure the macro parameter is used in the always-false expression so that we don't run into "unused variable" warnings from i915 builds if the IS_BATTLEMAGE() check is the only place the i915 pointer gets used in a function. While we're at it, also update the IS_LUNARLAKE macro to include the parameter in the false expression for consistency. Signed-off-by: Balasubramani Vivekanandan --- drivers/gpu/drm/i915/i915_drv.h | 10 +++++++++- 1 file changed, 9 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h index cf52d4adaa20..b41a414079f4 100644 --- a/drivers/gpu/drm/i915/i915_drv.h +++ b/drivers/gpu/drm/i915/i915_drv.h @@ -546,7 +546,15 @@ IS_SUBPLATFORM(const struct drm_i915_private *i915, #define IS_ALDERLAKE_P(i915) IS_PLATFORM(i915, INTEL_ALDERLAKE_P) #define IS_DG2(i915) IS_PLATFORM(i915, INTEL_DG2) #define IS_METEORLAKE(i915) IS_PLATFORM(i915, INTEL_METEORLAKE) -#define IS_LUNARLAKE(i915) 0 +/* + * Display code shared by i915 and Xe relies on macros like IS_LUNARLAKE, + * so we need to define these even on platforms that the i915 base driver + * doesn't support. Ensure the parameter is used in the definition to + * avoid 'unused variable' warnings when compiling the shared display code + * for i915. + */ +#define IS_LUNARLAKE(i915) (0 && i915) +#define IS_BATTLEMAGE(i915) (0 && i915) #define IS_DG2_G10(i915) \ IS_SUBPLATFORM(i915, INTEL_DG2, INTEL_SUBPLATFORM_G10) From patchwork Wed Apr 3 11:22:33 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Vivekanandan, Balasubramani" X-Patchwork-Id: 13615969 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 91AEDCD1288 for ; Wed, 3 Apr 2024 11:22:58 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id D5EAE112A13; Wed, 3 Apr 2024 11:22:57 +0000 (UTC) Authentication-Results: gabe.freedesktop.org; dkim=pass (2048-bit key; unprotected) header.d=intel.com header.i=@intel.com header.b="WfiAtth1"; dkim-atps=neutral Received: from mgamail.intel.com (mgamail.intel.com [198.175.65.10]) by gabe.freedesktop.org (Postfix) with ESMTPS id 128EA112A13; Wed, 3 Apr 2024 11:22:57 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1712143378; x=1743679378; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=E+/qmvmu7vA275hhKi/pscf3kXISOjYilu4tx04vdpY=; b=WfiAtth1265fSBAKbCxv7Zpee8ImzS71rxIwvPN/g6+OON6SxA8/7hE0 WKdszQuNzzQmYJiodxZg+srX4GaINxrvOEzyY8EGX2uzIJ59fydpQXi+3 tGxxB6bYFVylN3pKhwCcUmQjYll7qKN+mq21crnxpe7cnusvIdwTQfxgT lbg9WhiCeTtSDsQVL+oXY3X58IaC7vYGpFUUJkzm3Dh5mJpdOaPusjTd6 2i6mHVRfkaGDqIkNZ2mLijv/OkqWLw45HF5a1+IQ+xwKQ6OIdZrbGwUfR 1KTrihuJu4jIR4PZ04KZrBweG4wVAT9XagLzDlIuOpZGTmHBB2e+dcX4m Q==; X-CSE-ConnectionGUID: bSazC3ykSC+VOwgereLgQw== X-CSE-MsgGUID: t5aSzWgsT7Cqk+QQxXiPYw== X-IronPort-AV: E=McAfee;i="6600,9927,11032"; a="24824023" X-IronPort-AV: E=Sophos;i="6.07,177,1708416000"; d="scan'208";a="24824023" Received: from orviesa009.jf.intel.com ([10.64.159.149]) by orvoesa102.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 03 Apr 2024 04:22:57 -0700 X-CSE-ConnectionGUID: h6X1KBeaSlC6lqg3X5qwKw== X-CSE-MsgGUID: vu+vF8UBS+aoH0SzdqRN2Q== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.07,177,1708416000"; d="scan'208";a="18358503" Received: from bvivekan-desk.iind.intel.com ([10.190.238.63]) by orviesa009-auth.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 03 Apr 2024 04:22:56 -0700 From: Balasubramani Vivekanandan To: intel-gfx@lists.freedesktop.org, intel-xe@lists.freedesktop.org Cc: Matt Roper , Lucas De Marchi , Balasubramani Vivekanandan Subject: [PATCH v2 05/25] drm/i915/xe2: Skip CCS modifiers for Xe2 platforms Date: Wed, 3 Apr 2024 16:52:33 +0530 Message-Id: <20240403112253.1432390-6-balasubramani.vivekanandan@intel.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20240403112253.1432390-1-balasubramani.vivekanandan@intel.com> References: <20240403112253.1432390-1-balasubramani.vivekanandan@intel.com> MIME-Version: 1.0 X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" Xe2 platforms doesn't support Aux CCS and the Flat CCS is enabled through PAT. No CCS modifiers required for Xe2 platforms. Signed-off-by: Balasubramani Vivekanandan --- drivers/gpu/drm/i915/display/intel_fb.c | 14 +++++++++++--- 1 file changed, 11 insertions(+), 3 deletions(-) diff --git a/drivers/gpu/drm/i915/display/intel_fb.c b/drivers/gpu/drm/i915/display/intel_fb.c index 3ea6470d6d92..923e97c3aa6c 100644 --- a/drivers/gpu/drm/i915/display/intel_fb.c +++ b/drivers/gpu/drm/i915/display/intel_fb.c @@ -431,9 +431,17 @@ static bool plane_has_modifier(struct drm_i915_private *i915, * Separate AuxCCS and Flat CCS modifiers to be run only on platforms * where supported. */ - if (intel_fb_is_ccs_modifier(md->modifier) && - HAS_FLAT_CCS(i915) != !md->ccs.packed_aux_planes) - return false; + if (intel_fb_is_ccs_modifier(md->modifier)) { + /* + * No CCS modifiers available on Xe2 platforms as they don't + * support Aux CCS and the Flat CCS is enabled via PAT + */ + if ((DISPLAY_VER(i915) >= 20) || IS_BATTLEMAGE(i915)) + return false; + + if (HAS_FLAT_CCS(i915) != !md->ccs.packed_aux_planes) + return false; + } return true; } From patchwork Wed Apr 3 11:22:34 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Vivekanandan, Balasubramani" X-Patchwork-Id: 13615970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id C26FFCD1288 for ; Wed, 3 Apr 2024 11:23:01 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 2EFE2112236; Wed, 3 Apr 2024 11:23:01 +0000 (UTC) Authentication-Results: gabe.freedesktop.org; dkim=pass (2048-bit key; unprotected) header.d=intel.com header.i=@intel.com header.b="ie0lwNS+"; dkim-atps=neutral Received: from mgamail.intel.com (mgamail.intel.com [198.175.65.10]) by gabe.freedesktop.org (Postfix) with ESMTPS id 941A7112A17; Wed, 3 Apr 2024 11:22:59 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1712143380; x=1743679380; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=nFSyzKrDtDqDcvfqRCvLYsCntufo5yT5P8lczjLoZrs=; b=ie0lwNS+glOjm816XjYYqvg7hWrNb/ilW79Sf+lL1Yr7GhKMsZQIQFZP KfegFGL1VytpeXt3c6SvWkhFzOK0Q5Iwmhbxd/myI9Mwjcfjxe5HHZdub lzI2z9NLSz+Eh/xnUQHsoOspFHsqB1EZZE7JX0CcuVGEMp2f/3f3qtIi9 qXh6YPrhPQlvUfGPc6zNvS26CbyYb6DWOJj2ZDRy/DY/nLekhKKFjH3WI xsw1sNpLE3n6MQa0MV7+TlwUHoVUZAXfFWoGWxU8hfOEJdLZXCVWlJOO1 S4ogpYpXvT2PqWLa3UZ3Yw8c2cw3aQVyTSrhggi765fyJASIzniMyMfni Q==; X-CSE-ConnectionGUID: Gv26QzCoQpWYvvG6oZy8YQ== X-CSE-MsgGUID: S92AaKkfQ6abvL/0ehIipA== X-IronPort-AV: E=McAfee;i="6600,9927,11032"; a="24824042" X-IronPort-AV: E=Sophos;i="6.07,177,1708416000"; d="scan'208";a="24824042" Received: from orviesa009.jf.intel.com ([10.64.159.149]) by orvoesa102.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 03 Apr 2024 04:23:00 -0700 X-CSE-ConnectionGUID: GSZxGguJT1aaeoXHmGOcPg== X-CSE-MsgGUID: +B8vGS7jSvecs7jvIrVpgQ== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.07,177,1708416000"; d="scan'208";a="18358506" Received: from bvivekan-desk.iind.intel.com ([10.190.238.63]) by orviesa009-auth.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 03 Apr 2024 04:22:58 -0700 From: Balasubramani Vivekanandan To: intel-gfx@lists.freedesktop.org, intel-xe@lists.freedesktop.org Cc: Matt Roper , Lucas De Marchi , Clint Taylor , Balasubramani Vivekanandan Subject: [PATCH v2 06/25] drm/i915/xe2hpd: Initial cdclk table Date: Wed, 3 Apr 2024 16:52:34 +0530 Message-Id: <20240403112253.1432390-7-balasubramani.vivekanandan@intel.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20240403112253.1432390-1-balasubramani.vivekanandan@intel.com> References: <20240403112253.1432390-1-balasubramani.vivekanandan@intel.com> MIME-Version: 1.0 X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" From: Clint Taylor Add Xe2_HPD specific CDCLK table and use MTL Funcs. Bspec: 65243 Cc: Matt Roper CC: Lucas De Marchi Signed-off-by: Clint Taylor Signed-off-by: Balasubramani Vivekanandan Reviewed-by: Matt Roper --- drivers/gpu/drm/i915/display/intel_cdclk.c | 11 +++++++++++ 1 file changed, 11 insertions(+) diff --git a/drivers/gpu/drm/i915/display/intel_cdclk.c b/drivers/gpu/drm/i915/display/intel_cdclk.c index 31aaa9780dfc..da16c308670f 100644 --- a/drivers/gpu/drm/i915/display/intel_cdclk.c +++ b/drivers/gpu/drm/i915/display/intel_cdclk.c @@ -1444,6 +1444,14 @@ static const struct intel_cdclk_vals xe2lpd_cdclk_table[] = { {} }; +/* + * Xe2_HPD always uses the minimal cdclk table from Wa_15015413771 + */ +static const struct intel_cdclk_vals xe2hpd_cdclk_table[] = { + { .refclk = 38400, .cdclk = 652800, .ratio = 34, .waveform = 0xffff }, + {} +}; + static const int cdclk_squash_len = 16; static int cdclk_squash_divider(u16 waveform) @@ -3768,6 +3776,9 @@ void intel_init_cdclk_hooks(struct drm_i915_private *dev_priv) if (DISPLAY_VER(dev_priv) >= 20) { dev_priv->display.funcs.cdclk = &rplu_cdclk_funcs; dev_priv->display.cdclk.table = xe2lpd_cdclk_table; + } else if (DISPLAY_VER_FULL(dev_priv) >= IP_VER(14, 1)) { + dev_priv->display.funcs.cdclk = &rplu_cdclk_funcs; + dev_priv->display.cdclk.table = xe2hpd_cdclk_table; } else if (DISPLAY_VER(dev_priv) >= 14) { dev_priv->display.funcs.cdclk = &rplu_cdclk_funcs; dev_priv->display.cdclk.table = mtl_cdclk_table; From patchwork Wed Apr 3 11:22:35 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Vivekanandan, Balasubramani" X-Patchwork-Id: 13615971 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 03580CD128A for ; Wed, 3 Apr 2024 11:23:03 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 4A3B210ED19; Wed, 3 Apr 2024 11:23:03 +0000 (UTC) Authentication-Results: gabe.freedesktop.org; dkim=pass (2048-bit key; unprotected) header.d=intel.com header.i=@intel.com header.b="fcIADIhj"; dkim-atps=neutral Received: from mgamail.intel.com (mgamail.intel.com [198.175.65.10]) by gabe.freedesktop.org (Postfix) with ESMTPS id CC23D112A18; Wed, 3 Apr 2024 11:23:01 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1712143382; x=1743679382; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=QxM+kkrrWmnY6l+PtNpH+qYLdv73kcRtv8GuKIRMRN8=; b=fcIADIhjAuojkYI8PHbF+C2chxrqgeLpJTsfjHD2tEHPLjYiGkH+aeLm JNc94955tDL1Z4b9Yqjk3y585XqUt84VDaxmKeuvgzegHS9VGNA7Xcefd WgnAmdfgKh/48xsMHFD10ku2wrxm1iW5ayj0S6Zp37QpOhisJr3T1mZ6R Qz2fOy6ukaQQUp/vRJra+8TZBeoPwICMhbynIbNeHr8FH9IHpVN9RKfxa KP2CkLUmASP31HZHVaIiCwa3LHzFMoNsRNrpocz3QDcWhYHjBPUFyFpLY EvRbM/5/HCKMeHFirTvs/LZ3ykjRFnZf0QWHJIohMGDrgxR+sBWsWiy0v Q==; X-CSE-ConnectionGUID: a5OuARaCQvit/WaVD3B0fA== X-CSE-MsgGUID: ifmbQosIRqKiayMLYPNuHw== X-IronPort-AV: E=McAfee;i="6600,9927,11032"; a="24824053" X-IronPort-AV: E=Sophos;i="6.07,177,1708416000"; d="scan'208";a="24824053" Received: from orviesa009.jf.intel.com ([10.64.159.149]) by orvoesa102.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 03 Apr 2024 04:23:02 -0700 X-CSE-ConnectionGUID: kb/Vby8ZQ+Kppi5VMRNzVA== X-CSE-MsgGUID: HKZvaaqaQZ2i2P8hmQHRrA== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.07,177,1708416000"; d="scan'208";a="18358509" Received: from bvivekan-desk.iind.intel.com ([10.190.238.63]) by orviesa009-auth.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 03 Apr 2024 04:23:00 -0700 From: Balasubramani Vivekanandan To: intel-gfx@lists.freedesktop.org, intel-xe@lists.freedesktop.org Cc: Matt Roper , Lucas De Marchi , Ankit Nautiyal , Balasubramani Vivekanandan Subject: [PATCH v2 07/25] Revert "drm/i915/dgfx: DGFX uses direct VBT pin mapping" Date: Wed, 3 Apr 2024 16:52:35 +0530 Message-Id: <20240403112253.1432390-8-balasubramani.vivekanandan@intel.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20240403112253.1432390-1-balasubramani.vivekanandan@intel.com> References: <20240403112253.1432390-1-balasubramani.vivekanandan@intel.com> MIME-Version: 1.0 X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" From: Ankit Nautiyal This reverts commit 562f33836f519a235e5c5e71bcc723ab1faccd2f. For BMG it seems that the VBT to DDI mapping does not follow DG1, and DG2, but follows ADLP mapping given in Bspec:20124. Signed-off-by: Ankit Nautiyal Signed-off-by: Balasubramani Vivekanandan Reviewed-by: Matt Roper --- drivers/gpu/drm/i915/display/intel_bios.c | 5 ++--- 1 file changed, 2 insertions(+), 3 deletions(-) diff --git a/drivers/gpu/drm/i915/display/intel_bios.c b/drivers/gpu/drm/i915/display/intel_bios.c index 2abd2d7ceda2..03fbd6c73f3f 100644 --- a/drivers/gpu/drm/i915/display/intel_bios.c +++ b/drivers/gpu/drm/i915/display/intel_bios.c @@ -2238,15 +2238,14 @@ static u8 map_ddc_pin(struct drm_i915_private *i915, u8 vbt_pin) const u8 *ddc_pin_map; int i, n_entries; - if (IS_DGFX(i915)) - return vbt_pin; - if (INTEL_PCH_TYPE(i915) >= PCH_MTL || IS_ALDERLAKE_P(i915)) { ddc_pin_map = adlp_ddc_pin_map; n_entries = ARRAY_SIZE(adlp_ddc_pin_map); } else if (IS_ALDERLAKE_S(i915)) { ddc_pin_map = adls_ddc_pin_map; n_entries = ARRAY_SIZE(adls_ddc_pin_map); + } else if (INTEL_PCH_TYPE(i915) >= PCH_DG1) { + return vbt_pin; } else if (IS_ROCKETLAKE(i915) && INTEL_PCH_TYPE(i915) == PCH_TGP) { ddc_pin_map = rkl_pch_tgp_ddc_pin_map; n_entries = ARRAY_SIZE(rkl_pch_tgp_ddc_pin_map); From patchwork Wed Apr 3 11:22:36 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Vivekanandan, Balasubramani" X-Patchwork-Id: 13615972 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 53738CD1288 for ; Wed, 3 Apr 2024 11:23:06 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id C78BE112A17; Wed, 3 Apr 2024 11:23:05 +0000 (UTC) Authentication-Results: gabe.freedesktop.org; dkim=pass (2048-bit key; unprotected) header.d=intel.com header.i=@intel.com header.b="BU/ws40o"; dkim-atps=neutral Received: from mgamail.intel.com (mgamail.intel.com [198.175.65.10]) by gabe.freedesktop.org (Postfix) with ESMTPS id 21E0B112A17; Wed, 3 Apr 2024 11:23:04 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1712143385; x=1743679385; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=k5vVrDHOGXGIX6TqFn0d1Wmuo+zGSGpmn15xT/TVfYI=; b=BU/ws40oEedocpA7aBngUrHCzHuRMARlwx6xX/cEDvUUgnPCtIJJ14vZ v+TC7wrxQ8Fv7FOrttaSyx4UH/p9SpwEUX4nre3mCYTLHJmqPzZYN5K8+ 4TWgF5NfyzFd02OYfyr435Dn/LB039siU7RnWbVS+WEfABXT9/J4/MJF0 h67KMLCK99ubCUEgi3v6kv9LcVM3GgHKo00iAQXTb21+LExmoqpXatZ+B ERt5PDkNjbwHi0PoeBIqdvrn9aHj9liwGf6CTFQ6Mm//YgkYYWokMvt/y /uHadiXqHvWLkkdtF4oXPooc4HeQsXVhWzoNxqBpdMKaTLun1c5QA9QNe g==; X-CSE-ConnectionGUID: t+27z/MYQ2WXO8/NZ3G8Pw== X-CSE-MsgGUID: GeitHBAqTB2DJoMv+TKpvg== X-IronPort-AV: E=McAfee;i="6600,9927,11032"; a="24824061" X-IronPort-AV: E=Sophos;i="6.07,177,1708416000"; d="scan'208";a="24824061" Received: from orviesa009.jf.intel.com ([10.64.159.149]) by orvoesa102.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 03 Apr 2024 04:23:04 -0700 X-CSE-ConnectionGUID: c1WkxxQOSourjk7j6CDutg== X-CSE-MsgGUID: mnWicduuTy28gZnPQ9FL8Q== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.07,177,1708416000"; d="scan'208";a="18358512" Received: from bvivekan-desk.iind.intel.com ([10.190.238.63]) by orviesa009-auth.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 03 Apr 2024 04:23:02 -0700 From: Balasubramani Vivekanandan To: intel-gfx@lists.freedesktop.org, intel-xe@lists.freedesktop.org Cc: Matt Roper , Lucas De Marchi , Radhakrishna Sripada , Balasubramani Vivekanandan Subject: [PATCH v2 08/25] drm/i915/bmg: Extend DG2 tc check to future Date: Wed, 3 Apr 2024 16:52:36 +0530 Message-Id: <20240403112253.1432390-9-balasubramani.vivekanandan@intel.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20240403112253.1432390-1-balasubramani.vivekanandan@intel.com> References: <20240403112253.1432390-1-balasubramani.vivekanandan@intel.com> MIME-Version: 1.0 X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" From: Radhakrishna Sripada Discrete cards use the Port numbers TC1-4 for the offsets. The regular flow for type-c subsystem port initialization can be skipped. This check is present in DG2. Extend this to future discrete products. Signed-off-by: Radhakrishna Sripada Signed-off-by: Balasubramani Vivekanandan Reviewed-by: Matt Roper --- drivers/gpu/drm/i915/display/intel_display.c | 7 +++---- 1 file changed, 3 insertions(+), 4 deletions(-) diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c index 614e60420a29..aed25890b6f5 100644 --- a/drivers/gpu/drm/i915/display/intel_display.c +++ b/drivers/gpu/drm/i915/display/intel_display.c @@ -1861,11 +1861,10 @@ bool intel_phy_is_combo(struct drm_i915_private *dev_priv, enum phy phy) bool intel_phy_is_tc(struct drm_i915_private *dev_priv, enum phy phy) { /* - * DG2's "TC1", although TC-capable output, doesn't share the same flow - * as other platforms on the display engine side and rather rely on the - * SNPS PHY, that is programmed separately + * Discrete GPU phy's are not attached to FIA's to support TC + * subsystem Legacy or non-legacy, and only support native DP/HDMI */ - if (IS_DG2(dev_priv)) + if (IS_DGFX(dev_priv)) return false; if (DISPLAY_VER(dev_priv) >= 13) From patchwork Wed Apr 3 11:22:37 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: "Vivekanandan, Balasubramani" X-Patchwork-Id: 13615973 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 7B069CD1297 for ; Wed, 3 Apr 2024 11:23:08 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id C5EC8112A11; Wed, 3 Apr 2024 11:23:07 +0000 (UTC) Authentication-Results: gabe.freedesktop.org; dkim=pass (2048-bit key; unprotected) header.d=intel.com header.i=@intel.com header.b="m3MUrSYI"; dkim-atps=neutral Received: from mgamail.intel.com (mgamail.intel.com [198.175.65.10]) by gabe.freedesktop.org (Postfix) with ESMTPS id 7F678112A0A; Wed, 3 Apr 2024 11:23:06 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1712143387; x=1743679387; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=ZpNhdF8hP0Do7nHVqLGF8VqIUEPkpt0sLzH8f7HJXng=; b=m3MUrSYIrQu1O315Xe0OkP4xwia+xyoezu0h3sj0QGvGMNGBNmqYrJjB wm8sPiZiP417mP2qAQ3d7GIhy7YCNnViSK1/456rF7/tYy2CnQzxWX89a XOkf1bux3EtM+XXac19MxUeNveNFXpDUXoM4P/Y0bCuP9f9OgsIMzoJOm 5dF/z7ahenL6RPOzd0GConEXtWJbT4dcAgZE7rFUy59V6rzGwCRvKKpkE 4j/EN4ZtN9n3evHjb37dDf4zkH3xZvm+VndJJPj6L1DFl0QDadtL29HLJ ITkTRb+PSbZyYIuvwWEGtGQs7VJyFfmtsy91NLFUmT3bpA6vvBaSRas3W g==; X-CSE-ConnectionGUID: MvjzNikJQLyWUfEO8KdjBQ== X-CSE-MsgGUID: gNeSoQzeQVCndGm0vYP7QQ== X-IronPort-AV: E=McAfee;i="6600,9927,11032"; a="24824070" X-IronPort-AV: E=Sophos;i="6.07,177,1708416000"; d="scan'208";a="24824070" Received: from orviesa009.jf.intel.com ([10.64.159.149]) by orvoesa102.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 03 Apr 2024 04:23:07 -0700 X-CSE-ConnectionGUID: vzNaJ0wPSuS9dDU3Vc4OPw== X-CSE-MsgGUID: SlFY3NZzT7umLz7gVQ6lkg== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.07,177,1708416000"; d="scan'208";a="18358515" Received: from bvivekan-desk.iind.intel.com ([10.190.238.63]) by orviesa009-auth.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 03 Apr 2024 04:23:05 -0700 From: Balasubramani Vivekanandan To: intel-gfx@lists.freedesktop.org, intel-xe@lists.freedesktop.org Cc: Matt Roper , Lucas De Marchi , =?utf-8?q?Jos=C3=A9_Roberto_de_?= =?utf-8?q?Souza?= , Balasubramani Vivekanandan Subject: [PATCH v2 09/25] drm/i915/xe2hpd: Properly disable power in port A Date: Wed, 3 Apr 2024 16:52:37 +0530 Message-Id: <20240403112253.1432390-10-balasubramani.vivekanandan@intel.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20240403112253.1432390-1-balasubramani.vivekanandan@intel.com> References: <20240403112253.1432390-1-balasubramani.vivekanandan@intel.com> MIME-Version: 1.0 X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" From: José Roberto de Souza Xe2_HPD has a different value to power down port A. BSpec: 65450 CC: Matt Roper Signed-off-by: José Roberto de Souza Signed-off-by: Balasubramani Vivekanandan Reviewed-by: Matt Roper --- drivers/gpu/drm/i915/display/intel_cx0_phy.c | 17 ++++++++++++++--- 1 file changed, 14 insertions(+), 3 deletions(-) diff --git a/drivers/gpu/drm/i915/display/intel_cx0_phy.c b/drivers/gpu/drm/i915/display/intel_cx0_phy.c index 13a2e3db2812..caaae5d3758e 100644 --- a/drivers/gpu/drm/i915/display/intel_cx0_phy.c +++ b/drivers/gpu/drm/i915/display/intel_cx0_phy.c @@ -2921,17 +2921,28 @@ void intel_mtl_pll_enable(struct intel_encoder *encoder, intel_cx0pll_enable(encoder, crtc_state); } +static u8 cx0_power_control_disable_val(struct intel_encoder *encoder) +{ + struct drm_i915_private *i915 = to_i915(encoder->base.dev); + + if (intel_encoder_is_c10phy(encoder)) + return CX0_P2PG_STATE_DISABLE; + + if (IS_BATTLEMAGE(i915) && encoder->port == PORT_A) + return CX0_P2PG_STATE_DISABLE; + + return CX0_P4PG_STATE_DISABLE; +} + static void intel_cx0pll_disable(struct intel_encoder *encoder) { struct drm_i915_private *i915 = to_i915(encoder->base.dev); enum phy phy = intel_encoder_to_phy(encoder); - bool is_c10 = intel_encoder_is_c10phy(encoder); intel_wakeref_t wakeref = intel_cx0_phy_transaction_begin(encoder); /* 1. Change owned PHY lane power to Disable state. */ intel_cx0_powerdown_change_sequence(encoder, INTEL_CX0_BOTH_LANES, - is_c10 ? CX0_P2PG_STATE_DISABLE : - CX0_P4PG_STATE_DISABLE); + cx0_power_control_disable_val(encoder)); /* * 2. Follow the Display Voltage Frequency Switching Sequence Before From patchwork Wed Apr 3 11:22:38 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Vivekanandan, Balasubramani" X-Patchwork-Id: 13615974 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 81A6CCD128A for ; Wed, 3 Apr 2024 11:23:11 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id EA0C1112A18; Wed, 3 Apr 2024 11:23:10 +0000 (UTC) Authentication-Results: gabe.freedesktop.org; dkim=pass (2048-bit key; unprotected) header.d=intel.com header.i=@intel.com header.b="QHB1tvw+"; dkim-atps=neutral Received: from mgamail.intel.com (mgamail.intel.com [198.175.65.10]) by gabe.freedesktop.org (Postfix) with ESMTPS id A59A3112A10; Wed, 3 Apr 2024 11:23:08 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1712143389; x=1743679389; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=6R0fMystsVo5T+jMvskHwueBz3Hm2C+9jMDX3tPEKYc=; b=QHB1tvw+rrGVDqi+UK1/BVgNYVpTRYxaSutfujGHeK4+cVlSUF8ncnDb GdZojD23FzA3SEjuF3Hg1d/F13mj2SsHPUHYJczY+STWkeEQkeZr8LziM QVpep+664SEJGABWdYxZ0gREVeyHBbrFS1YYQHlcK81r39vLmlRS1YYjP UNbWf1P751Aj+ysyn7Hbg6x1lQzFFhjWNmNh5av6wtdjJ/AvO1pUdHzz/ NcxmanP91ltKt8mLPG4PY8st54zPdyijGeGqwNFDEgJC12PITJcpWKWXL VO0NoNMeVQqeGwlYo1i8mdVaSajDWJOfPl0demp4X2qfIW/P1W86UVlGg Q==; X-CSE-ConnectionGUID: Tdm8iQwzQTCY1tTmOZaXcg== X-CSE-MsgGUID: 3gpWRPHPRquhaAv5mUoCVQ== X-IronPort-AV: E=McAfee;i="6600,9927,11032"; a="24824085" X-IronPort-AV: E=Sophos;i="6.07,177,1708416000"; d="scan'208";a="24824085" Received: from orviesa009.jf.intel.com ([10.64.159.149]) by orvoesa102.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 03 Apr 2024 04:23:09 -0700 X-CSE-ConnectionGUID: sKjtL8gUTXaEguVT4gXfrg== X-CSE-MsgGUID: 69LLrOT3RE2YOKWgDTBOHg== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.07,177,1708416000"; d="scan'208";a="18358519" Received: from bvivekan-desk.iind.intel.com ([10.190.238.63]) by orviesa009-auth.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 03 Apr 2024 04:23:07 -0700 From: Balasubramani Vivekanandan To: intel-gfx@lists.freedesktop.org, intel-xe@lists.freedesktop.org Cc: Matt Roper , Lucas De Marchi , Balasubramani Vivekanandan , Clint Taylor , Gustavo Sousa Subject: [PATCH v2 10/25] drm/i915/xe2hpd: Add new C20 PLL register address Date: Wed, 3 Apr 2024 16:52:38 +0530 Message-Id: <20240403112253.1432390-11-balasubramani.vivekanandan@intel.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20240403112253.1432390-1-balasubramani.vivekanandan@intel.com> References: <20240403112253.1432390-1-balasubramani.vivekanandan@intel.com> MIME-Version: 1.0 X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" Xe2_HPD has different address for C20 PLL registers. Enable the support to use the right PLL register address based on display version. Note that Xe2_LPD uses the same C20 SRAM offsets used by Xe_LPDP (i.e. MTL's display). According to the BSpec, currently, only Xe2_HPD has different offsets, so make sure it is the only display using them in the driver. Bspec: 67610 Cc: Clint Taylor Cc: Gustavo Sousa Signed-off-by: Balasubramani Vivekanandan Signed-off-by: Lucas De Marchi --- drivers/gpu/drm/i915/display/intel_cx0_phy.c | 27 +++++++++++++++++-- .../gpu/drm/i915/display/intel_cx0_phy_regs.h | 9 +++++++ 2 files changed, 34 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/i915/display/intel_cx0_phy.c b/drivers/gpu/drm/i915/display/intel_cx0_phy.c index caaae5d3758e..6e4647859fc6 100644 --- a/drivers/gpu/drm/i915/display/intel_cx0_phy.c +++ b/drivers/gpu/drm/i915/display/intel_cx0_phy.c @@ -770,6 +770,17 @@ static struct intel_c20pll_reg mtl_c20_reg = { .mpllb_b = MTL_C20_B_MPLLB_CFG_ADDR }; +static struct intel_c20pll_reg xe2hpd_c20_reg = { + .tx_cnt_a = XE2HPD_C20_A_TX_CNTX_CFG_ADDR, + .tx_cnt_b = XE2HPD_C20_B_TX_CNTX_CFG_ADDR, + .cmn_cnt_a = XE2HPD_C20_A_CMN_CNTX_CFG_ADDR, + .cmn_cnt_b = XE2HPD_C20_B_CMN_CNTX_CFG_ADDR, + .mplla_a = XE2HPD_C20_A_MPLLA_CFG_ADDR, + .mplla_b = XE2HPD_C20_B_MPLLA_CFG_ADDR, + .mpllb_a = XE2HPD_C20_A_MPLLB_CFG_ADDR, + .mpllb_b = XE2HPD_C20_B_MPLLB_CFG_ADDR, +}; + /* C20 basic DP 1.4 tables */ static const struct intel_c20pll_state mtl_c20_dp_rbr = { .clock = 162000, @@ -2166,19 +2177,29 @@ static int intel_c20pll_calc_port_clock(struct intel_encoder *encoder, return vco << tx_rate_mult >> tx_clk_div >> tx_rate; } +static struct intel_c20pll_reg *intel_c20_get_pll_reg(struct drm_i915_private *i915) +{ + if (DISPLAY_VER_FULL(i915) == IP_VER(14, 1)) + return &xe2hpd_c20_reg; + else + return &mtl_c20_reg; +} + static void intel_c20pll_readout_hw_state(struct intel_encoder *encoder, struct intel_c20pll_state *pll_state) { bool cntx; intel_wakeref_t wakeref; int i; - struct intel_c20pll_reg *pll_reg = &mtl_c20_reg; + struct intel_c20pll_reg *pll_reg; wakeref = intel_cx0_phy_transaction_begin(encoder); /* 1. Read current context selection */ cntx = intel_cx0_read(encoder, INTEL_CX0_LANE0, PHY_C20_VDR_CUSTOM_SERDES_RATE) & PHY_C20_CONTEXT_TOGGLE; + pll_reg = intel_c20_get_pll_reg(to_i915(encoder->base.dev)); + /* Read Tx configuration */ for (i = 0; i < ARRAY_SIZE(pll_state->tx); i++) { if (cntx) @@ -2353,7 +2374,7 @@ static void intel_c20_pll_program(struct drm_i915_private *i915, u32 clock = crtc_state->port_clock; bool cntx; int i; - const struct intel_c20pll_reg *pll_reg = &mtl_c20_reg; + const struct intel_c20pll_reg *pll_reg; if (intel_crtc_has_dp_encoder(crtc_state)) dp = true; @@ -2372,6 +2393,8 @@ static void intel_c20_pll_program(struct drm_i915_private *i915, usleep_range(4000, 4100); } + pll_reg = intel_c20_get_pll_reg(i915); + /* 3. Write SRAM configuration context. If A in use, write configuration to B context */ /* 3.1 Tx configuration */ for (i = 0; i < ARRAY_SIZE(pll_state->tx); i++) { diff --git a/drivers/gpu/drm/i915/display/intel_cx0_phy_regs.h b/drivers/gpu/drm/i915/display/intel_cx0_phy_regs.h index 882b98dc347b..8e5fd605b99e 100644 --- a/drivers/gpu/drm/i915/display/intel_cx0_phy_regs.h +++ b/drivers/gpu/drm/i915/display/intel_cx0_phy_regs.h @@ -292,6 +292,15 @@ struct intel_c20pll_reg { #define MTL_C20_A_MPLLB_CFG_ADDR 0xCB5A #define MTL_C20_B_MPLLB_CFG_ADDR 0xCB4E +#define XE2HPD_C20_A_TX_CNTX_CFG_ADDR 0xCF5E +#define XE2HPD_C20_B_TX_CNTX_CFG_ADDR 0xCF5A +#define XE2HPD_C20_A_CMN_CNTX_CFG_ADDR 0xCE8E +#define XE2HPD_C20_B_CMN_CNTX_CFG_ADDR 0xCE89 +#define XE2HPD_C20_A_MPLLA_CFG_ADDR 0xCE58 +#define XE2HPD_C20_B_MPLLA_CFG_ADDR 0xCE4D +#define XE2HPD_C20_A_MPLLB_CFG_ADDR 0xCCC2 +#define XE2HPD_C20_B_MPLLB_CFG_ADDR 0xCCB6 + /* C20 Phy VSwing Masks */ #define C20_PHY_VSWING_PREEMPH_MASK REG_GENMASK8(5, 0) #define C20_PHY_VSWING_PREEMPH(val) REG_FIELD_PREP8(C20_PHY_VSWING_PREEMPH_MASK, val) From patchwork Wed Apr 3 11:22:39 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Vivekanandan, Balasubramani" X-Patchwork-Id: 13615975 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id AD38BCD128A for ; Wed, 3 Apr 2024 11:23:14 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 3B70E112A19; Wed, 3 Apr 2024 11:23:14 +0000 (UTC) Authentication-Results: gabe.freedesktop.org; dkim=pass (2048-bit key; unprotected) header.d=intel.com header.i=@intel.com header.b="iTAZu5xU"; dkim-atps=neutral Received: from mgamail.intel.com (mgamail.intel.com [198.175.65.10]) by gabe.freedesktop.org (Postfix) with ESMTPS id E991C112A10; Wed, 3 Apr 2024 11:23:10 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1712143391; x=1743679391; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=khyiAZwhH0HYIoe/8reGkGGOU5prsY6sqz1YhAgEQ3A=; b=iTAZu5xUZcURnde+nRKuMEh0TJolWtwkpiROVTZ0zr8X1C92zv+liIpn yFrJfut2+cS4iSCDC0gAhR53PuW1ml6jQHm6GazfJX78gtAH+hFrfdfjY RF9WtXR4n0FeQYaQtu86q0sMpvV93rKQWHq47sFHaKZCPulPxdZG+ZKny EJKeaFWEv7GAOLjPL+d3S9+KvfKXGpKuRaNze6nB7eaJlOlAS1csYqRgl DuJNmdXgQSO1OH/FPrSLcWJHnxhcbweLxo1y4mS/bHgZYl0AbxBxKGu53 pQRi5eKdeXXAqSzDLNSh1osuago8CmuFbCVUf39VcsWULXEGUDsSRVfkx w==; X-CSE-ConnectionGUID: tXdAtCIKT3OFjWSqpOCwtg== X-CSE-MsgGUID: 1dXHgP/MTYq6yIw9FIqKKQ== X-IronPort-AV: E=McAfee;i="6600,9927,11032"; a="24824089" X-IronPort-AV: E=Sophos;i="6.07,177,1708416000"; d="scan'208";a="24824089" Received: from orviesa009.jf.intel.com ([10.64.159.149]) by orvoesa102.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 03 Apr 2024 04:23:11 -0700 X-CSE-ConnectionGUID: V2GyLANjR5CqkXvzzckl5w== X-CSE-MsgGUID: lqHNZT3JTya5vS2722JHHA== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.07,177,1708416000"; d="scan'208";a="18358522" Received: from bvivekan-desk.iind.intel.com ([10.190.238.63]) by orviesa009-auth.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 03 Apr 2024 04:23:09 -0700 From: Balasubramani Vivekanandan To: intel-gfx@lists.freedesktop.org, intel-xe@lists.freedesktop.org Cc: Matt Roper , Lucas De Marchi , Balasubramani Vivekanandan , Clint Taylor Subject: [PATCH v2 11/25] drm/i915/xe2hpd: Add support for eDP PLL configuration Date: Wed, 3 Apr 2024 16:52:39 +0530 Message-Id: <20240403112253.1432390-12-balasubramani.vivekanandan@intel.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20240403112253.1432390-1-balasubramani.vivekanandan@intel.com> References: <20240403112253.1432390-1-balasubramani.vivekanandan@intel.com> MIME-Version: 1.0 X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" Tables for eDP PHY PLL configuration for different link rates added for Xe2_HPD. Previous platforms were using C10 PHY for eDP port whereas Xe2_HPD has C20 PHY. Bpsec: 64568 CC: Clint Taylor Signed-off-by: Balasubramani Vivekanandan Reviewed-by: Matt Roper --- drivers/gpu/drm/i915/display/intel_cx0_phy.c | 147 ++++++++++++++++++- 1 file changed, 146 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/i915/display/intel_cx0_phy.c b/drivers/gpu/drm/i915/display/intel_cx0_phy.c index 6e4647859fc6..d948035f07ad 100644 --- a/drivers/gpu/drm/i915/display/intel_cx0_phy.c +++ b/drivers/gpu/drm/i915/display/intel_cx0_phy.c @@ -967,6 +967,148 @@ static const struct intel_c20pll_state * const mtl_c20_dp_tables[] = { NULL, }; +/* + * eDP link rates with 38.4 MHz reference clock. + */ + +static const struct intel_c20pll_state xe2hpd_c20_edp_r216 = { + .clock = 216000, + .tx = { 0xbe88, + 0x4800, + 0x0000, + }, + .cmn = { 0x0500, + 0x0005, + 0x0000, + 0x0000, + }, + .mpllb = { 0x50e1, + 0x2120, + 0x8e18, + 0xbfc1, + 0x9000, + 0x78f6, + 0x0000, + 0x0000, + 0x0000, + 0x0000, + 0x0000, + }, +}; + +static const struct intel_c20pll_state xe2hpd_c20_edp_r243 = { + .clock = 243000, + .tx = { 0xbe88, + 0x4800, + 0x0000, + }, + .cmn = { 0x0500, + 0x0005, + 0x0000, + 0x0000, + }, + .mpllb = { 0x50fd, + 0x2120, + 0x8f18, + 0xbfc1, + 0xa200, + 0x8814, + 0x2000, + 0x0001, + 0x1000, + 0x0000, + 0x0000, + }, +}; + +static const struct intel_c20pll_state xe2hpd_c20_edp_r324 = { + .clock = 324000, + .tx = { 0xbe88, + 0x4800, + 0x0000, + }, + .cmn = { 0x0500, + 0x0005, + 0x0000, + 0x0000, + }, + .mpllb = { 0x30a8, + 0x2110, + 0xcd9a, + 0xbfc1, + 0x6c00, + 0x5ab8, + 0x2000, + 0x0001, + 0x6000, + 0x0000, + 0x0000, + }, +}; + +static const struct intel_c20pll_state xe2hpd_c20_edp_r432 = { + .clock = 432000, + .tx = { 0xbe88, + 0x4800, + 0x0000, + }, + .cmn = { 0x0500, + 0x0005, + 0x0000, + 0x0000, + }, + .mpllb = { 0x30e1, + 0x2110, + 0x8e18, + 0xbfc1, + 0x9000, + 0x78f6, + 0x0000, + 0x0000, + 0x0000, + 0x0000, + 0x0000, + }, +}; + +static const struct intel_c20pll_state xe2hpd_c20_edp_r675 = { + .clock = 675000, + .tx = { 0xbe88, + 0x4800, + 0x0000, + }, + .cmn = { 0x0500, + 0x0005, + 0x0000, + 0x0000, + }, + .mpllb = { 0x10af, + 0x2108, + 0xce1a, + 0xbfc1, + 0x7080, + 0x5e80, + 0x2000, + 0x0001, + 0x6400, + 0x0000, + 0x0000, + }, +}; + +static const struct intel_c20pll_state * const xe2hpd_c20_edp_tables[] = { + &mtl_c20_dp_rbr, + &xe2hpd_c20_edp_r216, + &xe2hpd_c20_edp_r243, + &mtl_c20_dp_hbr1, + &xe2hpd_c20_edp_r324, + &xe2hpd_c20_edp_r432, + &mtl_c20_dp_hbr2, + &xe2hpd_c20_edp_r675, + &mtl_c20_dp_hbr3, + NULL, +}; + /* * HDMI link rates with 38.4 MHz reference clock. */ @@ -2084,7 +2226,10 @@ intel_c20_pll_tables_get(struct intel_crtc_state *crtc_state, struct intel_encoder *encoder) { if (intel_crtc_has_dp_encoder(crtc_state)) - return mtl_c20_dp_tables; + if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_EDP)) + return xe2hpd_c20_edp_tables; + else + return mtl_c20_dp_tables; else if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI)) return mtl_c20_hdmi_tables; From patchwork Wed Apr 3 11:22:40 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Vivekanandan, Balasubramani" X-Patchwork-Id: 13615976 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 41676CD1294 for ; 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X-CSE-ConnectionGUID: 9P1vbDnCRAqUJSb9QAdGmg== X-CSE-MsgGUID: S4eAvM3WQy+BAzZmI7w4TA== X-IronPort-AV: E=McAfee;i="6600,9927,11032"; a="24824096" X-IronPort-AV: E=Sophos;i="6.07,177,1708416000"; d="scan'208";a="24824096" Received: from orviesa009.jf.intel.com ([10.64.159.149]) by orvoesa102.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 03 Apr 2024 04:23:14 -0700 X-CSE-ConnectionGUID: u75o4f9cShS1JyjQBioGTg== X-CSE-MsgGUID: DEXDmJVjS0Wv1RsO9/y4hg== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.07,177,1708416000"; d="scan'208";a="18358525" Received: from bvivekan-desk.iind.intel.com ([10.190.238.63]) by orviesa009-auth.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 03 Apr 2024 04:23:12 -0700 From: Balasubramani Vivekanandan To: intel-gfx@lists.freedesktop.org, intel-xe@lists.freedesktop.org Cc: Matt Roper , Lucas De Marchi , Ravi Kumar Vodapalli , Balasubramani Vivekanandan Subject: [PATCH v2 12/25] drm/i915/xe2hpd: update pll values in sync with Bspec Date: Wed, 3 Apr 2024 16:52:40 +0530 Message-Id: <20240403112253.1432390-13-balasubramani.vivekanandan@intel.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20240403112253.1432390-1-balasubramani.vivekanandan@intel.com> References: <20240403112253.1432390-1-balasubramani.vivekanandan@intel.com> MIME-Version: 1.0 X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" From: Ravi Kumar Vodapalli DP/eDP and HDMI pll values are updated for Xe2_HPD platform Bspec: 74165 Signed-off-by: Ravi Kumar Vodapalli Signed-off-by: Balasubramani Vivekanandan Reviewed-by: Matt Roper --- drivers/gpu/drm/i915/display/intel_cx0_phy.c | 47 +++++++++++++++++++- 1 file changed, 45 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/i915/display/intel_cx0_phy.c b/drivers/gpu/drm/i915/display/intel_cx0_phy.c index d948035f07ad..20035be015c3 100644 --- a/drivers/gpu/drm/i915/display/intel_cx0_phy.c +++ b/drivers/gpu/drm/i915/display/intel_cx0_phy.c @@ -1109,6 +1109,42 @@ static const struct intel_c20pll_state * const xe2hpd_c20_edp_tables[] = { NULL, }; +static const struct intel_c20pll_state xe2hpd_c20_dp_uhbr13_5 = { + .clock = 1350000, /* 13.5 Gbps */ + .tx = { 0xbea0, /* tx cfg0 */ + 0x4800, /* tx cfg1 */ + 0x0000, /* tx cfg2 */ + }, + .cmn = {0x0500, /* cmn cfg0*/ + 0x0005, /* cmn cfg1 */ + 0x0000, /* cmn cfg2 */ + 0x0000, /* cmn cfg3 */ + }, + .mpllb = { 0x015f, /* mpllb cfg0 */ + 0x2205, /* mpllb cfg1 */ + 0x1b17, /* mpllb cfg2 */ + 0xffc1, /* mpllb cfg3 */ + 0xbd00, /* mpllb cfg4 */ + 0x9ec3, /* mpllb cfg5 */ + 0x2000, /* mpllb cfg6 */ + 0x0001, /* mpllb cfg7 */ + 0x4800, /* mpllb cfg8 */ + 0x0000, /* mpllb cfg9 */ + 0x0000, /* mpllb cfg10 */ + }, +}; + +static const struct intel_c20pll_state * const xe2hpd_c20_dp_tables[] = { + &mtl_c20_dp_rbr, + &mtl_c20_dp_hbr1, + &mtl_c20_dp_hbr2, + &mtl_c20_dp_hbr3, + &mtl_c20_dp_uhbr10, + &xe2hpd_c20_dp_uhbr13_5, + &mtl_c20_dp_uhbr20, + NULL, +}; + /* * HDMI link rates with 38.4 MHz reference clock. */ @@ -2225,13 +2261,20 @@ static const struct intel_c20pll_state * const * intel_c20_pll_tables_get(struct intel_crtc_state *crtc_state, struct intel_encoder *encoder) { - if (intel_crtc_has_dp_encoder(crtc_state)) + struct drm_i915_private *i915 = to_i915(encoder->base.dev); + + if (intel_crtc_has_dp_encoder(crtc_state)) { if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_EDP)) return xe2hpd_c20_edp_tables; + + if (DISPLAY_VER_FULL(i915) == IP_VER(14, 1)) + return xe2hpd_c20_dp_tables; else return mtl_c20_dp_tables; - else if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI)) + + } else if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI)) { return mtl_c20_hdmi_tables; + } MISSING_CASE(encoder->type); return NULL; From patchwork Wed Apr 3 11:22:41 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Vivekanandan, Balasubramani" X-Patchwork-Id: 13615977 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 5905ECD128A for ; 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It is similar to xelpd, but with no PORT_B. Bspec: 67066 Signed-off-by: Lucas De Marchi Signed-off-by: Balasubramani Vivekanandan --- .../gpu/drm/i915/display/intel_display_device.c | 16 ++++++++++++++++ 1 file changed, 16 insertions(+) diff --git a/drivers/gpu/drm/i915/display/intel_display_device.c b/drivers/gpu/drm/i915/display/intel_display_device.c index b8903bd0e82a..0a26012041e9 100644 --- a/drivers/gpu/drm/i915/display/intel_display_device.c +++ b/drivers/gpu/drm/i915/display/intel_display_device.c @@ -771,6 +771,21 @@ static const struct intel_display_device_info xe2_lpd_display = { BIT(INTEL_FBC_C) | BIT(INTEL_FBC_D), }; +static const struct intel_display_device_info xe2_hpd_display = { + XE_LPD_FEATURES, + .has_cdclk_crawl = 1, + .has_cdclk_squash = 1, + + .__runtime_defaults.ip.ver = 14, + .__runtime_defaults.ip.rel = 1, + .__runtime_defaults.fbc_mask = BIT(INTEL_FBC_A) | BIT(INTEL_FBC_B), + .__runtime_defaults.cpu_transcoder_mask = + BIT(TRANSCODER_A) | BIT(TRANSCODER_B) | + BIT(TRANSCODER_C) | BIT(TRANSCODER_D), + .__runtime_defaults.port_mask = BIT(PORT_A) | + BIT(PORT_TC1) | BIT(PORT_TC2) | BIT(PORT_TC3) | BIT(PORT_TC4), +}; + __diag_pop(); /* @@ -852,6 +867,7 @@ static const struct { const struct intel_display_device_info *display; } gmdid_display_map[] = { { 14, 0, &xe_lpdp_display }, + { 14, 1, &xe2_hpd_display }, { 20, 0, &xe2_lpd_display }, }; From patchwork Wed Apr 3 11:22:42 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Vivekanandan, Balasubramani" X-Patchwork-Id: 13615978 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id B16FBCD1288 for ; Wed, 3 Apr 2024 11:23:19 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 37A2F112A15; Wed, 3 Apr 2024 11:23:19 +0000 (UTC) Authentication-Results: gabe.freedesktop.org; dkim=pass (2048-bit key; unprotected) header.d=intel.com header.i=@intel.com header.b="EV/FumAo"; dkim-atps=neutral Received: from mgamail.intel.com (mgamail.intel.com [198.175.65.10]) by gabe.freedesktop.org (Postfix) with ESMTPS id BC40A112A0D; Wed, 3 Apr 2024 11:23:17 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1712143398; x=1743679398; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=95rIAOk23JgjKHgGzwFjF7V4BcAHOjBvOInSOjzO5G0=; b=EV/FumAo0djsd94lwvSsYwfUqzNIvjbSOPjUlumEw5svoPVKeMfFXDIx acB87+qgW7xV6dzBU3Y6bjiaI6gfyuTi0/rmbPEWfziPNrLpXOoRTa0FY E2JQQszlLATtl5tbyc21qX/mQrWmEUmt+PItRQA97gS3rFCdSq4bcMQic hO4iQYMbImG4DIEeqnCzlETpjCYRv4gqwId/taY2CRXumVy2CVUCFW4i0 6Z/binFPiQ0ZFGFD2MIzJLnwes1VFddEimu+zc7RQK+ThfAkteT6pvvuX 1F6PEVBl46t1pKxJub+/FelUee9pmxBhk4HgsDJs6DkhraeqoNXMN0Sr6 A==; X-CSE-ConnectionGUID: 0MN1QaGXQ7STfiUfEpM1OA== X-CSE-MsgGUID: A1vBZ7ntRn27PkjO8fwhnA== X-IronPort-AV: E=McAfee;i="6600,9927,11032"; a="24824115" X-IronPort-AV: E=Sophos;i="6.07,177,1708416000"; d="scan'208";a="24824115" Received: from orviesa009.jf.intel.com ([10.64.159.149]) by orvoesa102.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 03 Apr 2024 04:23:18 -0700 X-CSE-ConnectionGUID: 07X8p49yT6a5is+19UPAgA== X-CSE-MsgGUID: 9+814vdSTtyZQl9gCi0wpg== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.07,177,1708416000"; d="scan'208";a="18358531" Received: from bvivekan-desk.iind.intel.com ([10.190.238.63]) by orviesa009-auth.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 03 Apr 2024 04:23:16 -0700 From: Balasubramani Vivekanandan To: intel-gfx@lists.freedesktop.org, intel-xe@lists.freedesktop.org Cc: Matt Roper , Lucas De Marchi , Anusha Srivatsa , Balasubramani Vivekanandan Subject: [PATCH v2 14/25] drm/i915/xe2hpd: Add missing chicken bit register programming Date: Wed, 3 Apr 2024 16:52:42 +0530 Message-Id: <20240403112253.1432390-15-balasubramani.vivekanandan@intel.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20240403112253.1432390-1-balasubramani.vivekanandan@intel.com> References: <20240403112253.1432390-1-balasubramani.vivekanandan@intel.com> MIME-Version: 1.0 X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" From: Anusha Srivatsa Add step 9 from initialize display sequence. Bpsec: 49189 Signed-off-by: Anusha Srivatsa Signed-off-by: Balasubramani Vivekanandan --- drivers/gpu/drm/i915/display/intel_display_power.c | 4 ++++ drivers/gpu/drm/i915/i915_reg.h | 1 + 2 files changed, 5 insertions(+) diff --git a/drivers/gpu/drm/i915/display/intel_display_power.c b/drivers/gpu/drm/i915/display/intel_display_power.c index 6fd4fa52253a..bf9685acf75a 100644 --- a/drivers/gpu/drm/i915/display/intel_display_power.c +++ b/drivers/gpu/drm/i915/display/intel_display_power.c @@ -1694,6 +1694,10 @@ static void icl_display_core_init(struct drm_i915_private *dev_priv, if (IS_DG2(dev_priv)) intel_snps_phy_wait_for_calibration(dev_priv); + /* 9. XE2_HPD: Program CHICKEN_MISC_2 before any cursor or planes are enabled */ + if (DISPLAY_VER_FULL(dev_priv) == IP_VER(14, 1)) + intel_de_rmw(dev_priv, CHICKEN_MISC_2, BMG_DARB_HALF_BLK_END_BURST, 1); + if (resume) intel_dmc_load_program(dev_priv); diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h index 58f3e4bfe254..875d76fb8cd0 100644 --- a/drivers/gpu/drm/i915/i915_reg.h +++ b/drivers/gpu/drm/i915/i915_reg.h @@ -4548,6 +4548,7 @@ #define CHICKEN_MISC_2 _MMIO(0x42084) #define CHICKEN_MISC_DISABLE_DPT REG_BIT(30) /* adl,dg2 */ +#define BMG_DARB_HALF_BLK_END_BURST REG_BIT(27) #define KBL_ARB_FILL_SPARE_14 REG_BIT(14) #define KBL_ARB_FILL_SPARE_13 REG_BIT(13) #define GLK_CL2_PWR_DOWN REG_BIT(12) From patchwork Wed Apr 3 11:22:43 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Vivekanandan, Balasubramani" X-Patchwork-Id: 13615979 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 470AACD1294 for ; Wed, 3 Apr 2024 11:23:22 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 5A6EE112A21; Wed, 3 Apr 2024 11:23:21 +0000 (UTC) Authentication-Results: gabe.freedesktop.org; dkim=pass (2048-bit key; unprotected) header.d=intel.com header.i=@intel.com header.b="YAt5KEvD"; dkim-atps=neutral Received: from mgamail.intel.com (mgamail.intel.com [198.175.65.10]) by gabe.freedesktop.org (Postfix) with ESMTPS id 21C1C112A1C; Wed, 3 Apr 2024 11:23:20 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1712143401; x=1743679401; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=pxE8liYJG+J5mArgQujDXsDDoZ4dIiDF9zL6jv08cCM=; b=YAt5KEvDqBg74oD0tT/IPFMUr8ZT0RE/oEW/iDWMGYx8IPgQs16oVRTN k8Vaf2xnCg25nZBZmwtA4n5Hc+WFoLqQBAoe8hRW6qbWNPb3P7dEhzq5O 6YhnyhmXjPFdANYPfVnpdeUtYp32DkP75NV8lw8rTnUjuPwU+syPrBjhW swZF5ts8f6bmHTYxXnIN4F1AvN5rlWvG7bE0ZmL2MuKA9ubPQTVqDk+rI aZUKJTnZfdemIt11QDU8kXbVnfA309GQre/YgIKKRZszhqGGLShOpt8Ja yl5AgXWkmtdV2hp65PIA151idTBowz0sGG2ujrl+l6TcmvrV7Q1Wg0bsG Q==; X-CSE-ConnectionGUID: PZBncZXFRlyn5Bxud4SwWg== X-CSE-MsgGUID: O/sa1+DGTMCrzFs9t//ZrA== X-IronPort-AV: E=McAfee;i="6600,9927,11032"; a="24824124" X-IronPort-AV: E=Sophos;i="6.07,177,1708416000"; d="scan'208";a="24824124" Received: from orviesa009.jf.intel.com ([10.64.159.149]) by orvoesa102.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 03 Apr 2024 04:23:20 -0700 X-CSE-ConnectionGUID: tVn0nhdcSha+t3gb7qnCqw== X-CSE-MsgGUID: Prpo5kh2QiSOn10ciptQRw== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.07,177,1708416000"; d="scan'208";a="18358534" Received: from bvivekan-desk.iind.intel.com ([10.190.238.63]) by orviesa009-auth.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 03 Apr 2024 04:23:18 -0700 From: Balasubramani Vivekanandan To: intel-gfx@lists.freedesktop.org, intel-xe@lists.freedesktop.org Cc: Matt Roper , Lucas De Marchi , Clint Taylor , Balasubramani Vivekanandan Subject: [PATCH v2 15/25] drm/xe/display: Lane reversal requires writes to both context lanes Date: Wed, 3 Apr 2024 16:52:43 +0530 Message-Id: <20240403112253.1432390-16-balasubramani.vivekanandan@intel.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20240403112253.1432390-1-balasubramani.vivekanandan@intel.com> References: <20240403112253.1432390-1-balasubramani.vivekanandan@intel.com> MIME-Version: 1.0 X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" From: Clint Taylor Write both CX0 Lanes for Context Toggle for all except TC pin assignment D. BSPEC: 64539 Signed-off-by: Clint Taylor Signed-off-by: Balasubramani Vivekanandan --- drivers/gpu/drm/i915/display/intel_cx0_phy.c | 10 +++++----- 1 file changed, 5 insertions(+), 5 deletions(-) diff --git a/drivers/gpu/drm/i915/display/intel_cx0_phy.c b/drivers/gpu/drm/i915/display/intel_cx0_phy.c index 20035be015c3..cbcb6651dfed 100644 --- a/drivers/gpu/drm/i915/display/intel_cx0_phy.c +++ b/drivers/gpu/drm/i915/display/intel_cx0_phy.c @@ -2558,7 +2558,7 @@ static void intel_c20_pll_program(struct drm_i915_private *i915, { const struct intel_c20pll_state *pll_state = &crtc_state->cx0pll_state.c20; bool dp = false; - int lane = crtc_state->lane_count > 2 ? INTEL_CX0_BOTH_LANES : INTEL_CX0_LANE0; + u8 owned_lane_mask = intel_cx0_get_owned_lane_mask(encoder); u32 clock = crtc_state->port_clock; bool cntx; int i; @@ -2634,19 +2634,19 @@ static void intel_c20_pll_program(struct drm_i915_private *i915, } /* 4. Program custom width to match the link protocol */ - intel_cx0_rmw(encoder, lane, PHY_C20_VDR_CUSTOM_WIDTH, + intel_cx0_rmw(encoder, owned_lane_mask, PHY_C20_VDR_CUSTOM_WIDTH, PHY_C20_CUSTOM_WIDTH_MASK, PHY_C20_CUSTOM_WIDTH(intel_get_c20_custom_width(clock, dp)), MB_WRITE_COMMITTED); /* 5. For DP or 6. For HDMI */ if (dp) { - intel_cx0_rmw(encoder, lane, PHY_C20_VDR_CUSTOM_SERDES_RATE, + intel_cx0_rmw(encoder, owned_lane_mask, PHY_C20_VDR_CUSTOM_SERDES_RATE, BIT(6) | PHY_C20_CUSTOM_SERDES_MASK, BIT(6) | PHY_C20_CUSTOM_SERDES(intel_c20_get_dp_rate(clock)), MB_WRITE_COMMITTED); } else { - intel_cx0_rmw(encoder, lane, PHY_C20_VDR_CUSTOM_SERDES_RATE, + intel_cx0_rmw(encoder, owned_lane_mask, PHY_C20_VDR_CUSTOM_SERDES_RATE, BIT(7) | PHY_C20_CUSTOM_SERDES_MASK, is_hdmi_frl(clock) ? BIT(7) : 0, MB_WRITE_COMMITTED); @@ -2660,7 +2660,7 @@ static void intel_c20_pll_program(struct drm_i915_private *i915, * 7. Write Vendor specific registers to toggle context setting to load * the updated programming toggle context bit */ - intel_cx0_rmw(encoder, lane, PHY_C20_VDR_CUSTOM_SERDES_RATE, + intel_cx0_rmw(encoder, owned_lane_mask, PHY_C20_VDR_CUSTOM_SERDES_RATE, BIT(0), cntx ? 0 : 1, MB_WRITE_COMMITTED); } From patchwork Wed Apr 3 11:22:44 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Vivekanandan, Balasubramani" X-Patchwork-Id: 13615980 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id F04D1CD128A for ; Wed, 3 Apr 2024 11:23:23 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 3B8BA112A1C; Wed, 3 Apr 2024 11:23:23 +0000 (UTC) Authentication-Results: gabe.freedesktop.org; dkim=pass (2048-bit key; unprotected) header.d=intel.com header.i=@intel.com header.b="jcfmaJYh"; dkim-atps=neutral Received: from mgamail.intel.com (mgamail.intel.com [198.175.65.10]) by gabe.freedesktop.org (Postfix) with ESMTPS id D5083112A26; Wed, 3 Apr 2024 11:23:21 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1712143402; x=1743679402; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=VRdiBD2h4YYNRaplzIAtm23xXiVy17j8IOALa3XHnlw=; b=jcfmaJYhYOZTDtLz5TP0fQzncJWNac3uLo+aAfSimAfPpdIA4YiTRZxO qnbSyl9HbhvkHSzXvcOtXrywUactq+pU67wBDbsdo82Bc8u25krLnaF/8 NXnCzckf1Y2ZtESPqjXntu6l544JlRO9dmKWEtiEfXlzw44B8SRO0ohrJ Ynb+BHGECpq/PgEo25qMPlGaLTkITKsZrYBlcTVzlPdjOQwBoA1LlncKG zsGyLAiabCC6xvljxRSb6Z3EwG70mqCVEFO/snVakwcUoM8mJUlNYSBO7 O7RpkTkM+MOBJx5B2JLqY+zMjYr5eGLBVCTvhAtSCS7xb9/In8pA4/egf g==; X-CSE-ConnectionGUID: SOnw4O5ZTIOHbmLKFZM4Hw== X-CSE-MsgGUID: nrv8jP+2Sci420e/3yS0bQ== X-IronPort-AV: E=McAfee;i="6600,9927,11032"; a="24824127" X-IronPort-AV: E=Sophos;i="6.07,177,1708416000"; d="scan'208";a="24824127" Received: from orviesa009.jf.intel.com ([10.64.159.149]) by orvoesa102.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 03 Apr 2024 04:23:22 -0700 X-CSE-ConnectionGUID: LcSkWG3URo6qOqMz6CS8XA== X-CSE-MsgGUID: hxEiHeAmRUOPiTi0i5WkDA== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.07,177,1708416000"; d="scan'208";a="18358537" Received: from bvivekan-desk.iind.intel.com ([10.190.238.63]) by orviesa009-auth.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 03 Apr 2024 04:23:21 -0700 From: Balasubramani Vivekanandan To: intel-gfx@lists.freedesktop.org, intel-xe@lists.freedesktop.org Cc: Matt Roper , Lucas De Marchi , Balasubramani Vivekanandan Subject: [PATCH v2 16/25] drm/xe/xe2hpd: Define a new DRAM type INTEL_DRAM_GDDR Date: Wed, 3 Apr 2024 16:52:44 +0530 Message-Id: <20240403112253.1432390-17-balasubramani.vivekanandan@intel.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20240403112253.1432390-1-balasubramani.vivekanandan@intel.com> References: <20240403112253.1432390-1-balasubramani.vivekanandan@intel.com> MIME-Version: 1.0 X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" Defined a new DRAM type to be used in the following patches. The following patch first makes use of this new type in the i915 display. So without this define, build would fail when the shared display code is built for Xe. Signed-off-by: Balasubramani Vivekanandan --- drivers/gpu/drm/xe/xe_device_types.h | 1 + 1 file changed, 1 insertion(+) diff --git a/drivers/gpu/drm/xe/xe_device_types.h b/drivers/gpu/drm/xe/xe_device_types.h index 1df3dcc17d75..e7aa2dd3df8d 100644 --- a/drivers/gpu/drm/xe/xe_device_types.h +++ b/drivers/gpu/drm/xe/xe_device_types.h @@ -480,6 +480,7 @@ struct xe_device { INTEL_DRAM_LPDDR4, INTEL_DRAM_DDR5, INTEL_DRAM_LPDDR5, + INTEL_DRAM_GDDR, } type; u8 num_qgv_points; u8 num_psf_gv_points; From patchwork Wed Apr 3 11:22:45 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Vivekanandan, Balasubramani" X-Patchwork-Id: 13615981 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id C979BCD1288 for ; Wed, 3 Apr 2024 11:23:25 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 13CB1112A14; Wed, 3 Apr 2024 11:23:25 +0000 (UTC) Authentication-Results: gabe.freedesktop.org; dkim=pass (2048-bit key; unprotected) header.d=intel.com header.i=@intel.com header.b="DXQdiXwC"; dkim-atps=neutral Received: from mgamail.intel.com (mgamail.intel.com [198.175.65.10]) by gabe.freedesktop.org (Postfix) with ESMTPS id 1B656112A22; Wed, 3 Apr 2024 11:23:24 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1712143405; x=1743679405; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=FINeNM6a8wAVXpANxBlkkzG2OA91ebVvYgbdjlA9008=; b=DXQdiXwCqkB9e65LLmmt+nEE+0EuhbUtIu18E0UYFU4RbCEbLYM7qxuF P2IYMFolJJNZ301PInoHa64S+JNMxzWl90uxL2sjydILDkId03957pK+q fykTdapwEFdoLkiy6Fwyc2nqAq/zbXOEH+hFkRTCXuoS8heFKM9nC4Xbm M0rkktX8maFf/eB+TcwKMn4y+kg1icY3aUIGaoobaUunY3cu/eXimihji zN35lLpoenywdrwmP+tZhqQNawiTiAH3Hp+ZhLox8LDOED5hnvOy8/riV fG+wgNgMEKLRPthWqMvuKhKX82/xpmtxZGRrUBb6dIe5NBfn4koQCm0bq w==; X-CSE-ConnectionGUID: WA4IVz9oR9S/tWuFZSR1tQ== X-CSE-MsgGUID: dM2+8xueTISsr3rU0Ciw+g== X-IronPort-AV: E=McAfee;i="6600,9927,11032"; a="24824131" X-IronPort-AV: E=Sophos;i="6.07,177,1708416000"; d="scan'208";a="24824131" Received: from orviesa009.jf.intel.com ([10.64.159.149]) by orvoesa102.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 03 Apr 2024 04:23:24 -0700 X-CSE-ConnectionGUID: c3kMLgm5Sbe9UdhNflzVRg== X-CSE-MsgGUID: iT4Fq0TbSgiAMe45x5LNJw== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.07,177,1708416000"; d="scan'208";a="18358540" Received: from bvivekan-desk.iind.intel.com ([10.190.238.63]) by orviesa009-auth.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 03 Apr 2024 04:23:23 -0700 From: Balasubramani Vivekanandan To: intel-gfx@lists.freedesktop.org, intel-xe@lists.freedesktop.org Cc: Matt Roper , Lucas De Marchi , Balasubramani Vivekanandan Subject: [PATCH v2 17/25] drm/i915/xe2hpd: Add max memory bandwidth algorithm Date: Wed, 3 Apr 2024 16:52:45 +0530 Message-Id: <20240403112253.1432390-18-balasubramani.vivekanandan@intel.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20240403112253.1432390-1-balasubramani.vivekanandan@intel.com> References: <20240403112253.1432390-1-balasubramani.vivekanandan@intel.com> MIME-Version: 1.0 X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" From: Matt Roper Unlike DG2, Xe2_HPD does support multiple GV points with different maximum memory bandwidths, but uses a much simpler algorithm than igpu platforms use. Bspec: 64631 Signed-off-by: Matt Roper Signed-off-by: Balasubramani Vivekanandan --- drivers/gpu/drm/i915/display/intel_bw.c | 65 ++++++++++++++++++++++++- drivers/gpu/drm/i915/i915_drv.h | 1 + drivers/gpu/drm/i915/soc/intel_dram.c | 4 ++ 3 files changed, 68 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/i915/display/intel_bw.c b/drivers/gpu/drm/i915/display/intel_bw.c index 7f2a50b4f494..dc9ac4831065 100644 --- a/drivers/gpu/drm/i915/display/intel_bw.c +++ b/drivers/gpu/drm/i915/display/intel_bw.c @@ -22,6 +22,8 @@ struct intel_qgv_point { u16 dclk, t_rp, t_rdpre, t_rc, t_ras, t_rcd; }; +#define DEPROGBWPCLIMIT 60 + struct intel_psf_gv_point { u8 clk; /* clock in multiples of 16.6666 MHz */ }; @@ -239,6 +241,9 @@ static int icl_get_qgv_points(struct drm_i915_private *dev_priv, qi->channel_width = 16; qi->deinterleave = 4; break; + case INTEL_DRAM_GDDR: + qi->channel_width = 32; + break; default: MISSING_CASE(dram_info->type); return -EINVAL; @@ -383,6 +388,12 @@ static const struct intel_sa_info mtl_sa_info = { .derating = 10, }; +static const struct intel_sa_info xe2_hpd_sa_info = { + .derating = 30, + .deprogbwlimit = 53, + /* Other values not used by simplified algorithm */ +}; + static int icl_get_bw_info(struct drm_i915_private *dev_priv, const struct intel_sa_info *sa) { struct intel_qgv_info qi = {}; @@ -489,7 +500,7 @@ static int tgl_get_bw_info(struct drm_i915_private *dev_priv, const struct intel dclk_max = icl_sagv_max_dclk(&qi); peakbw = num_channels * DIV_ROUND_UP(qi.channel_width, 8) * dclk_max; - maxdebw = min(sa->deprogbwlimit * 1000, peakbw * 6 / 10); /* 60% */ + maxdebw = min(sa->deprogbwlimit * 1000, peakbw * DEPROGBWPCLIMIT / 100); ipqdepth = min(ipqdepthpch, sa->displayrtids / num_channels); /* @@ -594,6 +605,54 @@ static void dg2_get_bw_info(struct drm_i915_private *i915) i915->display.sagv.status = I915_SAGV_NOT_CONTROLLED; } +static int xe2_hpd_get_bw_info(struct drm_i915_private *i915, + const struct intel_sa_info *sa) +{ + struct intel_qgv_info qi = {}; + int num_channels = i915->dram_info.num_channels; + int peakbw, maxdebw; + int ret, i; + + ret = icl_get_qgv_points(i915, &qi, true); + if (ret) { + drm_dbg_kms(&i915->drm, + "Failed to get memory subsystem information, ignoring bandwidth limits"); + return ret; + } + + peakbw = num_channels * qi.channel_width / 8 * icl_sagv_max_dclk(&qi); + maxdebw = min(sa->deprogbwlimit * 1000, peakbw * DEPROGBWPCLIMIT / 10); + + for (i = 0; i < qi.num_points; i++) { + const struct intel_qgv_point *point = &qi.points[i]; + int bw = num_channels * (qi.channel_width / 8) * point->dclk; + + i915->display.bw.max[0].deratedbw[i] = + min(maxdebw, (100 - sa->derating) * bw / 100); + i915->display.bw.max[0].peakbw[i] = bw; + + drm_dbg_kms(&i915->drm, "QGV %d: deratedbw=%u peakbw: %u\n", + i, i915->display.bw.max[0].deratedbw[i], + i915->display.bw.max[0].peakbw[i]); + } + + /* Bandwidth does not depend on # of planes; set all groups the same */ + i915->display.bw.max[0].num_planes = 1; + i915->display.bw.max[0].num_qgv_points = qi.num_points; + for (i = 1; i < ARRAY_SIZE(i915->display.bw.max); i++) + memcpy(&i915->display.bw.max[i], &i915->display.bw.max[0], + sizeof(i915->display.bw.max[0])); + + /* + * Xe2_HPD should always have exactly two QGV points representing + * battery and plugged-in operation. + */ + drm_WARN_ON(&i915->drm, qi.num_points != 2); + i915->display.sagv.status = I915_SAGV_ENABLED; + + return 0; +} + static unsigned int icl_max_bw_index(struct drm_i915_private *dev_priv, int num_planes, int qgv_point) { @@ -664,7 +723,9 @@ void intel_bw_init_hw(struct drm_i915_private *dev_priv) if (!HAS_DISPLAY(dev_priv)) return; - if (DISPLAY_VER(dev_priv) >= 14) + if (DISPLAY_VER_FULL(dev_priv) >= IP_VER(14, 1) && IS_DGFX(dev_priv)) + xe2_hpd_get_bw_info(dev_priv, &xe2_hpd_sa_info); + else if (DISPLAY_VER(dev_priv) >= 14) tgl_get_bw_info(dev_priv, &mtl_sa_info); else if (IS_DG2(dev_priv)) dg2_get_bw_info(dev_priv); diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h index b41a414079f4..eb3ad6ae0b2a 100644 --- a/drivers/gpu/drm/i915/i915_drv.h +++ b/drivers/gpu/drm/i915/i915_drv.h @@ -313,6 +313,7 @@ struct drm_i915_private { INTEL_DRAM_LPDDR4, INTEL_DRAM_DDR5, INTEL_DRAM_LPDDR5, + INTEL_DRAM_GDDR, } type; u8 num_qgv_points; u8 num_psf_gv_points; diff --git a/drivers/gpu/drm/i915/soc/intel_dram.c b/drivers/gpu/drm/i915/soc/intel_dram.c index 15492b69f698..99b541babb31 100644 --- a/drivers/gpu/drm/i915/soc/intel_dram.c +++ b/drivers/gpu/drm/i915/soc/intel_dram.c @@ -640,6 +640,10 @@ static int xelpdp_get_dram_info(struct drm_i915_private *i915) case 5: dram_info->type = INTEL_DRAM_LPDDR3; break; + case 8: + drm_WARN_ON(&i915->drm, !IS_DGFX(i915)); + dram_info->type = INTEL_DRAM_GDDR; + break; default: MISSING_CASE(val); return -EINVAL; From patchwork Wed Apr 3 11:22:46 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Vivekanandan, Balasubramani" X-Patchwork-Id: 13615982 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id B8C4DCD128A for ; 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X-CSE-ConnectionGUID: 9X7PoSSdT8uZIGsZA8VrPQ== X-CSE-MsgGUID: P2ZWZT+3R7617UR4ORKaow== X-IronPort-AV: E=McAfee;i="6600,9927,11032"; a="24824134" X-IronPort-AV: E=Sophos;i="6.07,177,1708416000"; d="scan'208";a="24824134" Received: from orviesa009.jf.intel.com ([10.64.159.149]) by orvoesa102.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 03 Apr 2024 04:23:27 -0700 X-CSE-ConnectionGUID: NquJDDDwRo+pofAP8B9YUw== X-CSE-MsgGUID: jhDN8j3wRES6HMzp5rl/RQ== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.07,177,1708416000"; d="scan'208";a="18358543" Received: from bvivekan-desk.iind.intel.com ([10.190.238.63]) by orviesa009-auth.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 03 Apr 2024 04:23:25 -0700 From: Balasubramani Vivekanandan To: intel-gfx@lists.freedesktop.org, intel-xe@lists.freedesktop.org Cc: Matt Roper , Lucas De Marchi , Mitul Golani , Suraj Kandpal , Balasubramani Vivekanandan Subject: [PATCH v2 18/25] drm/i915/display: Enable RM timeout detection Date: Wed, 3 Apr 2024 16:52:46 +0530 Message-Id: <20240403112253.1432390-19-balasubramani.vivekanandan@intel.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20240403112253.1432390-1-balasubramani.vivekanandan@intel.com> References: <20240403112253.1432390-1-balasubramani.vivekanandan@intel.com> MIME-Version: 1.0 X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" From: Mitul Golani Enable RM timeout interrupt to detect any hang during display engine register access. This interrupt is supported only on Display version 14. Current default timeout is 2ms. WA: 14012195489 Bspec: 50110 CC: Suraj Kandpal Signed-off-by: Mitul Golani Signed-off-by: Balasubramani Vivekanandan --- drivers/gpu/drm/i915/display/intel_display_irq.c | 10 ++++++++++ drivers/gpu/drm/i915/i915_reg.h | 3 +++ 2 files changed, 13 insertions(+) diff --git a/drivers/gpu/drm/i915/display/intel_display_irq.c b/drivers/gpu/drm/i915/display/intel_display_irq.c index f846c5b108b5..3035b50fcad9 100644 --- a/drivers/gpu/drm/i915/display/intel_display_irq.c +++ b/drivers/gpu/drm/i915/display/intel_display_irq.c @@ -851,6 +851,13 @@ gen8_de_misc_irq_handler(struct drm_i915_private *dev_priv, u32 iir) { bool found = false; + if (iir & GEN8_DE_RM_TIMEOUT) { + u32 val = intel_uncore_read(&dev_priv->uncore, + RMTIMEOUTREG_CAPTURE); + drm_warn(&dev_priv->drm, "Register Access Timeout = 0x%x\n", val); + found = true; + } + if (DISPLAY_VER(dev_priv) >= 14) { if (iir & (XELPDP_PMDEMAND_RSP | XELPDP_PMDEMAND_RSPTOUT_ERR)) { @@ -1666,6 +1673,9 @@ void gen8_de_irq_postinstall(struct drm_i915_private *dev_priv) de_port_masked |= DSI0_TE | DSI1_TE; } + if (DISPLAY_VER(dev_priv) == 14) + de_misc_masked |= GEN8_DE_RM_TIMEOUT; + de_pipe_enables = de_pipe_masked | GEN8_PIPE_VBLANK | gen8_de_pipe_underrun_mask(dev_priv) | diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h index 875d76fb8cd0..d1692b32bb8a 100644 --- a/drivers/gpu/drm/i915/i915_reg.h +++ b/drivers/gpu/drm/i915/i915_reg.h @@ -4212,6 +4212,8 @@ #define RM_TIMEOUT _MMIO(0x42060) #define MMIO_TIMEOUT_US(us) ((us) << 0) +#define RMTIMEOUTREG_CAPTURE _MMIO(0x420e0) + /* interrupts */ #define DE_MASTER_IRQ_CONTROL (1 << 31) #define DE_SPRITEB_FLIP_DONE (1 << 29) @@ -4398,6 +4400,7 @@ #define GEN8_DE_MISC_IMR _MMIO(0x44464) #define GEN8_DE_MISC_IIR _MMIO(0x44468) #define GEN8_DE_MISC_IER _MMIO(0x4446c) +#define GEN8_DE_RM_TIMEOUT REG_BIT(29) #define XELPDP_PMDEMAND_RSPTOUT_ERR REG_BIT(27) #define GEN8_DE_MISC_GSE REG_BIT(27) #define GEN8_DE_EDP_PSR REG_BIT(19) From patchwork Wed Apr 3 11:22:47 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: "Vivekanandan, Balasubramani" X-Patchwork-Id: 13615983 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 453D5CD1288 for ; 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X-CSE-ConnectionGUID: LKaNxbhASHWoj9PCH0Z/LQ== X-CSE-MsgGUID: TXNeiNzFSZuUbUGy9pU8yg== X-IronPort-AV: E=McAfee;i="6600,9927,11032"; a="24824148" X-IronPort-AV: E=Sophos;i="6.07,177,1708416000"; d="scan'208";a="24824148" Received: from orviesa009.jf.intel.com ([10.64.159.149]) by orvoesa102.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 03 Apr 2024 04:23:29 -0700 X-CSE-ConnectionGUID: JiGWVb1OQCC4y6h+SdXpsw== X-CSE-MsgGUID: HFG9j150QZGm0qcd2SGb9A== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.07,177,1708416000"; d="scan'208";a="18358552" Received: from bvivekan-desk.iind.intel.com ([10.190.238.63]) by orviesa009-auth.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 03 Apr 2024 04:23:27 -0700 From: Balasubramani Vivekanandan To: intel-gfx@lists.freedesktop.org, intel-xe@lists.freedesktop.org Cc: Matt Roper , Lucas De Marchi , =?utf-8?q?Jos=C3=A9_Roberto_de_?= =?utf-8?q?Souza?= , Balasubramani Vivekanandan Subject: [PATCH v2 19/25] drm/i915/xe2hpd: Do not program MBUS_DBOX BW credits Date: Wed, 3 Apr 2024 16:52:47 +0530 Message-Id: <20240403112253.1432390-20-balasubramani.vivekanandan@intel.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20240403112253.1432390-1-balasubramani.vivekanandan@intel.com> References: <20240403112253.1432390-1-balasubramani.vivekanandan@intel.com> MIME-Version: 1.0 X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" From: José Roberto de Souza Xe2_HPD doesn't have DBOX BW credits, so here programing it with zero. BSpec: 49213 Signed-off-by: José Roberto de Souza Signed-off-by: Balasubramani Vivekanandan --- drivers/gpu/drm/i915/display/skl_watermark.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/gpu/drm/i915/display/skl_watermark.c b/drivers/gpu/drm/i915/display/skl_watermark.c index bc341abcab2f..22ae782e89f4 100644 --- a/drivers/gpu/drm/i915/display/skl_watermark.c +++ b/drivers/gpu/drm/i915/display/skl_watermark.c @@ -3733,7 +3733,7 @@ void intel_mbus_dbox_update(struct intel_atomic_state *state) if (!new_crtc_state->hw.active) continue; - if (DISPLAY_VER(i915) >= 14) { + if (DISPLAY_VER(i915) >= 14 && !IS_BATTLEMAGE(i915)) { if (xelpdp_is_only_pipe_per_dbuf_bank(crtc->pipe, new_dbuf_state->active_pipes)) pipe_val |= MBUS_DBOX_BW_8CREDITS_MTL; From patchwork Wed Apr 3 11:22:48 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Vivekanandan, Balasubramani" X-Patchwork-Id: 13615984 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 8B8C5CD128A for ; Wed, 3 Apr 2024 11:23:32 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 0332F112A10; Wed, 3 Apr 2024 11:23:32 +0000 (UTC) Authentication-Results: gabe.freedesktop.org; dkim=pass (2048-bit key; unprotected) header.d=intel.com header.i=@intel.com header.b="ZjAZYDdM"; dkim-atps=neutral Received: from mgamail.intel.com (mgamail.intel.com [198.175.65.10]) by gabe.freedesktop.org (Postfix) with ESMTPS id F0B6A112A0D; Wed, 3 Apr 2024 11:23:30 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1712143411; x=1743679411; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=eIgqYGq4fLCpTqOPXETspxhbgXdmYP4yn2mIRzbzD4U=; b=ZjAZYDdMeg8AhoqU4T4It+g71dvquvZCxgBFhzbMmeCs8ImoMBUbks/d GGTK+uFstIW75e06p2RTdf3oy05Uq4oIp+cOEgxrBEYX3BdUhjmZfIMqc sBlr0WJqXETj4oeZDGRl2Lwg+eppcwMWMDtbkCYfceWf0n70YMg/PlhY7 woiqdgwJWS4cGqsAAjpEDgwMhhyc9BBWCg+kvHBJQ1sYR1L2EhN2pui5C 6KLgBRFlVSrc/R6r0+Y6LYPT40MHYP+kg2JKYbAj7dgAu0iiPQMQi98za vl3yjTEFOMBGvVtMztNAGy05oFZKavG3u8aJYBAvHnJARlmJTeONSCR4g Q==; X-CSE-ConnectionGUID: WUpZz1rHTQ+0Vrs5qZnw/g== X-CSE-MsgGUID: rX9TpA8SQUKBEQFw71X6pw== X-IronPort-AV: E=McAfee;i="6600,9927,11032"; a="24824151" X-IronPort-AV: E=Sophos;i="6.07,177,1708416000"; d="scan'208";a="24824151" Received: from orviesa009.jf.intel.com ([10.64.159.149]) by orvoesa102.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 03 Apr 2024 04:23:31 -0700 X-CSE-ConnectionGUID: CF3f0NkHToqJccqdvXAzIQ== X-CSE-MsgGUID: XNZvrs/YRpyiAvY3bkSs4Q== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.07,177,1708416000"; d="scan'208";a="18358559" Received: from bvivekan-desk.iind.intel.com ([10.190.238.63]) by orviesa009-auth.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 03 Apr 2024 04:23:29 -0700 From: Balasubramani Vivekanandan To: intel-gfx@lists.freedesktop.org, intel-xe@lists.freedesktop.org Cc: Matt Roper , Lucas De Marchi , Balasubramani Vivekanandan Subject: [PATCH v2 20/25] drm/i915/bmg: BMG should re-use MTL's south display logic Date: Wed, 3 Apr 2024 16:52:48 +0530 Message-Id: <20240403112253.1432390-21-balasubramani.vivekanandan@intel.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20240403112253.1432390-1-balasubramani.vivekanandan@intel.com> References: <20240403112253.1432390-1-balasubramani.vivekanandan@intel.com> MIME-Version: 1.0 X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" From: Matt Roper Battlemage's south display is the same as Meteor Lake's, including the need to invert the HPD pins, which Lunar Lake does not need. Signed-off-by: Matt Roper Signed-off-by: Balasubramani Vivekanandan Reviewed-by: Dnyaneshwar Bhadane --- drivers/gpu/drm/i915/soc/intel_pch.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/i915/soc/intel_pch.c b/drivers/gpu/drm/i915/soc/intel_pch.c index 3cad6dac06b0..542eea50093c 100644 --- a/drivers/gpu/drm/i915/soc/intel_pch.c +++ b/drivers/gpu/drm/i915/soc/intel_pch.c @@ -218,10 +218,10 @@ void intel_detect_pch(struct drm_i915_private *dev_priv) if (DISPLAY_VER(dev_priv) >= 20) { dev_priv->pch_type = PCH_LNL; return; - } else if (IS_METEORLAKE(dev_priv)) { + } else if (IS_BATTLEMAGE(dev_priv) || IS_METEORLAKE(dev_priv)) { /* * Both north display and south display are on the SoC die. - * The real PCH is uninvolved in display. + * The real PCH (if it even exists) is uninvolved in display. */ dev_priv->pch_type = PCH_MTL; return; From patchwork Wed Apr 3 11:22:49 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Vivekanandan, Balasubramani" X-Patchwork-Id: 13615985 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id D99E0CD1294 for ; Wed, 3 Apr 2024 11:23:34 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 2A815112A2A; Wed, 3 Apr 2024 11:23:34 +0000 (UTC) Authentication-Results: gabe.freedesktop.org; dkim=pass (2048-bit key; unprotected) header.d=intel.com header.i=@intel.com header.b="ibjU1RlD"; dkim-atps=neutral Received: from mgamail.intel.com (mgamail.intel.com [198.175.65.10]) by gabe.freedesktop.org (Postfix) with ESMTPS id C3391112A28; Wed, 3 Apr 2024 11:23:32 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1712143413; x=1743679413; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=FSXs20PJBJyOLgqakwjPbhb+TaNU4Tq3YC8JVaxUI0A=; b=ibjU1RlDXj6ga8HbO+lkbrvv+XWm6rzUB2psVwIsla2O0LTF2xS4nRLB /WuqJeo6zStRy+rUyK5Z04KC6OwbWuSOF/Ruq6GgkfAMA902JpdWf+WJB sdk33TCwid6zlq5tvZrA3lcd1rfqlFigTcZC6XjVq4+TApf3iS/PMaK2x XJ9U++8qcUN7Z1fBWjX6gSmRbG9tLOHasGjRCjgwSU62TxlCTFjhMydp4 1TWMDu95CghEVpa7Ge2NXrh4bYuaUg5qwa2vNxhDlVPK2bvWjnLlh+S7O JQwlgOUxRXWgQTWfUip/Tym50tpAt6taiUuDnNoXS/SVw/Got1G0NLBJX Q==; X-CSE-ConnectionGUID: ZUqxXn2fQgiIK0PGW2Xlng== X-CSE-MsgGUID: P53NNWHJQTSHzwuMzufgTg== X-IronPort-AV: E=McAfee;i="6600,9927,11032"; a="24824155" X-IronPort-AV: E=Sophos;i="6.07,177,1708416000"; d="scan'208";a="24824155" Received: from orviesa009.jf.intel.com ([10.64.159.149]) by orvoesa102.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 03 Apr 2024 04:23:33 -0700 X-CSE-ConnectionGUID: tn0s3VilQuKBwcVEiRkQOQ== X-CSE-MsgGUID: ls596PRQRWGJ/TDYy+PT+w== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.07,177,1708416000"; d="scan'208";a="18358564" Received: from bvivekan-desk.iind.intel.com ([10.190.238.63]) by orviesa009-auth.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 03 Apr 2024 04:23:31 -0700 From: Balasubramani Vivekanandan To: intel-gfx@lists.freedesktop.org, intel-xe@lists.freedesktop.org Cc: Matt Roper , Lucas De Marchi , Balasubramani Vivekanandan Subject: [PATCH v2 21/25] drm/i915/xe2hpd: Set maximum DP rate to UHBR13.5 Date: Wed, 3 Apr 2024 16:52:49 +0530 Message-Id: <20240403112253.1432390-22-balasubramani.vivekanandan@intel.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20240403112253.1432390-1-balasubramani.vivekanandan@intel.com> References: <20240403112253.1432390-1-balasubramani.vivekanandan@intel.com> MIME-Version: 1.0 X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" Max supported speed by xe2hpd is UHBR13.5. Limit the max DP source rate to it. Bspec: 67066 Signed-off-by: Balasubramani Vivekanandan Reviewed-by: Shekhar Chauhan --- drivers/gpu/drm/i915/display/intel_dp.c | 3 +++ 1 file changed, 3 insertions(+) diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c index b393ddbb7b35..d9d37f4971dd 100644 --- a/drivers/gpu/drm/i915/display/intel_dp.c +++ b/drivers/gpu/drm/i915/display/intel_dp.c @@ -466,6 +466,9 @@ static int mtl_max_source_rate(struct intel_dp *intel_dp) if (intel_encoder_is_c10phy(encoder)) return 810000; + if (DISPLAY_VER_FULL(to_i915(encoder->base.dev)) == IP_VER(14, 1)) + return 1350000; + return 2000000; } From patchwork Wed Apr 3 11:22:50 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Vivekanandan, Balasubramani" X-Patchwork-Id: 13615986 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 78626CD1288 for ; Wed, 3 Apr 2024 11:23:37 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id BC3F7112A23; Wed, 3 Apr 2024 11:23:36 +0000 (UTC) Authentication-Results: gabe.freedesktop.org; dkim=pass (2048-bit key; unprotected) header.d=intel.com header.i=@intel.com header.b="aHGu5ale"; dkim-atps=neutral Received: from mgamail.intel.com (mgamail.intel.com [198.175.65.10]) by gabe.freedesktop.org (Postfix) with ESMTPS id 48DD9112A28; Wed, 3 Apr 2024 11:23:35 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1712143416; x=1743679416; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=16hMndU3f7cgmqlWW160e2/ZvbO6vsyI1ZbGPYrwMsg=; b=aHGu5aleiDiJhNw8RqJhUT4Nrs8QqiZkOQsf06Y4VL9t4NZa3tmxYTri uYudmJeHFu7OR/PhW3VH8FYnid+pBCdUtakw+b+6tMavRuf3TfnIPimnW yAJfErWXJ41XJ9Tz2EmoqGkdL7w3N8Aih7+VICVBU0vrk4OV3rC0uKj9z JVOrXxXYwnu1bK01AbW5xwMUMmS6qplko2EEUFXZLBcUblB6a3oPP2ttX TViU5CVoqGna9d/QgZOdQmIcoAeuA4xupXItott8aiuYSgpFM4GcYkRNN 4HPyroaKh+8yOUhn194nkxwufjcjQQ/YXdMzWbvPJ4kBsZUf+pg3WiHAD g==; X-CSE-ConnectionGUID: dyrTQUJNRy2T1nk3mThKsA== X-CSE-MsgGUID: iHP32rOLSLuNCClP7OJyDQ== X-IronPort-AV: E=McAfee;i="6600,9927,11032"; a="24824161" X-IronPort-AV: E=Sophos;i="6.07,177,1708416000"; d="scan'208";a="24824161" Received: from orviesa009.jf.intel.com ([10.64.159.149]) by orvoesa102.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 03 Apr 2024 04:23:36 -0700 X-CSE-ConnectionGUID: zoEqUNCUTHyMzRsvfgi1MA== X-CSE-MsgGUID: ew8Iub/XTDm2eTXVoqXV0g== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.07,177,1708416000"; d="scan'208";a="18358588" Received: from bvivekan-desk.iind.intel.com ([10.190.238.63]) by orviesa009-auth.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 03 Apr 2024 04:23:34 -0700 From: Balasubramani Vivekanandan To: intel-gfx@lists.freedesktop.org, intel-xe@lists.freedesktop.org Cc: Matt Roper , Lucas De Marchi , Matthew Auld , Balasubramani Vivekanandan Subject: [PATCH v2 22/25] drm/xe/gt_print: add xe_gt_err_once() Date: Wed, 3 Apr 2024 16:52:50 +0530 Message-Id: <20240403112253.1432390-23-balasubramani.vivekanandan@intel.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20240403112253.1432390-1-balasubramani.vivekanandan@intel.com> References: <20240403112253.1432390-1-balasubramani.vivekanandan@intel.com> MIME-Version: 1.0 X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" From: Matthew Auld Needed in an upcoming patch, where we want GT level print, but only which to trigger once to avoid flooding dmesg. Signed-off-by: Matthew Auld Signed-off-by: Balasubramani Vivekanandan Reviewed-by: Nirmoy Das --- drivers/gpu/drm/xe/xe_gt_printk.h | 3 +++ 1 file changed, 3 insertions(+) diff --git a/drivers/gpu/drm/xe/xe_gt_printk.h b/drivers/gpu/drm/xe/xe_gt_printk.h index c2b004d3f48e..d6228baaff1e 100644 --- a/drivers/gpu/drm/xe/xe_gt_printk.h +++ b/drivers/gpu/drm/xe/xe_gt_printk.h @@ -13,6 +13,9 @@ #define xe_gt_printk(_gt, _level, _fmt, ...) \ drm_##_level(>_to_xe(_gt)->drm, "GT%u: " _fmt, (_gt)->info.id, ##__VA_ARGS__) +#define xe_gt_err_once(_gt, _fmt, ...) \ + xe_gt_printk((_gt), err_once, _fmt, ##__VA_ARGS__) + #define xe_gt_err(_gt, _fmt, ...) \ xe_gt_printk((_gt), err, _fmt, ##__VA_ARGS__) From patchwork Wed Apr 3 11:22:51 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Vivekanandan, Balasubramani" X-Patchwork-Id: 13615987 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id A3FE8CD1288 for ; Wed, 3 Apr 2024 11:23:39 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 4D763112A28; Wed, 3 Apr 2024 11:23:39 +0000 (UTC) Authentication-Results: gabe.freedesktop.org; dkim=pass (2048-bit key; unprotected) header.d=intel.com header.i=@intel.com header.b="iMAjGn7p"; dkim-atps=neutral Received: from mgamail.intel.com (mgamail.intel.com [198.175.65.10]) by gabe.freedesktop.org (Postfix) with ESMTPS id C5B59112A0F; Wed, 3 Apr 2024 11:23:37 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1712143418; x=1743679418; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=8XSbMrwSo2yIpEiTkyTs+DAck5PZ7WZSRJbHFvUd4Nc=; b=iMAjGn7pwIGTr1rU804xjSmZ0i3FkUxo7vVRjRi2fn8yLHFqLRsEZcsK xaSd75tD/M4n9MSOR1BPk/d4y41E5Ysors3n2gIelHRWY0GZcji5c5np+ uyhNAoZTLHtVVS3aYiPx1VbXSjmrp9luw48Ek40nwR24dmSoRJcDBxn9J nfO9PxrHQTedO1uNtGjYyC/gZmVk10ewtdmik0+3rLkUAWhYrrxzxSPeN wFumf0bd6Bx1E2zZcet+LNxOb+Foa6TVsPvio9/FUgpu1fSgJhNcTW/uo 0IaFha9mGpBmv1ZP0k901OFIYMy+N9VB7T0NvxFg4COLih96xY/FauG6L A==; X-CSE-ConnectionGUID: ThPgZj1dQpG4ArikZLgqJQ== X-CSE-MsgGUID: u4SruYMySY6brYjj/rmSeg== X-IronPort-AV: E=McAfee;i="6600,9927,11032"; a="24824169" X-IronPort-AV: E=Sophos;i="6.07,177,1708416000"; d="scan'208";a="24824169" Received: from orviesa009.jf.intel.com ([10.64.159.149]) by orvoesa102.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 03 Apr 2024 04:23:38 -0700 X-CSE-ConnectionGUID: t0lH08nYQ/CNzrIFX7rKXQ== X-CSE-MsgGUID: 10oseVLDSX2jM5NjqDs3xw== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.07,177,1708416000"; d="scan'208";a="18358602" Received: from bvivekan-desk.iind.intel.com ([10.190.238.63]) by orviesa009-auth.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 03 Apr 2024 04:23:36 -0700 From: Balasubramani Vivekanandan To: intel-gfx@lists.freedesktop.org, intel-xe@lists.freedesktop.org Cc: Matt Roper , Lucas De Marchi , Nirmoy Das , Matthew Auld , Balasubramani Vivekanandan Subject: [PATCH v2 23/25] drm/xe/device: implement transient flush Date: Wed, 3 Apr 2024 16:52:51 +0530 Message-Id: <20240403112253.1432390-24-balasubramani.vivekanandan@intel.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20240403112253.1432390-1-balasubramani.vivekanandan@intel.com> References: <20240403112253.1432390-1-balasubramani.vivekanandan@intel.com> MIME-Version: 1.0 X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" From: Nirmoy Das Display surfaces can be tagged as transient by mapping it using one of the various L3:XD PAT index modes on Xe2. The expectation is that KMD needs to request transient data flush at the start of flip sequence to ensure all transient data in L3 cache is flushed to memory. Add a routine for this which we can then call from the display code. Signed-off-by: Nirmoy Das Co-developed-by: Matthew Auld Signed-off-by: Matthew Auld Signed-off-by: Balasubramani Vivekanandan --- drivers/gpu/drm/xe/regs/xe_gt_regs.h | 3 ++ drivers/gpu/drm/xe/xe_device.c | 52 ++++++++++++++++++++++++++++ drivers/gpu/drm/xe/xe_device.h | 2 ++ 3 files changed, 57 insertions(+) diff --git a/drivers/gpu/drm/xe/regs/xe_gt_regs.h b/drivers/gpu/drm/xe/regs/xe_gt_regs.h index 6617c86a096b..7afe810b3441 100644 --- a/drivers/gpu/drm/xe/regs/xe_gt_regs.h +++ b/drivers/gpu/drm/xe/regs/xe_gt_regs.h @@ -306,6 +306,9 @@ #define XE2LPM_L3SQCREG5 XE_REG_MCR(0xb658) +#define XE2_TDF_CTRL XE_REG(0xb418) +#define TRANSIENT_FLUSH_REQUEST REG_BIT(0) + #define XEHP_MERT_MOD_CTRL XE_REG_MCR(0xcf28) #define RENDER_MOD_CTRL XE_REG_MCR(0xcf2c) #define COMP_MOD_CTRL XE_REG_MCR(0xcf30) diff --git a/drivers/gpu/drm/xe/xe_device.c b/drivers/gpu/drm/xe/xe_device.c index 01bd5ccf05ca..0c9769fe04f6 100644 --- a/drivers/gpu/drm/xe/xe_device.c +++ b/drivers/gpu/drm/xe/xe_device.c @@ -641,6 +641,58 @@ void xe_device_wmb(struct xe_device *xe) xe_mmio_write32(gt, SOFTWARE_FLAGS_SPR33, 0); } +/** + * xe_device_td_flush() - Flush transient L3 cache entries + * @xe: The device + * + * Display engine has direct access to memory and is never coherent with L3/L4 + * caches (or CPU caches), however KMD is responsible for specifically flushing + * transient L3 GPU cache entries prior to the flip sequence to ensure scanout + * can happen from such a surface without seeing corruption. + * + * Display surfaces can be tagged as transient by mapping it using one of the + * various L3:XD PAT index modes on Xe2. + * + * Note: On non-discrete xe2 platforms, like LNL, the entire L3 cache is flushed + * at the end of each submission via PIPE_CONTROL for compute/render, since SA + * Media is not coherent with L3 and we want to support render-vs-media + * usescases. For other engines like copy/blt the HW internally forces uncached + * behaviour, hence why we can skip the TDF on such platforms. + */ +void xe_device_td_flush(struct xe_device *xe) +{ + struct xe_gt *gt; + int err; + u8 id; + + if (!IS_DGFX(xe) || GRAPHICS_VER(xe) < 20) + return; + + for_each_gt(gt, xe, id) { + if (xe_gt_is_media_type(gt)) + continue; + + err = xe_force_wake_get(gt_to_fw(gt), XE_FW_GT); + if (err) + return; + + xe_mmio_write32(gt, XE2_TDF_CTRL, TRANSIENT_FLUSH_REQUEST); + /* + * FIXME: We can likely do better here with our choice of + * timeout. Currently we just assume the worst case, but really + * we should make this dependent on how much actual L3 there is + * for this system. Recomendation is to allow ~64us in the worst + * case for 8M of L3 (assumes all entries are transient and need + * to be flushed). + */ + if (xe_mmio_wait32(gt, XE2_TDF_CTRL, TRANSIENT_FLUSH_REQUEST, 0, + 150, NULL, false)) + xe_gt_err_once(gt, "TD flush timeout\n"); + + xe_force_wake_put(gt_to_fw(gt), XE_FW_GT); + } +} + u32 xe_device_ccs_bytes(struct xe_device *xe, u64 size) { return xe_device_has_flat_ccs(xe) ? diff --git a/drivers/gpu/drm/xe/xe_device.h b/drivers/gpu/drm/xe/xe_device.h index d413bc2c6be5..d3430f4b820a 100644 --- a/drivers/gpu/drm/xe/xe_device.h +++ b/drivers/gpu/drm/xe/xe_device.h @@ -176,4 +176,6 @@ void xe_device_snapshot_print(struct xe_device *xe, struct drm_printer *p); u64 xe_device_canonicalize_addr(struct xe_device *xe, u64 address); u64 xe_device_uncanonicalize_addr(struct xe_device *xe, u64 address); +void xe_device_td_flush(struct xe_device *xe); + #endif From patchwork Wed Apr 3 11:22:52 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: "Vivekanandan, Balasubramani" X-Patchwork-Id: 13615988 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 5D332CD128A for ; Wed, 3 Apr 2024 11:23:42 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id A7D5A112A29; Wed, 3 Apr 2024 11:23:41 +0000 (UTC) Authentication-Results: gabe.freedesktop.org; dkim=pass (2048-bit key; unprotected) header.d=intel.com header.i=@intel.com header.b="HM1BWlFG"; dkim-atps=neutral Received: from mgamail.intel.com (mgamail.intel.com [198.175.65.10]) by gabe.freedesktop.org (Postfix) with ESMTPS id 135A2112A1B; Wed, 3 Apr 2024 11:23:40 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1712143421; x=1743679421; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=/PDQm11gDnGYRRKglzs8lNk67iAS3UFBkGBHP2gN94o=; b=HM1BWlFGpifeFC/1pZuQrq/MwXrf54jIUEorm1v8Emve9Uv86qfBJ3fQ ayN2dCUN2c8K+7FQcmawMM3pXuSUfGLyKYIKKQjjGYo0Ey5CxIk5sjSN+ x13C4oERNhI7HJPKw4Hwt2f5j458ctBx/2NKq8scbUd6/O3tP8dmInX/3 mjA4jOw2zkGKhKuPsE5bvwYLHySPjDdBidcJ485pMb7E7c0s/RrjoodJk 4LUNPzI0seQeWZ36OtmvdlcofVRlrsQfBxjSirZ5/fQEmWJ+TTBdcCs0+ 1Qx592oQdEcxjdtNrtME3olBRYYVfgCVLxTpYQw+/0bxU2Rg/GIomKLAM g==; X-CSE-ConnectionGUID: VZJJ2oT0SNOyQb02ET4DkQ== X-CSE-MsgGUID: LSHAN3d8QCum4XE5/fK3qA== X-IronPort-AV: E=McAfee;i="6600,9927,11032"; a="24824174" X-IronPort-AV: E=Sophos;i="6.07,177,1708416000"; d="scan'208";a="24824174" Received: from orviesa009.jf.intel.com ([10.64.159.149]) by orvoesa102.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 03 Apr 2024 04:23:40 -0700 X-CSE-ConnectionGUID: /bIv9XGmQ4+r2uqfOoSf6w== X-CSE-MsgGUID: V2A4gbJIQMO1JfgvdUSa9w== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.07,177,1708416000"; d="scan'208";a="18358620" Received: from bvivekan-desk.iind.intel.com ([10.190.238.63]) by orviesa009-auth.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 03 Apr 2024 04:23:38 -0700 From: Balasubramani Vivekanandan To: intel-gfx@lists.freedesktop.org, intel-xe@lists.freedesktop.org Cc: Matt Roper , Lucas De Marchi , Matthew Auld , Balasubramani Vivekanandan Subject: [PATCH v2 24/25] drm/i915/display: perform transient flush Date: Wed, 3 Apr 2024 16:52:52 +0530 Message-Id: <20240403112253.1432390-25-balasubramani.vivekanandan@intel.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20240403112253.1432390-1-balasubramani.vivekanandan@intel.com> References: <20240403112253.1432390-1-balasubramani.vivekanandan@intel.com> MIME-Version: 1.0 X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" From: Matthew Auld Perform manual transient cache flush prior to flip and at the end of frontbuffer_flush. This is needed to ensure display engine doesn't see garbage if the surface is L3:XD dirty. Testcase: igt@xe-pat@display-vs-wb-transient Signed-off-by: Matthew Auld Signed-off-by: Balasubramani Vivekanandan Acked-by: Nirmoy Das --- drivers/gpu/drm/i915/display/intel_display.c | 3 +++ .../gpu/drm/i915/display/intel_frontbuffer.c | 2 ++ drivers/gpu/drm/i915/display/intel_tdf.h | 25 +++++++++++++++++++ drivers/gpu/drm/xe/Makefile | 3 ++- drivers/gpu/drm/xe/display/xe_tdf.c | 13 ++++++++++ 5 files changed, 45 insertions(+), 1 deletion(-) create mode 100644 drivers/gpu/drm/i915/display/intel_tdf.h create mode 100644 drivers/gpu/drm/xe/display/xe_tdf.c diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c index aed25890b6f5..0a720e9d12a7 100644 --- a/drivers/gpu/drm/i915/display/intel_display.c +++ b/drivers/gpu/drm/i915/display/intel_display.c @@ -110,6 +110,7 @@ #include "intel_sdvo.h" #include "intel_snps_phy.h" #include "intel_tc.h" +#include "intel_tdf.h" #include "intel_tv.h" #include "intel_vblank.h" #include "intel_vdsc.h" @@ -7095,6 +7096,8 @@ static void intel_atomic_commit_tail(struct intel_atomic_state *state) intel_atomic_commit_fence_wait(state); + intel_td_flush(dev_priv); + drm_atomic_helper_wait_for_dependencies(&state->base); drm_dp_mst_atomic_wait_for_dependencies(&state->base); intel_atomic_global_state_wait_for_dependencies(state); diff --git a/drivers/gpu/drm/i915/display/intel_frontbuffer.c b/drivers/gpu/drm/i915/display/intel_frontbuffer.c index 2ea37c0414a9..4923c340a0b6 100644 --- a/drivers/gpu/drm/i915/display/intel_frontbuffer.c +++ b/drivers/gpu/drm/i915/display/intel_frontbuffer.c @@ -65,6 +65,7 @@ #include "intel_fbc.h" #include "intel_frontbuffer.h" #include "intel_psr.h" +#include "intel_tdf.h" /** * frontbuffer_flush - flush frontbuffer @@ -93,6 +94,7 @@ static void frontbuffer_flush(struct drm_i915_private *i915, trace_intel_frontbuffer_flush(i915, frontbuffer_bits, origin); might_sleep(); + intel_td_flush(i915); intel_drrs_flush(i915, frontbuffer_bits); intel_psr_flush(i915, frontbuffer_bits, origin); intel_fbc_flush(i915, frontbuffer_bits, origin); diff --git a/drivers/gpu/drm/i915/display/intel_tdf.h b/drivers/gpu/drm/i915/display/intel_tdf.h new file mode 100644 index 000000000000..353cde21f6c2 --- /dev/null +++ b/drivers/gpu/drm/i915/display/intel_tdf.h @@ -0,0 +1,25 @@ +/* SPDX-License-Identifier: MIT */ +/* + * Copyright © 2024 Intel Corporation + */ + +#ifndef __INTEL_TDF_H__ +#define __INTEL_TDF_H__ + +/* + * TDF (Transient-Data-Flush) is needed for Xe2+ where special L3:XD caching can + * be enabled through various PAT index modes. Idea is to use this caching mode + * when for example rendering onto the display surface, with the promise that + * KMD will ensure transient cache entries are always flushed by the time we do + * the display flip, since display engine is never coherent with CPU/GPU caches. + */ + +struct drm_i915_private; + +#ifdef I915 +static inline void intel_td_flush(struct drm_i915_private *i915) {} +#else +void intel_td_flush(struct drm_i915_private *i915); +#endif + +#endif diff --git a/drivers/gpu/drm/xe/Makefile b/drivers/gpu/drm/xe/Makefile index e5b1715f721e..401a4492c625 100644 --- a/drivers/gpu/drm/xe/Makefile +++ b/drivers/gpu/drm/xe/Makefile @@ -196,7 +196,8 @@ xe-$(CONFIG_DRM_XE_DISPLAY) += \ display/xe_dsb_buffer.o \ display/xe_fb_pin.o \ display/xe_hdcp_gsc.o \ - display/xe_plane_initial.o + display/xe_plane_initial.o \ + display/xe_tdf.o # SOC code shared with i915 xe-$(CONFIG_DRM_XE_DISPLAY) += \ diff --git a/drivers/gpu/drm/xe/display/xe_tdf.c b/drivers/gpu/drm/xe/display/xe_tdf.c new file mode 100644 index 000000000000..2c0d4e144e09 --- /dev/null +++ b/drivers/gpu/drm/xe/display/xe_tdf.c @@ -0,0 +1,13 @@ +// SPDX-License-Identifier: MIT +/* + * Copyright © 2024 Intel Corporation + */ + +#include "xe_device.h" +#include "intel_display_types.h" +#include "intel_tdf.h" + +void intel_td_flush(struct drm_i915_private *i915) +{ + xe_device_td_flush(i915); +} From patchwork Wed Apr 3 11:22:53 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Vivekanandan, Balasubramani" X-Patchwork-Id: 13615989 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 49810CD1294 for ; Wed, 3 Apr 2024 11:23:44 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 99AD8112A2C; Wed, 3 Apr 2024 11:23:43 +0000 (UTC) Authentication-Results: gabe.freedesktop.org; dkim=pass (2048-bit key; unprotected) header.d=intel.com header.i=@intel.com header.b="hbS0mCKq"; dkim-atps=neutral Received: from mgamail.intel.com (mgamail.intel.com [198.175.65.10]) by gabe.freedesktop.org (Postfix) with ESMTPS id D793F112A2B; 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03 Apr 2024 04:23:42 -0700 X-CSE-ConnectionGUID: urEXMhJmSUSV4JW7kdJtWg== X-CSE-MsgGUID: Gc1+PZUpRB21/PfvOZj9Lg== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.07,177,1708416000"; d="scan'208";a="18358632" Received: from bvivekan-desk.iind.intel.com ([10.190.238.63]) by orviesa009-auth.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 03 Apr 2024 04:23:41 -0700 From: Balasubramani Vivekanandan To: intel-gfx@lists.freedesktop.org, intel-xe@lists.freedesktop.org Cc: Matt Roper , Lucas De Marchi , Balasubramani Vivekanandan Subject: [PATCH v2 25/25] drm/xe/bmg: Enable the display support Date: Wed, 3 Apr 2024 16:52:53 +0530 Message-Id: <20240403112253.1432390-26-balasubramani.vivekanandan@intel.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20240403112253.1432390-1-balasubramani.vivekanandan@intel.com> References: <20240403112253.1432390-1-balasubramani.vivekanandan@intel.com> MIME-Version: 1.0 X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" Enable the display support for Battlemage Signed-off-by: Balasubramani Vivekanandan Reviewed-by: Shekhar Chauhan --- drivers/gpu/drm/xe/xe_pci.c | 1 + 1 file changed, 1 insertion(+) diff --git a/drivers/gpu/drm/xe/xe_pci.c b/drivers/gpu/drm/xe/xe_pci.c index b3158053baee..835c18ec8fb9 100644 --- a/drivers/gpu/drm/xe/xe_pci.c +++ b/drivers/gpu/drm/xe/xe_pci.c @@ -340,6 +340,7 @@ static const struct xe_device_desc lnl_desc = { static const struct xe_device_desc bmg_desc = { DGFX_FEATURES, PLATFORM(XE_BATTLEMAGE), + .has_display = true, .require_force_probe = true, };