From patchwork Wed Apr 3 18:02:24 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Lucas Stach X-Patchwork-Id: 13616561 X-Patchwork-Delegate: kuba@kernel.org Received: from metis.whiteo.stw.pengutronix.de (metis.whiteo.stw.pengutronix.de [185.203.201.7]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id B0688152E11 for ; Wed, 3 Apr 2024 18:02:41 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=185.203.201.7 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1712167365; cv=none; b=KDanCH5B+o2YCfaPRjKlTdGDcrmaWsS9bwfEO/BrW+BDRXYVvWxFXVwqaMSISXo53v2o/1b8FnDIcZAC1Vb8gY/cKYccDbh5oMtd1Oo2mUydmMOGhnR/OAuVQ1Ekij00gs83/2y7MyuwjJ0Tqti9EiyZUdRzjdgJj8XmY21x7vY= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1712167365; c=relaxed/simple; bh=JdjwYqPhDf6w2ahYMzJ2MHjxXKvZXil2sc27dpJ3Ni8=; h=From:To:Cc:Subject:Date:Message-Id:MIME-Version; b=p14iGhtAPtfMKHWKTBKf9Mg5EFc9nQZI6O6xW04TMJNuB2S7fEUd1E2kWW0TfDVBwpsq5mJ9G0qMDhBcVP86NAMYklZ8V7uNVQy3WWaEfNRmjWR0QNvtDP9MsTubVZfTbhc2liDjNT/4SlOKFDDjW9fCNkCZ4k1cvN5LGGaEnIk= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=pengutronix.de; spf=pass smtp.mailfrom=pengutronix.de; arc=none smtp.client-ip=185.203.201.7 Authentication-Results: smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=pengutronix.de Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=pengutronix.de Received: from drehscheibe.grey.stw.pengutronix.de ([2a0a:edc0:0:c01:1d::a2]) by metis.whiteo.stw.pengutronix.de with esmtps (TLS1.3:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.92) (envelope-from ) id 1rs4wO-0008GA-WA; Wed, 03 Apr 2024 20:02:29 +0200 Received: from [2a0a:edc0:0:1101:1d::28] (helo=dude02.red.stw.pengutronix.de) by drehscheibe.grey.stw.pengutronix.de with esmtp (Exim 4.94.2) (envelope-from ) id 1rs4wN-00AE7z-2M; Wed, 03 Apr 2024 20:02:27 +0200 From: Lucas Stach To: Woojung Huh , UNGLinuxDriver@microchip.com, Andrew Lunn , Florian Fainelli , Vladimir Oltean Cc: netdev@vger.kernel.org, kernel@pengutronix.de, patchwork-lst@pengutronix.de Subject: [PATCH 1/3] net: dsa: microchip: lan9372: fix TX PHY access Date: Wed, 3 Apr 2024 20:02:24 +0200 Message-Id: <20240403180226.1641383-1-l.stach@pengutronix.de> X-Mailer: git-send-email 2.39.2 Precedence: bulk X-Mailing-List: netdev@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-SA-Exim-Connect-IP: 2a0a:edc0:0:c01:1d::a2 X-SA-Exim-Mail-From: l.stach@pengutronix.de X-SA-Exim-Scanned: No (on metis.whiteo.stw.pengutronix.de); SAEximRunCond expanded to false X-PTX-Original-Recipient: netdev@vger.kernel.org X-Patchwork-Delegate: kuba@kernel.org On the LAN9372 the 4th internal PHY is a TX PHY instead of a T1 PHY. TX PHYs have a different base register offset. Signed-off-by: Lucas Stach --- drivers/net/dsa/microchip/lan937x_main.c | 3 +++ drivers/net/dsa/microchip/lan937x_reg.h | 1 + 2 files changed, 4 insertions(+) diff --git a/drivers/net/dsa/microchip/lan937x_main.c b/drivers/net/dsa/microchip/lan937x_main.c index b479a628b1ae..6a20cbacc513 100644 --- a/drivers/net/dsa/microchip/lan937x_main.c +++ b/drivers/net/dsa/microchip/lan937x_main.c @@ -55,6 +55,9 @@ static int lan937x_vphy_ind_addr_wr(struct ksz_device *dev, int addr, int reg) u16 addr_base = REG_PORT_T1_PHY_CTRL_BASE; u16 temp; + if (dev->info->chip_id == LAN9372_CHIP_ID && addr == 3) + addr_base = REG_PORT_TX_PHY_CTRL_BASE; + /* get register address based on the logical port */ temp = PORT_CTRL_ADDR(addr, (addr_base + (reg << 2))); diff --git a/drivers/net/dsa/microchip/lan937x_reg.h b/drivers/net/dsa/microchip/lan937x_reg.h index 45b606b6429f..7ecada924023 100644 --- a/drivers/net/dsa/microchip/lan937x_reg.h +++ b/drivers/net/dsa/microchip/lan937x_reg.h @@ -147,6 +147,7 @@ /* 1 - Phy */ #define REG_PORT_T1_PHY_CTRL_BASE 0x0100 +#define REG_PORT_TX_PHY_CTRL_BASE 0x0280 /* 3 - xMII */ #define PORT_SGMII_SEL BIT(7) From patchwork Wed Apr 3 18:02:25 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Lucas Stach X-Patchwork-Id: 13616560 X-Patchwork-Delegate: kuba@kernel.org Received: from metis.whiteo.stw.pengutronix.de (metis.whiteo.stw.pengutronix.de [185.203.201.7]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id B06C6152E15 for ; Wed, 3 Apr 2024 18:02:41 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=185.203.201.7 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1712167364; cv=none; b=ZG86IPy8QmDTEogipiesrJ7UDOtRBgjAK5k2H8lHVnBldBAHn7tfUQxTBGKJyLx5OTkti0llfD6h+6BNYbMKgPBNoI8WDaZ0Wqslj0WhLpKhc2VgzblzXD9IU1xy2BnIENkArTZghqmiuiv1Jx/67PThSbcevWnLBAb6kF5/TFk= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1712167364; c=relaxed/simple; bh=ki4OM5Ry8mnfZfDN11pHYbJpj6KSQ2knegsHZMB+fZE=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=oNt9meO3WWma6jV7zCTX5Ph1z3/aB1YBnsenTqPOXwnSzhxTNgpNqVCCiTyGoRC1GCATBxjhPU/P8eKm0PiTTbctRHTJigvg6Tv3iezdGpgCzug6irMgv3ECFDDkvlg+EtGb+K1l724ETw7IKHReBdqR8ubaM79X8LMlAwbkyYo= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=pengutronix.de; spf=pass smtp.mailfrom=pengutronix.de; arc=none smtp.client-ip=185.203.201.7 Authentication-Results: smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=pengutronix.de Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=pengutronix.de Received: from drehscheibe.grey.stw.pengutronix.de ([2a0a:edc0:0:c01:1d::a2]) by metis.whiteo.stw.pengutronix.de with esmtps (TLS1.3:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.92) (envelope-from ) id 1rs4wO-0008GC-W9; Wed, 03 Apr 2024 20:02:29 +0200 Received: from [2a0a:edc0:0:1101:1d::28] (helo=dude02.red.stw.pengutronix.de) by drehscheibe.grey.stw.pengutronix.de with esmtp (Exim 4.94.2) (envelope-from ) id 1rs4wN-00AE7z-53; Wed, 03 Apr 2024 20:02:27 +0200 From: Lucas Stach To: Woojung Huh , UNGLinuxDriver@microchip.com, Andrew Lunn , Florian Fainelli , Vladimir Oltean Cc: netdev@vger.kernel.org, kernel@pengutronix.de, patchwork-lst@pengutronix.de Subject: [PATCH 2/3] net: dsa: microchip: lan937x: force RGMII interface into PHY mode Date: Wed, 3 Apr 2024 20:02:25 +0200 Message-Id: <20240403180226.1641383-2-l.stach@pengutronix.de> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20240403180226.1641383-1-l.stach@pengutronix.de> References: <20240403180226.1641383-1-l.stach@pengutronix.de> Precedence: bulk X-Mailing-List: netdev@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-SA-Exim-Connect-IP: 2a0a:edc0:0:c01:1d::a2 X-SA-Exim-Mail-From: l.stach@pengutronix.de X-SA-Exim-Scanned: No (on metis.whiteo.stw.pengutronix.de); SAEximRunCond expanded to false X-PTX-Original-Recipient: netdev@vger.kernel.org X-Patchwork-Delegate: kuba@kernel.org The register manual and datasheet documentation for the LAN937x series disagree about the polarity of the MII mode strap. As a consequence there are hardware designs that have the RGMII interface strapped into MAC mode, which is a invalid configuration and will prevent the internal clock from being fed into the port TX interface. Force the MII mode to PHY for RGMII interfaces where this is the only valid mode, to override the inproper strapping. Signed-off-by: Lucas Stach --- drivers/net/dsa/microchip/lan937x_main.c | 11 +++++++++++ drivers/net/dsa/microchip/lan937x_reg.h | 3 +++ 2 files changed, 14 insertions(+) diff --git a/drivers/net/dsa/microchip/lan937x_main.c b/drivers/net/dsa/microchip/lan937x_main.c index 6a20cbacc513..04fa74c7dcbe 100644 --- a/drivers/net/dsa/microchip/lan937x_main.c +++ b/drivers/net/dsa/microchip/lan937x_main.c @@ -217,6 +217,17 @@ void lan937x_config_cpu_port(struct dsa_switch *ds) if (dev->info->cpu_ports & (1 << dp->index)) { dev->cpu_port = dp->index; + /* + * Force RGMII interface into PHY mode, as that's the + * only valid mode, but it may be in MAC mode due to + * incorrect strapping. + */ + if (phy_interface_mode_is_rgmii(dev->ports[dp->index].interface)) { + lan937x_port_cfg(dev, dp->index, + REG_PORT_XMII_CTRL_1, + PORT_MII_MODE_MAC, false); + } + /* enable cpu port */ lan937x_port_setup(dev, dp->index, true); } diff --git a/drivers/net/dsa/microchip/lan937x_reg.h b/drivers/net/dsa/microchip/lan937x_reg.h index 7ecada924023..e36bcb155f54 100644 --- a/drivers/net/dsa/microchip/lan937x_reg.h +++ b/drivers/net/dsa/microchip/lan937x_reg.h @@ -150,6 +150,9 @@ #define REG_PORT_TX_PHY_CTRL_BASE 0x0280 /* 3 - xMII */ +#define REG_PORT_XMII_CTRL_1 0x0301 +#define PORT_MII_MODE_MAC BIT(2) + #define PORT_SGMII_SEL BIT(7) #define PORT_GRXC_ENABLE BIT(0) From patchwork Wed Apr 3 18:02:26 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Lucas Stach X-Patchwork-Id: 13616562 X-Patchwork-Delegate: kuba@kernel.org Received: from metis.whiteo.stw.pengutronix.de (metis.whiteo.stw.pengutronix.de [185.203.201.7]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id B0645152E0D for ; Wed, 3 Apr 2024 18:02:41 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=185.203.201.7 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1712167365; cv=none; b=LiugvHE4IHYexCcZ8ZAh5hA9u7nStqL2QxlW3Icg6czzJiTOLbJvPujpgbQ+0AA03s1k/6wxfTmGAloBVf29lVGQGgCFVvw1QBwmDq4GZztGzGGUCsOjtFyyoromUCuuAqO/WFqXTcIJojJ2Kium8fiBG3agdOQRMsnMWqfND/8= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1712167365; c=relaxed/simple; bh=WnGObgsV1CcvCJj8yb4xkruUyWL7miQ2+aDMKi/RxKM=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=SCyUFg5JZi++wAgZG3UMUgiF+G8aWw6V87DdxR3rVpnv4rvDW/j8oJnr4NSc6qgno/G4bJX5H82GNyWLpqYFu+dEqkSgVO01HMWrlWsfA7wiEDDz0buri34pwmajqeLZOF+6BqWffa4RTNmCWXYcQLT6nN0wc4loma9Yqa3P0fo= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=pengutronix.de; spf=pass smtp.mailfrom=pengutronix.de; arc=none smtp.client-ip=185.203.201.7 Authentication-Results: smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=pengutronix.de Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=pengutronix.de Received: from drehscheibe.grey.stw.pengutronix.de ([2a0a:edc0:0:c01:1d::a2]) by metis.whiteo.stw.pengutronix.de with esmtps (TLS1.3:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.92) (envelope-from ) id 1rs4wO-0008GE-W9; Wed, 03 Apr 2024 20:02:29 +0200 Received: from [2a0a:edc0:0:1101:1d::28] (helo=dude02.red.stw.pengutronix.de) by drehscheibe.grey.stw.pengutronix.de with esmtp (Exim 4.94.2) (envelope-from ) id 1rs4wN-00AE7z-7h; Wed, 03 Apr 2024 20:02:27 +0200 From: Lucas Stach To: Woojung Huh , UNGLinuxDriver@microchip.com, Andrew Lunn , Florian Fainelli , Vladimir Oltean Cc: netdev@vger.kernel.org, kernel@pengutronix.de, patchwork-lst@pengutronix.de Subject: [PATCH 3/3] net: dsa: microchip: lan937x: disable VPHY output Date: Wed, 3 Apr 2024 20:02:26 +0200 Message-Id: <20240403180226.1641383-3-l.stach@pengutronix.de> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20240403180226.1641383-1-l.stach@pengutronix.de> References: <20240403180226.1641383-1-l.stach@pengutronix.de> Precedence: bulk X-Mailing-List: netdev@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-SA-Exim-Connect-IP: 2a0a:edc0:0:c01:1d::a2 X-SA-Exim-Mail-From: l.stach@pengutronix.de X-SA-Exim-Scanned: No (on metis.whiteo.stw.pengutronix.de); SAEximRunCond expanded to false X-PTX-Original-Recipient: netdev@vger.kernel.org X-Patchwork-Delegate: kuba@kernel.org While the documented VPHY out-of-reset configuration should autonegotiate the maximum supported link speed on the CPU interface, that doesn't work on RGMII links, where the VPHY negotiates 100MBit speed. This causes the RGMII TX interface to run with a wrong clock rate. Disable the VPHY output altogether, so it doesn't interfere with the CPU interface configuration set via fixed-link. The VPHY is a compatibility functionality to be able to attach network drivers without fixed-link support to the switch, which generally should not be needed with linux network drivers. Signed-off-by: Lucas Stach Reviewed-by: Andrew Lunn --- drivers/net/dsa/microchip/lan937x_main.c | 3 +++ drivers/net/dsa/microchip/lan937x_reg.h | 4 ++++ 2 files changed, 7 insertions(+) diff --git a/drivers/net/dsa/microchip/lan937x_main.c b/drivers/net/dsa/microchip/lan937x_main.c index 04fa74c7dcbe..9db1d278ee9b 100644 --- a/drivers/net/dsa/microchip/lan937x_main.c +++ b/drivers/net/dsa/microchip/lan937x_main.c @@ -400,6 +400,9 @@ int lan937x_setup(struct dsa_switch *ds) lan937x_cfg(dev, REG_SW_GLOBAL_OUTPUT_CTRL__1, (SW_CLK125_ENB | SW_CLK25_ENB), true); + /* disable VPHY output*/ + ksz_rmw32(dev, REG_SW_CFG_STRAP_OVR, SW_VPHY_DISABLE, SW_VPHY_DISABLE); + return 0; } diff --git a/drivers/net/dsa/microchip/lan937x_reg.h b/drivers/net/dsa/microchip/lan937x_reg.h index e36bcb155f54..be553e23a964 100644 --- a/drivers/net/dsa/microchip/lan937x_reg.h +++ b/drivers/net/dsa/microchip/lan937x_reg.h @@ -37,6 +37,10 @@ #define SW_CLK125_ENB BIT(1) #define SW_CLK25_ENB BIT(0) +/* 2 - PHY Control */ +#define REG_SW_CFG_STRAP_OVR 0x214 +#define SW_VPHY_DISABLE BIT(31) + /* 3 - Operation Control */ #define REG_SW_OPERATION 0x0300