From patchwork Wed Apr 3 20:34:59 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Lad, Prabhakar" X-Patchwork-Id: 13616656 X-Patchwork-Delegate: geert@linux-m68k.org Received: from mail-wm1-f52.google.com (mail-wm1-f52.google.com [209.85.128.52]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 3B0C9156228; Wed, 3 Apr 2024 20:36:35 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.128.52 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1712176597; cv=none; b=H2gCL+JbCD3UcAN090TwqP1sknrJfBB7xrOTpP7JiaN68newS3N+wh1elvBFWULfZBoPY1dJ4vObOstSKEYlrwhZZbdPGQ0aYquPumSSL3H0EUy9iyzAWNEsayJjFqips3/j7DYYbm3YKjl6ivxicf++oA+HvXcj+v+KJKJFCog= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1712176597; c=relaxed/simple; bh=D3zZQSdy/uIrKwujVFSPQFERPXpObvA/I+ilYLzrLac=; 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The IRQC block on the RZ/Five SoC is almost identical to the one found on the RZ/G2L SoC, with the only difference being that it has additional mask control registers for NMI/IRQ/TINT. Hence new compatible string "renesas,r9a07g043f-irqc" is added for RZ/Five SoC. Signed-off-by: Lad Prabhakar Acked-by: Krzysztof Kozlowski Reviewed-by: Geert Uytterhoeven --- v1->v2 - Dropped the checks for interrupts as its already handled - Added SoC specific compat string --- .../renesas,rzg2l-irqc.yaml | 17 ++++++++++------- 1 file changed, 10 insertions(+), 7 deletions(-) diff --git a/Documentation/devicetree/bindings/interrupt-controller/renesas,rzg2l-irqc.yaml b/Documentation/devicetree/bindings/interrupt-controller/renesas,rzg2l-irqc.yaml index daef4ee06f4e..2a871cbf6f87 100644 --- a/Documentation/devicetree/bindings/interrupt-controller/renesas,rzg2l-irqc.yaml +++ b/Documentation/devicetree/bindings/interrupt-controller/renesas,rzg2l-irqc.yaml @@ -21,13 +21,16 @@ description: | properties: compatible: - items: - - enum: - - renesas,r9a07g043u-irqc # RZ/G2UL - - renesas,r9a07g044-irqc # RZ/G2{L,LC} - - renesas,r9a07g054-irqc # RZ/V2L - - renesas,r9a08g045-irqc # RZ/G3S - - const: renesas,rzg2l-irqc + oneOf: + - items: + - enum: + - renesas,r9a07g043u-irqc # RZ/G2UL + - renesas,r9a07g044-irqc # RZ/G2{L,LC} + - renesas,r9a07g054-irqc # RZ/V2L + - renesas,r9a08g045-irqc # RZ/G3S + - const: renesas,rzg2l-irqc + - items: + - const: renesas,r9a07g043f-irqc # RZ/Five '#interrupt-cells': description: The first cell should contain a macro RZG2L_{NMI,IRQX} included in the From patchwork Wed Apr 3 20:35:00 2024 Content-Type: text/plain; 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Introduce masking/unmasking support for IRQ and TINT interrupts in IRQC controller driver. Two new registers, IMSK and TMSK, are defined to handle masking on RZ/Five SoC. The implementation utilizes a new data structure, `struct rzg2l_irqc_data`, to determine mask support for a specific controller instance. Signed-off-by: Lad Prabhakar --- v1->v2 - Added IRQCHIP_MATCH() for RZ/Five - Retaining a copy of OF data in priv - Rebased the changes --- drivers/irqchip/irq-renesas-rzg2l.c | 137 +++++++++++++++++++++++++++- 1 file changed, 132 insertions(+), 5 deletions(-) diff --git a/drivers/irqchip/irq-renesas-rzg2l.c b/drivers/irqchip/irq-renesas-rzg2l.c index f6484bf15e0b..6fa8d65605dc 100644 --- a/drivers/irqchip/irq-renesas-rzg2l.c +++ b/drivers/irqchip/irq-renesas-rzg2l.c @@ -37,6 +37,8 @@ #define TSSEL_SHIFT(n) (8 * (n)) #define TSSEL_MASK GENMASK(7, 0) #define IRQ_MASK 0x3 +#define IMSK 0x10010 +#define TMSK 0x10020 #define TSSR_OFFSET(n) ((n) % 4) #define TSSR_INDEX(n) ((n) / 4) @@ -66,15 +68,25 @@ struct rzg2l_irqc_reg_cache { u32 titsr[2]; }; +/** + * struct rzg2l_irqc_of_data - OF data structure + * @mask_supported: Indicates if mask registers are available + */ +struct rzg2l_irqc_of_data { + bool mask_supported; +}; + /** * struct rzg2l_irqc_priv - IRQ controller private data structure * @base: Controller's base address + * @data: OF data pointer * @fwspec: IRQ firmware specific data * @lock: Lock to serialize access to hardware registers * @cache: Registers cache for suspend/resume */ static struct rzg2l_irqc_priv { void __iomem *base; + const struct rzg2l_irqc_of_data *data; struct irq_fwspec fwspec[IRQC_NUM_IRQ]; raw_spinlock_t lock; struct rzg2l_irqc_reg_cache cache; @@ -138,18 +150,102 @@ static void rzg2l_irqc_eoi(struct irq_data *d) irq_chip_eoi_parent(d); } +static void rzg2l_irqc_mask_irq_interrupt(struct rzg2l_irqc_priv *priv, + unsigned int hwirq) +{ + u32 imsk = readl_relaxed(priv->base + IMSK); + u32 bit = BIT(hwirq - IRQC_IRQ_START); + + writel_relaxed(imsk | bit, priv->base + IMSK); +} + +static void rzg2l_irqc_unmask_irq_interrupt(struct rzg2l_irqc_priv *priv, + unsigned int hwirq) +{ + u32 imsk = readl_relaxed(priv->base + IMSK); + u32 bit = BIT(hwirq - IRQC_IRQ_START); + + writel_relaxed(imsk & ~bit, priv->base + IMSK); +} + +static void rzg2l_irqc_mask_tint_interrupt(struct rzg2l_irqc_priv *priv, + unsigned int hwirq) +{ + u32 tmsk = readl_relaxed(priv->base + TMSK); + u32 bit = BIT(hwirq - IRQC_TINT_START); + + writel_relaxed(tmsk | bit, priv->base + TMSK); +} + +static void rzg2l_irqc_unmask_tint_interrupt(struct rzg2l_irqc_priv *priv, + unsigned int hwirq) +{ + u32 tmsk = readl_relaxed(priv->base + TMSK); + u32 bit = BIT(hwirq - IRQC_TINT_START); + + writel_relaxed(tmsk & ~bit, priv->base + TMSK); +} + +/* Must be called while priv->lock is held */ +static void rzg2l_irqc_mask_once(struct rzg2l_irqc_priv *priv, unsigned int hwirq) +{ + if (!priv->data->mask_supported) + return; + + if (hwirq >= IRQC_IRQ_START && hwirq <= IRQC_IRQ_COUNT) + rzg2l_irqc_mask_irq_interrupt(priv, hwirq); + else if (hwirq >= IRQC_TINT_START && hwirq < IRQC_NUM_IRQ) + rzg2l_irqc_mask_tint_interrupt(priv, hwirq); +} + +static void rzg2l_irqc_mask(struct irq_data *d) +{ + struct rzg2l_irqc_priv *priv = irq_data_to_priv(d); + + raw_spin_lock(&priv->lock); + rzg2l_irqc_mask_once(priv, irqd_to_hwirq(d)); + raw_spin_unlock(&priv->lock); + irq_chip_mask_parent(d); +} + +/* Must be called while priv->lock is held */ +static void rzg2l_irqc_unmask_once(struct rzg2l_irqc_priv *priv, unsigned int hwirq) +{ + if (!priv->data->mask_supported) + return; + + if (hwirq >= IRQC_IRQ_START && hwirq <= IRQC_IRQ_COUNT) + rzg2l_irqc_unmask_irq_interrupt(priv, hwirq); + else if (hwirq >= IRQC_TINT_START && hwirq < IRQC_NUM_IRQ) + rzg2l_irqc_unmask_tint_interrupt(priv, hwirq); +} + +static void rzg2l_irqc_unmask(struct irq_data *d) +{ + struct rzg2l_irqc_priv *priv = irq_data_to_priv(d); + + raw_spin_lock(&priv->lock); + rzg2l_irqc_unmask_once(priv, irqd_to_hwirq(d)); + raw_spin_unlock(&priv->lock); + irq_chip_unmask_parent(d); +} + static void rzg2l_tint_irq_endisable(struct irq_data *d, bool enable) { + struct rzg2l_irqc_priv *priv = irq_data_to_priv(d); unsigned int hw_irq = irqd_to_hwirq(d); if (hw_irq >= IRQC_TINT_START && hw_irq < IRQC_NUM_IRQ) { - struct rzg2l_irqc_priv *priv = irq_data_to_priv(d); u32 offset = hw_irq - IRQC_TINT_START; u32 tssr_offset = TSSR_OFFSET(offset); u8 tssr_index = TSSR_INDEX(offset); u32 reg; raw_spin_lock(&priv->lock); + if (enable) + rzg2l_irqc_unmask_once(priv, hw_irq); + else + rzg2l_irqc_mask_once(priv, hw_irq); reg = readl_relaxed(priv->base + TSSR(tssr_index)); if (enable) reg |= TIEN << TSSEL_SHIFT(tssr_offset); @@ -157,6 +253,13 @@ static void rzg2l_tint_irq_endisable(struct irq_data *d, bool enable) reg &= ~(TIEN << TSSEL_SHIFT(tssr_offset)); writel_relaxed(reg, priv->base + TSSR(tssr_index)); raw_spin_unlock(&priv->lock); + } else { + raw_spin_lock(&priv->lock); + if (enable) + rzg2l_irqc_unmask_once(priv, hw_irq); + else + rzg2l_irqc_mask_once(priv, hw_irq); + raw_spin_unlock(&priv->lock); } } @@ -324,8 +427,8 @@ static struct syscore_ops rzg2l_irqc_syscore_ops = { static const struct irq_chip irqc_chip = { .name = "rzg2l-irqc", .irq_eoi = rzg2l_irqc_eoi, - .irq_mask = irq_chip_mask_parent, - .irq_unmask = irq_chip_unmask_parent, + .irq_mask = rzg2l_irqc_mask, + .irq_unmask = rzg2l_irqc_unmask, .irq_disable = rzg2l_irqc_irq_disable, .irq_enable = rzg2l_irqc_irq_enable, .irq_get_irqchip_state = irq_chip_get_parent_state, @@ -401,7 +504,16 @@ static int rzg2l_irqc_parse_interrupts(struct rzg2l_irqc_priv *priv, return 0; } -static int rzg2l_irqc_init(struct device_node *node, struct device_node *parent) +static const struct rzg2l_irqc_of_data rzg2l_irqc_mask_supported_data = { + .mask_supported = true, +}; + +static const struct rzg2l_irqc_of_data rzg2l_irqc_default_data = { + .mask_supported = false, +}; + +static int rzg2l_irqc_init(struct device_node *node, struct device_node *parent, + const struct rzg2l_irqc_of_data *of_data) { struct irq_domain *irq_domain, *parent_domain; struct platform_device *pdev; @@ -422,6 +534,8 @@ static int rzg2l_irqc_init(struct device_node *node, struct device_node *parent) if (!rzg2l_irqc_data) return -ENOMEM; + rzg2l_irqc_data->data = of_data; + rzg2l_irqc_data->base = devm_of_iomap(&pdev->dev, pdev->dev.of_node, 0, NULL); if (IS_ERR(rzg2l_irqc_data->base)) return PTR_ERR(rzg2l_irqc_data->base); @@ -472,8 +586,21 @@ static int rzg2l_irqc_init(struct device_node *node, struct device_node *parent) return ret; } +static int __init rzg2l_irqc_default_init(struct device_node *node, + struct device_node *parent) +{ + return rzg2l_irqc_init(node, parent, &rzg2l_irqc_default_data); +} + +static int __init rzg2l_irqc_mask_supported_init(struct device_node *node, + struct device_node *parent) +{ + return rzg2l_irqc_init(node, parent, &rzg2l_irqc_mask_supported_data); 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Wed, 03 Apr 2024 13:36:36 -0700 (PDT) Received: from prasmi.home ([2a00:23c8:2500:a01:5eb:3d93:f2b6:25e8]) by smtp.gmail.com with ESMTPSA id p4-20020a05600c468400b00415f496b9b7sm244910wmo.39.2024.04.03.13.36.35 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 03 Apr 2024 13:36:36 -0700 (PDT) From: Prabhakar X-Google-Original-From: Prabhakar To: Geert Uytterhoeven , Thomas Gleixner , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Magnus Damm , Paul Walmsley , Palmer Dabbelt , Albert Ou Cc: linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, linux-renesas-soc@vger.kernel.org, linux-riscv@lists.infradead.org, Prabhakar , Lad Prabhakar Subject: [PATCH v2 3/5] riscv: dts: renesas: r9a07g043f: Add IRQC node to RZ/Five SoC DTSI Date: Wed, 3 Apr 2024 21:35:01 +0100 Message-Id: <20240403203503.634465-4-prabhakar.mahadev-lad.rj@bp.renesas.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240403203503.634465-1-prabhakar.mahadev-lad.rj@bp.renesas.com> References: <20240403203503.634465-1-prabhakar.mahadev-lad.rj@bp.renesas.com> Precedence: bulk X-Mailing-List: linux-renesas-soc@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 From: Lad Prabhakar Add the IRQC node to RZ/Five (R9A07G043F) SoC DTSI. Signed-off-by: Lad Prabhakar Reviewed-by: Geert Uytterhoeven --- v1->v2 - Dropped using SOC_PERIPHERAL_IRQ() macro --- arch/riscv/boot/dts/renesas/r9a07g043f.dtsi | 75 +++++++++++++++++++++ 1 file changed, 75 insertions(+) diff --git a/arch/riscv/boot/dts/renesas/r9a07g043f.dtsi b/arch/riscv/boot/dts/renesas/r9a07g043f.dtsi index f35324b9173c..e0ddf8f602c7 100644 --- a/arch/riscv/boot/dts/renesas/r9a07g043f.dtsi +++ b/arch/riscv/boot/dts/renesas/r9a07g043f.dtsi @@ -54,6 +54,81 @@ &soc { dma-noncoherent; interrupt-parent = <&plic>; + irqc: interrupt-controller@110a0000 { + compatible = "renesas,r9a07g043f-irqc"; + reg = <0 0x110a0000 0 0x20000>; + #interrupt-cells = <2>; + #address-cells = <0>; + interrupt-controller; + interrupts = <32 IRQ_TYPE_LEVEL_HIGH>, + <33 IRQ_TYPE_LEVEL_HIGH>, + <34 IRQ_TYPE_LEVEL_HIGH>, + <35 IRQ_TYPE_LEVEL_HIGH>, + <36 IRQ_TYPE_LEVEL_HIGH>, + <37 IRQ_TYPE_LEVEL_HIGH>, + <38 IRQ_TYPE_LEVEL_HIGH>, + <39 IRQ_TYPE_LEVEL_HIGH>, + <40 IRQ_TYPE_LEVEL_HIGH>, + <476 IRQ_TYPE_LEVEL_HIGH>, + <477 IRQ_TYPE_LEVEL_HIGH>, + <478 IRQ_TYPE_LEVEL_HIGH>, + <479 IRQ_TYPE_LEVEL_HIGH>, + <480 IRQ_TYPE_LEVEL_HIGH>, + <481 IRQ_TYPE_LEVEL_HIGH>, + <482 IRQ_TYPE_LEVEL_HIGH>, + <483 IRQ_TYPE_LEVEL_HIGH>, + <484 IRQ_TYPE_LEVEL_HIGH>, + <485 IRQ_TYPE_LEVEL_HIGH>, + <486 IRQ_TYPE_LEVEL_HIGH>, + <487 IRQ_TYPE_LEVEL_HIGH>, + <488 IRQ_TYPE_LEVEL_HIGH>, + <489 IRQ_TYPE_LEVEL_HIGH>, + <490 IRQ_TYPE_LEVEL_HIGH>, + <491 IRQ_TYPE_LEVEL_HIGH>, + <492 IRQ_TYPE_LEVEL_HIGH>, + <493 IRQ_TYPE_LEVEL_HIGH>, + <494 IRQ_TYPE_LEVEL_HIGH>, + <495 IRQ_TYPE_LEVEL_HIGH>, + <496 IRQ_TYPE_LEVEL_HIGH>, + <497 IRQ_TYPE_LEVEL_HIGH>, + <498 IRQ_TYPE_LEVEL_HIGH>, + <499 IRQ_TYPE_LEVEL_HIGH>, + <500 IRQ_TYPE_LEVEL_HIGH>, + <501 IRQ_TYPE_LEVEL_HIGH>, + <502 IRQ_TYPE_LEVEL_HIGH>, + <503 IRQ_TYPE_LEVEL_HIGH>, + <504 IRQ_TYPE_LEVEL_HIGH>, + <505 IRQ_TYPE_LEVEL_HIGH>, + <506 IRQ_TYPE_LEVEL_HIGH>, + <507 IRQ_TYPE_LEVEL_HIGH>, + <57 IRQ_TYPE_LEVEL_HIGH>, + <66 IRQ_TYPE_EDGE_RISING>, + <67 IRQ_TYPE_EDGE_RISING>, + <68 IRQ_TYPE_EDGE_RISING>, + <69 IRQ_TYPE_EDGE_RISING>, + <70 IRQ_TYPE_EDGE_RISING>, + <71 IRQ_TYPE_EDGE_RISING>; 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Wed, 03 Apr 2024 13:36:38 -0700 (PDT) Received: from prasmi.home ([2a00:23c8:2500:a01:5eb:3d93:f2b6:25e8]) by smtp.gmail.com with ESMTPSA id p4-20020a05600c468400b00415f496b9b7sm244910wmo.39.2024.04.03.13.36.37 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 03 Apr 2024 13:36:37 -0700 (PDT) From: Prabhakar X-Google-Original-From: Prabhakar To: Geert Uytterhoeven , Thomas Gleixner , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Magnus Damm , Paul Walmsley , Palmer Dabbelt , Albert Ou Cc: linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, linux-renesas-soc@vger.kernel.org, linux-riscv@lists.infradead.org, Prabhakar , Lad Prabhakar Subject: [PATCH v2 4/5] arm64: dts: renesas: r9a07g043: Move interrupt-parent property to common DTSI Date: Wed, 3 Apr 2024 21:35:02 +0100 Message-Id: <20240403203503.634465-5-prabhakar.mahadev-lad.rj@bp.renesas.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240403203503.634465-1-prabhakar.mahadev-lad.rj@bp.renesas.com> References: <20240403203503.634465-1-prabhakar.mahadev-lad.rj@bp.renesas.com> Precedence: bulk X-Mailing-List: linux-renesas-soc@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 From: Lad Prabhakar Now that we have added support for IRQC to both RZ/Five and RZ/G2UL SoCs we can move the interrupt-parent for pinctrl node back to the common shared r9a07g043.dtsi file. Signed-off-by: Lad Prabhakar Reviewed-by: Geert Uytterhoeven --- v1->v2 - Included RB tag from Geert --- arch/arm64/boot/dts/renesas/r9a07g043.dtsi | 1 + arch/arm64/boot/dts/renesas/r9a07g043u.dtsi | 4 ---- 2 files changed, 1 insertion(+), 4 deletions(-) diff --git a/arch/arm64/boot/dts/renesas/r9a07g043.dtsi b/arch/arm64/boot/dts/renesas/r9a07g043.dtsi index 766c54b91acc..6212ee550f33 100644 --- a/arch/arm64/boot/dts/renesas/r9a07g043.dtsi +++ b/arch/arm64/boot/dts/renesas/r9a07g043.dtsi @@ -598,6 +598,7 @@ pinctrl: pinctrl@11030000 { gpio-ranges = <&pinctrl 0 0 152>; #interrupt-cells = <2>; interrupt-controller; + interrupt-parent = <&irqc>; clocks = <&cpg CPG_MOD R9A07G043_GPIO_HCLK>; power-domains = <&cpg>; resets = <&cpg R9A07G043_GPIO_RSTN>, diff --git a/arch/arm64/boot/dts/renesas/r9a07g043u.dtsi b/arch/arm64/boot/dts/renesas/r9a07g043u.dtsi index 964b0a475eee..165bfcfef3bc 100644 --- a/arch/arm64/boot/dts/renesas/r9a07g043u.dtsi +++ b/arch/arm64/boot/dts/renesas/r9a07g043u.dtsi @@ -54,10 +54,6 @@ timer { }; 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Wed, 03 Apr 2024 13:36:38 -0700 (PDT) From: Prabhakar X-Google-Original-From: Prabhakar To: Geert Uytterhoeven , Thomas Gleixner , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Magnus Damm , Paul Walmsley , Palmer Dabbelt , Albert Ou Cc: linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, linux-renesas-soc@vger.kernel.org, linux-riscv@lists.infradead.org, Prabhakar , Lad Prabhakar Subject: [PATCH v2 5/5] riscv: dts: renesas: rzfive-smarc-som: Drop deleting interrupt properties from ETH0/1 nodes Date: Wed, 3 Apr 2024 21:35:03 +0100 Message-Id: <20240403203503.634465-6-prabhakar.mahadev-lad.rj@bp.renesas.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240403203503.634465-1-prabhakar.mahadev-lad.rj@bp.renesas.com> References: <20240403203503.634465-1-prabhakar.mahadev-lad.rj@bp.renesas.com> Precedence: bulk X-Mailing-List: linux-renesas-soc@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 From: Lad Prabhakar Now that we have enabled IRQC support for RZ/Five SoC switch to interrupt mode for ethernet0/1 PHYs instead of polling mode. Signed-off-by: Lad Prabhakar Reviewed-by: Geert Uytterhoeven --- v1->v2 - Included RB tag from Geert --- .../riscv/boot/dts/renesas/rzfive-smarc-som.dtsi | 16 ---------------- 1 file changed, 16 deletions(-) diff --git a/arch/riscv/boot/dts/renesas/rzfive-smarc-som.dtsi b/arch/riscv/boot/dts/renesas/rzfive-smarc-som.dtsi index 72d9b6fba526..86b2f15375ec 100644 --- a/arch/riscv/boot/dts/renesas/rzfive-smarc-som.dtsi +++ b/arch/riscv/boot/dts/renesas/rzfive-smarc-som.dtsi @@ -7,22 +7,6 @@ #include -#if (!SW_ET0_EN_N) -ð0 { - phy0: ethernet-phy@7 { - /delete-property/ interrupt-parent; - /delete-property/ interrupts; - }; -}; -#endif - -ð1 { - phy1: ethernet-phy@7 { - /delete-property/ interrupt-parent; - /delete-property/ interrupts; - }; -}; - &sbc { status = "disabled"; };