From patchwork Sun Apr 7 21:32:35 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Christoph_M=C3=BCllner?= X-Patchwork-Id: 13620297 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id EFDC3CD1296 for ; Sun, 7 Apr 2024 21:33:04 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:MIME-Version:References:In-Reply-To: Message-ID:Date:Subject:Cc:To:From:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; bh=VaQ1HylM5lwDLLlORFmy7JIv/U4E6Vr3kNi0j8GEI3U=; b=jr8q41nhE7j03g OM3aKd5rH5LNxDl7NrQvfW2HDIcgwE5cQkqvpSeqMHjp3WJmSsn0XKHYtv7zGMXmqQ74/qwwndNtI qllMF4gj3PC5rVerm0kzPhq4Jfs/e6mkZeFREIe50AnDLdZjgmpiDrt1sUX+BZaBr7efL7sySHY0F O96getns58vobyg4+Q58L3DaAUbYBe1B9x0OAAzJ0eA9i4K30O91UmOPDrzT/rSnGXEUoH40COe/s ummDd2jzd7HZAUOO7MFEBweMp9fezWsl7XILs/+eTgUrIhdlVRVhComVZ4qVSW4tqcwUNFPBIM4Fa vh5c8B04x6Fhn6XKmiuQ==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.97.1 #2 (Red Hat Linux)) id 1rta88-0000000DYZF-0ZhA; Sun, 07 Apr 2024 21:32:48 +0000 Received: from mail-lj1-x22f.google.com ([2a00:1450:4864:20::22f]) by bombadil.infradead.org with esmtps (Exim 4.97.1 #2 (Red Hat Linux)) id 1rta83-0000000DYY1-3n7r for linux-riscv@lists.infradead.org; Sun, 07 Apr 2024 21:32:45 +0000 Received: by mail-lj1-x22f.google.com with SMTP id 38308e7fff4ca-2d48d75ab70so52171431fa.0 for ; Sun, 07 Apr 2024 14:32:42 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=vrull.eu; s=google; t=1712525561; x=1713130361; darn=lists.infradead.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=4EsNSIHIYC4W6bV2ld6cL2XgDhSvlKY5N8B8yWmcW/U=; b=kIyfg8TByfRPbbLnrKFC4Qe+GKl/JWH/2CPEtx/aIMaIO5O2NS/8W3cV0sani4iarq ug6Ws1y2D7E08Q1kryNODb1uUlkkCqnWBBkMX1kKATMmuwbXmjKtHrnxsGeWhnEn4H3h tOq06KPkYlle5rg0QVaw212FfsHZ4WJhHFunbJkuhdKOVwOAGcb1vmu/kiWAppVhz93B 6IlOGCoFOC+HTpG565HaUxcFflmcOcYbjvvJrlLiUc4yE4uNSonV0ZaJsIHsVsj1KI2d tI4socR6nK0r2p5A2r4GQtvet6UmEfl/s7ZzW1Y9tqRBUrpbkVo8UEPJNIJbHgbYzXX1 1MuQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1712525561; x=1713130361; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=4EsNSIHIYC4W6bV2ld6cL2XgDhSvlKY5N8B8yWmcW/U=; b=P8wPS18Hw/Qwa0l4iUzUP6WABIQUQGYcooWOaGv7Se3BmqgFIUbCB45fvW5p4qOxUb eGK8AfOTeWKPap6KYZhce6yWqAM48SJMBGTRDIfWwyYK4UlHwq8iflNZPapI+frTk8/P tdB5PXh96vlKq/PF1n4Mo97aM0ftIvnNGpH/Umty8t+E7EjQIqXLrPUluS3foQTWYRj9 nRuWd4c0gD1li5ciuvp+6R4/9VP35PUxKkDf6P5/XL2fDflx5uT+hZVKiI5nEGlJJSex DcHHjErFgq82myzikyqMpeecL2j7T/BBjd56IMpRYKg5+T7oCxn8vpmp/owebs+o3m7U G5Sw== X-Gm-Message-State: AOJu0YxS6VURCfRWV1Bg+V1gAmPOgF8kVpfhH8s/ftbbM0H75ww4UtOD 9ZtUcp4w5exW/OKCrF/XS0uUvtY2Qt6stbF+rdj+HP7295SKKV0PCSEVpUrXcJDmi2kVi/ret58 sUhw= X-Google-Smtp-Source: AGHT+IGi22D+aAqEe+3xMw9LUgzcozlZLoUYTQmYP6THAXpqnmjX0IEtXPFfJdDttmWTP1xPE/azBw== X-Received: by 2002:a2e:b00c:0:b0:2d4:9201:d505 with SMTP id y12-20020a2eb00c000000b002d49201d505mr4908747ljk.51.1712525560966; Sun, 07 Apr 2024 14:32:40 -0700 (PDT) Received: from antares.fritz.box (62-178-148-172.cable.dynamic.surfer.at. [62.178.148.172]) by smtp.gmail.com with ESMTPSA id i2-20020a50fc02000000b0056e22be831dsm3267562edr.42.2024.04.07.14.32.39 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 07 Apr 2024 14:32:40 -0700 (PDT) From: =?utf-8?q?Christoph_M=C3=BCllner?= To: linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org, Palmer Dabbelt , Paul Walmsley , Albert Ou , Philipp Tomsich , =?utf-8?b?QmrDtnJuIFTDtnBlbA==?= , Daniel Henrique Barboza , Heiko Stuebner , Cooper Qu , Zhiwei Liu , Huang Tao , Alistair Francis , Andrew Jones , Conor Dooley , Qingfang Deng , Alexandre Ghiti , Samuel Holland Cc: =?utf-8?q?Christoph_M=C3=BCllner?= , Conor Dooley Subject: [PATCH v3 1/2] riscv: thead: Rename T-Head PBMT to MAE Date: Sun, 7 Apr 2024 23:32:35 +0200 Message-ID: <20240407213236.2121592-2-christoph.muellner@vrull.eu> X-Mailer: git-send-email 2.44.0 In-Reply-To: <20240407213236.2121592-1-christoph.muellner@vrull.eu> References: <20240407213236.2121592-1-christoph.muellner@vrull.eu> MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20240407_143243_969955_BE1D85AF X-CRM114-Status: GOOD ( 15.15 ) X-BeenThere: linux-riscv@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-riscv" Errors-To: linux-riscv-bounces+linux-riscv=archiver.kernel.org@lists.infradead.org T-Head's vendor extension to set page attributes has the name MAE (memory attribute extension). Let's rename it, so it is clear what this referes to. Link: https://github.com/T-head-Semi/thead-extension-spec/blob/master/xtheadmae.adoc Reviewed-by: Conor Dooley Signed-off-by: Christoph Müllner --- arch/riscv/Kconfig.errata | 8 ++++---- arch/riscv/errata/thead/errata.c | 10 +++++----- arch/riscv/include/asm/errata_list.h | 20 ++++++++++---------- 3 files changed, 19 insertions(+), 19 deletions(-) diff --git a/arch/riscv/Kconfig.errata b/arch/riscv/Kconfig.errata index 910ba8837add..2acc7d876e1f 100644 --- a/arch/riscv/Kconfig.errata +++ b/arch/riscv/Kconfig.errata @@ -82,14 +82,14 @@ config ERRATA_THEAD Otherwise, please say "N" here to avoid unnecessary overhead. -config ERRATA_THEAD_PBMT - bool "Apply T-Head memory type errata" +config ERRATA_THEAD_MAE + bool "Apply T-Head's memory attribute extension (XTheadMae) errata" depends on ERRATA_THEAD && 64BIT && MMU select RISCV_ALTERNATIVE_EARLY default y help - This will apply the memory type errata to handle the non-standard - memory type bits in page-table-entries on T-Head SoCs. + This will apply the memory attribute extension errata to handle the + non-standard PTE utilization on T-Head SoCs (XTheadMae). If you don't know what to do here, say "Y". diff --git a/arch/riscv/errata/thead/errata.c b/arch/riscv/errata/thead/errata.c index b1c410bbc1ae..6e7ee1f16bee 100644 --- a/arch/riscv/errata/thead/errata.c +++ b/arch/riscv/errata/thead/errata.c @@ -19,10 +19,10 @@ #include #include -static bool errata_probe_pbmt(unsigned int stage, - unsigned long arch_id, unsigned long impid) +static bool errata_probe_mae(unsigned int stage, + unsigned long arch_id, unsigned long impid) { - if (!IS_ENABLED(CONFIG_ERRATA_THEAD_PBMT)) + if (!IS_ENABLED(CONFIG_ERRATA_THEAD_MAE)) return false; if (arch_id != 0 || impid != 0) @@ -140,8 +140,8 @@ static u32 thead_errata_probe(unsigned int stage, { u32 cpu_req_errata = 0; - if (errata_probe_pbmt(stage, archid, impid)) - cpu_req_errata |= BIT(ERRATA_THEAD_PBMT); + if (errata_probe_mae(stage, archid, impid)) + cpu_req_errata |= BIT(ERRATA_THEAD_MAE); errata_probe_cmo(stage, archid, impid); diff --git a/arch/riscv/include/asm/errata_list.h b/arch/riscv/include/asm/errata_list.h index 1f2dbfb8a8bf..efd851e1b483 100644 --- a/arch/riscv/include/asm/errata_list.h +++ b/arch/riscv/include/asm/errata_list.h @@ -23,7 +23,7 @@ #endif #ifdef CONFIG_ERRATA_THEAD -#define ERRATA_THEAD_PBMT 0 +#define ERRATA_THEAD_MAE 0 #define ERRATA_THEAD_PMU 1 #define ERRATA_THEAD_NUMBER 2 #endif @@ -53,20 +53,20 @@ asm(ALTERNATIVE("sfence.vma %0", "sfence.vma", SIFIVE_VENDOR_ID, \ * in the default case. */ #define ALT_SVPBMT_SHIFT 61 -#define ALT_THEAD_PBMT_SHIFT 59 +#define ALT_THEAD_MAE_SHIFT 59 #define ALT_SVPBMT(_val, prot) \ asm(ALTERNATIVE_2("li %0, 0\t\nnop", \ "li %0, %1\t\nslli %0,%0,%3", 0, \ RISCV_ISA_EXT_SVPBMT, CONFIG_RISCV_ISA_SVPBMT, \ "li %0, %2\t\nslli %0,%0,%4", THEAD_VENDOR_ID, \ - ERRATA_THEAD_PBMT, CONFIG_ERRATA_THEAD_PBMT) \ + ERRATA_THEAD_MAE, CONFIG_ERRATA_THEAD_MAE) \ : "=r"(_val) \ : "I"(prot##_SVPBMT >> ALT_SVPBMT_SHIFT), \ - "I"(prot##_THEAD >> ALT_THEAD_PBMT_SHIFT), \ + "I"(prot##_THEAD >> ALT_THEAD_MAE_SHIFT), \ "I"(ALT_SVPBMT_SHIFT), \ - "I"(ALT_THEAD_PBMT_SHIFT)) + "I"(ALT_THEAD_MAE_SHIFT)) -#ifdef CONFIG_ERRATA_THEAD_PBMT +#ifdef CONFIG_ERRATA_THEAD_MAE /* * IO/NOCACHE memory types are handled together with svpbmt, * so on T-Head chips, check if no other memory type is set, @@ -83,11 +83,11 @@ asm volatile(ALTERNATIVE( \ "slli t3, t3, %3\n\t" \ "or %0, %0, t3\n\t" \ "2:", THEAD_VENDOR_ID, \ - ERRATA_THEAD_PBMT, CONFIG_ERRATA_THEAD_PBMT) \ + ERRATA_THEAD_MAE, CONFIG_ERRATA_THEAD_MAE) \ : "+r"(_val) \ - : "I"(_PAGE_MTMASK_THEAD >> ALT_THEAD_PBMT_SHIFT), \ - "I"(_PAGE_PMA_THEAD >> ALT_THEAD_PBMT_SHIFT), \ - "I"(ALT_THEAD_PBMT_SHIFT) \ + : "I"(_PAGE_MTMASK_THEAD >> ALT_THEAD_MAE_SHIFT), \ + "I"(_PAGE_PMA_THEAD >> ALT_THEAD_MAE_SHIFT), \ + "I"(ALT_THEAD_MAE_SHIFT) \ : "t3") #else #define ALT_THEAD_PMA(_val) From patchwork Sun Apr 7 21:32:36 2024 Content-Type: text/plain; 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[62.178.148.172]) by smtp.gmail.com with ESMTPSA id i2-20020a50fc02000000b0056e22be831dsm3267562edr.42.2024.04.07.14.32.41 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 07 Apr 2024 14:32:41 -0700 (PDT) From: =?utf-8?q?Christoph_M=C3=BCllner?= To: linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org, Palmer Dabbelt , Paul Walmsley , Albert Ou , Philipp Tomsich , =?utf-8?b?QmrDtnJuIFTDtnBlbA==?= , Daniel Henrique Barboza , Heiko Stuebner , Cooper Qu , Zhiwei Liu , Huang Tao , Alistair Francis , Andrew Jones , Conor Dooley , Qingfang Deng , Alexandre Ghiti , Samuel Holland Cc: =?utf-8?q?Christoph_M=C3=BCllner?= , Conor Dooley Subject: [PATCH v3 2/2] riscv: T-Head: Test availability bit before enabling MAE errata Date: Sun, 7 Apr 2024 23:32:36 +0200 Message-ID: <20240407213236.2121592-3-christoph.muellner@vrull.eu> X-Mailer: git-send-email 2.44.0 In-Reply-To: <20240407213236.2121592-1-christoph.muellner@vrull.eu> References: <20240407213236.2121592-1-christoph.muellner@vrull.eu> MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20240407_143245_025659_9BF64FE3 X-CRM114-Status: GOOD ( 14.07 ) X-BeenThere: linux-riscv@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-riscv" Errors-To: linux-riscv-bounces+linux-riscv=archiver.kernel.org@lists.infradead.org T-Head's memory attribute extension (XTheadMae) (non-compatible equivalent of RVI's Svpbmt) is currently assumed for all T-Head harts. However, QEMU recently decided to drop acceptance of guests that write reserved bits in PTEs. As XTheadMae uses reserved bits in PTEs and Linux applies the MAE errata for all T-Head harts, this broke the Linux startup on QEMU emulations of the C906 emulation. This patch attempts to address this issue by testing the MAE-enable bit in the th.sxstatus CSR. This CSR is available in HW and can be emulated in QEMU. This patch also makes the XTheadMae probing mechanism reliable, because a test for the right combination of mvendorid, marchid, and mimpid is not sufficient to enable MAE. Reviewed-by: Conor Dooley Signed-off-by: Christoph Müllner --- arch/riscv/errata/thead/errata.c | 14 ++++++++++---- 1 file changed, 10 insertions(+), 4 deletions(-) diff --git a/arch/riscv/errata/thead/errata.c b/arch/riscv/errata/thead/errata.c index 6e7ee1f16bee..bf6a0a6318ee 100644 --- a/arch/riscv/errata/thead/errata.c +++ b/arch/riscv/errata/thead/errata.c @@ -19,6 +19,9 @@ #include #include +#define CSR_TH_SXSTATUS 0x5c0 +#define SXSTATUS_MAEE _AC(0x200000, UL) + static bool errata_probe_mae(unsigned int stage, unsigned long arch_id, unsigned long impid) { @@ -28,11 +31,14 @@ static bool errata_probe_mae(unsigned int stage, if (arch_id != 0 || impid != 0) return false; - if (stage == RISCV_ALTERNATIVES_EARLY_BOOT || - stage == RISCV_ALTERNATIVES_MODULE) - return true; + if (stage != RISCV_ALTERNATIVES_EARLY_BOOT && + stage != RISCV_ALTERNATIVES_MODULE) + return false; - return false; + if (!(csr_read(CSR_TH_SXSTATUS) & SXSTATUS_MAEE)) + return false; + + return true; } /*