From patchwork Wed Apr 10 23:22:03 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Samuel Holland X-Patchwork-Id: 13625124 X-Patchwork-Delegate: mail@conchuod.ie Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id E3448CD129D for ; Wed, 10 Apr 2024 23:22:33 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:MIME-Version:References:In-Reply-To: Message-ID:Date:Subject:Cc:To:From:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; 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| ^~~~~~ This is expected, since QUIRK_NONSTANDARD_CACHE_OPS is the only quirk still handled in this function. Fixes: c90847bcbfb6 ("cache: sifive_ccache: Partially convert to a platform driver") Reported-by: kernel test robot Closes: https://lore.kernel.org/oe-kbuild-all/202403311253.Z4NvIBxI-lkp@intel.com/ Signed-off-by: Samuel Holland --- drivers/cache/sifive_ccache.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/cache/sifive_ccache.c b/drivers/cache/sifive_ccache.c index e9cc8b4786fb..6874b72ec59d 100644 --- a/drivers/cache/sifive_ccache.c +++ b/drivers/cache/sifive_ccache.c @@ -290,7 +290,7 @@ static int __init sifive_ccache_init(void) struct device_node *np; struct resource res; const struct of_device_id *match; - unsigned long quirks; + unsigned long quirks __maybe_unused; int rc; np = of_find_matching_node_and_match(NULL, sifive_ccache_ids, &match); From patchwork Wed Apr 10 23:22:04 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Samuel Holland X-Patchwork-Id: 13625120 X-Patchwork-Delegate: mail@conchuod.ie Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 43245CD128A for ; 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Wed, 10 Apr 2024 16:22:15 -0700 (PDT) Received: from sw06.internal.sifive.com ([4.53.31.132]) by smtp.gmail.com with ESMTPSA id o19-20020a17090aac1300b002a269828bb8sm161865pjq.40.2024.04.10.16.22.14 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 10 Apr 2024 16:22:14 -0700 (PDT) From: Samuel Holland To: Conor Dooley , linux-riscv@lists.infradead.org Cc: Samuel Holland , Paul Walmsley , linux-kernel@vger.kernel.org Subject: [PATCH 2/4] cache: sifive_ccache: Use of_iomap() helper Date: Wed, 10 Apr 2024 16:22:04 -0700 Message-ID: <20240410232211.438277-3-samuel.holland@sifive.com> X-Mailer: git-send-email 2.44.0 In-Reply-To: <20240410232211.438277-1-samuel.holland@sifive.com> References: <20240410232211.438277-1-samuel.holland@sifive.com> MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20240410_162216_518546_BEEB1E14 X-CRM114-Status: GOOD ( 11.07 ) X-BeenThere: linux-riscv@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-riscv" Errors-To: linux-riscv-bounces+linux-riscv=archiver.kernel.org@lists.infradead.org This simplifies the code with no functional change. Signed-off-by: Samuel Holland --- drivers/cache/sifive_ccache.c | 8 +------- 1 file changed, 1 insertion(+), 7 deletions(-) diff --git a/drivers/cache/sifive_ccache.c b/drivers/cache/sifive_ccache.c index 6874b72ec59d..9833e9f6f36c 100644 --- a/drivers/cache/sifive_ccache.c +++ b/drivers/cache/sifive_ccache.c @@ -288,7 +288,6 @@ static struct platform_driver sifive_ccache_driver = { static int __init sifive_ccache_init(void) { struct device_node *np; - struct resource res; const struct of_device_id *match; unsigned long quirks __maybe_unused; int rc; @@ -299,12 +298,7 @@ static int __init sifive_ccache_init(void) quirks = (uintptr_t)match->data; - if (of_address_to_resource(np, 0, &res)) { - rc = -ENODEV; - goto err_node_put; - } - - ccache_base = ioremap(res.start, resource_size(&res)); + ccache_base = of_iomap(np, 0); if (!ccache_base) { rc = -ENOMEM; goto err_node_put; From patchwork Wed Apr 10 23:22:05 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Samuel Holland X-Patchwork-Id: 13625122 X-Patchwork-Delegate: mail@conchuod.ie Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 8C54DCD1297 for ; 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Wed, 10 Apr 2024 16:22:16 -0700 (PDT) Received: from sw06.internal.sifive.com ([4.53.31.132]) by smtp.gmail.com with ESMTPSA id o19-20020a17090aac1300b002a269828bb8sm161865pjq.40.2024.04.10.16.22.15 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 10 Apr 2024 16:22:16 -0700 (PDT) From: Samuel Holland To: Conor Dooley , linux-riscv@lists.infradead.org Cc: Samuel Holland , Paul Walmsley , linux-kernel@vger.kernel.org Subject: [PATCH 3/4] cache: sifive_ccache: Export base address for child drivers Date: Wed, 10 Apr 2024 16:22:05 -0700 Message-ID: <20240410232211.438277-4-samuel.holland@sifive.com> X-Mailer: git-send-email 2.44.0 In-Reply-To: <20240410232211.438277-1-samuel.holland@sifive.com> References: <20240410232211.438277-1-samuel.holland@sifive.com> MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20240410_162217_835114_5F2421C7 X-CRM114-Status: GOOD ( 16.51 ) X-BeenThere: linux-riscv@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-riscv" Errors-To: linux-riscv-bounces+linux-riscv=archiver.kernel.org@lists.infradead.org The SiFive Composable Cache functionality is split across multiple drivers, including the base cache driver, the EDAC driver, and a PMU driver. Export the MMIO base address from the main driver so the child drivers can access the MMIO space. Since each driver uses a different subset of registers, there are no synchronization concerns. Signed-off-by: Samuel Holland --- drivers/cache/sifive_ccache.c | 44 +++++++++++++++--------------- include/soc/sifive/sifive_ccache.h | 4 +++ 2 files changed, 26 insertions(+), 22 deletions(-) diff --git a/drivers/cache/sifive_ccache.c b/drivers/cache/sifive_ccache.c index 9833e9f6f36c..42dac39c41cf 100644 --- a/drivers/cache/sifive_ccache.c +++ b/drivers/cache/sifive_ccache.c @@ -53,7 +53,7 @@ #define SIFIVE_CCACHE_MAX_ECCINTR 4 #define SIFIVE_CCACHE_LINE_SIZE 64 -static void __iomem *ccache_base; +static struct sifive_ccache ccache; static int g_irq[SIFIVE_CCACHE_MAX_ECCINTR]; static struct riscv_cacheinfo_ops ccache_cache_ops; static int level; @@ -81,7 +81,7 @@ static ssize_t ccache_write(struct file *file, const char __user *data, if (kstrtouint_from_user(data, count, 0, &val)) return -EINVAL; if ((val < 0xFF) || (val >= 0x10000 && val < 0x100FF)) - writel(val, ccache_base + SIFIVE_CCACHE_ECCINJECTERR); + writel(val, ccache.base + SIFIVE_CCACHE_ECCINJECTERR); else return -EINVAL; return count; @@ -106,14 +106,14 @@ static void ccache_config_read(void) { u32 cfg; - cfg = readl(ccache_base + SIFIVE_CCACHE_CONFIG); + cfg = readl(ccache.base + SIFIVE_CCACHE_CONFIG); pr_info("%llu banks, %llu ways, sets/bank=%llu, bytes/block=%llu\n", FIELD_GET(SIFIVE_CCACHE_CONFIG_BANK_MASK, cfg), FIELD_GET(SIFIVE_CCACHE_CONFIG_WAYS_MASK, cfg), BIT_ULL(FIELD_GET(SIFIVE_CCACHE_CONFIG_SETS_MASK, cfg)), BIT_ULL(FIELD_GET(SIFIVE_CCACHE_CONFIG_BLKS_MASK, cfg))); - cfg = readl(ccache_base + SIFIVE_CCACHE_WAYENABLE); + cfg = readl(ccache.base + SIFIVE_CCACHE_WAYENABLE); pr_info("Index of the largest way enabled: %u\n", cfg); } @@ -153,9 +153,9 @@ static void ccache_flush_range(phys_addr_t start, size_t len) for (line = ALIGN_DOWN(start, SIFIVE_CCACHE_LINE_SIZE); line < end; line += SIFIVE_CCACHE_LINE_SIZE) { #ifdef CONFIG_32BIT - writel(line >> 4, ccache_base + SIFIVE_CCACHE_FLUSH32); + writel(line >> 4, ccache.base + SIFIVE_CCACHE_FLUSH32); #else - writeq(line, ccache_base + SIFIVE_CCACHE_FLUSH64); + writeq(line, ccache.base + SIFIVE_CCACHE_FLUSH64); #endif mb(); } @@ -170,7 +170,7 @@ static const struct riscv_nonstd_cache_ops ccache_mgmt_ops __initconst = { static int ccache_largest_wayenabled(void) { - return readl(ccache_base + SIFIVE_CCACHE_WAYENABLE) & 0xFF; + return readl(ccache.base + SIFIVE_CCACHE_WAYENABLE) & 0xFF; } static ssize_t number_of_ways_enabled_show(struct device *dev, @@ -206,41 +206,41 @@ static irqreturn_t ccache_int_handler(int irq, void *device) unsigned int add_h, add_l; if (irq == g_irq[DIR_CORR]) { - add_h = readl(ccache_base + SIFIVE_CCACHE_DIRECCFIX_HIGH); - add_l = readl(ccache_base + SIFIVE_CCACHE_DIRECCFIX_LOW); + add_h = readl(ccache.base + SIFIVE_CCACHE_DIRECCFIX_HIGH); + add_l = readl(ccache.base + SIFIVE_CCACHE_DIRECCFIX_LOW); pr_err("DirError @ 0x%08X.%08X\n", add_h, add_l); /* Reading this register clears the DirError interrupt sig */ - readl(ccache_base + SIFIVE_CCACHE_DIRECCFIX_COUNT); + readl(ccache.base + SIFIVE_CCACHE_DIRECCFIX_COUNT); atomic_notifier_call_chain(&ccache_err_chain, SIFIVE_CCACHE_ERR_TYPE_CE, "DirECCFix"); } if (irq == g_irq[DIR_UNCORR]) { - add_h = readl(ccache_base + SIFIVE_CCACHE_DIRECCFAIL_HIGH); - add_l = readl(ccache_base + SIFIVE_CCACHE_DIRECCFAIL_LOW); + add_h = readl(ccache.base + SIFIVE_CCACHE_DIRECCFAIL_HIGH); + add_l = readl(ccache.base + SIFIVE_CCACHE_DIRECCFAIL_LOW); /* Reading this register clears the DirFail interrupt sig */ - readl(ccache_base + SIFIVE_CCACHE_DIRECCFAIL_COUNT); + readl(ccache.base + SIFIVE_CCACHE_DIRECCFAIL_COUNT); atomic_notifier_call_chain(&ccache_err_chain, SIFIVE_CCACHE_ERR_TYPE_UE, "DirECCFail"); panic("CCACHE: DirFail @ 0x%08X.%08X\n", add_h, add_l); } if (irq == g_irq[DATA_CORR]) { - add_h = readl(ccache_base + SIFIVE_CCACHE_DATECCFIX_HIGH); - add_l = readl(ccache_base + SIFIVE_CCACHE_DATECCFIX_LOW); + add_h = readl(ccache.base + SIFIVE_CCACHE_DATECCFIX_HIGH); + add_l = readl(ccache.base + SIFIVE_CCACHE_DATECCFIX_LOW); pr_err("DataError @ 0x%08X.%08X\n", add_h, add_l); /* Reading this register clears the DataError interrupt sig */ - readl(ccache_base + SIFIVE_CCACHE_DATECCFIX_COUNT); + readl(ccache.base + SIFIVE_CCACHE_DATECCFIX_COUNT); atomic_notifier_call_chain(&ccache_err_chain, SIFIVE_CCACHE_ERR_TYPE_CE, "DatECCFix"); } if (irq == g_irq[DATA_UNCORR]) { - add_h = readl(ccache_base + SIFIVE_CCACHE_DATECCFAIL_HIGH); - add_l = readl(ccache_base + SIFIVE_CCACHE_DATECCFAIL_LOW); + add_h = readl(ccache.base + SIFIVE_CCACHE_DATECCFAIL_HIGH); + add_l = readl(ccache.base + SIFIVE_CCACHE_DATECCFAIL_LOW); pr_err("DataFail @ 0x%08X.%08X\n", add_h, add_l); /* Reading this register clears the DataFail interrupt sig */ - readl(ccache_base + SIFIVE_CCACHE_DATECCFAIL_COUNT); + readl(ccache.base + SIFIVE_CCACHE_DATECCFAIL_COUNT); atomic_notifier_call_chain(&ccache_err_chain, SIFIVE_CCACHE_ERR_TYPE_UE, "DatECCFail"); @@ -298,8 +298,8 @@ static int __init sifive_ccache_init(void) quirks = (uintptr_t)match->data; - ccache_base = of_iomap(np, 0); - if (!ccache_base) { + ccache.base = of_iomap(np, 0); + if (!ccache.base) { rc = -ENOMEM; goto err_node_put; } @@ -335,7 +335,7 @@ static int __init sifive_ccache_init(void) return 0; err_unmap: - iounmap(ccache_base); + iounmap(ccache.base); err_node_put: of_node_put(np); return rc; diff --git a/include/soc/sifive/sifive_ccache.h b/include/soc/sifive/sifive_ccache.h index 4d4ed49388a0..85fd1ff1355a 100644 --- a/include/soc/sifive/sifive_ccache.h +++ b/include/soc/sifive/sifive_ccache.h @@ -7,6 +7,10 @@ #ifndef __SOC_SIFIVE_CCACHE_H #define __SOC_SIFIVE_CCACHE_H +struct sifive_ccache { + void __iomem *base; +}; + extern int register_sifive_ccache_error_notifier(struct notifier_block *nb); extern int unregister_sifive_ccache_error_notifier(struct notifier_block *nb); From patchwork Wed Apr 10 23:22:06 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Samuel Holland X-Patchwork-Id: 13625123 X-Patchwork-Delegate: mail@conchuod.ie Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 0CEF6CD11C2 for ; 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Wed, 10 Apr 2024 16:22:17 -0700 (PDT) Received: from sw06.internal.sifive.com ([4.53.31.132]) by smtp.gmail.com with ESMTPSA id o19-20020a17090aac1300b002a269828bb8sm161865pjq.40.2024.04.10.16.22.16 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 10 Apr 2024 16:22:17 -0700 (PDT) From: Samuel Holland To: Conor Dooley , linux-riscv@lists.infradead.org Cc: Samuel Holland , Paul Walmsley , linux-kernel@vger.kernel.org Subject: [PATCH 4/4] cache: sifive_ccache: Add EDAC and PMU as auxiliary devices Date: Wed, 10 Apr 2024 16:22:06 -0700 Message-ID: <20240410232211.438277-5-samuel.holland@sifive.com> X-Mailer: git-send-email 2.44.0 In-Reply-To: <20240410232211.438277-1-samuel.holland@sifive.com> References: <20240410232211.438277-1-samuel.holland@sifive.com> MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20240410_162218_727395_2F59B333 X-CRM114-Status: GOOD ( 16.81 ) X-BeenThere: linux-riscv@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-riscv" Errors-To: linux-riscv-bounces+linux-riscv=archiver.kernel.org@lists.infradead.org This allows the child drivers to access the Composable Cache device's MMIO space and ties them to the lifecycle of the main platform device. Currently, the EDAC driver is probed regardless of whether a Composable Cache device actually exists on the system. Once converted to use the auxiliary device bus, it will only be probed when needed. Signed-off-by: Samuel Holland --- drivers/cache/Kconfig | 1 + drivers/cache/sifive_ccache.c | 42 ++++++++++++++++++++++++++++++ include/soc/sifive/sifive_ccache.h | 4 +++ 3 files changed, 47 insertions(+) diff --git a/drivers/cache/Kconfig b/drivers/cache/Kconfig index 9345ce4976d7..08e0415eba80 100644 --- a/drivers/cache/Kconfig +++ b/drivers/cache/Kconfig @@ -11,6 +11,7 @@ config AX45MP_L2_CACHE config SIFIVE_CCACHE bool "Sifive Composable Cache controller" depends on ARCH_SIFIVE || ARCH_STARFIVE + select AUXILIARY_BUS help Support for the composable cache controller on SiFive platforms. diff --git a/drivers/cache/sifive_ccache.c b/drivers/cache/sifive_ccache.c index 42dac39c41cf..c7aa6f360967 100644 --- a/drivers/cache/sifive_ccache.c +++ b/drivers/cache/sifive_ccache.c @@ -9,6 +9,7 @@ #define pr_fmt(fmt) "CCACHE: " fmt #include +#include #include #include #include @@ -249,6 +250,39 @@ static irqreturn_t ccache_int_handler(int irq, void *device) return IRQ_HANDLED; } +static void sifive_ccache_del_aux_dev(void *adev) +{ + auxiliary_device_delete(adev); + auxiliary_device_uninit(adev); +} + +static int sifive_ccache_add_aux_dev(struct device *dev, struct auxiliary_device *adev, + const char *name) +{ + int rc; + + adev->dev.parent = dev; + adev->name = name; + + rc = auxiliary_device_init(adev); + if (rc) + return rc; + + rc = auxiliary_device_add(adev); + if (rc) + goto err_uninit; + + rc = devm_add_action_or_reset(dev, sifive_ccache_del_aux_dev, adev); + if (rc) + return rc; + + return 0; + +err_uninit: + auxiliary_device_uninit(adev); + return rc; +} + static int sifive_ccache_probe(struct platform_device *pdev) { struct device *dev = &pdev->dev; @@ -274,6 +308,14 @@ static int sifive_ccache_probe(struct platform_device *pdev) return dev_err_probe(dev, rc, "Could not request IRQ %d\n", g_irq[i]); } + rc = sifive_ccache_add_aux_dev(dev, &ccache.edac_dev, "edac"); + if (rc) + return rc; + + rc = sifive_ccache_add_aux_dev(dev, &ccache.pmu_dev, "pmu"); + if (rc) + return rc; + return 0; } diff --git a/include/soc/sifive/sifive_ccache.h b/include/soc/sifive/sifive_ccache.h index 85fd1ff1355a..034dc8b6e4e4 100644 --- a/include/soc/sifive/sifive_ccache.h +++ b/include/soc/sifive/sifive_ccache.h @@ -7,8 +7,12 @@ #ifndef __SOC_SIFIVE_CCACHE_H #define __SOC_SIFIVE_CCACHE_H +#include + struct sifive_ccache { void __iomem *base; + struct auxiliary_device edac_dev; + struct auxiliary_device pmu_dev; }; extern int register_sifive_ccache_error_notifier(struct notifier_block *nb);