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Miller" , Jakub Kicinski , Paolo Abeni , Eric Dumazet CC: , Saeed Mahameed , Gal Pressman , Leon Romanovsky , Shay Drory , Maor Gottlieb , Tariq Toukan Subject: [PATCH net 1/6] net/mlx5: Lag, restore buckets number to default after hash LAG deactivation Date: Thu, 11 Apr 2024 14:54:39 +0300 Message-ID: <20240411115444.374475-2-tariqt@nvidia.com> X-Mailer: git-send-email 2.44.0 In-Reply-To: <20240411115444.374475-1-tariqt@nvidia.com> References: <20240411115444.374475-1-tariqt@nvidia.com> Precedence: bulk X-Mailing-List: netdev@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-NV-OnPremToCloud: ExternallySecured X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: CH1PEPF0000AD81:EE_|SA3PR12MB7952:EE_ X-MS-Office365-Filtering-Correlation-Id: dea5e423-6a16-4f47-8104-08dc5a1e4e81 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: np1VIxbmMReTZils+wyS7kyEaplac7f2K7mui/VBzeWqrYarnrnO7ML/FAu7IGyRvV12DoxDrqJNR8gQuMeWs7WHGXcedMfqgljgGbIlUU2UI9R4E+twEFONNQj7hw3gbIJ/pF99ITHEOj2WJTlIuliVcFYfY/HMO6JPVM64OvvqCHROjMaYJPlEr/vLk5QQ8tt/JrGh+lP2tr6WK07y4qhzhFM26OEpUI3claN4ffKCrtOE7KtmNFueUpLYBPSTlxh9rhGxzunCXLx2n47HO/YLGX+wxx22t9STusP1vOx+bVM/wQZDCaZNm9i44svTIsSWJWHaIGtNsnJ+hUwgWcV8fivRZO8zStxLFxaAtnk3AJhSv5Fszxj3yD0Z224cv2OKq+/GMHX5+N4YkiYr3TN297mr8UXeziVcKuwpChgvP+sxW1BchI8/gPJ3qRcqFAaYgFvPTco5IornUFmneqv/zf9mcj5RAqWI+nQwlBAlQu5bL6vKFqfhgVU/2xbZFuwDG0iXwGr/i39jEH2VgZcpjKTx7WIAB2hq+Kn4pqj0zGYWI3dYxoSYTLU23KVpt2v37Nk3YBmcf2caKNb1zPLzck/+462skZyRy6VqYK/4hgmRuvW0QVJcEVUJmrJ8GyAsuvEMThPJYy2jldKwuKHjXSD1WYtRr4OpN3E+AkK9w1bsYjvq9e1Io6pez+KsXRtm/J0byjnZDz+ovrE2AaL83f1usYdKRFJtys3jUzfCLKxXPndNhFZAuOwuJGoV X-Forefront-Antispam-Report: CIP:216.228.118.232;CTRY:US;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:mail.nvidia.com;PTR:dc7edge1.nvidia.com;CAT:NONE;SFS:(13230031)(376005)(82310400014)(1800799015)(36860700004);DIR:OUT;SFP:1101; X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 11 Apr 2024 11:55:39.0834 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: dea5e423-6a16-4f47-8104-08dc5a1e4e81 X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.118.232];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: CH1PEPF0000AD81.namprd04.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: SA3PR12MB7952 X-Patchwork-Delegate: kuba@kernel.org From: Shay Drory The cited patch introduces the concept of buckets in LAG in hash mode. However, the patch doesn't clear the number of buckets in the LAG deactivation. This results in using the wrong number of buckets in case user create a hash mode LAG and afterwards create a non-hash mode LAG. Hence, restore buckets number to default after hash mode LAG deactivation. Fixes: 352899f384d4 ("net/mlx5: Lag, use buckets in hash mode") Signed-off-by: Shay Drory Reviewed-by: Maor Gottlieb Signed-off-by: Tariq Toukan --- drivers/net/ethernet/mellanox/mlx5/core/lag/lag.c | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/drivers/net/ethernet/mellanox/mlx5/core/lag/lag.c b/drivers/net/ethernet/mellanox/mlx5/core/lag/lag.c index d14459e5c04f..69d482f7c5a2 100644 --- a/drivers/net/ethernet/mellanox/mlx5/core/lag/lag.c +++ b/drivers/net/ethernet/mellanox/mlx5/core/lag/lag.c @@ -703,8 +703,10 @@ int mlx5_deactivate_lag(struct mlx5_lag *ldev) return err; } - if (test_bit(MLX5_LAG_MODE_FLAG_HASH_BASED, &flags)) + if (test_bit(MLX5_LAG_MODE_FLAG_HASH_BASED, &flags)) { mlx5_lag_port_sel_destroy(ldev); + ldev->buckets = 1; + } if (mlx5_lag_has_drop_rule(ldev)) mlx5_lag_drop_rule_cleanup(ldev); From patchwork Thu Apr 11 11:54:40 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Tariq Toukan X-Patchwork-Id: 13625830 X-Patchwork-Delegate: kuba@kernel.org Received: from NAM12-MW2-obe.outbound.protection.outlook.com (mail-mw2nam12on2043.outbound.protection.outlook.com [40.107.244.43]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id EC15C14AD2B for ; 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Miller" , Jakub Kicinski , Paolo Abeni , Eric Dumazet CC: , Saeed Mahameed , Gal Pressman , Leon Romanovsky , Tariq Toukan , Dan Carpenter Subject: [PATCH net 2/6] net/mlx5: SD, Handle possible devcom ERR_PTR Date: Thu, 11 Apr 2024 14:54:40 +0300 Message-ID: <20240411115444.374475-3-tariqt@nvidia.com> X-Mailer: git-send-email 2.44.0 In-Reply-To: <20240411115444.374475-1-tariqt@nvidia.com> References: <20240411115444.374475-1-tariqt@nvidia.com> Precedence: bulk X-Mailing-List: netdev@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-NV-OnPremToCloud: ExternallySecured X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: DS2PEPF00003447:EE_|PH7PR12MB5950:EE_ X-MS-Office365-Filtering-Correlation-Id: 8a331166-be0d-4a84-6355-08dc5a1e58fe X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: H9Bm9G80wBh0KrRY0Y3gGUTRCxMiWb6rmeKoBXhtWanIghfeOMT3X4QFs8d30bL9UeuXdeav9nsWbYh6EwmdG+FKW/3Q6wQMXa/jxSHLJ363AyvuaXQtsTlnCYhP0Jf5ABGh5OaM+NdAmDw4ui0cwaw4A8Bsep8Y73Zz1UaIr9ctgohb93OcmzrdJziSgjkBb5KNzLkEpgLWvtLt1IgfjgmSH+SkvdRxbp83Zi2NHy8bbWJSohHC8BOpw7kBIx4wFn27rn+4tR/qiC3jE26rwyXWfAvF+qpopHbBvdNsam5Q6fwpMI3/mtLhOevep+jj+XBulmcpdfkWZ+qtgoJYHDZStpV4ocIQ5Yr2CqX7T0diueI61dtqFHgDVmOEa2phUcR7Q97/EekeYk26DAc3GE6O5mVQb7FFJBs+I2Y5t0gDTiRHcwOGp3YZxHHr37NgZDmb+HqaKTCa0xr+BU+wN8EWWNtcXHJvKkO0wTxz79Y6hyAVp3lpWFPxxtTY6hoC8qB9dKEtnOFp+4nknZ/JJWoMUkJsTLt5VhRgBTVg5p0xs91QFbqtzDwkhCysN1RRcEleu/WEGcZPVWoIX2vf6MOsVmge4Z4YxW90mmtPZx5Tz6LWBXwmJLsH3Pn8YWlqu0P4EG4BPxamvKduFzO7quet/lbd+lQ2U1mM1wi6C2C1MDrKNUcXf7pTRue2z8iQgUzrG5yDH8mWud395XU/BmMR6kTjUkqRqnx8qHGRAxe2hcRk67+0TrVuzYfCyUAN X-Forefront-Antispam-Report: CIP:216.228.118.233;CTRY:US;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:mail.nvidia.com;PTR:dc7edge2.nvidia.com;CAT:NONE;SFS:(13230031)(36860700004)(376005)(1800799015)(82310400014);DIR:OUT;SFP:1101; X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 11 Apr 2024 11:55:56.6946 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 8a331166-be0d-4a84-6355-08dc5a1e58fe X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.118.233];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: DS2PEPF00003447.namprd04.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: PH7PR12MB5950 X-Patchwork-Delegate: kuba@kernel.org Check if devcom holds an error pointer and return immediately. This fixes Smatch static checker warning: drivers/net/ethernet/mellanox/mlx5/core/lib/sd.c:221 sd_register() error: 'devcom' dereferencing possible ERR_PTR() Enhance mlx5_devcom_register_component() so it stops returning NULL, making it easier for its callers. Fixes: d3d057666090 ("net/mlx5: SD, Implement devcom communication and primary election") Reported-by: Dan Carpenter Link: https://lore.kernel.org/all/f09666c8-e604-41f6-958b-4cc55c73faf9@gmail.com/T/ Signed-off-by: Tariq Toukan Reviewed-by: Gal Pressman --- drivers/net/ethernet/mellanox/mlx5/core/en_main.c | 4 ++-- drivers/net/ethernet/mellanox/mlx5/core/eswitch_offloads.c | 2 +- drivers/net/ethernet/mellanox/mlx5/core/lib/devcom.c | 2 +- drivers/net/ethernet/mellanox/mlx5/core/lib/sd.c | 4 ++-- drivers/net/ethernet/mellanox/mlx5/core/main.c | 2 +- 5 files changed, 7 insertions(+), 7 deletions(-) diff --git a/drivers/net/ethernet/mellanox/mlx5/core/en_main.c b/drivers/net/ethernet/mellanox/mlx5/core/en_main.c index b375ef268671..319930c04093 100644 --- a/drivers/net/ethernet/mellanox/mlx5/core/en_main.c +++ b/drivers/net/ethernet/mellanox/mlx5/core/en_main.c @@ -209,8 +209,8 @@ static int mlx5e_devcom_init_mpv(struct mlx5e_priv *priv, u64 *data) *data, mlx5e_devcom_event_mpv, priv); - if (IS_ERR_OR_NULL(priv->devcom)) - return -EOPNOTSUPP; + if (IS_ERR(priv->devcom)) + return PTR_ERR(priv->devcom); if (mlx5_core_is_mp_master(priv->mdev)) { mlx5_devcom_send_event(priv->devcom, MPV_DEVCOM_MASTER_UP, diff --git a/drivers/net/ethernet/mellanox/mlx5/core/eswitch_offloads.c b/drivers/net/ethernet/mellanox/mlx5/core/eswitch_offloads.c index 1f60954c12f7..844d3e3a65dd 100644 --- a/drivers/net/ethernet/mellanox/mlx5/core/eswitch_offloads.c +++ b/drivers/net/ethernet/mellanox/mlx5/core/eswitch_offloads.c @@ -3060,7 +3060,7 @@ void mlx5_esw_offloads_devcom_init(struct mlx5_eswitch *esw, u64 key) key, mlx5_esw_offloads_devcom_event, esw); - if (IS_ERR_OR_NULL(esw->devcom)) + if (IS_ERR(esw->devcom)) return; mlx5_devcom_send_event(esw->devcom, diff --git a/drivers/net/ethernet/mellanox/mlx5/core/lib/devcom.c b/drivers/net/ethernet/mellanox/mlx5/core/lib/devcom.c index e7d59cfa8708..7b0766c89f4c 100644 --- a/drivers/net/ethernet/mellanox/mlx5/core/lib/devcom.c +++ b/drivers/net/ethernet/mellanox/mlx5/core/lib/devcom.c @@ -220,7 +220,7 @@ mlx5_devcom_register_component(struct mlx5_devcom_dev *devc, struct mlx5_devcom_comp *comp; if (IS_ERR_OR_NULL(devc)) - return NULL; + return ERR_PTR(-EINVAL); mutex_lock(&comp_list_lock); comp = devcom_component_get(devc, id, key, handler); diff --git a/drivers/net/ethernet/mellanox/mlx5/core/lib/sd.c b/drivers/net/ethernet/mellanox/mlx5/core/lib/sd.c index 5b28084e8a03..dd5d186dc614 100644 --- a/drivers/net/ethernet/mellanox/mlx5/core/lib/sd.c +++ b/drivers/net/ethernet/mellanox/mlx5/core/lib/sd.c @@ -213,8 +213,8 @@ static int sd_register(struct mlx5_core_dev *dev) sd = mlx5_get_sd(dev); devcom = mlx5_devcom_register_component(dev->priv.devc, MLX5_DEVCOM_SD_GROUP, sd->group_id, NULL, dev); - if (!devcom) - return -ENOMEM; + if (IS_ERR(devcom)) + return PTR_ERR(devcom); sd->devcom = devcom; diff --git a/drivers/net/ethernet/mellanox/mlx5/core/main.c b/drivers/net/ethernet/mellanox/mlx5/core/main.c index 59806553889e..a39c4b25ba28 100644 --- a/drivers/net/ethernet/mellanox/mlx5/core/main.c +++ b/drivers/net/ethernet/mellanox/mlx5/core/main.c @@ -956,7 +956,7 @@ static void mlx5_register_hca_devcom_comp(struct mlx5_core_dev *dev) mlx5_devcom_register_component(dev->priv.devc, MLX5_DEVCOM_HCA_PORTS, mlx5_query_nic_system_image_guid(dev), NULL, dev); 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Miller" , Jakub Kicinski , Paolo Abeni , Eric Dumazet CC: , Saeed Mahameed , Gal Pressman , Leon Romanovsky , Shay Drory , Tariq Toukan Subject: [PATCH net 3/6] net/mlx5: Restore mistakenly dropped parts in register devlink flow Date: Thu, 11 Apr 2024 14:54:41 +0300 Message-ID: <20240411115444.374475-4-tariqt@nvidia.com> X-Mailer: git-send-email 2.44.0 In-Reply-To: <20240411115444.374475-1-tariqt@nvidia.com> References: <20240411115444.374475-1-tariqt@nvidia.com> Precedence: bulk X-Mailing-List: netdev@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-NV-OnPremToCloud: ExternallySecured X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: DS2PEPF00003447:EE_|SJ0PR12MB6711:EE_ X-MS-Office365-Filtering-Correlation-Id: a995bca6-4ad2-4982-8f29-08dc5a1e5a4e X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: q7BvgCjAtu0/oU8Aaq4EwwBVebE033QQqN630A1BYDDmzO9z7k3LTk3rctWYarOsXgZ+OW/cjCZiHCZqo1Kz0NCFYomqOuGNWZeLkp9D8AsZQJ28u1s0Rl7AwZMlFDnR+ZNXEZReZXcjmdkVPR2/8g9FNQ6PyxM1vMU8ibU3nIBa3zaYYwBsoNZiLzg2zuuZjO/8qe7ZUIOhfwPvTJumG7kLbC2TuOjZvg7Q52ySZ0QPe76uM8yN3T9uzVYIeV8Gsy1YMs4q80CdPMiYXVwQcZ5EEDXQZe+Ty+HEuwoLbZbaIHLvgpwD1h+Lox99lWUwJ+ah9b1fuwCc4cFEs7iJoRCpLCJ22HYTwPd2S4R+5H5y833JgspQnHbHW6icSue4XTmVZ78zMt4esBMeznisdxhn5jFbfWW6gLZgg6kKLTV6QVM504d8ExPNF93xdcia8aT4tAjtqvoC3B5NGSmSfwY3C8hXDGYTO8sk+TNfXyeIdKK5mYXCoa9HPOiBWyJebVKOE+feOwMvzQqUDNz82nVSv4FK6RM06geqScXBLP6+j7pu2dAFMoVd6Z5nNFoQHQNhvQEbQWG+2aRrDoU428X17tG2BlJOwIk4Vp8dI3wjxi47gk6TahHauneM7Jeu+/iFREiwioBeI5JWlFiA2KzZIIiRla0COecBgMC8zsDV/2LquhuARK1WQlDFIcH/Tl92YfjVpLs9Uw1BVotBRxvPBrrqYSdAgJSp065ae9tybOLbo6iC6DBkTy0TaOjM X-Forefront-Antispam-Report: CIP:216.228.118.233;CTRY:US;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:mail.nvidia.com;PTR:dc7edge2.nvidia.com;CAT:NONE;SFS:(13230031)(376005)(36860700004)(82310400014)(1800799015);DIR:OUT;SFP:1101; X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 11 Apr 2024 11:55:58.8821 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: a995bca6-4ad2-4982-8f29-08dc5a1e5a4e X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.118.233];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: DS2PEPF00003447.namprd04.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: SJ0PR12MB6711 X-Patchwork-Delegate: kuba@kernel.org From: Shay Drory Code parts from cited commit were mistakenly dropped while rebasing before submission. Add them here. Fixes: c6e77aa9dd82 ("net/mlx5: Register devlink first under devlink lock") Signed-off-by: Shay Drory Signed-off-by: Tariq Toukan --- drivers/net/ethernet/mellanox/mlx5/core/main.c | 5 ++++- drivers/net/ethernet/mellanox/mlx5/core/sf/dev/driver.c | 1 - 2 files changed, 4 insertions(+), 2 deletions(-) diff --git a/drivers/net/ethernet/mellanox/mlx5/core/main.c b/drivers/net/ethernet/mellanox/mlx5/core/main.c index a39c4b25ba28..331ce47f51a1 100644 --- a/drivers/net/ethernet/mellanox/mlx5/core/main.c +++ b/drivers/net/ethernet/mellanox/mlx5/core/main.c @@ -1699,12 +1699,15 @@ int mlx5_init_one_light(struct mlx5_core_dev *dev) err = mlx5_devlink_params_register(priv_to_devlink(dev)); if (err) { mlx5_core_warn(dev, "mlx5_devlink_param_reg err = %d\n", err); - goto query_hca_caps_err; + goto params_reg_err; } devl_unlock(devlink); return 0; +params_reg_err: + devl_unregister(devlink); + devl_unlock(devlink); query_hca_caps_err: devl_unregister(devlink); devl_unlock(devlink); diff --git a/drivers/net/ethernet/mellanox/mlx5/core/sf/dev/driver.c b/drivers/net/ethernet/mellanox/mlx5/core/sf/dev/driver.c index e3bf8c7e4baa..7ebe71280827 100644 --- a/drivers/net/ethernet/mellanox/mlx5/core/sf/dev/driver.c +++ b/drivers/net/ethernet/mellanox/mlx5/core/sf/dev/driver.c @@ -75,7 +75,6 @@ static int mlx5_sf_dev_probe(struct auxiliary_device *adev, const struct auxilia goto peer_devlink_set_err; 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Miller" , Jakub Kicinski , Paolo Abeni , Eric Dumazet CC: , Saeed Mahameed , Gal Pressman , Leon Romanovsky , Rahul Rameshbabu , Tariq Toukan Subject: [PATCH net 4/6] net/mlx5e: Use channel mdev reference instead of global mdev instance for coalescing Date: Thu, 11 Apr 2024 14:54:42 +0300 Message-ID: <20240411115444.374475-5-tariqt@nvidia.com> X-Mailer: git-send-email 2.44.0 In-Reply-To: <20240411115444.374475-1-tariqt@nvidia.com> References: <20240411115444.374475-1-tariqt@nvidia.com> Precedence: bulk X-Mailing-List: netdev@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-NV-OnPremToCloud: ExternallySecured X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: CH1PEPF0000AD7E:EE_|DS0PR12MB8344:EE_ X-MS-Office365-Filtering-Correlation-Id: 5a7ba1ff-fee4-462e-a9a5-08dc5a1e5461 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: TlUGvYsS0aQYXzi6CiXBGcsrM/LNmvKNkQqPghag5ldVHM1I0Fx9CRgCgPs34W4gvbhfm4mS6/2KPcF3JbF9ijonRlqlCFDdWypi7nf13bSeDFu0aKsRr+aCtuK7kAqYlpVOXbt8/FRhvyZl6DTZvHVRmfHGe4AMfx3nvNcb498svr8DeXa4kERo2H7zpSE3yvbwLBTy2GJAR+L2fgDyCG14psyrz9z6PQGo+LfXAVIwUr337TFRK0HrBaNlgmrVX/Uuhs/Sc8q3lLnWusQ+ujEjb334itTAaYQNz7iphwA5PRf7IxBk3Jo+kMGEVnLQVvbl/48Bxzby/0QKsxlImHfu0TzVthub2u0pV3QavqmLAF4fb45UJaAvOMgQ+g+UaL/elRlTsqLuXa8vdC4mZOqyTxJjm6IuO82jtmSlCjQ8Pb27qvYxmkdjsfq6i2Dpdh5eUm+7X1UtXHoJcCGvZV7hAaN7R+0x9tgu756FXkvvOa8WPczVofPN4uRGVVxo7QShhpSmPOUPXr62a6syBe4pG4ZBEUfnlSCivSDUo/ZFvGPMSkkrJlnF/t3kSBcBoyhm8+Rx5gTc4YbbGmfL1ixzjxxsBFWBslA7XEi4D81Z2mWBNo87TvyJWjNn2tWoFH/bxzpdOmdUEZb6L+PRVomwDc3cBfAN0sKbwk5T8K1mcO5z4aAg4HEvASbifcjpIPNLjGQmacbpTqOsuKlf40FruovJN+SimVGyDYRSM7RnsvFSh1UyIDp+GtneOeUv X-Forefront-Antispam-Report: CIP:216.228.118.232;CTRY:US;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:mail.nvidia.com;PTR:dc7edge1.nvidia.com;CAT:NONE;SFS:(13230031)(82310400014)(36860700004)(1800799015)(376005);DIR:OUT;SFP:1101; X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 11 Apr 2024 11:55:48.9566 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 5a7ba1ff-fee4-462e-a9a5-08dc5a1e5461 X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.118.232];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: CH1PEPF0000AD7E.namprd04.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: DS0PR12MB8344 X-Patchwork-Delegate: kuba@kernel.org From: Rahul Rameshbabu Channels can potentially have independent mdev instances. Do not refer to the global mdev instance in the mlx5e_priv instance for channel FW operations related to coalescing. CQ numbers that would be valid on the channel's mdev instance may not be correctly referenced if using the mlx5e_priv instance. Fixes: 67936e138586 ("net/mlx5e: Let channels be SD-aware") Signed-off-by: Rahul Rameshbabu Signed-off-by: Tariq Toukan --- drivers/net/ethernet/mellanox/mlx5/core/en_ethtool.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/net/ethernet/mellanox/mlx5/core/en_ethtool.c b/drivers/net/ethernet/mellanox/mlx5/core/en_ethtool.c index 8f101181648c..67a29826bb57 100644 --- a/drivers/net/ethernet/mellanox/mlx5/core/en_ethtool.c +++ b/drivers/net/ethernet/mellanox/mlx5/core/en_ethtool.c @@ -589,12 +589,12 @@ static int mlx5e_get_coalesce(struct net_device *netdev, static void mlx5e_set_priv_channels_tx_coalesce(struct mlx5e_priv *priv, struct ethtool_coalesce *coal) { - struct mlx5_core_dev *mdev = priv->mdev; int tc; int i; for (i = 0; i < priv->channels.num; ++i) { struct mlx5e_channel *c = priv->channels.c[i]; + struct mlx5_core_dev *mdev = c->mdev; for (tc = 0; tc < c->num_tc; tc++) { mlx5_core_modify_cq_moderation(mdev, @@ -608,11 +608,11 @@ mlx5e_set_priv_channels_tx_coalesce(struct mlx5e_priv *priv, struct ethtool_coal static void mlx5e_set_priv_channels_rx_coalesce(struct mlx5e_priv *priv, struct ethtool_coalesce *coal) { - struct mlx5_core_dev *mdev = priv->mdev; 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Miller" , Jakub Kicinski , Paolo Abeni , Eric Dumazet CC: , Saeed Mahameed , Gal Pressman , Leon Romanovsky , Carolina Jubran , Joe Damato , Rahul Rameshbabu , Tariq Toukan Subject: [PATCH net 5/6] net/mlx5e: Acquire RTNL lock before RQs/SQs activation/deactivation Date: Thu, 11 Apr 2024 14:54:43 +0300 Message-ID: <20240411115444.374475-6-tariqt@nvidia.com> X-Mailer: git-send-email 2.44.0 In-Reply-To: <20240411115444.374475-1-tariqt@nvidia.com> References: <20240411115444.374475-1-tariqt@nvidia.com> Precedence: bulk X-Mailing-List: netdev@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-NV-OnPremToCloud: ExternallySecured X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: CH1PEPF0000AD7E:EE_|CY8PR12MB7537:EE_ X-MS-Office365-Filtering-Correlation-Id: b30f02cf-1d0e-41e4-22c4-08dc5a1e5785 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: 6jss9nX4QYyKEXaWB5icWtwC73mzkxlzPxSahFiQk+gkg0FyLIEbwX/yD3gCxw1wYlzzqUKdXqyBzEEJZEoe/2ZzPQ2fFZWhHiOMBs7IxkNcjlt6ptVL1in8fiPhWmEq06y6aSncgEhQYCoVVByj5Q3QvY0NjZcnHNZq1Wcbb9BBk9AW3JPEaLW/gh4NJu+dhA0UrqWBkyUc9QtayrTRLJKKZJQ507pkhiXxe3TNIqIab1lTARQTS35sszWAjuB7uBzD/4nLDcl1mLEzYgF0KatXhpCXXcVuV2GfsZZNocJuv25RMHcBbSI1H1xHx6a5/hjQwLcv8D4pP3UDWkAdifyxK3OXeTCDQ6I/pNiHpfJXz2CLvKywp6RKnBj0spForqvPqfreILblnkiDhpXyEpn65VIo2K7YZ5jZnK9HCxtbudQ/PO5OrwNV+VSRUPe0yFyUXqMqE1M6d4spnFvTNK6nk+lispmQrCnyg9uSIh0Ff6RW24NrbjnKThXy70pCes0CVZrn9aBz3Pde43XLddTSi+r+EnxlRXbujGCGzDGiGpD4PP5wQka4oilxleIY7BJK/W0xVX3CQPJtfbcUvJpV4VQyPGArwXgEiSz30No19xOLHz7+mF7DHx1fHJTVYLJINr+/wkJgozTjQarJagL8HeIBjplSSpUiPr4ev4FpyBvsm1Zw3DdW+YnSC9WzRTweaWzUF4fDyVU08Krqxksfmgb8fXva35jSZvHkSXitnK+SJQKEl2JcvfV9+Obq X-Forefront-Antispam-Report: CIP:216.228.118.232;CTRY:US;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:mail.nvidia.com;PTR:dc7edge1.nvidia.com;CAT:NONE;SFS:(13230031)(36860700004)(376005)(1800799015)(82310400014);DIR:OUT;SFP:1101; X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 11 Apr 2024 11:55:54.2066 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: b30f02cf-1d0e-41e4-22c4-08dc5a1e5785 X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.118.232];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: CH1PEPF0000AD7E.namprd04.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: CY8PR12MB7537 X-Patchwork-Delegate: kuba@kernel.org From: Carolina Jubran netif_queue_set_napi asserts whether RTNL lock is held if the netdev is initialized. Acquire the RTNL lock before activating or deactivating RQs/SQs if the lock has not been held before in the flow. Fixes: f25e7b82635f ("net/mlx5e: link NAPI instances to queues and IRQs") Cc: Joe Damato Cc: Jakub Kicinski Signed-off-by: Carolina Jubran Reviewed-by: Rahul Rameshbabu Signed-off-by: Tariq Toukan --- drivers/net/ethernet/mellanox/mlx5/core/en/reporter_tx.c | 7 +++++++ 1 file changed, 7 insertions(+) diff --git a/drivers/net/ethernet/mellanox/mlx5/core/en/reporter_tx.c b/drivers/net/ethernet/mellanox/mlx5/core/en/reporter_tx.c index 0ab9db319530..22918b2ef7f1 100644 --- a/drivers/net/ethernet/mellanox/mlx5/core/en/reporter_tx.c +++ b/drivers/net/ethernet/mellanox/mlx5/core/en/reporter_tx.c @@ -108,7 +108,10 @@ static int mlx5e_tx_reporter_err_cqe_recover(void *ctx) mlx5e_reset_txqsq_cc_pc(sq); sq->stats->recover++; clear_bit(MLX5E_SQ_STATE_RECOVERING, &sq->state); + rtnl_lock(); mlx5e_activate_txqsq(sq); + rtnl_unlock(); + if (sq->channel) mlx5e_trigger_napi_icosq(sq->channel); else @@ -179,12 +182,16 @@ static int mlx5e_tx_reporter_ptpsq_unhealthy_recover(void *ctx) carrier_ok = netif_carrier_ok(netdev); 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Miller" , Jakub Kicinski , Paolo Abeni , Eric Dumazet CC: , Saeed Mahameed , Gal Pressman , Leon Romanovsky , Carolina Jubran , Tariq Toukan Subject: [PATCH net 6/6] net/mlx5e: Prevent deadlock while disabling aRFS Date: Thu, 11 Apr 2024 14:54:44 +0300 Message-ID: <20240411115444.374475-7-tariqt@nvidia.com> X-Mailer: git-send-email 2.44.0 In-Reply-To: <20240411115444.374475-1-tariqt@nvidia.com> References: <20240411115444.374475-1-tariqt@nvidia.com> Precedence: bulk X-Mailing-List: netdev@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-NV-OnPremToCloud: ExternallySecured X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: CH1PEPF0000AD81:EE_|PH7PR12MB5877:EE_ X-MS-Office365-Filtering-Correlation-Id: c94c7632-bba5-4af6-4baa-08dc5a1e58e6 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: sKffVDWUvZKSiaKy54VrowMNuu0i3Cj9M1c50xeQonA01JnQsLKEkOZlzBt6cu8LSCcIZZ+rqmH6r0QgNl2A0jjw81cxssp9JiDvOh4psTMSvR5MjTxripm02aX0xJPov4b1BUO7765SrGR2OT6y7D5bxP2i3D7vzAtB42V1wQGYD5muAzZjXPC574kNX8NMEAXs2VGmFdfwBgrDBgfG7iSHpoadGXrpy7Soyc5Ef1C7WS6dldy6Q0QRDpZmUt3UB7Svdeoh8yN4K3P3nI8BtJhvZu57hTZoi93r0KMrsmxfdVtrw20M+08afLDRLD9Gh669l/6GK5XIe3epRw0TK4CwERpQUEVhRN0ND2SRgmqS/A9xvaSJ19OPHQwpWXko6gtRCstiP/7O9BPyrCQ0xmUd7/1VA3sr5vKaqI7+K/d3d/6Xq6gNsJEFAtpk5c1hwo8K9YL/70hf8zRiKcRJMZ6vMRApycZTnI0oKL6HXEhWFyObIXVlTYw5szjhEefMFHlUBGNMgbLhZZ9fJ07qree8N0/rkbC8n5Od5xbY+vYoG/XmbM2z5Z9vgwk2ltJMEVDJD8yFTpdIxkjM0tul1A01Sl0r2vK6tBcZcbxJPJhWzQdDOJSP7ug90cVu+MMEldXAFoEcJCenQYKPLWT4ilpiuoMXwuZKv/9MoDCByVQzKhetp0i2wg4WbXEOw/RxbZB4RPFvphFDmp2TgVX6VvFv/0HJJb8T7FH/NGEDYsCnUyiBgluZS8qujIwnmGVq X-Forefront-Antispam-Report: CIP:216.228.118.232;CTRY:US;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:mail.nvidia.com;PTR:dc7edge1.nvidia.com;CAT:NONE;SFS:(13230031)(1800799015)(376005)(82310400014)(36860700004);DIR:OUT;SFP:1101; X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 11 Apr 2024 11:55:56.5211 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: c94c7632-bba5-4af6-4baa-08dc5a1e58e6 X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.118.232];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: CH1PEPF0000AD81.namprd04.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: PH7PR12MB5877 X-Patchwork-Delegate: kuba@kernel.org From: Carolina Jubran When disabling aRFS under the `priv->state_lock`, any scheduled aRFS works are canceled using the `cancel_work_sync` function, which waits for the work to end if it has already started. However, while waiting for the work handler, the handler will try to acquire the `state_lock` which is already acquired. The worker acquires the lock to delete the rules if the state is down, which is not the worker's responsibility since disabling aRFS deletes the rules. Add an aRFS state variable, which indicates whether the aRFS is enabled and prevent adding rules when the aRFS is disabled. Kernel log: ====================================================== WARNING: possible circular locking dependency detected 6.7.0-rc4_net_next_mlx5_5483eb2 #1 Tainted: G I ------------------------------------------------------ ethtool/386089 is trying to acquire lock: ffff88810f21ce68 ((work_completion)(&rule->arfs_work)){+.+.}-{0:0}, at: __flush_work+0x74/0x4e0 but task is already holding lock: ffff8884a1808cc0 (&priv->state_lock){+.+.}-{3:3}, at: mlx5e_ethtool_set_channels+0x53/0x200 [mlx5_core] which lock already depends on the new lock. the existing dependency chain (in reverse order) is: -> #1 (&priv->state_lock){+.+.}-{3:3}: __mutex_lock+0x80/0xc90 arfs_handle_work+0x4b/0x3b0 [mlx5_core] process_one_work+0x1dc/0x4a0 worker_thread+0x1bf/0x3c0 kthread+0xd7/0x100 ret_from_fork+0x2d/0x50 ret_from_fork_asm+0x11/0x20 -> #0 ((work_completion)(&rule->arfs_work)){+.+.}-{0:0}: __lock_acquire+0x17b4/0x2c80 lock_acquire+0xd0/0x2b0 __flush_work+0x7a/0x4e0 __cancel_work_timer+0x131/0x1c0 arfs_del_rules+0x143/0x1e0 [mlx5_core] mlx5e_arfs_disable+0x1b/0x30 [mlx5_core] mlx5e_ethtool_set_channels+0xcb/0x200 [mlx5_core] ethnl_set_channels+0x28f/0x3b0 ethnl_default_set_doit+0xec/0x240 genl_family_rcv_msg_doit+0xd0/0x120 genl_rcv_msg+0x188/0x2c0 netlink_rcv_skb+0x54/0x100 genl_rcv+0x24/0x40 netlink_unicast+0x1a1/0x270 netlink_sendmsg+0x214/0x460 __sock_sendmsg+0x38/0x60 __sys_sendto+0x113/0x170 __x64_sys_sendto+0x20/0x30 do_syscall_64+0x40/0xe0 entry_SYSCALL_64_after_hwframe+0x46/0x4e other info that might help us debug this: Possible unsafe locking scenario: CPU0 CPU1 ---- ---- lock(&priv->state_lock); lock((work_completion)(&rule->arfs_work)); lock(&priv->state_lock); lock((work_completion)(&rule->arfs_work)); *** DEADLOCK *** 3 locks held by ethtool/386089: #0: ffffffff82ea7210 (cb_lock){++++}-{3:3}, at: genl_rcv+0x15/0x40 #1: ffffffff82e94c88 (rtnl_mutex){+.+.}-{3:3}, at: ethnl_default_set_doit+0xd3/0x240 #2: ffff8884a1808cc0 (&priv->state_lock){+.+.}-{3:3}, at: mlx5e_ethtool_set_channels+0x53/0x200 [mlx5_core] stack backtrace: CPU: 15 PID: 386089 Comm: ethtool Tainted: G I 6.7.0-rc4_net_next_mlx5_5483eb2 #1 Hardware name: QEMU Standard PC (Q35 + ICH9, 2009), BIOS rel-1.13.0-0-gf21b5a4aeb02-prebuilt.qemu.org 04/01/2014 Call Trace: dump_stack_lvl+0x60/0xa0 check_noncircular+0x144/0x160 __lock_acquire+0x17b4/0x2c80 lock_acquire+0xd0/0x2b0 ? __flush_work+0x74/0x4e0 ? save_trace+0x3e/0x360 ? __flush_work+0x74/0x4e0 __flush_work+0x7a/0x4e0 ? __flush_work+0x74/0x4e0 ? __lock_acquire+0xa78/0x2c80 ? lock_acquire+0xd0/0x2b0 ? mark_held_locks+0x49/0x70 __cancel_work_timer+0x131/0x1c0 ? mark_held_locks+0x49/0x70 arfs_del_rules+0x143/0x1e0 [mlx5_core] mlx5e_arfs_disable+0x1b/0x30 [mlx5_core] mlx5e_ethtool_set_channels+0xcb/0x200 [mlx5_core] ethnl_set_channels+0x28f/0x3b0 ethnl_default_set_doit+0xec/0x240 genl_family_rcv_msg_doit+0xd0/0x120 genl_rcv_msg+0x188/0x2c0 ? ethnl_ops_begin+0xb0/0xb0 ? genl_family_rcv_msg_dumpit+0xf0/0xf0 netlink_rcv_skb+0x54/0x100 genl_rcv+0x24/0x40 netlink_unicast+0x1a1/0x270 netlink_sendmsg+0x214/0x460 __sock_sendmsg+0x38/0x60 __sys_sendto+0x113/0x170 ? do_user_addr_fault+0x53f/0x8f0 __x64_sys_sendto+0x20/0x30 do_syscall_64+0x40/0xe0 entry_SYSCALL_64_after_hwframe+0x46/0x4e Fixes: 45bf454ae884 ("net/mlx5e: Enabling aRFS mechanism") Signed-off-by: Carolina Jubran Signed-off-by: Tariq Toukan --- .../net/ethernet/mellanox/mlx5/core/en_arfs.c | 27 +++++++++++-------- 1 file changed, 16 insertions(+), 11 deletions(-) diff --git a/drivers/net/ethernet/mellanox/mlx5/core/en_arfs.c b/drivers/net/ethernet/mellanox/mlx5/core/en_arfs.c index c7f542d0b8f0..93cf23278d93 100644 --- a/drivers/net/ethernet/mellanox/mlx5/core/en_arfs.c +++ b/drivers/net/ethernet/mellanox/mlx5/core/en_arfs.c @@ -46,6 +46,10 @@ struct arfs_table { struct hlist_head rules_hash[ARFS_HASH_SIZE]; }; +enum { + MLX5E_ARFS_STATE_ENABLED, +}; + enum arfs_type { ARFS_IPV4_TCP, ARFS_IPV6_TCP, @@ -60,6 +64,7 @@ struct mlx5e_arfs_tables { spinlock_t arfs_lock; int last_filter_id; struct workqueue_struct *wq; + unsigned long state; }; struct arfs_tuple { @@ -170,6 +175,8 @@ int mlx5e_arfs_enable(struct mlx5e_flow_steering *fs) return err; } } + set_bit(MLX5E_ARFS_STATE_ENABLED, &arfs->state); + return 0; } @@ -455,6 +462,8 @@ static void arfs_del_rules(struct mlx5e_flow_steering *fs) int i; int j; + clear_bit(MLX5E_ARFS_STATE_ENABLED, &arfs->state); + spin_lock_bh(&arfs->arfs_lock); mlx5e_for_each_arfs_rule(rule, htmp, arfs->arfs_tables, i, j) { hlist_del_init(&rule->hlist); @@ -627,17 +636,8 @@ static void arfs_handle_work(struct work_struct *work) struct mlx5_flow_handle *rule; arfs = mlx5e_fs_get_arfs(priv->fs); - mutex_lock(&priv->state_lock); - if (!test_bit(MLX5E_STATE_OPENED, &priv->state)) { - spin_lock_bh(&arfs->arfs_lock); - hlist_del(&arfs_rule->hlist); - spin_unlock_bh(&arfs->arfs_lock); - - mutex_unlock(&priv->state_lock); - kfree(arfs_rule); - goto out; - } - mutex_unlock(&priv->state_lock); + if (!test_bit(MLX5E_ARFS_STATE_ENABLED, &arfs->state)) + return; if (!arfs_rule->rule) { rule = arfs_add_rule(priv, arfs_rule); @@ -753,6 +753,11 @@ int mlx5e_rx_flow_steer(struct net_device *dev, const struct sk_buff *skb, return -EPROTONOSUPPORT; spin_lock_bh(&arfs->arfs_lock); + if (!test_bit(MLX5E_ARFS_STATE_ENABLED, &arfs->state)) { + spin_unlock_bh(&arfs->arfs_lock); + return -EPERM; + } + arfs_rule = arfs_find_rule(arfs_t, &fk); if (arfs_rule) { if (arfs_rule->rxq == rxq_index || work_busy(&arfs_rule->arfs_work)) {