From patchwork Fri Apr 12 06:48:57 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Andy Chiu X-Patchwork-Id: 13626937 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 22DB5C4345F for ; Fri, 12 Apr 2024 06:49:14 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:Cc:To:In-Reply-To:References:Message-Id :MIME-Version:Subject:Date:From:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; bh=FnbptbPd82blWdPa+RcgtJcBy6Zn4gmFyenZW72M4pM=; b=Sp51bKu9Dbt7tQ 5XHvbzLIHRKPMTetFW4nz2+BskJefJEItp2mLA75C02mc0paa5QdGZym800dhvHWGItmGuTo4Wi09 ciQjy1o/yKfEihiCsM50UKU+vbRsuWac6W83KkcZG9TSvQ1yqmbe7wOE122+Q3GtbIvI2toaHnCII 8iFVJaAEIzeCmu2bE2ZW0AT1h+g6RayG/SqxKV4wboaMuKSEhAMvNcrhYgCSTQI80JAdVLa5AJ3If D3AY1XZBuOY+7gnyFYBa9Oqt3iqCuQF/oJOh2N9Ndvw/eiC/wv067fB2d5Or2erNlnAWkPs0fvTF5 OFix74lu2ffF8cj07HkQ==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.97.1 #2 (Red Hat Linux)) id 1rvAik-0000000FdHT-2QKu; Fri, 12 Apr 2024 06:49:10 +0000 Received: from mail-pf1-x433.google.com ([2607:f8b0:4864:20::433]) by bombadil.infradead.org with esmtps (Exim 4.97.1 #2 (Red Hat Linux)) id 1rvAii-0000000FdGO-0sN7 for linux-riscv@lists.infradead.org; Fri, 12 Apr 2024 06:49:09 +0000 Received: by mail-pf1-x433.google.com with SMTP id d2e1a72fcca58-6ed2dbf3c92so478717b3a.2 for ; Thu, 11 Apr 2024 23:49:07 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=sifive.com; s=google; t=1712904547; x=1713509347; darn=lists.infradead.org; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:from:to:cc:subject:date:message-id :reply-to; bh=srXw+GM0AbxLDkn2sukHjOTHYGaz4TEKS2v/bKB+HwE=; b=WTH+Mm64j28fmeUwAFdcKipjm+P6aU4Z2nhXBixOqiw+5wgWDy0XrpqAKI6x8TBPcI aw9F07dTtggpGBBtRX0wvXjeq3DFnFRVKaZeSv3GjM8bfeNQ2nncbCxBSquGTZQ/Di7S +GiwipumTLdS2nOWOFPCyjtGOYouZMCUyGRmEdAI8eZD9nXqbEFoXYoPg1dU2FLs+MLc qw/8LLId2GNTSfns3Pd8dCsKWPSHthVGtOCNwVymc8fv/KRhJ6BBfZWoQ8bIFmSA16SC LpuQH3fSKkqQPP0WbWgdWMgslMbpr3WAyIDKHPU9J8AcMxar13zEG0WW6Z+luyi8wMUc qwhQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1712904547; x=1713509347; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=srXw+GM0AbxLDkn2sukHjOTHYGaz4TEKS2v/bKB+HwE=; b=d1Du63HoEeN6r/FRNhVSIghhjim4VwIsspwW6oGHHP49mezsl3oTGGOO4yAOBDd/CG IlsyjL2StijuGvT0990XoRpuT41LL1wsrMZhQUmQqSPcWgcLkQ49WwZDPiHZGYYj1qGk 2VPeljsqgt8lVVBIajvLRL0edrWPN7JByNW6mYHhp4arbwcbapSZH4aySLcUGwjJkWPi rL0eeENyf9vmb8nJ/7xGkhc12hAjHa9vk8SfKCIwI3V0ru7aKI1LHGnVSd5f52eZ0l98 V7B/TnXBZI9sguPNsMDG3BFMPhbVeNh1a4IVOlV/RaL8A8vV/K4P3nQpkJUwBC1bnebn VRhg== X-Gm-Message-State: AOJu0YwphkL9FyIf7pryhTZfM5hoVt96BRl7lacnf35KhVYo9LpKCSww KZDvbDH0ohZvz/pYgmVEhB5jOEUaeQK0yYTsXugpuxM5GJ5yYMFZFbIA6YsgdpM= X-Google-Smtp-Source: AGHT+IF5X1v/E+xWlHK5pNpmDBocfNqmMv4DyaPfDHN3Yc/L8+Q+p/aEL01S9Eh4YMSg/dpHO62FGw== X-Received: by 2002:a05:6a20:bf2a:b0:1a3:afdc:fe5 with SMTP id gc42-20020a056a20bf2a00b001a3afdc0fe5mr1702435pzb.42.1712904546736; Thu, 11 Apr 2024 23:49:06 -0700 (PDT) Received: from [127.0.1.1] (59-124-168-89.hinet-ip.hinet.net. [59.124.168.89]) by smtp.gmail.com with ESMTPSA id q8-20020a170902b10800b001e107222eb5sm2258818plr.191.2024.04.11.23.49.03 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 11 Apr 2024 23:49:06 -0700 (PDT) From: Andy Chiu Date: Fri, 12 Apr 2024 14:48:57 +0800 Subject: [PATCH v4 1/9] riscv: vector: add a comment when calling riscv_setup_vsize() MIME-Version: 1.0 Message-Id: <20240412-zve-detection-v4-1-e0c45bb6b253@sifive.com> References: <20240412-zve-detection-v4-0-e0c45bb6b253@sifive.com> In-Reply-To: <20240412-zve-detection-v4-0-e0c45bb6b253@sifive.com> To: Paul Walmsley , Palmer Dabbelt , Albert Ou , Conor Dooley , Heiko Stuebner , Andy Chiu , Guo Ren , Conor Dooley , Rob Herring , Krzysztof Kozlowski , Jonathan Corbet , Evan Green , =?utf-8?b?Q2zDqW1lbnQgTMOpZ2Vy?= , Shuah Khan Cc: linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org, Palmer Dabbelt , Vincent Chen , Greentime Hu , devicetree@vger.kernel.org, linux-doc@vger.kernel.org, linux-kselftest@vger.kernel.org X-Mailer: b4 0.13-dev-a684c X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20240411_234908_298751_1843C5A3 X-CRM114-Status: GOOD ( 11.92 ) X-BeenThere: linux-riscv@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-riscv" Errors-To: linux-riscv-bounces+linux-riscv=archiver.kernel.org@lists.infradead.org The function would fail when it detects the calling hart's vlen doesn't match the first one's. The boot hart is the first hart calling this function during riscv_fill_hwcap, so it is impossible to fail here. Add a comment about this behavior. Signed-off-by: Andy Chiu Reviewed-by: Conor Dooley --- Changelog v2: - update the comment (Conor) --- arch/riscv/kernel/cpufeature.c | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/arch/riscv/kernel/cpufeature.c b/arch/riscv/kernel/cpufeature.c index 3ed2359eae35..d22b12072579 100644 --- a/arch/riscv/kernel/cpufeature.c +++ b/arch/riscv/kernel/cpufeature.c @@ -683,6 +683,10 @@ void __init riscv_fill_hwcap(void) } if (elf_hwcap & COMPAT_HWCAP_ISA_V) { + /* + * This callsite can't fail here. It cannot fail when called on + * the boot hart. + */ riscv_v_setup_vsize(); /* * ISA string in device tree might have 'v' flag, but From patchwork Fri Apr 12 06:48:58 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Andy Chiu X-Patchwork-Id: 13626939 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id C0FCCC4345F for ; Fri, 12 Apr 2024 06:49:19 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:Cc:To:In-Reply-To:References:Message-Id :MIME-Version:Subject:Date:From:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; bh=xkJj3vG3sRcSUiGiEl0Spdnmo0ecEDwluIo9Q6L+iDY=; b=DeU0kKoWkNmMrU 7gI4ksj1Hv46Hf4SwGsKrXXdtGhJmkZhlLGi1hNWJid0j8l3FG3Mstw08s/Qb+k6GQoBl2fnBXrwp bkXIw/eRzmfyPmi0toOvC/9aAkmXRAAqSSUvBxpMJko271MlhiUg+dO2E87QpjvDzMbBR004U+T+V w4e3Tgx3IBbCh5SbFD49N52Ye5wo3yVqtpgALEmzLq1saUwhpn49+MahxELtizVi51B0Xv7gFbSpC SWzkWS9Vp5/qIZJ0oGXyHEBPdPDpFVeUyYQknYi0SXSpSQFpnyzN9frOFtIJ19K1YPYXgYmM2zPiG MPFm0N9gKZ/O4PAe7kxA==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.97.1 #2 (Red Hat Linux)) id 1rvAio-0000000FdJz-2o6g; Fri, 12 Apr 2024 06:49:14 +0000 Received: from mail-pl1-x634.google.com ([2607:f8b0:4864:20::634]) by bombadil.infradead.org with esmtps (Exim 4.97.1 #2 (Red Hat Linux)) id 1rvAil-0000000FdHV-482J for linux-riscv@lists.infradead.org; Fri, 12 Apr 2024 06:49:13 +0000 Received: by mail-pl1-x634.google.com with SMTP id d9443c01a7336-1e5715a9ebdso5788985ad.2 for ; Thu, 11 Apr 2024 23:49:10 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=sifive.com; s=google; t=1712904550; x=1713509350; darn=lists.infradead.org; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:from:to:cc:subject:date:message-id :reply-to; bh=IE7PNdtEhi9KW+zIWld3aHVp99xlyaQhdGOlf9pdhFA=; b=J5fzixm0o4pvNdDi296nDphfPTvYhYecGNjC/ua2iLt282QxmFwy6fh2VEGh/IgdN9 1HqeM2tlYBRqzhQegJ2TbVMGZC59g3lBBoiNOD1BJLFWKZtUY5OfiRBCysYzWOJkFHAn S6t6/G0Pn97fd6qwMFlmKTZN9xZBptYMcaDHFNmT7uKGWdegUb+3JDFh/tn6XRNVDFy3 W7mEaybGR8TMwldkwm7PlJ/tLj4mOX4qZhoGT6iFuh/JNO7jn4BIyQpj5WecXj1W4G1y WzzsrEutgbNV/5BVbUTQLX6/5L2EPFXJFWsLDr1LP8e5u4ngTNorPVHevH+4so5g8O5F E3qw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1712904550; x=1713509350; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=IE7PNdtEhi9KW+zIWld3aHVp99xlyaQhdGOlf9pdhFA=; b=RuHoWWU7g8f4jM918Hn1C61q+m+3XxMTW+xKy0eJsFGwFFJmRzuIFi0QBxFEyIiz6B 5DJQbrtcr1wT+KK1MQeYWbFDJwJh+nJR3UyoDQrTaWnWfN7e4gRHCdCJT71FP0aZS9Ab 2XI7mDQ+/QrwTt3dKxmYqGr/MQ0sVJ0maIChtBG8jjX5/MhWGbq06eRQA2mxgKlO6ps6 NjiOZAiJzYM4qD2ftP6n8A32tu0iSaaWKtPPh8aRHGsiJuHzTR1m16N1gAOv2zftF8PF 6j7Em6M5QqxdcF999lQ3tTvHXqq9mZLLZzlismXoIDMnLLHplj5Zxv7cRPbm3zJNOQQo rZXg== X-Gm-Message-State: AOJu0YyGCEL2A8Dwjf0gXgoZ/PVffO4gplEMz4pDDwyxCIYaM43bloAi SorgjjuenkkYvINDK8P2fvz3vwxyGD89lRkPeos/6XH3kUUZZF5Ny4C2udaDwh0= X-Google-Smtp-Source: AGHT+IE8CTAbzbIbDZAwGKJBJYZimAcWW4i3f7cikqAXGoGmEwow1T9cytWYxzK5BB3Uu6leAZrAPw== X-Received: by 2002:a17:903:1210:b0:1e2:adad:75f4 with SMTP id l16-20020a170903121000b001e2adad75f4mr2046388plh.28.1712904550318; Thu, 11 Apr 2024 23:49:10 -0700 (PDT) Received: from [127.0.1.1] (59-124-168-89.hinet-ip.hinet.net. [59.124.168.89]) by smtp.gmail.com with ESMTPSA id q8-20020a170902b10800b001e107222eb5sm2258818plr.191.2024.04.11.23.49.07 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 11 Apr 2024 23:49:10 -0700 (PDT) From: Andy Chiu Date: Fri, 12 Apr 2024 14:48:58 +0800 Subject: [PATCH v4 2/9] riscv: smp: fail booting up smp if inconsistent vlen is detected MIME-Version: 1.0 Message-Id: <20240412-zve-detection-v4-2-e0c45bb6b253@sifive.com> References: <20240412-zve-detection-v4-0-e0c45bb6b253@sifive.com> In-Reply-To: <20240412-zve-detection-v4-0-e0c45bb6b253@sifive.com> To: Paul Walmsley , Palmer Dabbelt , Albert Ou , Conor Dooley , Heiko Stuebner , Andy Chiu , Guo Ren , Conor Dooley , Rob Herring , Krzysztof Kozlowski , Jonathan Corbet , Evan Green , =?utf-8?b?Q2zDqW1lbnQgTMOpZ2Vy?= , Shuah Khan Cc: linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org, Palmer Dabbelt , Vincent Chen , Greentime Hu , devicetree@vger.kernel.org, linux-doc@vger.kernel.org, linux-kselftest@vger.kernel.org X-Mailer: b4 0.13-dev-a684c X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20240411_234912_119901_965B1827 X-CRM114-Status: GOOD ( 15.70 ) X-BeenThere: linux-riscv@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-riscv" Errors-To: linux-riscv-bounces+linux-riscv=archiver.kernel.org@lists.infradead.org Currently we only support Vector for SMP platforms, that is, all SMP cores have the same vlenb. If we happen to detect a mismatching vlen, it is better to just fail bootting it up to prevent further race/scheduling issues. Also, move .Lsecondary_park forward and chage `tail smp_callin` into a regular call in the early assembly. So a core would be parked right after a return from smp_callin. Note that a successful smp_callin does not return. Fixes: 7017858eb2d7 ("riscv: Introduce riscv_v_vsize to record size of Vector context") Reported-by: Conor Dooley Closes: https://lore.kernel.org/linux-riscv/20240228-vicinity-cornstalk-4b8eb5fe5730@spud/ Signed-off-by: Andy Chiu Reviewed-by: Conor Dooley Reviewed-by: Yunhui Cui --- Changelog v4: - update comment also in the assembly code (Yunhui) Changelog v2: - update commit message to explain asm code change (Conor) --- arch/riscv/kernel/head.S | 19 ++++++++++++------- arch/riscv/kernel/smpboot.c | 14 +++++++++----- 2 files changed, 21 insertions(+), 12 deletions(-) diff --git a/arch/riscv/kernel/head.S b/arch/riscv/kernel/head.S index 4236a69c35cb..a00f7523cb91 100644 --- a/arch/riscv/kernel/head.S +++ b/arch/riscv/kernel/head.S @@ -165,9 +165,20 @@ secondary_start_sbi: #endif call .Lsetup_trap_vector scs_load_current - tail smp_callin + call smp_callin #endif /* CONFIG_SMP */ +.align 2 +.Lsecondary_park: + /* + * Park this hart if we: + * - have too many harts on CONFIG_RISCV_BOOT_SPINWAIT + * - receive an early trap, before setup_trap_vector finished + * - fail in smp_callin(), as a successful one wouldn't return + */ + wfi + j .Lsecondary_park + .align 2 .Lsetup_trap_vector: /* Set trap vector to exception handler */ @@ -181,12 +192,6 @@ secondary_start_sbi: csrw CSR_SCRATCH, zero ret -.align 2 -.Lsecondary_park: - /* We lack SMP support or have too many harts, so park this hart */ - wfi - j .Lsecondary_park - SYM_CODE_END(_start) SYM_CODE_START(_start_kernel) diff --git a/arch/riscv/kernel/smpboot.c b/arch/riscv/kernel/smpboot.c index d41090fc3203..673437ccc13d 100644 --- a/arch/riscv/kernel/smpboot.c +++ b/arch/riscv/kernel/smpboot.c @@ -214,6 +214,15 @@ asmlinkage __visible void smp_callin(void) struct mm_struct *mm = &init_mm; unsigned int curr_cpuid = smp_processor_id(); + if (has_vector()) { + /* + * Return as early as possible so the hart with a mismatching + * vlen won't boot. + */ + if (riscv_v_setup_vsize()) + return; + } + /* All kernel threads share the same mm context. */ mmgrab(mm); current->active_mm = mm; @@ -226,11 +235,6 @@ asmlinkage __visible void smp_callin(void) numa_add_cpu(curr_cpuid); set_cpu_online(curr_cpuid, 1); - if (has_vector()) { - if (riscv_v_setup_vsize()) - elf_hwcap &= ~COMPAT_HWCAP_ISA_V; - } - riscv_user_isa_enable(); /* From patchwork Fri Apr 12 06:48:59 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Andy Chiu X-Patchwork-Id: 13626940 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 9EAB0C4345F for ; Fri, 12 Apr 2024 06:49:22 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:Cc:To:In-Reply-To:References:Message-Id :MIME-Version:Subject:Date:From:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; bh=HRkK5JLUjSd3c4Ht8r5i6PGIVCfC60w84kg1y0rhn/g=; b=OnkrWav4wP12CF D0cgNl7spoM9tqUD3W55YwXtg+pPcE/1fI2K2I4M7d1idwStyZdItUpqENoOr/w9s1FhbVXTFRWC1 wBqwuPy3Kobo6/eIbS8mQNwZbOuijM6PU2lImRdTLEg/9eLoI/2thPfjUWuloXjmvb5hNSC3hHJTc g/6A2BYP92ZmixbixwrxGkkZBVeTAW6OB6m8GRFCpixNzNPvHUUIcCoOsaCiZAlShxtGIlyD3UwL5 WCRNy0vCIGJpJ7if3rMWlmUKWh8W5YBhSkuFvKUeRyeK2fBuQ25hzHBtDCx0xG3USpW/iuGeOPJJ/ 5jASUnA7x2uZtHDIOOyw==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.97.1 #2 (Red Hat Linux)) id 1rvAir-0000000FdM5-3OL9; Fri, 12 Apr 2024 06:49:17 +0000 Received: from mail-pl1-x635.google.com ([2607:f8b0:4864:20::635]) by bombadil.infradead.org with esmtps (Exim 4.97.1 #2 (Red Hat Linux)) id 1rvAio-0000000FdJg-2UQI for linux-riscv@lists.infradead.org; Fri, 12 Apr 2024 06:49:16 +0000 Received: by mail-pl1-x635.google.com with SMTP id d9443c01a7336-1e5aa82d1f6so1522915ad.0 for ; Thu, 11 Apr 2024 23:49:14 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=sifive.com; s=google; t=1712904554; x=1713509354; darn=lists.infradead.org; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:from:to:cc:subject:date:message-id :reply-to; bh=OADn3kHEewLkE3kxFhkvk62eojDLq3ulyri6MOmjFqk=; b=KwgN23MlPFkiMxQxAtnFM7ZUkiDpTDCwR7/u4v1h9Udm1WEqSjFvbUrj5Ipg3Edv2p OMwkxTbsNrCNTIZawDQlYqlsZyQQAeBCVl+gyqOtq8fADun11Vi9xUN0aDeeB3mrkDO5 eTrLMMz4OGKDKQWAG4iWmoubvsiRqHZsuTqR7tPzIoIK87RKPzWiGrN24WHNVwXQXYhx Ejqf4Wdv0JV5zFg/raf2hDv3ZmhqIZ5CJSLBPw4jkTrbkMgp/oPzo72AxcWt8oK4Fvz5 HgY1QtRv8Y52ylv5WqDIKnr51X5c18DGDpP95cPeNO7H/CQiYg4lWuMn3JKnfI4pmxI8 ihkQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1712904554; x=1713509354; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=OADn3kHEewLkE3kxFhkvk62eojDLq3ulyri6MOmjFqk=; b=KWsOS8O0l28vCNz2p1K9vNUOaGZx6zLVUjSsYijwMEuqChKGs8fRV8Y2ExRGwvpSZO o+OYnHZuixE7mVG+/+U2kqqBmTdrvZCLa082DHvpOom4bv+nkHtbMtvNf2xQ8+UegfXa k26Uqpt8eehThxNBBt/qFm/Jsp8ajO2WWXmTeoOhSbkBNXO3UUJW+Wz5qIybzXMTaujm 7RQgHUkWzcZJs24P100DZdSDJ/WKeUTrJKNsKJTqqsRLxBoVX06aI3uwr2VBcwnnPFcX aIB6nQ8SLaBAbBZoHC3GCMqztqVyYjsybC0HczUjR9plqFhf8T7qWPeK9jchZ8wtJu3E LnYA== X-Gm-Message-State: AOJu0YxdTSjXrDNNEZvWSGzqcrHuIGSiokFi27hmWurJCuGPe51IyH/T 1qeqB/YFvrXNjAyc/QS8jOCJu0NrbuI8Z83XoMoV0DDxg+yVKiNhktZYGCR5Ucc= X-Google-Smtp-Source: AGHT+IFbQ2c5TpJxdrKyUl2ru1yHmpDc6XY0Qm2Yv9aIIgLh9stQZB1+mDwKdX6s0oRU3mLmFdEA7w== X-Received: by 2002:a17:902:cec1:b0:1e3:ce12:ef77 with SMTP id d1-20020a170902cec100b001e3ce12ef77mr2423696plg.11.1712904553854; Thu, 11 Apr 2024 23:49:13 -0700 (PDT) Received: from [127.0.1.1] (59-124-168-89.hinet-ip.hinet.net. [59.124.168.89]) by smtp.gmail.com with ESMTPSA id q8-20020a170902b10800b001e107222eb5sm2258818plr.191.2024.04.11.23.49.10 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 11 Apr 2024 23:49:13 -0700 (PDT) From: Andy Chiu Date: Fri, 12 Apr 2024 14:48:59 +0800 Subject: [PATCH v4 3/9] riscv: cpufeature: call match_isa_ext() for single-letter extensions MIME-Version: 1.0 Message-Id: <20240412-zve-detection-v4-3-e0c45bb6b253@sifive.com> References: <20240412-zve-detection-v4-0-e0c45bb6b253@sifive.com> In-Reply-To: <20240412-zve-detection-v4-0-e0c45bb6b253@sifive.com> To: Paul Walmsley , Palmer Dabbelt , Albert Ou , Conor Dooley , Heiko Stuebner , Andy Chiu , Guo Ren , Conor Dooley , Rob Herring , Krzysztof Kozlowski , Jonathan Corbet , Evan Green , =?utf-8?b?Q2zDqW1lbnQgTMOpZ2Vy?= , Shuah Khan Cc: linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org, Palmer Dabbelt , Vincent Chen , Greentime Hu , devicetree@vger.kernel.org, linux-doc@vger.kernel.org, linux-kselftest@vger.kernel.org X-Mailer: b4 0.13-dev-a684c X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20240411_234914_699947_0A36032C X-CRM114-Status: GOOD ( 11.57 ) X-BeenThere: linux-riscv@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-riscv" Errors-To: linux-riscv-bounces+linux-riscv=archiver.kernel.org@lists.infradead.org Single-letter extensions may also imply multiple subextensions. For example, Vector extension implies zve64d, and zve64d implies zve64f. Extension parsing for "riscv,isa-extensions" has the ability to resolve the dependency by calling match_isa_ext(). This patch makes deprecated parser call the same function for single letter extensions. Signed-off-by: Andy Chiu Reviewed-by: Conor Dooley --- Changelog v3: - Remove set_bit for single-letter extensions as they are all checked in match_isa_ext. (Clément) --- arch/riscv/kernel/cpufeature.c | 11 +++++------ 1 file changed, 5 insertions(+), 6 deletions(-) diff --git a/arch/riscv/kernel/cpufeature.c b/arch/riscv/kernel/cpufeature.c index d22b12072579..f6f3ece60d69 100644 --- a/arch/riscv/kernel/cpufeature.c +++ b/arch/riscv/kernel/cpufeature.c @@ -468,16 +468,15 @@ static void __init riscv_parse_isa_string(unsigned long *this_hwcap, struct risc if (unlikely(ext_err)) continue; + + for (int i = 0; i < riscv_isa_ext_count; i++) + match_isa_ext(&riscv_isa_ext[i], ext, ext_end, isainfo); + if (!ext_long) { int nr = tolower(*ext) - 'a'; - if (riscv_isa_extension_check(nr)) { + if (riscv_isa_extension_check(nr)) *this_hwcap |= isa2hwcap[nr]; - set_bit(nr, isainfo->isa); - } - } else { - for (int i = 0; i < riscv_isa_ext_count; i++) - match_isa_ext(&riscv_isa_ext[i], ext, ext_end, isainfo); } } } From patchwork Fri Apr 12 06:49:00 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Andy Chiu X-Patchwork-Id: 13626941 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 264C8C4345F for ; Fri, 12 Apr 2024 06:49:25 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:Cc:To:In-Reply-To:References:Message-Id :MIME-Version:Subject:Date:From:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; bh=lH9JzmaxcmL251tr6CVMCa9IeBz8So4IlOmxhYL0BZg=; b=YAGUTrc8VwR5Xk vAbPx694AePOf73MAWQ4zewRV/5T7uKJAecoB1amBGAGw7fWQk4KbtG+/VvtXfZMBkBD90JyKcjQx ksoikM4UW+eLHpaNZ3GbNqXDEi+tltA4qI5xLQCeLW0F5L1uErjtcm0N1KyCNjaAcp1uZ2iSV5Sys 2eVm+wxW+v+oKbDvOVcVJVJyejVS+SwidA8enf9ijopfl81q0+YqMLnRvQYVhVOKnQnecIk0pepxv tr+WzrZHKmBRO5VH9BWcrg952+qPKpbF3yeqLyJmeanPNLWD497+duG1qqQycKpZ3gKSerQ/b8Vd7 lvltIwhdNMn8mNvgIJoQ==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.97.1 #2 (Red Hat Linux)) id 1rvAiv-0000000FdOV-3zJy; Fri, 12 Apr 2024 06:49:21 +0000 Received: from mail-pf1-x42c.google.com ([2607:f8b0:4864:20::42c]) by bombadil.infradead.org with esmtps (Exim 4.97.1 #2 (Red Hat Linux)) id 1rvAis-0000000FdME-2QU1 for linux-riscv@lists.infradead.org; Fri, 12 Apr 2024 06:49:20 +0000 Received: by mail-pf1-x42c.google.com with SMTP id d2e1a72fcca58-6ecf406551aso497709b3a.2 for ; Thu, 11 Apr 2024 23:49:18 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=sifive.com; s=google; t=1712904557; x=1713509357; darn=lists.infradead.org; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:from:to:cc:subject:date:message-id :reply-to; bh=OG/1LVtmS5PJqTGfRsDdfy/GBt6FFfLWIvrVveL3MDU=; b=aef7Cehs9ccg4PhKCHjoZzosw6rLVGbqi+3fEPSt74MWrgzWIZuUuvsg7jP7m0xMQQ F0kvYBygHTs5lC7hQf92U7oi65Q8VgLLxiGRer8T6ZVmYc5iA7TacWX6avR4hD//Jw7P i/vSIbX+Vd4y/Cx/CVQZKGVwih2TMUBB3awD8/JS6gHcUJeObO/d3yhRdfrEey2Ho9ZM 1P+a1OdRbaN7Cs7REk00H7PiU1hHRSi887afk/2xZNhZJ12/QnpVhJ9qFhhFkZ9E3Jje 3fZ8D4D0ayOuG+3/OiyjmDkG0A9bhHbE7l/2OTfK0ZDepP8bFLHvrGJFbu2KDRwxxQLV PduQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1712904557; x=1713509357; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=OG/1LVtmS5PJqTGfRsDdfy/GBt6FFfLWIvrVveL3MDU=; b=hibUOALXYxTaJiaMcTrcBpB/hppXzKtGhNeBp0IO/BEQ5ywNuihTJxP6d83Wkqxves O3+T+ylvD/91Yzsbzvy62UmYKAlyM2KtTh0Y8yvj2s/gFfT26RvNujVSIHErnabIel4W xfYsWJyeUxbCCPEYn360/QBchJgFc3ItziUonpxU/vKmkWxSQ8YQOrbJlQmZuBdhOnsZ bE1FDekRaeo7FI0cp2TTpIJKWwCLhWbmaarvGTfmMYlmFxajc3CTjYIz77P83L0yHvaC blqKmIMco4CaKAzGv1TknllhURoj7N1xriVN1BlqTGeX0fllpfEuYr51v0h7CtxV3E5m 2YVg== X-Gm-Message-State: AOJu0Yz/NaO5hvwh6xY61oV85MjMrwKJfxlwWw7kaFnYenaN6YGCfrTS XGFkijWzxyTaRYCeclcVMWo/6WQSO045t8df1PDGmt46Y43QCXaEAQQwPDEG540= X-Google-Smtp-Source: AGHT+IFZRErvycpHhYv8nDAOA0AKK9dvDMskucFNFf/LNGcE2rSUEQs2FrZTO0yAgsH3aEtNLPJo3w== X-Received: by 2002:a05:6a20:3d85:b0:1a7:4962:6fad with SMTP id s5-20020a056a203d8500b001a749626fadmr2551948pzi.10.1712904557446; Thu, 11 Apr 2024 23:49:17 -0700 (PDT) Received: from [127.0.1.1] (59-124-168-89.hinet-ip.hinet.net. [59.124.168.89]) by smtp.gmail.com with ESMTPSA id q8-20020a170902b10800b001e107222eb5sm2258818plr.191.2024.04.11.23.49.14 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 11 Apr 2024 23:49:17 -0700 (PDT) From: Andy Chiu Date: Fri, 12 Apr 2024 14:49:00 +0800 Subject: [PATCH v4 4/9] riscv: cpufeature: add zve32[xf] and zve64[xfd] isa detection MIME-Version: 1.0 Message-Id: <20240412-zve-detection-v4-4-e0c45bb6b253@sifive.com> References: <20240412-zve-detection-v4-0-e0c45bb6b253@sifive.com> In-Reply-To: <20240412-zve-detection-v4-0-e0c45bb6b253@sifive.com> To: Paul Walmsley , Palmer Dabbelt , Albert Ou , Conor Dooley , Heiko Stuebner , Andy Chiu , Guo Ren , Conor Dooley , Rob Herring , Krzysztof Kozlowski , Jonathan Corbet , Evan Green , =?utf-8?b?Q2zDqW1lbnQgTMOpZ2Vy?= , Shuah Khan Cc: linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org, Palmer Dabbelt , Vincent Chen , Greentime Hu , devicetree@vger.kernel.org, linux-doc@vger.kernel.org, linux-kselftest@vger.kernel.org X-Mailer: b4 0.13-dev-a684c X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20240411_234918_687524_B7762941 X-CRM114-Status: GOOD ( 13.24 ) X-BeenThere: linux-riscv@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-riscv" Errors-To: linux-riscv-bounces+linux-riscv=archiver.kernel.org@lists.infradead.org Multiple Vector subextensions are added. Also, the patch takes care of the dependencies of Vector subextensions by macro expansions. So, if some "embedded" platform only reports "zve64f" on the ISA string, the parser is able to expand it to zve32x zve32f zve64x and zve64f. Signed-off-by: Andy Chiu Reviewed-by: Conor Dooley --- Changelog v3: - renumber RISCV_ISA_EXT_ZVE* to rebase on top of 6.9 - alphabetically sort added extensions (Clément) Changelog v2: - remove the extension itself from its isa_exts[] list (Clément) - use riscv_zve64d_exts for v's extension list (Samuel) --- arch/riscv/include/asm/hwcap.h | 5 +++++ arch/riscv/kernel/cpufeature.c | 36 +++++++++++++++++++++++++++++++++++- 2 files changed, 40 insertions(+), 1 deletion(-) diff --git a/arch/riscv/include/asm/hwcap.h b/arch/riscv/include/asm/hwcap.h index e17d0078a651..f64d4e98e67c 100644 --- a/arch/riscv/include/asm/hwcap.h +++ b/arch/riscv/include/asm/hwcap.h @@ -81,6 +81,11 @@ #define RISCV_ISA_EXT_ZTSO 72 #define RISCV_ISA_EXT_ZACAS 73 #define RISCV_ISA_EXT_XANDESPMU 74 +#define RISCV_ISA_EXT_ZVE32X 75 +#define RISCV_ISA_EXT_ZVE32F 76 +#define RISCV_ISA_EXT_ZVE64X 77 +#define RISCV_ISA_EXT_ZVE64F 78 +#define RISCV_ISA_EXT_ZVE64D 79 #define RISCV_ISA_EXT_XLINUXENVCFG 127 diff --git a/arch/riscv/kernel/cpufeature.c b/arch/riscv/kernel/cpufeature.c index f6f3ece60d69..38d09de518b1 100644 --- a/arch/riscv/kernel/cpufeature.c +++ b/arch/riscv/kernel/cpufeature.c @@ -188,6 +188,35 @@ static const unsigned int riscv_zvbb_exts[] = { RISCV_ISA_EXT_ZVKB }; +#define RISCV_ISA_EXT_ZVE32F_IMPLY_LIST \ + RISCV_ISA_EXT_ZVE32X, + +#define RISCV_ISA_EXT_ZVE64F_IMPLY_LIST \ + RISCV_ISA_EXT_ZVE64X, \ + RISCV_ISA_EXT_ZVE32F, \ + RISCV_ISA_EXT_ZVE32F_IMPLY_LIST + +#define RISCV_ISA_EXT_ZVE64D_IMPLY_LIST \ + RISCV_ISA_EXT_ZVE64F, \ + RISCV_ISA_EXT_ZVE64F_IMPLY_LIST + +static const unsigned int riscv_zve32f_exts[] = { + RISCV_ISA_EXT_ZVE32F_IMPLY_LIST +}; + +static const unsigned int riscv_zve64f_exts[] = { + RISCV_ISA_EXT_ZVE64F_IMPLY_LIST +}; + +static const unsigned int riscv_zve64d_exts[] = { + RISCV_ISA_EXT_ZVE64D_IMPLY_LIST +}; + +static const unsigned int riscv_zve64x_exts[] = { + RISCV_ISA_EXT_ZVE32X, + RISCV_ISA_EXT_ZVE64X +}; + /* * While the [ms]envcfg CSRs were not defined until version 1.12 of the RISC-V * privileged ISA, the existence of the CSRs is implied by any extension which @@ -245,7 +274,7 @@ const struct riscv_isa_ext_data riscv_isa_ext[] = { __RISCV_ISA_EXT_DATA(d, RISCV_ISA_EXT_d), __RISCV_ISA_EXT_DATA(q, RISCV_ISA_EXT_q), __RISCV_ISA_EXT_DATA(c, RISCV_ISA_EXT_c), - __RISCV_ISA_EXT_DATA(v, RISCV_ISA_EXT_v), + __RISCV_ISA_EXT_SUPERSET(v, RISCV_ISA_EXT_v, riscv_zve64d_exts), __RISCV_ISA_EXT_DATA(h, RISCV_ISA_EXT_h), __RISCV_ISA_EXT_SUPERSET(zicbom, RISCV_ISA_EXT_ZICBOM, riscv_xlinuxenvcfg_exts), __RISCV_ISA_EXT_SUPERSET(zicboz, RISCV_ISA_EXT_ZICBOZ, riscv_xlinuxenvcfg_exts), @@ -280,6 +309,11 @@ const struct riscv_isa_ext_data riscv_isa_ext[] = { __RISCV_ISA_EXT_DATA(ztso, RISCV_ISA_EXT_ZTSO), __RISCV_ISA_EXT_SUPERSET(zvbb, RISCV_ISA_EXT_ZVBB, riscv_zvbb_exts), __RISCV_ISA_EXT_DATA(zvbc, RISCV_ISA_EXT_ZVBC), + __RISCV_ISA_EXT_SUPERSET(zve32f, RISCV_ISA_EXT_ZVE32F, riscv_zve32f_exts), + __RISCV_ISA_EXT_DATA(zve32x, RISCV_ISA_EXT_ZVE32X), + __RISCV_ISA_EXT_SUPERSET(zve64d, RISCV_ISA_EXT_ZVE64D, riscv_zve64d_exts), + __RISCV_ISA_EXT_SUPERSET(zve64f, RISCV_ISA_EXT_ZVE64F, riscv_zve64f_exts), + __RISCV_ISA_EXT_SUPERSET(zve64x, RISCV_ISA_EXT_ZVE64X, riscv_zve64x_exts), __RISCV_ISA_EXT_DATA(zvfh, RISCV_ISA_EXT_ZVFH), __RISCV_ISA_EXT_DATA(zvfhmin, RISCV_ISA_EXT_ZVFHMIN), __RISCV_ISA_EXT_DATA(zvkb, RISCV_ISA_EXT_ZVKB), From patchwork Fri Apr 12 06:49:01 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Andy Chiu X-Patchwork-Id: 13626942 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 47DE1C4345F for ; Fri, 12 Apr 2024 06:49:32 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:Cc:To:In-Reply-To:References:Message-Id :MIME-Version:Subject:Date:From:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; bh=WZTJ8gm7+SvtMbWdj5FipBM/3otlkgk7Nt3Uh6bg3fw=; b=WllIoqz8ZiEtjc ROYe4GbBgDLlSNo7BcQH9qNbyMzTuZDkJKdDs5biD67pPyDavkmZxty7AwVuEnKFOd+IhUx1ZO35d fD+o064ZR20iSJlLhCMA4EjtgB6+L/6/dX2QHbSdRCgATK2O5Z0A++VUf2RGzWn9Nti4Zbkzdr/RZ D3wenVgbIsciKG37hSPbphif1GJQT5F7YDUo4mI2lAoml/vILc8yqbBIEI/iAQa8cptqDdr+FMQTC 8GpbrdKVOenS08QeXgugw9UxNsYOkZtMKUZEJ0IuHdR660MeMH3nv6iC5XNuWnioPRXYe0ki+peH6 Tz6QdnHAte8D+jx+2taw==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.97.1 #2 (Red Hat Linux)) id 1rvAj2-0000000FdTl-1dgg; Fri, 12 Apr 2024 06:49:28 +0000 Received: from mail-pl1-x633.google.com ([2607:f8b0:4864:20::633]) by bombadil.infradead.org with esmtps (Exim 4.97.1 #2 (Red Hat Linux)) id 1rvAiw-0000000FdON-2lL2 for linux-riscv@lists.infradead.org; Fri, 12 Apr 2024 06:49:25 +0000 Received: by mail-pl1-x633.google.com with SMTP id d9443c01a7336-1e36b7e7dd2so5422355ad.1 for ; Thu, 11 Apr 2024 23:49:22 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=sifive.com; s=google; t=1712904561; x=1713509361; darn=lists.infradead.org; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:from:to:cc:subject:date:message-id :reply-to; bh=wmjJM7prKhSJUQ/iHjZSKFVAIwCvyZorqbvL8NpufQk=; b=c8ianW2qsiC1LdnvaFt0gjmxZUeVS5ymV65lwf7lDR1UZcEvaHkkIXrhXl+41AQUSq 6DREcIQKw68/JDuF//FXsLE6KEw5lqpcKNGbCw3WAjGe4A3RZkk4vwQoI7va8wY/Re5D rOj943dq3WkHn0d7jbs+Fw/Ju2uRUR2su9hTRMIFhI7uVE/SuKXVkeDhb8n0XEJn7b8D 1QopLttYvtfURteSx98C0Nyvqt3+lzllVGQsxkXt4vbIgyAyI1/FnJLmtdVMlSO/Lu+3 gzrtO0KdMu+si70eQV6Xz79ndjsf3SijIrZtsVnwfdgEJjG4TZTXNltL1EXqLTBaovZh JPKQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1712904561; x=1713509361; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=wmjJM7prKhSJUQ/iHjZSKFVAIwCvyZorqbvL8NpufQk=; b=qZ0hQOqM1yE9m6gP6Agdiubx8AMjnrBdNEQEQCUtbjcR1rY9w/F4NYku0IDt4vaOb2 am2Wol8wSIybwigcYcoEuySfzNeumuBscbVP5t/WTCtHBDtimLlPAeNEvGLJ1/mEtAI6 BgePR4fSU0EbrLZkYiD9wl4lJsQ14dXNnbhqd7E+DzEgrJe21Ytx4Te9IM+8/KDJ1geU lqfwKnMa2Wi4HY4RnfGMnBnP3QXOoYK8Yng0CQhLwmUmwgs9yqv0ZYtAUx7J36PjOxJL /ZH9H15M6HbfHWubgTjJK3OQMplL6UxLOL4uz2lpapXa1hR7cgCYgksnTvAchKvAdyAE oBQg== X-Gm-Message-State: AOJu0Yz6ONARNqlQFqQnkSUkiy6zjwMKyZaYnIkLP1gMEyTIgLnIv7Q5 liY4x4IL0sSadxxpmk4zeyB8Ih97c15gcprb9STz2js0f0jj3BWQH/20BKqi3LA= X-Google-Smtp-Source: AGHT+IGm9y8I11+R6SyRv/t5G6RHmcLUsT36+9WxupmJkWY3E0gV+Me9Ik9kATEAv67/WzjE2CXInQ== X-Received: by 2002:a17:902:f711:b0:1e0:157a:846c with SMTP id h17-20020a170902f71100b001e0157a846cmr1494556plo.55.1712904561015; Thu, 11 Apr 2024 23:49:21 -0700 (PDT) Received: from [127.0.1.1] (59-124-168-89.hinet-ip.hinet.net. [59.124.168.89]) by smtp.gmail.com with ESMTPSA id q8-20020a170902b10800b001e107222eb5sm2258818plr.191.2024.04.11.23.49.17 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 11 Apr 2024 23:49:20 -0700 (PDT) From: Andy Chiu Date: Fri, 12 Apr 2024 14:49:01 +0800 Subject: [PATCH v4 5/9] dt-bindings: riscv: add Zve32[xf] Zve64[xfd] ISA extension description MIME-Version: 1.0 Message-Id: <20240412-zve-detection-v4-5-e0c45bb6b253@sifive.com> References: <20240412-zve-detection-v4-0-e0c45bb6b253@sifive.com> In-Reply-To: <20240412-zve-detection-v4-0-e0c45bb6b253@sifive.com> To: Paul Walmsley , Palmer Dabbelt , Albert Ou , Conor Dooley , Heiko Stuebner , Andy Chiu , Guo Ren , Conor Dooley , Rob Herring , Krzysztof Kozlowski , Jonathan Corbet , Evan Green , =?utf-8?b?Q2zDqW1lbnQgTMOpZ2Vy?= , Shuah Khan Cc: linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org, Palmer Dabbelt , Vincent Chen , Greentime Hu , devicetree@vger.kernel.org, linux-doc@vger.kernel.org, linux-kselftest@vger.kernel.org X-Mailer: b4 0.13-dev-a684c X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20240411_234922_884207_5531BDDD X-CRM114-Status: UNSURE ( 8.27 ) X-CRM114-Notice: Please train this message. X-BeenThere: linux-riscv@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-riscv" Errors-To: linux-riscv-bounces+linux-riscv=archiver.kernel.org@lists.infradead.org Add description for Zve32x Zve32f Zve64x Zve64f Zve64d ISA extensions. Signed-off-by: Andy Chiu Acked-by: Conor Dooley --- Changelog v3: - Correct extension names and their order (Stefan) Changelog v2: - new patch since v2 --- .../devicetree/bindings/riscv/extensions.yaml | 30 ++++++++++++++++++++++ 1 file changed, 30 insertions(+) diff --git a/Documentation/devicetree/bindings/riscv/extensions.yaml b/Documentation/devicetree/bindings/riscv/extensions.yaml index 468c646247aa..cfed80ad5540 100644 --- a/Documentation/devicetree/bindings/riscv/extensions.yaml +++ b/Documentation/devicetree/bindings/riscv/extensions.yaml @@ -381,6 +381,36 @@ properties: instructions, as ratified in commit 56ed795 ("Update riscv-crypto-spec-vector.adoc") of riscv-crypto. + - const: zve32f + description: + The standard Zve32f extension for embedded processors, as ratified + in commit 6f702a2 ("Vector extensions are now ratified") of + riscv-v-spec. + + - const: zve32x + description: + The standard Zve32x extension for embedded processors, as ratified + in commit 6f702a2 ("Vector extensions are now ratified") of + riscv-v-spec. + + - const: zve64d + description: + The standard Zve64d extension for embedded processors, as ratified + in commit 6f702a2 ("Vector extensions are now ratified") of + riscv-v-spec. + + - const: zve64f + description: + The standard Zve64f extension for embedded processors, as ratified + in commit 6f702a2 ("Vector extensions are now ratified") of + riscv-v-spec. + + - const: zve64x + description: + The standard Zve64x extension for embedded processors, as ratified + in commit 6f702a2 ("Vector extensions are now ratified") of + riscv-v-spec. + - const: zvfh description: The standard Zvfh extension for vectored half-precision From patchwork Fri Apr 12 06:49:02 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Andy Chiu X-Patchwork-Id: 13626943 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id EC985C4345F for ; Fri, 12 Apr 2024 06:49:34 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:Cc:To:In-Reply-To:References:Message-Id :MIME-Version:Subject:Date:From:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; bh=hR3Ia0lUEDK9v2t69WHiUMBKt+Zvge/TI/Mk9+FtGNA=; b=tteC9XKuEzF4Kl TYktzWyJkyB9iavdtjXBfRsaBQpMivdb5GqYvQuNdYms+NUK33DutAOj6IxWSftPnQ7769f78y/+7 Quhb4VKOq8Z2apk2sB/Zu+PPRKVdLlxDSBDp6vmTctw1WsYdOD1sPHJ8ndB1+lTUZhtco+ZCofNmu +C+wDTs+uasfN8zz78QbYqK5cmugpK3FR0gSeDfJTmmGvOHueI+wXacQGrRZ2nWLzVJf0k8hVyBhC 0hO9E3TyEc4+sshZaPRLsjOr8g212pc0XRSxsj/hsZQi+BOutpBIrR4kxiHqC5fg7gXTmUx3Rjeb+ Tntn5ZnfMRBGIb+EMP8Q==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.97.1 #2 (Red Hat Linux)) id 1rvAj4-0000000FdVS-08mu; Fri, 12 Apr 2024 06:49:30 +0000 Received: from mail-pl1-x62b.google.com ([2607:f8b0:4864:20::62b]) by bombadil.infradead.org with esmtps (Exim 4.97.1 #2 (Red Hat Linux)) id 1rvAiz-0000000FdRZ-4AIA for linux-riscv@lists.infradead.org; Fri, 12 Apr 2024 06:49:28 +0000 Received: by mail-pl1-x62b.google.com with SMTP id d9443c01a7336-1e2bbc2048eso5360395ad.3 for ; Thu, 11 Apr 2024 23:49:25 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=sifive.com; s=google; t=1712904565; x=1713509365; darn=lists.infradead.org; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:from:to:cc:subject:date:message-id :reply-to; bh=pHRXW9BfVlGJGTuBqz21x9jZhOCb5ENaxkoeEzRsV8g=; b=QxSKWsVLZHQfCv3lfmu/wWz0Q1UcCN6vlOfhUhH2TZSSq1X0832BUMly4A7jHv0eIm z3fnrmOgQorpbeu957th9i3NbFZJyno0wnmQYcNbPJzmlHCsED1ldNefkgMgpcI2gOTU hQppqwKknDoIWDcKoH0R/4lCfO8/ClScjWYSZMfvdeaebrDVTY9YfCUUF1L2ycuXwvGi v0f2YJIxI4bom9Nf5GHsD5at7n87c63cKXjivXfAOydyA9ANOhszqL0uqAujcwzJqxii IeouLHXX0B+WbRoVq4n6V7q4KKc/GijfKZLO0O6hUvqXoTq8DU50CJeqcBLL8HzsLfDN Waeg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1712904565; x=1713509365; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=pHRXW9BfVlGJGTuBqz21x9jZhOCb5ENaxkoeEzRsV8g=; b=vxAzBkqptpiuqQJjZNF0ksqMqOEcDd0/VNcfVAjwxKa6wyA2jIQJWuP+9NKkkjlh/i 72SVbru3xHZ1Ez2qy/3xGno0f3FiDyvQgZ36XXFJDydsrxYSbjUZdweq8ZNVg8rPEYp5 yB6hyIhgG2xmnmyoVMNAYhRghMpeVY5uVxGK2baV1Xi0Xdmfyuk+3ULuxgxyREasXXH7 VJ5Yu5wY84BCIe1Q8PWkcro72TN5FvnZ0Kws4btG4QDMloS6PmBo+bCuH9RWZGDgkQqv diGpZoLIqCsg7MepkvToFIy9CG+C3jC2LTGyRW9StpZ/h2R9LSFaogRvg8Fs2YNOrKGy l2dQ== X-Gm-Message-State: AOJu0YxnyqAcQl08ZPkNk5u312xzLLbD+oe/QvAova/n3jt2HECvrqRL gCDAZQ9WCHNwC8kkx4RwYpCPIEmAkBU7lRbOhHGvrydHrvI2YqZ7CQL11DXqbFI= X-Google-Smtp-Source: AGHT+IF7aPtREGbQgxU3TxWKZAFkNQpbZfw9mJVRZm3GBajMC7PPTHtPXu4zJ9ZgxwJ5Yt7MgcH+hA== X-Received: by 2002:a17:902:9a09:b0:1e2:7fb2:b08 with SMTP id v9-20020a1709029a0900b001e27fb20b08mr1486377plp.43.1712904564631; Thu, 11 Apr 2024 23:49:24 -0700 (PDT) Received: from [127.0.1.1] (59-124-168-89.hinet-ip.hinet.net. [59.124.168.89]) by smtp.gmail.com with ESMTPSA id q8-20020a170902b10800b001e107222eb5sm2258818plr.191.2024.04.11.23.49.21 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 11 Apr 2024 23:49:24 -0700 (PDT) From: Andy Chiu Date: Fri, 12 Apr 2024 14:49:02 +0800 Subject: [PATCH v4 6/9] riscv: hwprobe: add zve Vector subextensions into hwprobe interface MIME-Version: 1.0 Message-Id: <20240412-zve-detection-v4-6-e0c45bb6b253@sifive.com> References: <20240412-zve-detection-v4-0-e0c45bb6b253@sifive.com> In-Reply-To: <20240412-zve-detection-v4-0-e0c45bb6b253@sifive.com> To: Paul Walmsley , Palmer Dabbelt , Albert Ou , Conor Dooley , Heiko Stuebner , Andy Chiu , Guo Ren , Conor Dooley , Rob Herring , Krzysztof Kozlowski , Jonathan Corbet , Evan Green , =?utf-8?b?Q2zDqW1lbnQgTMOpZ2Vy?= , Shuah Khan Cc: linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org, Palmer Dabbelt , Vincent Chen , Greentime Hu , devicetree@vger.kernel.org, linux-doc@vger.kernel.org, linux-kselftest@vger.kernel.org X-Mailer: b4 0.13-dev-a684c X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20240411_234926_323326_2E13E243 X-CRM114-Status: GOOD ( 10.47 ) X-BeenThere: linux-riscv@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-riscv" Errors-To: linux-riscv-bounces+linux-riscv=archiver.kernel.org@lists.infradead.org The following Vector subextensions for "embedded" platforms are added into RISCV_HWPROBE_KEY_IMA_EXT_0: - ZVE32X - ZVE32F - ZVE64X - ZVE64F - ZVE64D Extensions ending with an X indicates that the platform doesn't have a vector FPU. Extensions ending with F/D mean that whether single (F) or double (D) precision vector operation is supported. The number 32 or 64 follows from ZVE tells the maximum element length. Signed-off-by: Andy Chiu Reviewed-by: Clément Léger --- Changelog v2: - zve* extensions in hwprobe depends on whether kernel supports v, so include them after has_vector(). Fix a typo. (Clément) --- Documentation/arch/riscv/hwprobe.rst | 15 +++++++++++++++ arch/riscv/include/uapi/asm/hwprobe.h | 5 +++++ arch/riscv/kernel/sys_hwprobe.c | 5 +++++ 3 files changed, 25 insertions(+) diff --git a/Documentation/arch/riscv/hwprobe.rst b/Documentation/arch/riscv/hwprobe.rst index b2bcc9eed9aa..d0b02e012e5d 100644 --- a/Documentation/arch/riscv/hwprobe.rst +++ b/Documentation/arch/riscv/hwprobe.rst @@ -188,6 +188,21 @@ The following keys are defined: manual starting from commit 95cf1f9 ("Add changes requested by Ved during signoff") + * :c:macro:`RISCV_HWPROBE_EXT_ZVE32X`: The Vector sub-extension Zve32x is + supported, as defined by version 1.0 of the RISC-V Vector extension manual. + + * :c:macro:`RISCV_HWPROBE_EXT_ZVE32F`: The Vector sub-extension Zve32f is + supported, as defined by version 1.0 of the RISC-V Vector extension manual. + + * :c:macro:`RISCV_HWPROBE_EXT_ZVE64X`: The Vector sub-extension Zve64x is + supported, as defined by version 1.0 of the RISC-V Vector extension manual. + + * :c:macro:`RISCV_HWPROBE_EXT_ZVE64F`: The Vector sub-extension Zve64f is + supported, as defined by version 1.0 of the RISC-V Vector extension manual. + + * :c:macro:`RISCV_HWPROBE_EXT_ZVE64D`: The Vector sub-extension Zve64d is + supported, as defined by version 1.0 of the RISC-V Vector extension manual. + * :c:macro:`RISCV_HWPROBE_KEY_CPUPERF_0`: A bitmask that contains performance information about the selected set of processors. diff --git a/arch/riscv/include/uapi/asm/hwprobe.h b/arch/riscv/include/uapi/asm/hwprobe.h index 9f2a8e3ff204..b9a0876e969f 100644 --- a/arch/riscv/include/uapi/asm/hwprobe.h +++ b/arch/riscv/include/uapi/asm/hwprobe.h @@ -59,6 +59,11 @@ struct riscv_hwprobe { #define RISCV_HWPROBE_EXT_ZTSO (1ULL << 33) #define RISCV_HWPROBE_EXT_ZACAS (1ULL << 34) #define RISCV_HWPROBE_EXT_ZICOND (1ULL << 35) +#define RISCV_HWPROBE_EXT_ZVE32X (1ULL << 36) +#define RISCV_HWPROBE_EXT_ZVE32F (1ULL << 37) +#define RISCV_HWPROBE_EXT_ZVE64X (1ULL << 38) +#define RISCV_HWPROBE_EXT_ZVE64F (1ULL << 39) +#define RISCV_HWPROBE_EXT_ZVE64D (1ULL << 40) #define RISCV_HWPROBE_KEY_CPUPERF_0 5 #define RISCV_HWPROBE_MISALIGNED_UNKNOWN (0 << 0) #define RISCV_HWPROBE_MISALIGNED_EMULATED (1 << 0) diff --git a/arch/riscv/kernel/sys_hwprobe.c b/arch/riscv/kernel/sys_hwprobe.c index 8cae41a502dd..c8219b82fbfc 100644 --- a/arch/riscv/kernel/sys_hwprobe.c +++ b/arch/riscv/kernel/sys_hwprobe.c @@ -113,6 +113,11 @@ static void hwprobe_isa_ext0(struct riscv_hwprobe *pair, EXT_KEY(ZICOND); if (has_vector()) { + EXT_KEY(ZVE32X); + EXT_KEY(ZVE32F); + EXT_KEY(ZVE64X); + EXT_KEY(ZVE64F); + EXT_KEY(ZVE64D); EXT_KEY(ZVBB); EXT_KEY(ZVBC); EXT_KEY(ZVKB); From patchwork Fri Apr 12 06:49:03 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Andy Chiu X-Patchwork-Id: 13626944 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id AF316C4345F for ; Fri, 12 Apr 2024 06:49:41 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:Cc:To:In-Reply-To:References:Message-Id :MIME-Version:Subject:Date:From:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; bh=XysxFlMtW7wmqsDieMYLjd8hYQkx5zEg7ebV2Qt2BFk=; b=3l30l2JzJekq7C x1tmRSz1UIYx5j4fIh33D/UoDv1FQ3CS7ix0iU/9ruejbjtsTDBtPZc052kbs0BSrW4Xgrt/3vUqY XGt2gwDMgDBSN41yHt+acmLqDgsxqaEKSdd2FDXXbp2ji/S+YzWOdaggXKOYrgR+1WxPyCGATUXEW Dv5aa+UCkjSI3BTirP8tT5EqA4KoP6Yr08ix2mubE+dBwI2MU4fIR5+tXFLJ7ulDn1J0ZoqGF8QqU UuOjqSvejXCT7KIw9umOwqEfUijeV7brltufV37+85F0JKl6zpumZdK7E9TekwY9XD2nJa3F+4iLL sXggMeL63EmEazUxKnMw==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.97.1 #2 (Red Hat Linux)) id 1rvAjA-0000000Fdb3-1mWO; Fri, 12 Apr 2024 06:49:37 +0000 Received: from mail-pl1-x62d.google.com ([2607:f8b0:4864:20::62d]) by bombadil.infradead.org with esmtps (Exim 4.97.1 #2 (Red Hat Linux)) id 1rvAj3-0000000FdUJ-0bI4 for linux-riscv@lists.infradead.org; Fri, 12 Apr 2024 06:49:34 +0000 Received: by mail-pl1-x62d.google.com with SMTP id d9443c01a7336-1e4266673bbso5510375ad.2 for ; Thu, 11 Apr 2024 23:49:29 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=sifive.com; s=google; t=1712904568; x=1713509368; darn=lists.infradead.org; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:from:to:cc:subject:date:message-id :reply-to; bh=FOuafaR+mjq+MYJkSxgX4aHmBjLBIxtiIz1NyA+Fd2M=; b=LygIaOAGtQZF4nilfFhhE3c/W7ud9aah3t0MhfcbfflWG0goA41zAO+3ioNWky4FBG HuBzAPsGtpNmMGVCimiYZU4qnLadxaBz8N2nlg7/P/JP3Ws0siV1/iZ67SNrmIsYNfSs MwggmzLl9PMQYASMORKaJnrGqLTNY2yihh2/f8PhxpgLwIY8nHl1mBdzBFogISt4zxzr E7TSl74waZbZb4IFw5CwH9Yy0A7017Ah6n96JlKewhioibqb7TSsrMqO0ZDLesmclxdZ sBk8zW2zdwA/NzDhqq8bq7nz2+WvHhIZewoAf3dnPT4EtkxS/WKclrDmJPQ4w+CqmdQq YfpA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1712904568; x=1713509368; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=FOuafaR+mjq+MYJkSxgX4aHmBjLBIxtiIz1NyA+Fd2M=; b=XuXX2FcyBV40S3VB3aGrQz+iApuf7eIOK3TmKI8WJDvx57Eg2b0HzdLa3bN0x/gJUO ejVNc3z+m2N5u96l2WSe40B3HJBU9Rdd14vqwDZTtXzjjqelja6p1hXkTFUbI8fjtEha l2eXiJKDIB7mtMqYMUZSSadvluk3cDPq176fwRqLCnBIBBtu2WpT/Nvi/7N+loCli2DL 473r4IC3Ke+6vs85x7mgAQiIxzIvJKGZTKY1C1rlOaiYXAdqRhwlD9/A3WD1Lp3/mAaQ X8ocaLSe3cyrwEb9D7/Rv9DvehLgC+NARQvKKxPkiChQxiYIYADrXlJCLAqW5I1qo4ql +pVw== X-Gm-Message-State: AOJu0YylcrX7/62MtGtU6FB6wL6L1YJcLqasWrYgbDnPA4EzOpHaHwe6 M7ptMz2unnl5JLc5DYEc/L2XeAoqmLPw+/cf85Abzn6+24FX7ngKV+q2KLXitXo= X-Google-Smtp-Source: AGHT+IEDXD7c8vSh0DrtgrLf6HVJpbPoGyR+BhcXU5h+oReLKxmtw8WNkWbHz36pzavQ7NvX29f3Yw== X-Received: by 2002:a17:902:d507:b0:1e3:e8e9:5f28 with SMTP id b7-20020a170902d50700b001e3e8e95f28mr1840980plg.57.1712904568420; Thu, 11 Apr 2024 23:49:28 -0700 (PDT) Received: from [127.0.1.1] (59-124-168-89.hinet-ip.hinet.net. [59.124.168.89]) by smtp.gmail.com with ESMTPSA id q8-20020a170902b10800b001e107222eb5sm2258818plr.191.2024.04.11.23.49.24 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 11 Apr 2024 23:49:28 -0700 (PDT) From: Andy Chiu Date: Fri, 12 Apr 2024 14:49:03 +0800 Subject: [PATCH v4 7/9] riscv: vector: adjust minimum Vector requirement to ZVE32X MIME-Version: 1.0 Message-Id: <20240412-zve-detection-v4-7-e0c45bb6b253@sifive.com> References: <20240412-zve-detection-v4-0-e0c45bb6b253@sifive.com> In-Reply-To: <20240412-zve-detection-v4-0-e0c45bb6b253@sifive.com> To: Paul Walmsley , Palmer Dabbelt , Albert Ou , Conor Dooley , Heiko Stuebner , Andy Chiu , Guo Ren , Conor Dooley , Rob Herring , Krzysztof Kozlowski , Jonathan Corbet , Evan Green , =?utf-8?b?Q2zDqW1lbnQgTMOpZ2Vy?= , Shuah Khan Cc: linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org, Palmer Dabbelt , Vincent Chen , Greentime Hu , devicetree@vger.kernel.org, linux-doc@vger.kernel.org, linux-kselftest@vger.kernel.org, Joel Granados X-Mailer: b4 0.13-dev-a684c X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20240411_234929_295771_B4D82922 X-CRM114-Status: GOOD ( 25.43 ) X-BeenThere: linux-riscv@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-riscv" Errors-To: linux-riscv-bounces+linux-riscv=archiver.kernel.org@lists.infradead.org Make has_vector take one argument. This argument represents the minimum Vector subextension that the following Vector actions assume. Also, change riscv_v_first_use_handler(), and boot code that calls riscv_v_setup_vsize() to accept the minimum Vector sub-extension, ZVE32X. Most kernel/user interfaces requires minimum of ZVE32X. Thus, programs compiled and run with ZVE32X should be supported by the kernel on most aspects. This includes context-switch, signal, ptrace, prctl, and hwprobe. One exception is that ELF_HWCAP returns 'V' only if full V is supported on the platform. This means that the system without a full V must not rely on ELF_HWCAP to tell whether it is allowable to execute Vector without first invoking a prctl() check. Signed-off-by: Andy Chiu Acked-by: Joel Granados --- Changelog v4: - check static_assert for !CONFIG_RISCV_ISA_V case in has_vector. Changelog v2: - update the comment in hwprobe. --- arch/riscv/include/asm/switch_to.h | 2 +- arch/riscv/include/asm/vector.h | 25 ++++++++++++++++--------- arch/riscv/include/asm/xor.h | 2 +- arch/riscv/kernel/cpufeature.c | 5 ++++- arch/riscv/kernel/kernel_mode_vector.c | 4 ++-- arch/riscv/kernel/process.c | 4 ++-- arch/riscv/kernel/signal.c | 6 +++--- arch/riscv/kernel/smpboot.c | 2 +- arch/riscv/kernel/sys_hwprobe.c | 8 ++++++-- arch/riscv/kernel/vector.c | 15 +++++++++------ arch/riscv/lib/uaccess.S | 2 +- 11 files changed, 46 insertions(+), 29 deletions(-) diff --git a/arch/riscv/include/asm/switch_to.h b/arch/riscv/include/asm/switch_to.h index 7efdb0584d47..df1adf196c4f 100644 --- a/arch/riscv/include/asm/switch_to.h +++ b/arch/riscv/include/asm/switch_to.h @@ -78,7 +78,7 @@ do { \ struct task_struct *__next = (next); \ if (has_fpu()) \ __switch_to_fpu(__prev, __next); \ - if (has_vector()) \ + if (has_vector(ZVE32X)) \ __switch_to_vector(__prev, __next); \ ((last) = __switch_to(__prev, __next)); \ } while (0) diff --git a/arch/riscv/include/asm/vector.h b/arch/riscv/include/asm/vector.h index 731dcd0ed4de..ed5fb6515d54 100644 --- a/arch/riscv/include/asm/vector.h +++ b/arch/riscv/include/asm/vector.h @@ -8,6 +8,19 @@ #include #include +#include +#include + +#define has_vector(VEXT) \ +({ \ + static_assert(RISCV_ISA_EXT_##VEXT == RISCV_ISA_EXT_ZVE32X || \ + RISCV_ISA_EXT_##VEXT == RISCV_ISA_EXT_ZVE32F || \ + RISCV_ISA_EXT_##VEXT == RISCV_ISA_EXT_ZVE64X || \ + RISCV_ISA_EXT_##VEXT == RISCV_ISA_EXT_ZVE64F || \ + RISCV_ISA_EXT_##VEXT == RISCV_ISA_EXT_ZVE64D || \ + RISCV_ISA_EXT_##VEXT == RISCV_ISA_EXT_v); \ + IS_ENABLED(CONFIG_RISCV_ISA_V) && riscv_has_extension_unlikely(RISCV_ISA_EXT_##VEXT); \ +}) #ifdef CONFIG_RISCV_ISA_V @@ -15,9 +28,9 @@ #include #include #include -#include #include #include +#include extern unsigned long riscv_v_vsize; int riscv_v_setup_vsize(void); @@ -35,11 +48,6 @@ static inline u32 riscv_v_flags(void) return READ_ONCE(current->thread.riscv_v_flags); } -static __always_inline bool has_vector(void) -{ - return riscv_has_extension_unlikely(RISCV_ISA_EXT_v); -} - static inline void __riscv_v_vstate_clean(struct pt_regs *regs) { regs->status = (regs->status & ~SR_VS) | SR_VS_CLEAN; @@ -131,7 +139,7 @@ static inline void __riscv_v_vstate_restore(struct __riscv_v_ext_state *restore_ riscv_v_enable(); asm volatile ( ".option push\n\t" - ".option arch, +v\n\t" + ".option arch, +zve32x\n\t" "vsetvli %0, x0, e8, m8, ta, ma\n\t" "vle8.v v0, (%1)\n\t" "add %1, %1, %0\n\t" @@ -153,7 +161,7 @@ static inline void __riscv_v_vstate_discard(void) riscv_v_enable(); asm volatile ( ".option push\n\t" - ".option arch, +v\n\t" + ".option arch, +zve32x\n\t" "vsetvli %0, x0, e8, m8, ta, ma\n\t" "vmv.v.i v0, -1\n\t" "vmv.v.i v8, -1\n\t" @@ -267,7 +275,6 @@ bool riscv_v_vstate_ctrl_user_allowed(void); struct pt_regs; static inline int riscv_v_setup_vsize(void) { return -EOPNOTSUPP; } -static __always_inline bool has_vector(void) { return false; } static inline bool riscv_v_first_use_handler(struct pt_regs *regs) { return false; } static inline bool riscv_v_vstate_query(struct pt_regs *regs) { return false; } static inline bool riscv_v_vstate_ctrl_user_allowed(void) { return false; } diff --git a/arch/riscv/include/asm/xor.h b/arch/riscv/include/asm/xor.h index 96011861e46b..46042ef5a2f7 100644 --- a/arch/riscv/include/asm/xor.h +++ b/arch/riscv/include/asm/xor.h @@ -61,7 +61,7 @@ static struct xor_block_template xor_block_rvv = { do { \ xor_speed(&xor_block_8regs); \ xor_speed(&xor_block_32regs); \ - if (has_vector()) { \ + if (has_vector(ZVE32X)) { \ xor_speed(&xor_block_rvv);\ } \ } while (0) diff --git a/arch/riscv/kernel/cpufeature.c b/arch/riscv/kernel/cpufeature.c index 38d09de518b1..8b52060649d2 100644 --- a/arch/riscv/kernel/cpufeature.c +++ b/arch/riscv/kernel/cpufeature.c @@ -715,12 +715,15 @@ void __init riscv_fill_hwcap(void) elf_hwcap &= ~COMPAT_HWCAP_ISA_F; } - if (elf_hwcap & COMPAT_HWCAP_ISA_V) { + if (__riscv_isa_extension_available(NULL, RISCV_ISA_EXT_ZVE32X)) { /* * This callsite can't fail here. It cannot fail when called on * the boot hart. */ riscv_v_setup_vsize(); + } + + if (elf_hwcap & COMPAT_HWCAP_ISA_V) { /* * ISA string in device tree might have 'v' flag, but * CONFIG_RISCV_ISA_V is disabled in kernel. diff --git a/arch/riscv/kernel/kernel_mode_vector.c b/arch/riscv/kernel/kernel_mode_vector.c index 6afe80c7f03a..0d4d1a03d1c7 100644 --- a/arch/riscv/kernel/kernel_mode_vector.c +++ b/arch/riscv/kernel/kernel_mode_vector.c @@ -208,7 +208,7 @@ void kernel_vector_begin(void) { bool nested = false; - if (WARN_ON(!has_vector())) + if (WARN_ON(!has_vector(ZVE32X))) return; BUG_ON(!may_use_simd()); @@ -236,7 +236,7 @@ EXPORT_SYMBOL_GPL(kernel_vector_begin); */ void kernel_vector_end(void) { - if (WARN_ON(!has_vector())) + if (WARN_ON(!has_vector(ZVE32X))) return; riscv_v_disable(); diff --git a/arch/riscv/kernel/process.c b/arch/riscv/kernel/process.c index 92922dbd5b5c..919e72f9fff6 100644 --- a/arch/riscv/kernel/process.c +++ b/arch/riscv/kernel/process.c @@ -178,7 +178,7 @@ void flush_thread(void) void arch_release_task_struct(struct task_struct *tsk) { /* Free the vector context of datap. */ - if (has_vector()) + if (has_vector(ZVE32X)) riscv_v_thread_free(tsk); } @@ -225,7 +225,7 @@ int copy_thread(struct task_struct *p, const struct kernel_clone_args *args) p->thread.s[0] = 0; } p->thread.riscv_v_flags = 0; - if (has_vector()) + if (has_vector(ZVE32X)) riscv_v_thread_alloc(p); p->thread.ra = (unsigned long)ret_from_fork; p->thread.sp = (unsigned long)childregs; /* kernel sp */ diff --git a/arch/riscv/kernel/signal.c b/arch/riscv/kernel/signal.c index 501e66debf69..a96e6e969a3f 100644 --- a/arch/riscv/kernel/signal.c +++ b/arch/riscv/kernel/signal.c @@ -188,7 +188,7 @@ static long restore_sigcontext(struct pt_regs *regs, return 0; case RISCV_V_MAGIC: - if (!has_vector() || !riscv_v_vstate_query(regs) || + if (!has_vector(ZVE32X) || !riscv_v_vstate_query(regs) || size != riscv_v_sc_size) return -EINVAL; @@ -210,7 +210,7 @@ static size_t get_rt_frame_size(bool cal_all) frame_size = sizeof(*frame); - if (has_vector()) { + if (has_vector(ZVE32X)) { if (cal_all || riscv_v_vstate_query(task_pt_regs(current))) total_context_size += riscv_v_sc_size; } @@ -283,7 +283,7 @@ static long setup_sigcontext(struct rt_sigframe __user *frame, if (has_fpu()) err |= save_fp_state(regs, &sc->sc_fpregs); /* Save the vector state. */ - if (has_vector() && riscv_v_vstate_query(regs)) + if (has_vector(ZVE32X) && riscv_v_vstate_query(regs)) err |= save_v_state(regs, (void __user **)&sc_ext_ptr); /* Write zero to fp-reserved space and check it on restore_sigcontext */ err |= __put_user(0, &sc->sc_extdesc.reserved); diff --git a/arch/riscv/kernel/smpboot.c b/arch/riscv/kernel/smpboot.c index 673437ccc13d..7252666ce0da 100644 --- a/arch/riscv/kernel/smpboot.c +++ b/arch/riscv/kernel/smpboot.c @@ -214,7 +214,7 @@ asmlinkage __visible void smp_callin(void) struct mm_struct *mm = &init_mm; unsigned int curr_cpuid = smp_processor_id(); - if (has_vector()) { + if (has_vector(ZVE32X)) { /* * Return as early as possible so the hart with a mismatching * vlen won't boot. diff --git a/arch/riscv/kernel/sys_hwprobe.c b/arch/riscv/kernel/sys_hwprobe.c index c8219b82fbfc..e7c3fcac62a1 100644 --- a/arch/riscv/kernel/sys_hwprobe.c +++ b/arch/riscv/kernel/sys_hwprobe.c @@ -69,7 +69,7 @@ static void hwprobe_isa_ext0(struct riscv_hwprobe *pair, if (riscv_isa_extension_available(NULL, c)) pair->value |= RISCV_HWPROBE_IMA_C; - if (has_vector()) + if (has_vector(v)) pair->value |= RISCV_HWPROBE_IMA_V; /* @@ -112,7 +112,11 @@ static void hwprobe_isa_ext0(struct riscv_hwprobe *pair, EXT_KEY(ZACAS); EXT_KEY(ZICOND); - if (has_vector()) { + /* + * Vector crypto and ZVE* extensions are supported only if + * kernel has minimum V support of ZVE32X. + */ + if (has_vector(ZVE32X)) { EXT_KEY(ZVE32X); EXT_KEY(ZVE32F); EXT_KEY(ZVE64X); diff --git a/arch/riscv/kernel/vector.c b/arch/riscv/kernel/vector.c index 6727d1d3b8f2..e8a47fa72351 100644 --- a/arch/riscv/kernel/vector.c +++ b/arch/riscv/kernel/vector.c @@ -53,7 +53,7 @@ int riscv_v_setup_vsize(void) void __init riscv_v_setup_ctx_cache(void) { - if (!has_vector()) + if (!has_vector(ZVE32X)) return; riscv_v_user_cachep = kmem_cache_create_usercopy("riscv_vector_ctx", @@ -173,8 +173,11 @@ bool riscv_v_first_use_handler(struct pt_regs *regs) u32 __user *epc = (u32 __user *)regs->epc; u32 insn = (u32)regs->badaddr; + if (!has_vector(ZVE32X)) + return false; + /* Do not handle if V is not supported, or disabled */ - if (!(ELF_HWCAP & COMPAT_HWCAP_ISA_V)) + if (!riscv_v_vstate_ctrl_user_allowed()) return false; /* If V has been enabled then it is not the first-use trap */ @@ -213,7 +216,7 @@ void riscv_v_vstate_ctrl_init(struct task_struct *tsk) bool inherit; int cur, next; - if (!has_vector()) + if (!has_vector(ZVE32X)) return; next = riscv_v_ctrl_get_next(tsk); @@ -235,7 +238,7 @@ void riscv_v_vstate_ctrl_init(struct task_struct *tsk) long riscv_v_vstate_ctrl_get_current(void) { - if (!has_vector()) + if (!has_vector(ZVE32X)) return -EINVAL; return current->thread.vstate_ctrl & PR_RISCV_V_VSTATE_CTRL_MASK; @@ -246,7 +249,7 @@ long riscv_v_vstate_ctrl_set_current(unsigned long arg) bool inherit; int cur, next; - if (!has_vector()) + if (!has_vector(ZVE32X)) return -EINVAL; if (arg & ~PR_RISCV_V_VSTATE_CTRL_MASK) @@ -296,7 +299,7 @@ static struct ctl_table riscv_v_default_vstate_table[] = { static int __init riscv_v_sysctl_init(void) { - if (has_vector()) + if (has_vector(ZVE32X)) if (!register_sysctl("abi", riscv_v_default_vstate_table)) return -EINVAL; return 0; diff --git a/arch/riscv/lib/uaccess.S b/arch/riscv/lib/uaccess.S index bc22c078aba8..bbe143bb32a0 100644 --- a/arch/riscv/lib/uaccess.S +++ b/arch/riscv/lib/uaccess.S @@ -14,7 +14,7 @@ SYM_FUNC_START(__asm_copy_to_user) #ifdef CONFIG_RISCV_ISA_V - ALTERNATIVE("j fallback_scalar_usercopy", "nop", 0, RISCV_ISA_EXT_v, CONFIG_RISCV_ISA_V) + ALTERNATIVE("j fallback_scalar_usercopy", "nop", 0, RISCV_ISA_EXT_ZVE32X, CONFIG_RISCV_ISA_V) REG_L t0, riscv_v_usercopy_threshold bltu a2, t0, fallback_scalar_usercopy tail enter_vector_usercopy From patchwork Fri Apr 12 06:49:04 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Andy Chiu X-Patchwork-Id: 13627122 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 49BD5C04FFE for ; Fri, 12 Apr 2024 08:03:50 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:Cc:To:In-Reply-To:References:Message-Id :MIME-Version:Subject:Date:From:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; bh=M27zrXSjVdG2Ecn9QERBg/EnQxGvY/eqH1MUXD2s8hY=; b=vCKMUEPekmMLj8 BlM+XQFNZiqIY3bsSVc+qioXJjhiyRsf8Dfn5aoTMe3LiwuXaNZqlfaqU2rdSbZByxJ6l1XrYmn+J EgIGik5pLkjWDGslbGsONwHEW833W3wa3fN7mvNKWQ2yU3TK15PqFNdXk4cJwEwapY7dC2rM44J7p 7uBSH9SGXeOYmbd1XW63Wpko/l6+fMAWIMnS+rukjGUDLhjbDuegPht1OZK16ryQZxJ6VkMHZy6kU UWJNcsppdAqiDljUnBCOpRoorqRponxVj8qY9jqIILG9xUYJCakp7qg/YoZ1e3YwYCFRLqPohXZUi ErwWsE4m+C0+3cah5ubA==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.97.1 #2 (Red Hat Linux)) id 1rvBst-0000000FyMu-0dqC; Fri, 12 Apr 2024 08:03:43 +0000 Received: from mail-pl1-x629.google.com ([2607:f8b0:4864:20::629]) by bombadil.infradead.org with esmtps (Exim 4.97.1 #2 (Red Hat Linux)) id 1rvAj9-0000000FdXn-1yLP for linux-riscv@lists.infradead.org; Fri, 12 Apr 2024 06:49:37 +0000 Received: by mail-pl1-x629.google.com with SMTP id d9443c01a7336-1e4f341330fso6018625ad.0 for ; Thu, 11 Apr 2024 23:49:32 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=sifive.com; s=google; t=1712904572; x=1713509372; darn=lists.infradead.org; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:from:to:cc:subject:date:message-id :reply-to; bh=R0+TwQ5GqFH8aHlUKPdqP3mrZz0YybL9qzmJdYvs5ws=; b=cUUDqURwbgdlrrSIZa8blhsvwTWyZgrserAZe/xYF8kwBYo6k14Tt5k7LLShBRG2wd rKt2C1wngucHXRHJeCYBZxBCHi/l3KbMxxA+YQy1C5XmjTsJL3VYx35C2DAXu+NiOMMh l9L3n4Ko3j/m1skV5Tmc3xBaxdKePWa5JvfO1WwY4sR0NPweWo8rhKOeUINCuUTPJ8+S Go/rbBaVsm5zjXX3V2rA2HJyST4hryF/grVQ3l0m7SoFn8pXtKyZD4O7HrrwT6HPaaFz VdirPfA0D6XErsWK2D9sUGJ0ONngUaWNsxHDdPp4KOODSYLHmG3/iPKrcsqVwVQL8D55 rhaw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1712904572; x=1713509372; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=R0+TwQ5GqFH8aHlUKPdqP3mrZz0YybL9qzmJdYvs5ws=; b=oMtPpODyLT5KJ2GEXPsKeNmreEkHbNgrYi8Tz1VdEL2a8BT7rxiolFs2tYay0Dh1Am TmtCDJ4GP7dcFo7vETOYTnR9l8nyT5LZ1HmDVNi3nSu8UMSSLqO6gacK9Mx+L/OJ39wD q+uTYiQ8WpPiFmYY7WuuKKjgrfwk/1RzvP6zjDgSJJUe+RdqJSdlLfY1bT7xWF1TMzWc /kZkCsRRWGY8/WjJiR0QDoxiUJlu9qbEwempnv6p4e+6MeWkFRcznExsD+ZDUPQ+tuv8 pGnOw85ULjfV4brywHhx0zVtVcok68qmGfoTdCtt+QnKnPcJLWIuoQl9chT4elNe31N9 3Adw== X-Gm-Message-State: AOJu0YyNh09D3SwW/TxmAGF8rvWvYgqbbVpSdTRpUFwvLcgpAaYQVEnv BCUrozMOrcSDrlGWfB2JXTqfnsLn8IvQS8JzBTAt8OqxWOHnMntBkKfaafgYFvQ= X-Google-Smtp-Source: AGHT+IEyMJ5oVk6CfLCQcJcfX/ZIjOVHG1NEnrkJlbePak6mm9DdqGhN0zRdg6Q82lhK4umpLFADiw== X-Received: by 2002:a17:902:ce92:b0:1e2:4c85:82ea with SMTP id f18-20020a170902ce9200b001e24c8582eamr2036574plg.24.1712904571996; Thu, 11 Apr 2024 23:49:31 -0700 (PDT) Received: from [127.0.1.1] (59-124-168-89.hinet-ip.hinet.net. [59.124.168.89]) by smtp.gmail.com with ESMTPSA id q8-20020a170902b10800b001e107222eb5sm2258818plr.191.2024.04.11.23.49.28 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 11 Apr 2024 23:49:31 -0700 (PDT) From: Andy Chiu Date: Fri, 12 Apr 2024 14:49:04 +0800 Subject: [PATCH v4 8/9] hwprobe: fix integer promotion in RISCV_HWPROBE_EXT macro MIME-Version: 1.0 Message-Id: <20240412-zve-detection-v4-8-e0c45bb6b253@sifive.com> References: <20240412-zve-detection-v4-0-e0c45bb6b253@sifive.com> In-Reply-To: <20240412-zve-detection-v4-0-e0c45bb6b253@sifive.com> To: Paul Walmsley , Palmer Dabbelt , Albert Ou , Conor Dooley , Heiko Stuebner , Andy Chiu , Guo Ren , Conor Dooley , Rob Herring , Krzysztof Kozlowski , Jonathan Corbet , Evan Green , =?utf-8?b?Q2zDqW1lbnQgTMOpZ2Vy?= , Shuah Khan Cc: linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org, Palmer Dabbelt , Vincent Chen , Greentime Hu , devicetree@vger.kernel.org, linux-doc@vger.kernel.org, linux-kselftest@vger.kernel.org X-Mailer: b4 0.13-dev-a684c X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20240411_234935_707026_1DE5F561 X-CRM114-Status: GOOD ( 10.97 ) X-BeenThere: linux-riscv@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-riscv" Errors-To: linux-riscv-bounces+linux-riscv=archiver.kernel.org@lists.infradead.org (1 << 31) is a signed negative integer, and it was sign-extended when being or'ed into the "missing" variable. This casues hwprobe not reflecing extensions named after RISCV_HWPROBE_EXT_ZVFHMIN. Fix it by defining it as a unsigend long long. Fixes: 5dadda5e6a59 ("riscv: hwprobe: export Zvfh[min] ISA extensions") Signed-off-by: Andy Chiu --- Changelog v4: - new patch since v4 --- arch/riscv/include/uapi/asm/hwprobe.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/riscv/include/uapi/asm/hwprobe.h b/arch/riscv/include/uapi/asm/hwprobe.h index b9a0876e969f..dfa7bdbcce92 100644 --- a/arch/riscv/include/uapi/asm/hwprobe.h +++ b/arch/riscv/include/uapi/asm/hwprobe.h @@ -54,7 +54,7 @@ struct riscv_hwprobe { #define RISCV_HWPROBE_EXT_ZFHMIN (1 << 28) #define RISCV_HWPROBE_EXT_ZIHINTNTL (1 << 29) #define RISCV_HWPROBE_EXT_ZVFH (1 << 30) -#define RISCV_HWPROBE_EXT_ZVFHMIN (1 << 31) +#define RISCV_HWPROBE_EXT_ZVFHMIN (1ULL << 31) #define RISCV_HWPROBE_EXT_ZFA (1ULL << 32) #define RISCV_HWPROBE_EXT_ZTSO (1ULL << 33) #define RISCV_HWPROBE_EXT_ZACAS (1ULL << 34) From patchwork Fri Apr 12 06:49:05 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Andy Chiu X-Patchwork-Id: 13626945 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 53B6CC4345F for ; Fri, 12 Apr 2024 06:49:51 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:Cc:To:In-Reply-To:References:Message-Id :MIME-Version:Subject:Date:From:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; bh=h/rsv8inJhngMwH2RITWvknbc7hPsZDXeMso7v3K/JE=; b=iaEXHq5yK+bXp2 NlzmVmwkzK16duljCB/ocoWx1oRdHyPqOILuFiJW9P+EdKgg9webG+XyL9Vc/VqUd7UzJkO05lYgN lgeIjH2uzAcwunRhjn8H5fR56WAdg6EHkkyvKikG0UcZFOsno71KxNJSG5gEBDihmuslFU/v7dqAI IN4c5SZSHBt4G5OglvR1Pi+dVZ9o7NDBN/ALI0bHJ0v9SJkaDcIM6MEpC65oRSvE45+O0YB6uEAL1 0dS/8dKI3GosMd6yd3YBcVleWhRd6FLFsvm9oJm2/0vdEG0W1szTvOQuW6QKItXZ5Jmv3zfqRWCmo HS99nkBWEr8eSv0XwLzg==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.97.1 #2 (Red Hat Linux)) id 1rvAjK-0000000Fdkx-2SKq; Fri, 12 Apr 2024 06:49:46 +0000 Received: from mail-pl1-x62d.google.com ([2607:f8b0:4864:20::62d]) by bombadil.infradead.org with esmtps (Exim 4.97.1 #2 (Red Hat Linux)) id 1rvAjA-0000000Fdad-0wqW for linux-riscv@lists.infradead.org; Fri, 12 Apr 2024 06:49:39 +0000 Received: by mail-pl1-x62d.google.com with SMTP id d9443c01a7336-1e4bf0b3e06so6348085ad.1 for ; Thu, 11 Apr 2024 23:49:36 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=sifive.com; s=google; t=1712904576; x=1713509376; darn=lists.infradead.org; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:from:to:cc:subject:date:message-id :reply-to; bh=v6E6ZusRhlxuRh8LTz85NPr0A8l1rMIJWkDOWsfceGk=; b=ZOB9NgbiWBxXOUvLsLtVJuaYraSlMjKaG8S4FBFo96tRynr5Mc+YKeEYwrh6AODVYh 9xEcaZ6JRnneeKSHdQRU+SxUMocpN38B+RZpgFGSa+kXuDQhrfim+CT5W8Gh/7rxhJVB 8i2DxIr+yPhhxQRqQcOSLoGFnwrrX7fuI82BgUwIAwIE/MSWGFWjdQII6sbdAxrUXZfs ccV4MMifgvzTJA86WpEC32N9XhMZW93q7O12+ZrZNUZP2MXY+kpy+F7S3mAYvUdovd6V Zui9JoKauVCXID7lEYRLWgErMkUj93x9piz6m64mVR52TcjtriTfEf/eTlMczXGhoZ6a wzxA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1712904576; x=1713509376; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=v6E6ZusRhlxuRh8LTz85NPr0A8l1rMIJWkDOWsfceGk=; b=mmlr5NiSs+ymVtQpnuS2MGMZVjnJA+ItsfJDPWaaKKvXr4ZSG9wCHSlclTwIs1+d2r OeMv2vXZDvV7YIito2toqhzol7Ud5m3q2/9HNs3OC55iyu8jaW24D60s+5A80QJCT2Ui ve0Dni4X/0TEFdb9ufoTcPovLws/tbkCE7isEXrhNORoV6EpdRZ3qsklVV52DddARUw+ agMNjcXzRGEgXIutdtjMb+Fj+FY+bNTISJ54I/JA2HQn+61Yq9EOfOXrc3B4XrL+FrVu Pb1EGK/+5ig+uCZU9WX+rGotT12UMq1tAl0ycj8u2qRj6jXqW1Aq9/LZBt3j+JV5moKy V3cg== X-Gm-Message-State: AOJu0YxOizdRq92yECxZIL4bfc5rT80E0UVR1OCsqnfnkubt94ZkFrkJ s5JEJmE7hLrtWFBZyLeB6PVlXvcgIlepeE2S+Epwk3SHl3czftIY+3oAInTTZzg= X-Google-Smtp-Source: AGHT+IFN+2rlBM0atFvz5drmpqdxYuReC7akcGJxFgtrZUemr79CcqpTCReQ9/O3Fl7hLYkZ38tKJA== X-Received: by 2002:a17:902:b187:b0:1e0:b62c:460d with SMTP id s7-20020a170902b18700b001e0b62c460dmr1459758plr.38.1712904575557; Thu, 11 Apr 2024 23:49:35 -0700 (PDT) Received: from [127.0.1.1] (59-124-168-89.hinet-ip.hinet.net. [59.124.168.89]) by smtp.gmail.com with ESMTPSA id q8-20020a170902b10800b001e107222eb5sm2258818plr.191.2024.04.11.23.49.32 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 11 Apr 2024 23:49:35 -0700 (PDT) From: Andy Chiu Date: Fri, 12 Apr 2024 14:49:05 +0800 Subject: [PATCH v4 9/9] selftest: run vector prctl test for ZVE32X MIME-Version: 1.0 Message-Id: <20240412-zve-detection-v4-9-e0c45bb6b253@sifive.com> References: <20240412-zve-detection-v4-0-e0c45bb6b253@sifive.com> In-Reply-To: <20240412-zve-detection-v4-0-e0c45bb6b253@sifive.com> To: Paul Walmsley , Palmer Dabbelt , Albert Ou , Conor Dooley , Heiko Stuebner , Andy Chiu , Guo Ren , Conor Dooley , Rob Herring , Krzysztof Kozlowski , Jonathan Corbet , Evan Green , =?utf-8?b?Q2zDqW1lbnQgTMOpZ2Vy?= , Shuah Khan Cc: linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org, Palmer Dabbelt , Vincent Chen , Greentime Hu , devicetree@vger.kernel.org, linux-doc@vger.kernel.org, linux-kselftest@vger.kernel.org X-Mailer: b4 0.13-dev-a684c X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20240411_234936_869304_539813EB X-CRM114-Status: GOOD ( 10.55 ) X-BeenThere: linux-riscv@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-riscv" Errors-To: linux-riscv-bounces+linux-riscv=archiver.kernel.org@lists.infradead.org The minimal requirement for running Vector subextension on Linux is ZVE32X. So change the test accordingly to run prctl as long as it find it. Signed-off-by: Andy Chiu --- Changelog v4: - new patch since v4 --- tools/testing/selftests/riscv/vector/vstate_prctl.c | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/tools/testing/selftests/riscv/vector/vstate_prctl.c b/tools/testing/selftests/riscv/vector/vstate_prctl.c index 27668fb3b6d0..895177f6bf4c 100644 --- a/tools/testing/selftests/riscv/vector/vstate_prctl.c +++ b/tools/testing/selftests/riscv/vector/vstate_prctl.c @@ -88,16 +88,16 @@ int main(void) return -2; } - if (!(pair.value & RISCV_HWPROBE_IMA_V)) { + if (!(pair.value & RISCV_HWPROBE_EXT_ZVE32X)) { rc = prctl(PR_RISCV_V_GET_CONTROL); if (rc != -1 || errno != EINVAL) { - ksft_test_result_fail("GET_CONTROL should fail on kernel/hw without V\n"); + ksft_test_result_fail("GET_CONTROL should fail on kernel/hw without ZVE32X\n"); return -3; } rc = prctl(PR_RISCV_V_SET_CONTROL, PR_RISCV_V_VSTATE_CTRL_ON); if (rc != -1 || errno != EINVAL) { - ksft_test_result_fail("GET_CONTROL should fail on kernel/hw without V\n"); + ksft_test_result_fail("SET_CONTROL should fail on kernel/hw without ZVE32X\n"); return -4; }