From patchwork Mon Apr 15 12:16:28 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Teddy Astie X-Patchwork-Id: 13629896 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.xenproject.org (lists.xenproject.org [192.237.175.120]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 437FFC00A94 for ; Mon, 15 Apr 2024 12:16:47 +0000 (UTC) Received: from list by lists.xenproject.org with outflank-mailman.706125.1103188 (Exim 4.92) (envelope-from ) id 1rwLGE-0006xp-4C; Mon, 15 Apr 2024 12:16:34 +0000 X-Outflank-Mailman: Message body and most headers restored to incoming version Received: by outflank-mailman (output) from mailman id 706125.1103188; Mon, 15 Apr 2024 12:16:34 +0000 Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1rwLGE-0006x9-0C; Mon, 15 Apr 2024 12:16:34 +0000 Received: by outflank-mailman (input) for mailman id 706125; Mon, 15 Apr 2024 12:16:32 +0000 Received: from se1-gles-sth1-in.inumbo.com ([159.253.27.254] helo=se1-gles-sth1.inumbo.com) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1rwLGC-0006Sb-K2 for xen-devel@lists.xenproject.org; Mon, 15 Apr 2024 12:16:32 +0000 Received: from mail145-16.atl61.mandrillapp.com (mail145-16.atl61.mandrillapp.com [198.2.145.16]) by se1-gles-sth1.inumbo.com (Halon) with ESMTPS id fd3dd77f-fb21-11ee-b908-491648fe20b8; Mon, 15 Apr 2024 14:16:30 +0200 (CEST) Received: from pmta06.mandrill.prod.atl01.rsglab.com (localhost [127.0.0.1]) by mail145-16.atl61.mandrillapp.com (Mailchimp) with ESMTP id 4VJ5kN3c36z8XRt03 for ; Mon, 15 Apr 2024 12:16:28 +0000 (GMT) Received: from [37.26.189.201] by mandrillapp.com id 76c1b1f5afb645dab066be61273b0aca; Mon, 15 Apr 2024 12:16:28 +0000 X-BeenThere: xen-devel@lists.xenproject.org List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , Errors-To: xen-devel-bounces@lists.xenproject.org Precedence: list Sender: "Xen-devel" X-Inumbo-ID: fd3dd77f-fb21-11ee-b908-491648fe20b8 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=mandrillapp.com; s=mte1; t=1713183388; x=1713443888; bh=sMGoHoVGbP7Qy7MkWN2iK9K6d7d7gexdPaWo2on0a1c=; h=From:Subject:To:Cc:Message-Id:In-Reply-To:References:Feedback-ID: Date:MIME-Version:Content-Type:Content-Transfer-Encoding:CC:Date: Subject:From; b=KzzGEhegveDaeiTGgoeXGg+dPBsltLt76hyczkdN3PNQ/MEhwoecclNdYNncAfuG/ jLYe3sIoljv6ztptFwIzNlOK4JxB4f/CG1qEvtGK5LYKWfKoBtDLc0vFfBuo89l6uS rUe2nGlDco/p4RbGZyp5tFYnTx+pNwh1tNhv2Tz+9aD2Bl33n3a8lVqmINysY3vBzo A0Ye/QyNoXdsPqaAw/EE5xjZH19/+J4vy0c5QgyOGYew+P5uewligMcWTpLjqL+1WP Z4Xjdx5szzFG12/tStu3OV1bUz0a58tRmWhlKantQJii7wk6OR0Mlx644rJIRuQizC LU2c6qNlM1wsg== DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=vates.tech; s=mte1; t=1713183388; x=1713443888; i=teddy.astie@vates.tech; bh=sMGoHoVGbP7Qy7MkWN2iK9K6d7d7gexdPaWo2on0a1c=; h=From:Subject:To:Cc:Message-Id:In-Reply-To:References:Feedback-ID: Date:MIME-Version:Content-Type:Content-Transfer-Encoding:CC:Date: Subject:From; b=mkL8Ez9Jous7q8NJSw2rwxYryhuAlCuYTHx9tJgyYgC00E/rc1Cf+A0UXUO1mWnuH 0yjymdb83KJTCUffjpbcIUUE2mSK1Gb2QqP64AciQ9XPkjOvCfdlUzHdoQyOo5XbPa 6ckdIBY/3MUldQBm01R9CzlSw2Tn7PfF4ZqIP7U1SZA/zgPylqp2X/XUMHhy3JSVto 81oSoPs0jgZYjtefNAkC9MSiuxEwRGb43OdiRiDzFR53FDPtE1/v/dpXHAOAVOXViE aofqdKJQbZlzhSqAAlK0RKsQzdhwRUlR+yaVDFHHP+FyDGXP8gxhQRafKmdBja19d6 6siWdcv93AOKw== From: Teddy Astie Subject: =?utf-8?q?=5BXEN_PATCH_v4_1/5=5D_VT-d=3A_Disable_IOMMU_if_cx16_isn?= =?utf-8?q?=27t_supported?= X-Mailer: git-send-email 2.44.0 X-Bm-Disclaimer: Yes X-Bm-Milter-Handled: 4ffbd6c1-ee69-4e1b-aabd-f977039bd3e2 X-Bm-Transport-Timestamp: 1713183386062 To: xen-devel@lists.xenproject.org Cc: Teddy Astie , Andrew Cooper Message-Id: <4d229d23a0d4ece607e0d0b9f685c1e5e7a19c95.1713174878.git.teddy.astie@vates.tech> In-Reply-To: References: X-Native-Encoded: 1 X-Report-Abuse: =?utf-8?q?Please_forward_a_copy_of_this_message=2C_including?= =?utf-8?q?_all_headers=2C_to_abuse=40mandrill=2Ecom=2E_You_can_also_report_?= =?utf-8?q?abuse_here=3A_https=3A//mandrillapp=2Ecom/contact/abuse=3Fid=3D30?= =?utf-8?q?504962=2E76c1b1f5afb645dab066be61273b0aca?= X-Mandrill-User: md_30504962 Feedback-ID: 30504962:30504962.20240415:md Date: Mon, 15 Apr 2024 12:16:28 +0000 MIME-Version: 1.0 All hardware with VT-d has CMPXCHG16B support. Check this at initialisation time, and remove the effectively-dead logic for the non-cx16 case. Suggested-by: Andrew Cooper Signed-off-by: Teddy Astie --- xen/drivers/passthrough/vtd/iommu.c | 73 ++++++++++------------------- 1 file changed, 25 insertions(+), 48 deletions(-) diff --git a/xen/drivers/passthrough/vtd/iommu.c b/xen/drivers/passthrough/vtd/iommu.c index c7110af7c9..9c787ba9eb 100644 --- a/xen/drivers/passthrough/vtd/iommu.c +++ b/xen/drivers/passthrough/vtd/iommu.c @@ -1482,7 +1482,7 @@ int domain_context_mapping_one( { struct domain_iommu *hd = dom_iommu(domain); struct context_entry *context, *context_entries, lctxt; - __uint128_t old; + __uint128_t res, old; uint64_t maddr; uint16_t seg = iommu->drhd->segment, prev_did = 0; struct domain *prev_dom = NULL; @@ -1580,55 +1580,23 @@ int domain_context_mapping_one( ASSERT(!context_fault_disable(lctxt)); } - if ( cpu_has_cx16 ) - { - __uint128_t res = cmpxchg16b(context, &old, &lctxt.full); - - /* - * Hardware does not update the context entry behind our backs, - * so the return value should match "old". - */ - if ( res != old ) - { - if ( pdev ) - check_cleanup_domid_map(domain, pdev, iommu); - printk(XENLOG_ERR - "%pp: unexpected context entry %016lx_%016lx (expected %016lx_%016lx)\n", - &PCI_SBDF(seg, bus, devfn), - (uint64_t)(res >> 64), (uint64_t)res, - (uint64_t)(old >> 64), (uint64_t)old); - rc = -EILSEQ; - goto unlock; - } - } - else if ( !prev_dom || !(mode & MAP_WITH_RMRR) ) - { - context_clear_present(*context); - iommu_sync_cache(context, sizeof(*context)); + res = cmpxchg16b(context, &old, &lctxt.full); - write_atomic(&context->hi, lctxt.hi); - /* No barrier should be needed between these two. */ - write_atomic(&context->lo, lctxt.lo); - } - else /* Best effort, updating DID last. */ + /* + * Hardware does not update the context entry behind our backs, + * so the return value should match "old". + */ + if ( res != old ) { - /* - * By non-atomically updating the context entry's DID field last, - * during a short window in time TLB entries with the old domain ID - * but the new page tables may be inserted. This could affect I/O - * of other devices using this same (old) domain ID. Such updating - * therefore is not a problem if this was the only device associated - * with the old domain ID. Diverting I/O of any of a dying domain's - * devices to the quarantine page tables is intended anyway. - */ - if ( !(mode & (MAP_OWNER_DYING | MAP_SINGLE_DEVICE)) ) - printk(XENLOG_WARNING VTDPREFIX - " %pp: reassignment may cause %pd data corruption\n", - &PCI_SBDF(seg, bus, devfn), prev_dom); - - write_atomic(&context->lo, lctxt.lo); - /* No barrier should be needed between these two. */ - write_atomic(&context->hi, lctxt.hi); + if ( pdev ) + check_cleanup_domid_map(domain, pdev, iommu); + printk(XENLOG_ERR + "%pp: unexpected context entry %016lx_%016lx (expected %016lx_%016lx)\n", + &PCI_SBDF(seg, bus, devfn), + (uint64_t)(res >> 64), (uint64_t)res, + (uint64_t)(old >> 64), (uint64_t)old); + rc = -EILSEQ; + goto unlock; } iommu_sync_cache(context, sizeof(struct context_entry)); @@ -2630,6 +2598,15 @@ static int __init cf_check vtd_setup(void) int ret; bool reg_inval_supported = true; + if ( unlikely(!cpu_has_cx16) ) + { + printk(XENLOG_ERR VTDPREFIX + "IOMMU: CPU doesn't support CMPXCHG16B, disabling\n"); + + ret = -ENODEV; + goto error; + } + if ( list_empty(&acpi_drhd_units) ) { ret = -ENODEV; From patchwork Mon Apr 15 12:16:27 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Teddy Astie X-Patchwork-Id: 13629898 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.xenproject.org (lists.xenproject.org [192.237.175.120]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 3BF6AC05024 for ; Mon, 15 Apr 2024 12:16:48 +0000 (UTC) Received: from list by lists.xenproject.org with outflank-mailman.706123.1103167 (Exim 4.92) (envelope-from ) id 1rwLGB-0006W9-MP; Mon, 15 Apr 2024 12:16:31 +0000 X-Outflank-Mailman: Message body and most headers restored to incoming version Received: by outflank-mailman (output) from mailman id 706123.1103167; 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c=relaxed/relaxed; d=vates.tech; s=mte1; t=1713183387; x=1713443887; i=teddy.astie@vates.tech; bh=pVW5u35fq+zXx1B2L8XZPx9h9eXL6mZato+52jJIsMA=; h=From:Subject:To:Cc:Message-Id:In-Reply-To:References:Feedback-ID: Date:MIME-Version:Content-Type:Content-Transfer-Encoding:CC:Date: Subject:From; b=UmfWPwzlkKnvKJo1IhUYm6sd2WMBdqKSDOIpv6g0yAro8eN3OeX6++w3tGaPwCfIi B4ow3VSfkEwdhfmC/wDgeckisISoA0sH8QDNNBkroK59GI1VxSOnY5IllsMxftXa+Z aSAQb9G0yoRTM2zY35HNaF6RukpqjZvp2uQYBvsQkuknSCwnI+Ge1eOqqV5XVZGdb6 rLIubdMh0XTUBLIkzH64P3mAqRHZCLsCYfkHMip0E9WwFE0kW32VFCn0HU/oBe6tf/ dC1qmenMTMs+95YSzCRSbNGwr95ANQjiEf8Yp7TYTwsa+8LAL93m3dfP2/wYyYDTD7 bmVrxXhlJxCFQ== From: Teddy Astie Subject: =?utf-8?q?=5BXEN_PATCH_v4_2/5=5D_AMD-Vi=3A_Disable_IOMMU_if_cx16_is?= =?utf-8?q?n=27t_supported?= X-Mailer: git-send-email 2.44.0 X-Bm-Disclaimer: Yes X-Bm-Milter-Handled: 4ffbd6c1-ee69-4e1b-aabd-f977039bd3e2 X-Bm-Transport-Timestamp: 1713183386410 To: xen-devel@lists.xenproject.org Cc: Teddy Astie , Andrew Cooper Message-Id: In-Reply-To: References: X-Native-Encoded: 1 X-Report-Abuse: =?utf-8?q?Please_forward_a_copy_of_this_message=2C_including?= =?utf-8?q?_all_headers=2C_to_abuse=40mandrill=2Ecom=2E_You_can_also_report_?= =?utf-8?q?abuse_here=3A_https=3A//mandrillapp=2Ecom/contact/abuse=3Fid=3D30?= =?utf-8?q?504962=2E8426781ae7c74282b1e6f20712725546?= X-Mandrill-User: md_30504962 Feedback-ID: 30504962:30504962.20240415:md Date: Mon, 15 Apr 2024 12:16:27 +0000 MIME-Version: 1.0 All hardware with AMD-Vi has CMPXCHG16 support. Check this at initialisation time, and remove the effectively-dead logic for the non-cx16 case. Suggested-by: Andrew Cooper Signed-off-by: Teddy Astie --- xen/drivers/passthrough/amd/iommu_map.c | 42 +++++++-------------- xen/drivers/passthrough/amd/pci_amd_iommu.c | 6 +++ 2 files changed, 20 insertions(+), 28 deletions(-) diff --git a/xen/drivers/passthrough/amd/iommu_map.c b/xen/drivers/passthrough/amd/iommu_map.c index e0f4fe736a..f67975e700 100644 --- a/xen/drivers/passthrough/amd/iommu_map.c +++ b/xen/drivers/passthrough/amd/iommu_map.c @@ -167,15 +167,14 @@ int amd_iommu_set_root_page_table(struct amd_iommu_dte *dte, { bool valid = flags & SET_ROOT_VALID; - if ( dte->v && dte->tv && - (cpu_has_cx16 || (flags & SET_ROOT_WITH_UNITY_MAP)) ) + if ( dte->v && dte->tv ) { union { struct amd_iommu_dte dte; uint64_t raw64[4]; __uint128_t raw128[2]; } ldte = { .dte = *dte }; - __uint128_t old = ldte.raw128[0]; + __uint128_t res, old = ldte.raw128[0]; int ret = 0; ldte.dte.domain_id = domain_id; @@ -185,33 +184,20 @@ int amd_iommu_set_root_page_table(struct amd_iommu_dte *dte, ldte.dte.paging_mode = paging_mode; ldte.dte.v = valid; - if ( cpu_has_cx16 ) - { - __uint128_t res = cmpxchg16b(dte, &old, &ldte.raw128[0]); + res = cmpxchg16b(dte, &old, &ldte.raw128[0]); - /* - * Hardware does not update the DTE behind our backs, so the - * return value should match "old". - */ - if ( res != old ) - { - printk(XENLOG_ERR - "Dom%d: unexpected DTE %016lx_%016lx (expected %016lx_%016lx)\n", - domain_id, - (uint64_t)(res >> 64), (uint64_t)res, - (uint64_t)(old >> 64), (uint64_t)old); - ret = -EILSEQ; - } - } - else /* Best effort, updating domain_id last. */ + /* + * Hardware does not update the DTE behind our backs, so the + * return value should match "old". + */ + if ( res != old ) { - uint64_t *ptr = (void *)dte; - - write_atomic(ptr + 0, ldte.raw64[0]); - /* No barrier should be needed between these two. */ - write_atomic(ptr + 1, ldte.raw64[1]); - - ret = 1; + printk(XENLOG_ERR + "Dom%d: unexpected DTE %016lx_%016lx (expected %016lx_%016lx)\n", + domain_id, + (uint64_t)(res >> 64), (uint64_t)res, + (uint64_t)(old >> 64), (uint64_t)old); + ret = -EILSEQ; } return ret; diff --git a/xen/drivers/passthrough/amd/pci_amd_iommu.c b/xen/drivers/passthrough/amd/pci_amd_iommu.c index f6efd88e36..3a6a23f706 100644 --- a/xen/drivers/passthrough/amd/pci_amd_iommu.c +++ b/xen/drivers/passthrough/amd/pci_amd_iommu.c @@ -305,6 +305,12 @@ static int __init cf_check iov_detect(void) if ( !iommu_enable && !iommu_intremap ) return 0; + if ( unlikely(!cpu_has_cx16) ) + { + printk("AMD-Vi: CPU doesn't support CMPXCHG16B, disabling\n"); + return -ENODEV; + } + if ( (init_done ? amd_iommu_init_late() : amd_iommu_init(false)) != 0 ) { From patchwork Mon Apr 15 12:16:27 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Teddy Astie X-Patchwork-Id: 13629895 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.xenproject.org (lists.xenproject.org [192.237.175.120]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 272DCC05023 for ; Mon, 15 Apr 2024 12:16:48 +0000 (UTC) Received: from list by lists.xenproject.org with outflank-mailman.706127.1103214 (Exim 4.92) (envelope-from ) id 1rwLGF-0007cx-UX; Mon, 15 Apr 2024 12:16:35 +0000 X-Outflank-Mailman: Message body and most headers restored to incoming version Received: by outflank-mailman (output) from mailman id 706127.1103214; Mon, 15 Apr 2024 12:16:35 +0000 Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1rwLGF-0007cq-Ne; Mon, 15 Apr 2024 12:16:35 +0000 Received: by outflank-mailman (input) for mailman id 706127; Mon, 15 Apr 2024 12:16:34 +0000 Received: from se1-gles-flk1-in.inumbo.com ([94.247.172.50] helo=se1-gles-flk1.inumbo.com) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1rwLGE-0006tb-IR for xen-devel@lists.xenproject.org; Mon, 15 Apr 2024 12:16:34 +0000 Received: from mail145-16.atl61.mandrillapp.com (mail145-16.atl61.mandrillapp.com [198.2.145.16]) by se1-gles-flk1.inumbo.com (Halon) with ESMTPS id fd3bc35b-fb21-11ee-94a3-07e782e9044d; Mon, 15 Apr 2024 14:16:30 +0200 (CEST) Received: from pmta06.mandrill.prod.atl01.rsglab.com (localhost [127.0.0.1]) by mail145-16.atl61.mandrillapp.com (Mailchimp) with ESMTP id 4VJ5kM3bNpz8XRtln for ; Mon, 15 Apr 2024 12:16:27 +0000 (GMT) Received: from [37.26.189.201] by mandrillapp.com id bdf670edfcd74494a0a1568848e67be1; Mon, 15 Apr 2024 12:16:27 +0000 X-BeenThere: xen-devel@lists.xenproject.org List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , Errors-To: xen-devel-bounces@lists.xenproject.org Precedence: list Sender: "Xen-devel" X-Inumbo-ID: fd3bc35b-fb21-11ee-94a3-07e782e9044d DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=mandrillapp.com; s=mte1; t=1713183387; x=1713443887; bh=RRod8nx7vQ+DrBaq1mB+2iQAFOffxbEGL4R3xb8mHC8=; h=From:Subject:To:Cc:Message-Id:In-Reply-To:References:Feedback-ID: Date:MIME-Version:Content-Type:Content-Transfer-Encoding:CC:Date: Subject:From; b=GSJUHtN2i4nhoX29yCMABYqzwrKKDs/yaoOmcpEiR53Z3FpPs+J1q7Mgag9qSOCtC ePfIq8NjXtscDhdK1LrW3+iMoLhtI9xxrvCPKWpnLfDOIoCs/C4L8C05uEc2hIauEr ZekO0K+ek6lWSvlcL5oDthIERcjvJO8oYvHsHZc6VlzX8M/xTooQzjkmBYDFSSX6PR AKn3oRJQD7MGZsozwSJpQMHT9JrAScgXUrY7gx1Gtbn7x2e8PfTrdUxOIKfdiZa6Nt taUM6V/s9AxzJ0ajANlR3Fg2DioEsYj4qlp8RNNVpYOPLddXQiNXnT+qeK73XrAzB2 9q1gAzgnw81Kw== DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=vates.tech; s=mte1; t=1713183387; x=1713443887; i=teddy.astie@vates.tech; bh=RRod8nx7vQ+DrBaq1mB+2iQAFOffxbEGL4R3xb8mHC8=; h=From:Subject:To:Cc:Message-Id:In-Reply-To:References:Feedback-ID: Date:MIME-Version:Content-Type:Content-Transfer-Encoding:CC:Date: Subject:From; b=fqyN5yuwC0m/N/enB11o7oyguyV0J7Etf9vE3o0BbkSODelsxyVWGOCD4rmisW9iT bgA8VUp3FipV1o7TIC4GEUdIHwqCNJr3xRGS6a2U2bI+3kTuFQWqUOvmD9A4188DeN ERP7zZIAftJvXP88LCiD+rUSiM2cFcR1CiVneXPftlauhFn5tLXVHWpj/XA0G6v/Ae GFLOzjcQO+jbYh0aT6wRkDqwGy3xx7Fs/coggxlGf1KXAEZfC0ARslVCdRj4qLnErG uYGLltLKxlIEPzBhYEg6LbX6IcYiFkfO7l0jhpGA6fFvhVu1q2bbi4HnUZjnQ5Aq6b 72CAcele30zzA== From: Teddy Astie Subject: =?utf-8?q?=5BXEN_PATCH_v4_3/5=5D_VT-d=3A_Cleanup_MAP=5FSINGLE=5FDEV?= =?utf-8?q?ICE_and_related_code?= X-Mailer: git-send-email 2.44.0 X-Bm-Disclaimer: Yes X-Bm-Milter-Handled: 4ffbd6c1-ee69-4e1b-aabd-f977039bd3e2 X-Bm-Transport-Timestamp: 1713183386723 To: xen-devel@lists.xenproject.org Cc: Teddy Astie Message-Id: <43876112df408c6f11fa399337db4f3104a969a2.1713174878.git.teddy.astie@vates.tech> In-Reply-To: References: X-Native-Encoded: 1 X-Report-Abuse: =?utf-8?q?Please_forward_a_copy_of_this_message=2C_including?= =?utf-8?q?_all_headers=2C_to_abuse=40mandrill=2Ecom=2E_You_can_also_report_?= =?utf-8?q?abuse_here=3A_https=3A//mandrillapp=2Ecom/contact/abuse=3Fid=3D30?= =?utf-8?q?504962=2Ebdf670edfcd74494a0a1568848e67be1?= X-Mandrill-User: md_30504962 Feedback-ID: 30504962:30504962.20240415:md Date: Mon, 15 Apr 2024 12:16:27 +0000 MIME-Version: 1.0 This flag was only used in case cx16 is not available, as those code paths no longer exist, this flag now does basically nothing. Signed-off-by: Teddy Astie --- xen/drivers/passthrough/vtd/iommu.c | 12 +++--------- xen/drivers/passthrough/vtd/vtd.h | 5 ++--- 2 files changed, 5 insertions(+), 12 deletions(-) diff --git a/xen/drivers/passthrough/vtd/iommu.c b/xen/drivers/passthrough/vtd/iommu.c index 9c787ba9eb..7c6bae0256 100644 --- a/xen/drivers/passthrough/vtd/iommu.c +++ b/xen/drivers/passthrough/vtd/iommu.c @@ -1692,15 +1692,9 @@ static int domain_context_mapping(struct domain *domain, u8 devfn, break; } - if ( domain != pdev->domain && pdev->domain != dom_io ) - { - if ( pdev->domain->is_dying ) - mode |= MAP_OWNER_DYING; - else if ( drhd && - !any_pdev_behind_iommu(pdev->domain, pdev, drhd->iommu) && - !pdev->phantom_stride ) - mode |= MAP_SINGLE_DEVICE; - } + if ( domain != pdev->domain && pdev->domain != dom_io && + pdev->domain->is_dying ) + mode |= MAP_OWNER_DYING; switch ( pdev->type ) { diff --git a/xen/drivers/passthrough/vtd/vtd.h b/xen/drivers/passthrough/vtd/vtd.h index cb2df76eed..43f06a353d 100644 --- a/xen/drivers/passthrough/vtd/vtd.h +++ b/xen/drivers/passthrough/vtd/vtd.h @@ -28,9 +28,8 @@ */ #define MAP_WITH_RMRR (1u << 0) #define MAP_OWNER_DYING (1u << 1) -#define MAP_SINGLE_DEVICE (1u << 2) -#define MAP_ERROR_RECOVERY (1u << 3) -#define UNMAP_ME_PHANTOM_FUNC (1u << 4) +#define MAP_ERROR_RECOVERY (1u << 2) +#define UNMAP_ME_PHANTOM_FUNC (1u << 3) /* Allow for both IOAPIC and IOSAPIC. */ #define IO_xAPIC_route_entry IO_APIC_route_entry From patchwork Mon Apr 15 12:16:27 2024 Content-Type: text/plain; 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Check this at initialisation time, and remove the effectively-dead logic for the non-cx16 case. Suggested-by: Andrew Cooper Signed-off-by: Teddy Astie --- xen/drivers/passthrough/vtd/intremap.c | 70 ++++++++------------------ xen/drivers/passthrough/vtd/iommu.c | 7 +-- 2 files changed, 21 insertions(+), 56 deletions(-) diff --git a/xen/drivers/passthrough/vtd/intremap.c b/xen/drivers/passthrough/vtd/intremap.c index c504852eb8..7d4d907b4f 100644 --- a/xen/drivers/passthrough/vtd/intremap.c +++ b/xen/drivers/passthrough/vtd/intremap.c @@ -150,6 +150,13 @@ bool __init cf_check intel_iommu_supports_eim(void) if ( !iommu_qinval || !iommu_intremap || list_empty(&acpi_drhd_units) ) return false; + if ( unlikely(!cpu_has_cx16) ) + { + printk(XENLOG_WARNING VTDPREFIX + "CPU doesn't support CMPXCHG16B, disable interrupt remapping\n"); + return false; + } + /* We MUST have a DRHD unit for each IOAPIC. */ for ( apic = 0; apic < nr_ioapics; apic++ ) if ( !ioapic_to_drhd(IO_APIC_ID(apic)) ) @@ -173,47 +180,26 @@ bool __init cf_check intel_iommu_supports_eim(void) * Assume iremap_lock has been acquired. It is to make sure software will not * change the same IRTE behind us. With this assumption, if only high qword or * low qword in IRTE is to be updated, this function's atomic variant can - * present an atomic update to VT-d hardware even when cmpxchg16b - * instruction is not supported. + * present an atomic update to VT-d hardware. */ static void update_irte(struct vtd_iommu *iommu, struct iremap_entry *entry, const struct iremap_entry *new_ire, bool atomic) { - ASSERT(spin_is_locked(&iommu->intremap.lock)); + __uint128_t ret; + struct iremap_entry old_ire; - if ( cpu_has_cx16 ) - { - __uint128_t ret; - struct iremap_entry old_ire; + ASSERT(spin_is_locked(&iommu->intremap.lock)); - old_ire = *entry; - ret = cmpxchg16b(entry, &old_ire, new_ire); + old_ire = *entry; + ret = cmpxchg16b(entry, &old_ire, new_ire); - /* - * In the above, we use cmpxchg16 to atomically update the 128-bit - * IRTE, and the hardware cannot update the IRTE behind us, so - * the return value of cmpxchg16 should be the same as old_ire. - * This ASSERT validate it. - */ - ASSERT(ret == old_ire.val); - } - else - { - /* - * VT-d hardware doesn't update IRTEs behind us, nor the software - * since we hold iremap_lock. If the caller wants VT-d hardware to - * always see a consistent entry, but we can't meet it, a bug will - * be raised. - */ - if ( entry->lo == new_ire->lo ) - write_atomic(&entry->hi, new_ire->hi); - else if ( entry->hi == new_ire->hi ) - write_atomic(&entry->lo, new_ire->lo); - else if ( !atomic ) - *entry = *new_ire; - else - BUG(); - } + /* + * In the above, we use cmpxchg16 to atomically update the 128-bit + * IRTE, and the hardware cannot update the IRTE behind us, so + * the return value of cmpxchg16 should be the same as old_ire. + * This ASSERT validate it. + */ + ASSERT(ret == old_ire.val); } /* Mark specified intr remap entry as free */ @@ -395,7 +381,6 @@ static int ioapic_rte_to_remap_entry(struct vtd_iommu *iommu, /* Indicate remap format. */ remap_rte->format = 1; - /* If cmpxchg16b is not available the caller must mask the IO-APIC pin. */ update_irte(iommu, iremap_entry, &new_ire, !init && !masked); iommu_sync_cache(iremap_entry, sizeof(*iremap_entry)); iommu_flush_iec_index(iommu, 0, index); @@ -437,21 +422,6 @@ void cf_check io_apic_write_remap_rte( bool masked = true; int rc; - if ( !cpu_has_cx16 ) - { - /* - * Cannot atomically update the IRTE entry: mask the IO-APIC pin to - * avoid interrupts seeing an inconsistent IRTE entry. - */ - old_rte = __ioapic_read_entry(apic, pin, true); - if ( !old_rte.mask ) - { - masked = false; - old_rte.mask = 1; - __ioapic_write_entry(apic, pin, true, old_rte); - } - } - /* Not the initializer, for old gcc to cope. */ new_rte.raw = rte; diff --git a/xen/drivers/passthrough/vtd/iommu.c b/xen/drivers/passthrough/vtd/iommu.c index 7c6bae0256..a1bd3c5ff6 100644 --- a/xen/drivers/passthrough/vtd/iommu.c +++ b/xen/drivers/passthrough/vtd/iommu.c @@ -2663,12 +2663,7 @@ static int __init cf_check vtd_setup(void) iommu_intremap = iommu_intremap_off; #ifndef iommu_intpost - /* - * We cannot use posted interrupt if X86_FEATURE_CX16 is - * not supported, since we count on this feature to - * atomically update 16-byte IRTE in posted format. - */ - if ( !cap_intr_post(iommu->cap) || !iommu_intremap || !cpu_has_cx16 ) + if ( !cap_intr_post(iommu->cap) || !iommu_intremap ) iommu_intpost = false; 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Check this at initialisation time, and remove the effectively-dead logic for the non-cx16 case. Suggested-by: Andrew Cooper Signed-off-by: Teddy Astie --- xen/drivers/passthrough/amd/iommu_intr.c | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/xen/drivers/passthrough/amd/iommu_intr.c b/xen/drivers/passthrough/amd/iommu_intr.c index 7fc796dec2..9ab7c68749 100644 --- a/xen/drivers/passthrough/amd/iommu_intr.c +++ b/xen/drivers/passthrough/amd/iommu_intr.c @@ -649,6 +649,12 @@ bool __init cf_check iov_supports_xt(void) if ( !iommu_enable || !iommu_intremap ) return false; + if ( unlikely(!cpu_has_cx16) ) + { + AMD_IOMMU_WARN("CPU doesn't support CMPXCHG16B, disable interrupt remapping\n"); + return false; + } + if ( amd_iommu_prepare(true) ) return false;