From patchwork Tue Apr 16 22:10:00 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Imre Deak X-Patchwork-Id: 13632658 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 8A669C4345F for ; Tue, 16 Apr 2024 22:09:44 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 41471112EAB; Tue, 16 Apr 2024 22:09:42 +0000 (UTC) Authentication-Results: gabe.freedesktop.org; dkim=pass (2048-bit key; unprotected) header.d=intel.com header.i=@intel.com header.b="hE1eMNf5"; dkim-atps=neutral Received: from mgamail.intel.com (mgamail.intel.com [192.198.163.10]) by gabe.freedesktop.org (Postfix) with ESMTPS id 6258F112EAB; Tue, 16 Apr 2024 22:09:39 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1713305379; x=1744841379; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=UC38b05/7bGOTFo1gBV9OejdYxVqJPRZS/+T23pculg=; b=hE1eMNf5J9Ad7ZvO4e523MjetS+oiZuHuLoPqw2u0azX7SL5lUG9FN7T rETd2MeZrkWcaPpD4CQ7eF5ec17ItOUn9LdcjxGzMHs6m/TyY5TNuGzX0 p3JeZaMrkHbOKfdejfgZ3Gjyi1HkG605j+IFEYNmbtxOgv10seviMPsQ6 67yiSQfEZk9vhVx+YQLAQC8xapGTluprRhWGF3TUVy8uxqMEp2VEwFAT3 BY4dR2aJq4trkFok7RZU9qlGioFvU/93U/Ps8ONWYr/lGfLdSgxEeafkK E29EA/qF9M686i8nWGhPOAGADGeDI1GhJJ3wLkF63GdQh6Sd+t2vg8K0r g==; X-CSE-ConnectionGUID: NaNBYpNkQh6wzdG5IzdxZQ== X-CSE-MsgGUID: +iHqOq+PQ36m1gWJ9CvRVg== X-IronPort-AV: E=McAfee;i="6600,9927,11046"; a="20165142" X-IronPort-AV: E=Sophos;i="6.07,207,1708416000"; d="scan'208";a="20165142" Received: from fmviesa003.fm.intel.com ([10.60.135.143]) by fmvoesa104.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 16 Apr 2024 15:09:39 -0700 X-CSE-ConnectionGUID: XSVJbvlTT0eR1QvJQITkGg== X-CSE-MsgGUID: twJ6l7x8ToSrOR+aycNdBw== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.07,207,1708416000"; d="scan'208";a="26965467" Received: from ideak-desk.fi.intel.com ([10.237.72.78]) by fmviesa003-auth.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 16 Apr 2024 15:09:38 -0700 From: Imre Deak To: intel-gfx@lists.freedesktop.org Cc: dri-devel@lists.freedesktop.org, Ankit Nautiyal , Manasi Navare , Maarten Lankhorst Subject: [PATCH v2 01/11] drm/i915/dp: Fix DSC line buffer depth programming Date: Wed, 17 Apr 2024 01:10:00 +0300 Message-ID: <20240416221010.376865-2-imre.deak@intel.com> X-Mailer: git-send-email 2.43.3 In-Reply-To: <20240416221010.376865-1-imre.deak@intel.com> References: <20240416221010.376865-1-imre.deak@intel.com> MIME-Version: 1.0 X-BeenThere: dri-devel@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Direct Rendering Infrastructure - Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dri-devel-bounces@lists.freedesktop.org Sender: "dri-devel" Fix the calculation of the DSC line buffer depth. This is limited both by the source's and sink's maximum line buffer depth, but the former one was not taken into account. On all Intel platform's the source's maximum buffer depth is 13, so the overall limit is simply the minimum of the source/sink's limit, regardless of the DSC version. This leaves the DSI DSC line buffer depth calculation as-is, trusting VBT. On DSC version 1.2 for sinks reporting a maximum line buffer depth of 16 the line buffer depth was incorrectly programmed as 0, leading to a corruption in color gradients / lines on the decompressed screen image. Cc: dri-devel@lists.freedesktop.org Reviewed-by: Ankit Nautiyal Reviewed-by: Manasi Navare Acked-by: Maarten Lankhorst Signed-off-by: Imre Deak --- drivers/gpu/drm/i915/display/intel_dp.c | 16 ++++++---------- include/drm/display/drm_dsc.h | 3 --- 2 files changed, 6 insertions(+), 13 deletions(-) diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c index 163da48bc4065..23808e9d41d5d 100644 --- a/drivers/gpu/drm/i915/display/intel_dp.c +++ b/drivers/gpu/drm/i915/display/intel_dp.c @@ -89,6 +89,9 @@ #define DP_DSC_MAX_ENC_THROUGHPUT_0 340000 #define DP_DSC_MAX_ENC_THROUGHPUT_1 400000 +/* Max DSC line buffer depth supported by HW. */ +#define INTEL_DP_DSC_MAX_LINE_BUF_DEPTH 13 + /* DP DSC FEC Overhead factor in ppm = 1/(0.972261) = 1.028530 */ #define DP_DSC_FEC_OVERHEAD_FACTOR 1028530 @@ -1705,7 +1708,6 @@ static int intel_dp_dsc_compute_params(const struct intel_connector *connector, { struct drm_i915_private *i915 = to_i915(connector->base.dev); struct drm_dsc_config *vdsc_cfg = &crtc_state->dsc.config; - u8 line_buf_depth; int ret; /* @@ -1734,20 +1736,14 @@ static int intel_dp_dsc_compute_params(const struct intel_connector *connector, connector->dp.dsc_dpcd[DP_DSC_DEC_COLOR_FORMAT_CAP - DP_DSC_SUPPORT] & DP_DSC_RGB; - line_buf_depth = drm_dp_dsc_sink_line_buf_depth(connector->dp.dsc_dpcd); - if (!line_buf_depth) { + vdsc_cfg->line_buf_depth = min(INTEL_DP_DSC_MAX_LINE_BUF_DEPTH, + drm_dp_dsc_sink_line_buf_depth(connector->dp.dsc_dpcd)); + if (!vdsc_cfg->line_buf_depth) { drm_dbg_kms(&i915->drm, "DSC Sink Line Buffer Depth invalid\n"); return -EINVAL; } - if (vdsc_cfg->dsc_version_minor == 2) - vdsc_cfg->line_buf_depth = (line_buf_depth == DSC_1_2_MAX_LINEBUF_DEPTH_BITS) ? - DSC_1_2_MAX_LINEBUF_DEPTH_VAL : line_buf_depth; - else - vdsc_cfg->line_buf_depth = (line_buf_depth > DSC_1_1_MAX_LINEBUF_DEPTH_BITS) ? - DSC_1_1_MAX_LINEBUF_DEPTH_BITS : line_buf_depth; - vdsc_cfg->block_pred_enable = connector->dp.dsc_dpcd[DP_DSC_BLK_PREDICTION_SUPPORT - DP_DSC_SUPPORT] & DP_DSC_BLK_PREDICTION_IS_SUPPORTED; diff --git a/include/drm/display/drm_dsc.h b/include/drm/display/drm_dsc.h index bc90273d06a62..bbbe7438473d3 100644 --- a/include/drm/display/drm_dsc.h +++ b/include/drm/display/drm_dsc.h @@ -40,9 +40,6 @@ #define DSC_PPS_RC_RANGE_MINQP_SHIFT 11 #define DSC_PPS_RC_RANGE_MAXQP_SHIFT 6 #define DSC_PPS_NATIVE_420_SHIFT 1 -#define DSC_1_2_MAX_LINEBUF_DEPTH_BITS 16 -#define DSC_1_2_MAX_LINEBUF_DEPTH_VAL 0 -#define DSC_1_1_MAX_LINEBUF_DEPTH_BITS 13 /** * struct drm_dsc_rc_range_parameters - DSC Rate Control range parameters From patchwork Tue Apr 16 22:10:06 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Imre Deak X-Patchwork-Id: 13632659 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 734E5C04FFF for ; Tue, 16 Apr 2024 22:09:50 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 79EDC112EB2; Tue, 16 Apr 2024 22:09:47 +0000 (UTC) Authentication-Results: gabe.freedesktop.org; dkim=pass (2048-bit key; unprotected) header.d=intel.com header.i=@intel.com header.b="nv5U2P6a"; dkim-atps=neutral Received: from mgamail.intel.com (mgamail.intel.com [192.198.163.10]) by gabe.freedesktop.org (Postfix) with ESMTPS id B3493112EB3; Tue, 16 Apr 2024 22:09:46 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1713305387; x=1744841387; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=CehbAt/+gn4naKc4KR36grWFyIic0bmBXgkYinHvbDs=; b=nv5U2P6aefyvt6s18dGJjULO0ef0dufcg7u1eijYVJsHHRfzsuNRpD1S FTvMFSvWiSUmkn+EXE+8yQk6UxncazYSXjaa9CrwcKq108iCShzj2fYq9 GSjyNbmWF1QeQWh+5saAeZ6JPiveb9wml+4N8wUzldHrEqVZnkW1REi2w t0f1vIJPtyAhBoXB6Kz3kkN6HjsfAvt75VGBy1NHUiL9RoTO8Z8X2ZGNE b9GSkeKBLWvCoU5JJwEqbDcWtDu0TKcCVZ2dCSZVH7QOaBfNugqwi5LoR RcMFH/e7oTd8cAoe3Ok9BnemQNrWG5n1C6nOrVWMPpqPWihStlC5FwBTP w==; X-CSE-ConnectionGUID: 9cpUnJeuQAeS7UGBDdEqgg== X-CSE-MsgGUID: jXGuvSUwTYGrLbGpg/PK6w== X-IronPort-AV: E=McAfee;i="6600,9927,11046"; a="20165169" X-IronPort-AV: E=Sophos;i="6.07,207,1708416000"; d="scan'208";a="20165169" Received: from fmviesa003.fm.intel.com ([10.60.135.143]) by fmvoesa104.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 16 Apr 2024 15:09:46 -0700 X-CSE-ConnectionGUID: MKzvqEisTsqUWp2eVwjefQ== X-CSE-MsgGUID: q7uWgtFxT2WCzrXAccB5rw== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.07,207,1708416000"; d="scan'208";a="26965497" Received: from ideak-desk.fi.intel.com ([10.237.72.78]) by fmviesa003-auth.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 16 Apr 2024 15:09:45 -0700 From: Imre Deak To: intel-gfx@lists.freedesktop.org Cc: dri-devel@lists.freedesktop.org, Ankit Nautiyal , Manasi Navare , Maarten Lankhorst Subject: [PATCH v2 07/11] drm/dp: Add drm_dp_uhbr_channel_coding_supported() Date: Wed, 17 Apr 2024 01:10:06 +0300 Message-ID: <20240416221010.376865-8-imre.deak@intel.com> X-Mailer: git-send-email 2.43.3 In-Reply-To: <20240416221010.376865-1-imre.deak@intel.com> References: <20240416221010.376865-1-imre.deak@intel.com> MIME-Version: 1.0 X-BeenThere: dri-devel@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Direct Rendering Infrastructure - Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dri-devel-bounces@lists.freedesktop.org Sender: "dri-devel" Factor out a function to check for UHBR channel coding support used by a follow-up patch in the patchset. Cc: dri-devel@lists.freedesktop.org Reviewed-by: Ankit Nautiyal Reviewed-by: Manasi Navare Acked-by: Maarten Lankhorst Signed-off-by: Imre Deak --- drivers/gpu/drm/i915/display/intel_dp.c | 2 +- include/drm/display/drm_dp_helper.h | 6 ++++++ 2 files changed, 7 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c index 23808e9d41d5d..41127069b55e4 100644 --- a/drivers/gpu/drm/i915/display/intel_dp.c +++ b/drivers/gpu/drm/i915/display/intel_dp.c @@ -225,7 +225,7 @@ static void intel_dp_set_dpcd_sink_rates(struct intel_dp *intel_dp) * Sink rates for 128b/132b. If set, sink should support all 8b/10b * rates and 10 Gbps. */ - if (intel_dp->dpcd[DP_MAIN_LINK_CHANNEL_CODING] & DP_CAP_ANSI_128B132B) { + if (drm_dp_uhbr_channel_coding_supported(intel_dp->dpcd)) { u8 uhbr_rates = 0; BUILD_BUG_ON(ARRAY_SIZE(intel_dp->sink_rates) < ARRAY_SIZE(dp_rates) + 3); diff --git a/include/drm/display/drm_dp_helper.h b/include/drm/display/drm_dp_helper.h index baf9949ff96fc..8a64fe8d97af2 100644 --- a/include/drm/display/drm_dp_helper.h +++ b/include/drm/display/drm_dp_helper.h @@ -251,6 +251,12 @@ drm_dp_channel_coding_supported(const u8 dpcd[DP_RECEIVER_CAP_SIZE]) return dpcd[DP_MAIN_LINK_CHANNEL_CODING] & DP_CAP_ANSI_8B10B; } +static inline bool +drm_dp_uhbr_channel_coding_supported(const u8 dpcd[DP_RECEIVER_CAP_SIZE]) +{ + return dpcd[DP_MAIN_LINK_CHANNEL_CODING] & DP_CAP_ANSI_128B132B; +} + static inline bool drm_dp_alternate_scrambler_reset_cap(const u8 dpcd[DP_RECEIVER_CAP_SIZE]) { From patchwork Tue Apr 16 22:10:07 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Imre Deak X-Patchwork-Id: 13632660 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 04D6FC04FF6 for ; Tue, 16 Apr 2024 22:09:52 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 9565B112EAE; Tue, 16 Apr 2024 22:09:49 +0000 (UTC) Authentication-Results: gabe.freedesktop.org; dkim=pass (2048-bit key; unprotected) header.d=intel.com header.i=@intel.com header.b="fm85RkDA"; dkim-atps=neutral Received: from mgamail.intel.com (mgamail.intel.com [192.198.163.10]) by gabe.freedesktop.org (Postfix) with ESMTPS id 678AE112EAE; Tue, 16 Apr 2024 22:09:48 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1713305388; x=1744841388; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=tcOTZvPluUWi3TlBWm1Rt6q+OAoeayjbbfJiJqcFrRg=; b=fm85RkDAT3hwoYlQqnTeBI3OeExOilzrXDzURGbPhA4st27vvG5Zou0A zw3PRKtw7w7siiXk6clDNjJlUwpbLc85MbYDqCS3FtC7Ji92y/wzyQjge c7wecxnIbfAJSREUWreD4nV767NpBIRsy5/rDIs3YZcMMSetKUQkIi+6h 4NvkCxUwRH7Y9JiwiviGic8fJvFr7EdUE1jw5Yrw492UBjSQn5vGZOAYA b+aFAQ/DguxTfZ4Bm6Hd7s1x6XSQeoE4z2BUM62r5mTBTiG3YbA68qiVk gNEneAQzK+LAV7BlYlzudHlQwC9JJKDaGrspOx7gjeuosHIWVxDPyLqjc w==; X-CSE-ConnectionGUID: UVMSU0VgR7iGElHFaqPCCA== X-CSE-MsgGUID: p+6Odq6cQLu49BP4uAbZtA== X-IronPort-AV: E=McAfee;i="6600,9927,11046"; a="20165176" X-IronPort-AV: E=Sophos;i="6.07,207,1708416000"; d="scan'208";a="20165176" Received: from fmviesa003.fm.intel.com ([10.60.135.143]) by fmvoesa104.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 16 Apr 2024 15:09:48 -0700 X-CSE-ConnectionGUID: bcK/CPCKSxSiY4Pfsgg8Yg== X-CSE-MsgGUID: jkaC6CYkSiOWF6qct3KZWg== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.07,207,1708416000"; d="scan'208";a="26965502" Received: from ideak-desk.fi.intel.com ([10.237.72.78]) by fmviesa003-auth.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 16 Apr 2024 15:09:47 -0700 From: Imre Deak To: intel-gfx@lists.freedesktop.org Cc: Lyude Paul , dri-devel@lists.freedesktop.org, Ankit Nautiyal , Maarten Lankhorst Subject: [PATCH v2 08/11] drm/dp_mst: Factor out drm_dp_mst_port_is_logical() Date: Wed, 17 Apr 2024 01:10:07 +0300 Message-ID: <20240416221010.376865-9-imre.deak@intel.com> X-Mailer: git-send-email 2.43.3 In-Reply-To: <20240416221010.376865-1-imre.deak@intel.com> References: <20240416221010.376865-1-imre.deak@intel.com> MIME-Version: 1.0 X-BeenThere: dri-devel@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Direct Rendering Infrastructure - Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dri-devel-bounces@lists.freedesktop.org Sender: "dri-devel" Factor out a function to check if an MST port is logical, used by a follow-up i915 patch in the patchset. v2: Move drm_dp_mst_aux_for_parent() forward declaration to the next patch. (Ankit) Cc: Lyude Paul Cc: dri-devel@lists.freedesktop.org Reviewed-by: Ankit Nautiyal Acked-by: Maarten Lankhorst Signed-off-by: Imre Deak --- drivers/gpu/drm/display/drm_dp_mst_topology.c | 6 +++--- include/drm/display/drm_dp_mst_helper.h | 6 ++++++ 2 files changed, 9 insertions(+), 3 deletions(-) diff --git a/drivers/gpu/drm/display/drm_dp_mst_topology.c b/drivers/gpu/drm/display/drm_dp_mst_topology.c index c193be3577f7a..46b99d5fe0086 100644 --- a/drivers/gpu/drm/display/drm_dp_mst_topology.c +++ b/drivers/gpu/drm/display/drm_dp_mst_topology.c @@ -2274,7 +2274,7 @@ drm_dp_mst_port_add_connector(struct drm_dp_mst_branch *mstb, if (port->pdt != DP_PEER_DEVICE_NONE && drm_dp_mst_is_end_device(port->pdt, port->mcs) && - port->port_num >= DP_MST_LOGICAL_PORT_0) + drm_dp_mst_port_is_logical(port)) port->cached_edid = drm_edid_read_ddc(port->connector, &port->aux.ddc); @@ -4219,7 +4219,7 @@ drm_dp_mst_detect_port(struct drm_connector *connector, case DP_PEER_DEVICE_SST_SINK: ret = connector_status_connected; /* for logical ports - cache the EDID */ - if (port->port_num >= DP_MST_LOGICAL_PORT_0 && !port->cached_edid) + if (drm_dp_mst_port_is_logical(port) && !port->cached_edid) port->cached_edid = drm_edid_read_ddc(connector, &port->aux.ddc); break; case DP_PEER_DEVICE_DP_LEGACY_CONV: @@ -5983,7 +5983,7 @@ static bool drm_dp_mst_is_virtual_dpcd(struct drm_dp_mst_port *port) return false; /* Virtual DP Sink (Internal Display Panel) */ - if (port->port_num >= 8) + if (drm_dp_mst_port_is_logical(port)) return true; /* DP-to-HDMI Protocol Converter */ diff --git a/include/drm/display/drm_dp_mst_helper.h b/include/drm/display/drm_dp_mst_helper.h index cbcb49cb6a460..f00e32b0315d7 100644 --- a/include/drm/display/drm_dp_mst_helper.h +++ b/include/drm/display/drm_dp_mst_helper.h @@ -948,6 +948,12 @@ int __must_check drm_dp_mst_root_conn_atomic_check(struct drm_connector_state *n void drm_dp_mst_get_port_malloc(struct drm_dp_mst_port *port); void drm_dp_mst_put_port_malloc(struct drm_dp_mst_port *port); +static inline +bool drm_dp_mst_port_is_logical(struct drm_dp_mst_port *port) +{ + return port->port_num >= DP_MST_LOGICAL_PORT_0; +} + struct drm_dp_aux *drm_dp_mst_dsc_aux_for_port(struct drm_dp_mst_port *port); static inline struct drm_dp_mst_topology_state * From patchwork Tue Apr 16 22:10:08 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Imre Deak X-Patchwork-Id: 13632662 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id E3786C04FFF for ; Tue, 16 Apr 2024 22:09:58 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 85BCD112EBB; Tue, 16 Apr 2024 22:09:57 +0000 (UTC) Authentication-Results: gabe.freedesktop.org; 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a="20165183" X-IronPort-AV: E=Sophos;i="6.07,207,1708416000"; d="scan'208";a="20165183" Received: from fmviesa003.fm.intel.com ([10.60.135.143]) by fmvoesa104.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 16 Apr 2024 15:09:50 -0700 X-CSE-ConnectionGUID: /69XeE08Rs+AEFMIo3jqUA== X-CSE-MsgGUID: 4a8tCrXGQ02YvEAheClqBQ== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.07,207,1708416000"; d="scan'208";a="26965507" Received: from ideak-desk.fi.intel.com ([10.237.72.78]) by fmviesa003-auth.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 16 Apr 2024 15:09:48 -0700 From: Imre Deak To: intel-gfx@lists.freedesktop.org Cc: Lyude Paul , dri-devel@lists.freedesktop.org, Ankit Nautiyal , Maarten Lankhorst Subject: [PATCH v2 09/11] drm/dp_mst: Add drm_dp_mst_aux_for_parent() Date: Wed, 17 Apr 2024 01:10:08 +0300 Message-ID: <20240416221010.376865-10-imre.deak@intel.com> X-Mailer: git-send-email 2.43.3 In-Reply-To: <20240416221010.376865-1-imre.deak@intel.com> References: <20240416221010.376865-1-imre.deak@intel.com> MIME-Version: 1.0 X-BeenThere: dri-devel@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Direct Rendering Infrastructure - Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dri-devel-bounces@lists.freedesktop.org Sender: "dri-devel" Add a function to get the AUX device of the parent of an MST port, used by a follow-up i915 patch in the patchset. v2: Move drm_dp_mst_aux_for_parent() forward declaration to this patch (Ankit) Cc: Lyude Paul Cc: dri-devel@lists.freedesktop.org Reviewed-by: Ankit Nautiyal Acked-by: Maarten Lankhorst Signed-off-by: Imre Deak --- drivers/gpu/drm/display/drm_dp_mst_topology.c | 16 ++++++++++++++++ include/drm/display/drm_dp_mst_helper.h | 1 + 2 files changed, 17 insertions(+) diff --git a/drivers/gpu/drm/display/drm_dp_mst_topology.c b/drivers/gpu/drm/display/drm_dp_mst_topology.c index 46b99d5fe0086..3577786b5db2c 100644 --- a/drivers/gpu/drm/display/drm_dp_mst_topology.c +++ b/drivers/gpu/drm/display/drm_dp_mst_topology.c @@ -6010,6 +6010,22 @@ static bool drm_dp_mst_is_virtual_dpcd(struct drm_dp_mst_port *port) return false; } +/** + * drm_dp_mst_aux_for_parent() - Get the AUX device for an MST port's parent + * @port: MST port whose parent's AUX device is returned + * + * Return the AUX device for @port's parent or NULL if port's parent is the + * root port. + */ +struct drm_dp_aux *drm_dp_mst_aux_for_parent(struct drm_dp_mst_port *port) +{ + if (!port->parent || !port->parent->port_parent) + return NULL; + + return &port->parent->port_parent->aux; +} +EXPORT_SYMBOL(drm_dp_mst_aux_for_parent); + /** * drm_dp_mst_dsc_aux_for_port() - Find the correct aux for DSC * @port: The port to check. A leaf of the MST tree with an attached display. diff --git a/include/drm/display/drm_dp_mst_helper.h b/include/drm/display/drm_dp_mst_helper.h index f00e32b0315d7..3546b58a121bc 100644 --- a/include/drm/display/drm_dp_mst_helper.h +++ b/include/drm/display/drm_dp_mst_helper.h @@ -954,6 +954,7 @@ bool drm_dp_mst_port_is_logical(struct drm_dp_mst_port *port) return port->port_num >= DP_MST_LOGICAL_PORT_0; } +struct drm_dp_aux *drm_dp_mst_aux_for_parent(struct drm_dp_mst_port *port); struct drm_dp_aux *drm_dp_mst_dsc_aux_for_port(struct drm_dp_mst_port *port); static inline struct drm_dp_mst_topology_state * From patchwork Tue Apr 16 22:10:10 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Imre Deak X-Patchwork-Id: 13632661 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 9EBADC04FFF for ; Tue, 16 Apr 2024 22:09:55 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 92013112EB3; Tue, 16 Apr 2024 22:09:54 +0000 (UTC) Authentication-Results: gabe.freedesktop.org; dkim=pass (2048-bit key; unprotected) header.d=intel.com header.i=@intel.com header.b="Ts+MgW0q"; dkim-atps=neutral Received: from mgamail.intel.com (mgamail.intel.com [192.198.163.10]) by gabe.freedesktop.org (Postfix) with ESMTPS id D5C6F112EB3; Tue, 16 Apr 2024 22:09:52 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1713305393; x=1744841393; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=xClQFpiUgrpWK+9cqOXOuA9IExFysUih7No0me29b9o=; b=Ts+MgW0q01fb13mBb8/Q5RwLQ9dKb87mb2Scgrk4GFPfs0Pn4GovdwRC D78X41PjNvpa9OXeAPWK2cGwzbDzzTmjbYG1rpD/xFWNGxH3fXqL9CV7e CiK9xhHZRj0pY+4v8dkGQXmgNgyWFy/H1UHWRTtl2YMrysq3673Ty+E0g RDJkDkyS5lnLbpjyY+tKFeMqY6g7M865/UBb4rSqT+ObviiotqGIH/d1T g3tUh/DREp94weXsk0c26SkV+e464o9ZVwkS179BiFqmvpoEL8a+8eYZu /1bwcR2LHpRcOvtaVN3C+zMMEPJryaKxVCXPMPun0nTidIsQ3QbWf3Gw+ w==; X-CSE-ConnectionGUID: ZqBJaRkRScmG3K6/d3cpBg== X-CSE-MsgGUID: SQ/YzsTXTtSb3csX37HFbw== X-IronPort-AV: E=McAfee;i="6600,9927,11046"; a="20165189" X-IronPort-AV: E=Sophos;i="6.07,207,1708416000"; d="scan'208";a="20165189" Received: from fmviesa003.fm.intel.com ([10.60.135.143]) by fmvoesa104.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 16 Apr 2024 15:09:53 -0700 X-CSE-ConnectionGUID: nFRXkvL4RKC2cr5kfdNv3w== X-CSE-MsgGUID: mP8JiiNdQxicQiARzTTU6Q== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.07,207,1708416000"; d="scan'208";a="26965517" Received: from ideak-desk.fi.intel.com ([10.237.72.78]) by fmviesa003-auth.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 16 Apr 2024 15:09:51 -0700 From: Imre Deak To: intel-gfx@lists.freedesktop.org Cc: dri-devel@lists.freedesktop.org, Ankit Nautiyal , Khaled Almahallawy Subject: [PATCH v2 11/11] drm/i915/dp_mst: Enable HBLANK expansion quirk for UHBR rates Date: Wed, 17 Apr 2024 01:10:10 +0300 Message-ID: <20240416221010.376865-12-imre.deak@intel.com> X-Mailer: git-send-email 2.43.3 In-Reply-To: <20240416221010.376865-1-imre.deak@intel.com> References: <20240416221010.376865-1-imre.deak@intel.com> MIME-Version: 1.0 X-BeenThere: dri-devel@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Direct Rendering Infrastructure - Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dri-devel-bounces@lists.freedesktop.org Sender: "dri-devel" Enabling the 5k@60Hz uncompressed mode on the MediaTek/Dell U3224KBA monitor results in a blank screen, at least on MTL platforms on UHBR link rates with some (<30) uncompressed bpp values. Enabling compression fixes the problem, so do that for now. Windows enables DSC always if the sink supports it and forcing it to enable the mode without compression leads to the same problem above (which suggests a panel issue with uncompressed mode). The same 5k mode on non-UHBR link rates is not affected and lower resolution modes are not affected either. The problem is similar to the one fixed by the HBLANK expansion quirk on Synaptics hubs, with the difference that the problematic mode has a longer HBLANK duration. Also the monitor doesn't report supporting HBLANK expansion; either its internal MST hub does the expansion internally - similarly to the Synaptics hub - or the issue has another root cause, but still related to the mode's short HBLANK duration. Enable the quirk for the monitor adjusting the detection for the above differences. Cc: dri-devel@lists.freedesktop.org Reviewed-by: Ankit Nautiyal Tested-by: Khaled Almahallawy Signed-off-by: Imre Deak --- drivers/gpu/drm/display/drm_dp_helper.c | 2 ++ drivers/gpu/drm/i915/display/intel_dp_mst.c | 22 +++++++++++++++++---- 2 files changed, 20 insertions(+), 4 deletions(-) diff --git a/drivers/gpu/drm/display/drm_dp_helper.c b/drivers/gpu/drm/display/drm_dp_helper.c index 023907da98581..79a615667aab1 100644 --- a/drivers/gpu/drm/display/drm_dp_helper.c +++ b/drivers/gpu/drm/display/drm_dp_helper.c @@ -2281,6 +2281,8 @@ static const struct dpcd_quirk dpcd_quirk_list[] = { { OUI(0x90, 0xCC, 0x24), DEVICE_ID_ANY, true, BIT(DP_DPCD_QUIRK_DSC_WITHOUT_VIRTUAL_DPCD) }, /* Synaptics DP1.4 MST hubs require DSC for some modes on which it applies HBLANK expansion. */ { OUI(0x90, 0xCC, 0x24), DEVICE_ID_ANY, true, BIT(DP_DPCD_QUIRK_HBLANK_EXPANSION_REQUIRES_DSC) }, + /* MediaTek panels (at least in U3224KBA) require DSC for modes with a short HBLANK on UHBR links. */ + { OUI(0x00, 0x0C, 0xE7), DEVICE_ID_ANY, false, BIT(DP_DPCD_QUIRK_HBLANK_EXPANSION_REQUIRES_DSC) }, /* Apple MacBookPro 2017 15 inch eDP Retina panel reports too low DP_MAX_LINK_RATE */ { OUI(0x00, 0x10, 0xfa), DEVICE_ID(101, 68, 21, 101, 98, 97), false, BIT(DP_DPCD_QUIRK_CAN_DO_MAX_LINK_RATE_3_24_GBPS) }, }; diff --git a/drivers/gpu/drm/i915/display/intel_dp_mst.c b/drivers/gpu/drm/i915/display/intel_dp_mst.c index fb5e167c3c659..71b01f7631919 100644 --- a/drivers/gpu/drm/i915/display/intel_dp_mst.c +++ b/drivers/gpu/drm/i915/display/intel_dp_mst.c @@ -421,15 +421,22 @@ static int mode_hblank_period_ns(const struct drm_display_mode *mode) static bool hblank_expansion_quirk_needs_dsc(const struct intel_connector *connector, - const struct intel_crtc_state *crtc_state) + const struct intel_crtc_state *crtc_state, + const struct link_config_limits *limits) { const struct drm_display_mode *adjusted_mode = &crtc_state->hw.adjusted_mode; + bool is_uhbr_sink = connector->mst_port && + drm_dp_uhbr_channel_coding_supported(connector->mst_port->dpcd); + int hblank_limit = is_uhbr_sink ? 500 : 300; if (!connector->dp.dsc_hblank_expansion_quirk) return false; - if (mode_hblank_period_ns(adjusted_mode) > 300) + if (is_uhbr_sink && !drm_dp_is_uhbr_rate(limits->max_rate)) + return false; + + if (mode_hblank_period_ns(adjusted_mode) > hblank_limit) return false; return true; @@ -445,7 +452,7 @@ adjust_limits_for_dsc_hblank_expansion_quirk(const struct intel_connector *conne const struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); int min_bpp_x16 = limits->link.min_bpp_x16; - if (!hblank_expansion_quirk_needs_dsc(connector, crtc_state)) + if (!hblank_expansion_quirk_needs_dsc(connector, crtc_state, limits)) return true; if (!dsc) { @@ -1604,7 +1611,14 @@ static bool detect_dsc_hblank_expansion_quirk(const struct intel_connector *conn DP_DPCD_QUIRK_HBLANK_EXPANSION_REQUIRES_DSC)) return false; - if (!(dpcd[DP_RECEIVE_PORT_0_CAP_0] & DP_HBLANK_EXPANSION_CAPABLE)) + /* + * UHBR (MST sink) devices requiring this quirk doesn't advertise the + * HBLANK expansion support. Presuming that they perform HBLANK + * expansion internally, or are affected by this issue on modes with a + * short HBLANK for other reasons. + */ + if (!drm_dp_uhbr_channel_coding_supported(dpcd) && + !(dpcd[DP_RECEIVE_PORT_0_CAP_0] & DP_HBLANK_EXPANSION_CAPABLE)) return false; drm_dbg_kms(&i915->drm,