From patchwork Tue Apr 16 22:10:00 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Imre Deak X-Patchwork-Id: 13632666 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 66F92C04FF6 for ; Tue, 16 Apr 2024 22:09:42 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 8939910F3D4; Tue, 16 Apr 2024 22:09:41 +0000 (UTC) Authentication-Results: gabe.freedesktop.org; dkim=pass (2048-bit key; unprotected) header.d=intel.com header.i=@intel.com header.b="hE1eMNf5"; dkim-atps=neutral Received: from mgamail.intel.com (mgamail.intel.com [192.198.163.10]) by gabe.freedesktop.org (Postfix) with ESMTPS id 6258F112EAB; Tue, 16 Apr 2024 22:09:39 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1713305379; x=1744841379; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=UC38b05/7bGOTFo1gBV9OejdYxVqJPRZS/+T23pculg=; b=hE1eMNf5J9Ad7ZvO4e523MjetS+oiZuHuLoPqw2u0azX7SL5lUG9FN7T rETd2MeZrkWcaPpD4CQ7eF5ec17ItOUn9LdcjxGzMHs6m/TyY5TNuGzX0 p3JeZaMrkHbOKfdejfgZ3Gjyi1HkG605j+IFEYNmbtxOgv10seviMPsQ6 67yiSQfEZk9vhVx+YQLAQC8xapGTluprRhWGF3TUVy8uxqMEp2VEwFAT3 BY4dR2aJq4trkFok7RZU9qlGioFvU/93U/Ps8ONWYr/lGfLdSgxEeafkK E29EA/qF9M686i8nWGhPOAGADGeDI1GhJJ3wLkF63GdQh6Sd+t2vg8K0r g==; X-CSE-ConnectionGUID: NaNBYpNkQh6wzdG5IzdxZQ== X-CSE-MsgGUID: +iHqOq+PQ36m1gWJ9CvRVg== X-IronPort-AV: E=McAfee;i="6600,9927,11046"; a="20165142" X-IronPort-AV: E=Sophos;i="6.07,207,1708416000"; d="scan'208";a="20165142" Received: from fmviesa003.fm.intel.com ([10.60.135.143]) by fmvoesa104.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 16 Apr 2024 15:09:39 -0700 X-CSE-ConnectionGUID: XSVJbvlTT0eR1QvJQITkGg== X-CSE-MsgGUID: twJ6l7x8ToSrOR+aycNdBw== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.07,207,1708416000"; d="scan'208";a="26965467" Received: from ideak-desk.fi.intel.com ([10.237.72.78]) by fmviesa003-auth.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 16 Apr 2024 15:09:38 -0700 From: Imre Deak To: intel-gfx@lists.freedesktop.org Cc: dri-devel@lists.freedesktop.org, Ankit Nautiyal , Manasi Navare , Maarten Lankhorst Subject: [PATCH v2 01/11] drm/i915/dp: Fix DSC line buffer depth programming Date: Wed, 17 Apr 2024 01:10:00 +0300 Message-ID: <20240416221010.376865-2-imre.deak@intel.com> X-Mailer: git-send-email 2.43.3 In-Reply-To: <20240416221010.376865-1-imre.deak@intel.com> References: <20240416221010.376865-1-imre.deak@intel.com> MIME-Version: 1.0 X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" Fix the calculation of the DSC line buffer depth. This is limited both by the source's and sink's maximum line buffer depth, but the former one was not taken into account. On all Intel platform's the source's maximum buffer depth is 13, so the overall limit is simply the minimum of the source/sink's limit, regardless of the DSC version. This leaves the DSI DSC line buffer depth calculation as-is, trusting VBT. On DSC version 1.2 for sinks reporting a maximum line buffer depth of 16 the line buffer depth was incorrectly programmed as 0, leading to a corruption in color gradients / lines on the decompressed screen image. Cc: dri-devel@lists.freedesktop.org Reviewed-by: Ankit Nautiyal Reviewed-by: Manasi Navare Acked-by: Maarten Lankhorst Signed-off-by: Imre Deak --- drivers/gpu/drm/i915/display/intel_dp.c | 16 ++++++---------- include/drm/display/drm_dsc.h | 3 --- 2 files changed, 6 insertions(+), 13 deletions(-) diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c index 163da48bc4065..23808e9d41d5d 100644 --- a/drivers/gpu/drm/i915/display/intel_dp.c +++ b/drivers/gpu/drm/i915/display/intel_dp.c @@ -89,6 +89,9 @@ #define DP_DSC_MAX_ENC_THROUGHPUT_0 340000 #define DP_DSC_MAX_ENC_THROUGHPUT_1 400000 +/* Max DSC line buffer depth supported by HW. */ +#define INTEL_DP_DSC_MAX_LINE_BUF_DEPTH 13 + /* DP DSC FEC Overhead factor in ppm = 1/(0.972261) = 1.028530 */ #define DP_DSC_FEC_OVERHEAD_FACTOR 1028530 @@ -1705,7 +1708,6 @@ static int intel_dp_dsc_compute_params(const struct intel_connector *connector, { struct drm_i915_private *i915 = to_i915(connector->base.dev); struct drm_dsc_config *vdsc_cfg = &crtc_state->dsc.config; - u8 line_buf_depth; int ret; /* @@ -1734,20 +1736,14 @@ static int intel_dp_dsc_compute_params(const struct intel_connector *connector, connector->dp.dsc_dpcd[DP_DSC_DEC_COLOR_FORMAT_CAP - DP_DSC_SUPPORT] & DP_DSC_RGB; - line_buf_depth = drm_dp_dsc_sink_line_buf_depth(connector->dp.dsc_dpcd); - if (!line_buf_depth) { + vdsc_cfg->line_buf_depth = min(INTEL_DP_DSC_MAX_LINE_BUF_DEPTH, + drm_dp_dsc_sink_line_buf_depth(connector->dp.dsc_dpcd)); + if (!vdsc_cfg->line_buf_depth) { drm_dbg_kms(&i915->drm, "DSC Sink Line Buffer Depth invalid\n"); return -EINVAL; } - if (vdsc_cfg->dsc_version_minor == 2) - vdsc_cfg->line_buf_depth = (line_buf_depth == DSC_1_2_MAX_LINEBUF_DEPTH_BITS) ? - DSC_1_2_MAX_LINEBUF_DEPTH_VAL : line_buf_depth; - else - vdsc_cfg->line_buf_depth = (line_buf_depth > DSC_1_1_MAX_LINEBUF_DEPTH_BITS) ? - DSC_1_1_MAX_LINEBUF_DEPTH_BITS : line_buf_depth; - vdsc_cfg->block_pred_enable = connector->dp.dsc_dpcd[DP_DSC_BLK_PREDICTION_SUPPORT - DP_DSC_SUPPORT] & DP_DSC_BLK_PREDICTION_IS_SUPPORTED; diff --git a/include/drm/display/drm_dsc.h b/include/drm/display/drm_dsc.h index bc90273d06a62..bbbe7438473d3 100644 --- a/include/drm/display/drm_dsc.h +++ b/include/drm/display/drm_dsc.h @@ -40,9 +40,6 @@ #define DSC_PPS_RC_RANGE_MINQP_SHIFT 11 #define DSC_PPS_RC_RANGE_MAXQP_SHIFT 6 #define DSC_PPS_NATIVE_420_SHIFT 1 -#define DSC_1_2_MAX_LINEBUF_DEPTH_BITS 16 -#define DSC_1_2_MAX_LINEBUF_DEPTH_VAL 0 -#define DSC_1_1_MAX_LINEBUF_DEPTH_BITS 13 /** * struct drm_dsc_rc_range_parameters - DSC Rate Control range parameters From patchwork Tue Apr 16 22:10:01 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Imre Deak X-Patchwork-Id: 13632667 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 1B2F6C04FFF for ; Tue, 16 Apr 2024 22:09:43 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 3958F112EA9; Tue, 16 Apr 2024 22:09:42 +0000 (UTC) Authentication-Results: gabe.freedesktop.org; dkim=pass (2048-bit key; unprotected) header.d=intel.com header.i=@intel.com header.b="RteDjbTe"; dkim-atps=neutral Received: from mgamail.intel.com (mgamail.intel.com [192.198.163.10]) by gabe.freedesktop.org (Postfix) with ESMTPS id 7E54710F3D4 for ; Tue, 16 Apr 2024 22:09:40 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1713305380; x=1744841380; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=wRCVqrGmiMdOVn5x5SuyYtOdwC+JubeBA4htvUFYAlM=; b=RteDjbTeT3nLdtlDAcHh/N01zB1k4Nh8Ot787GmHilCFXFMw7ut0qQ3h f0F9U+GSQ6d2qbNwUo0xq77FsKQJ83XSfw0FHGKjgHHuSPpChwyNBKM85 tqcYr8Wymiw3wV9Ke+myO2XxxWd4MoaRnuUDvvrYMioDy2xQmT03Ff82G CKNiRcbDWV9bFlwLtImq4brM/a9HlTicu3/G7LMVwVptehWOekFEW4fDk MvioQI0CBKZUNQsgkkPpFm4HNYXlBfokXxeZJ4eC+qP+knL8yVrDgRvGe lSwOUKJ/6rTqE509oxSpO4redMkZ21AjsIZbMyn16TwMo1MD0Fnm6fkmt w==; X-CSE-ConnectionGUID: EuuWUGVhSl63zQ6BQNAcCw== X-CSE-MsgGUID: v5uNUC93Rn+BI4uylJLq4w== X-IronPort-AV: E=McAfee;i="6600,9927,11046"; a="20165148" X-IronPort-AV: E=Sophos;i="6.07,207,1708416000"; d="scan'208";a="20165148" Received: from fmviesa003.fm.intel.com ([10.60.135.143]) by fmvoesa104.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 16 Apr 2024 15:09:40 -0700 X-CSE-ConnectionGUID: 6j/6gW5CSk2vE6sRP0iorg== X-CSE-MsgGUID: KEaqX8kYRE2znEUPHgcoig== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.07,207,1708416000"; d="scan'208";a="26965473" Received: from ideak-desk.fi.intel.com ([10.237.72.78]) by fmviesa003-auth.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 16 Apr 2024 15:09:39 -0700 From: Imre Deak To: intel-gfx@lists.freedesktop.org Cc: Ankit Nautiyal Subject: [PATCH v2 02/11] drm/i915/dp_mst: Fix symbol clock when calculating the DSC DPT bpp limit Date: Wed, 17 Apr 2024 01:10:01 +0300 Message-ID: <20240416221010.376865-3-imre.deak@intel.com> X-Mailer: git-send-email 2.43.3 In-Reply-To: <20240416221010.376865-1-imre.deak@intel.com> References: <20240416221010.376865-1-imre.deak@intel.com> MIME-Version: 1.0 X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" The expected link symbol clock unit when calculating the DSC DPT bpp limit is kSymbols/sec, aligning with the dotclock's kPixels/sec unit based on the crtc clock. As opposed to this port_clock is used - which has a 10 kbits/sec unit - with the resulting symbol clock in 10 kSymbols/sec units (disregarding the rounding error for the 13.5Gbps rate). Fix the calculation using the expected 10x factor. Reviewed-by: Ankit Nautiyal Signed-off-by: Imre Deak --- drivers/gpu/drm/i915/display/intel_dp_mst.c | 3 +-- 1 file changed, 1 insertion(+), 2 deletions(-) diff --git a/drivers/gpu/drm/i915/display/intel_dp_mst.c b/drivers/gpu/drm/i915/display/intel_dp_mst.c index d43617734009c..196eeead8cf02 100644 --- a/drivers/gpu/drm/i915/display/intel_dp_mst.c +++ b/drivers/gpu/drm/i915/display/intel_dp_mst.c @@ -58,8 +58,7 @@ static int intel_dp_mst_check_constraints(struct drm_i915_private *i915, int bpp { if (intel_dp_is_uhbr(crtc_state) && DISPLAY_VER(i915) < 14 && dsc) { int output_bpp = bpp; - /* DisplayPort 2 128b/132b, bits per lane is always 32 */ - int symbol_clock = crtc_state->port_clock / 32; + int symbol_clock = intel_dp_link_symbol_clock(crtc_state->port_clock); if (output_bpp * adjusted_mode->crtc_clock >= symbol_clock * 72) { From patchwork Tue Apr 16 22:10:02 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Imre Deak X-Patchwork-Id: 13632670 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 05DFFC04FF6 for ; Tue, 16 Apr 2024 22:09:49 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 00EFF112EB4; Tue, 16 Apr 2024 22:09:45 +0000 (UTC) Authentication-Results: gabe.freedesktop.org; dkim=pass (2048-bit key; unprotected) header.d=intel.com header.i=@intel.com header.b="O0IoRVlt"; dkim-atps=neutral Received: from mgamail.intel.com (mgamail.intel.com [192.198.163.10]) by gabe.freedesktop.org (Postfix) with ESMTPS id 9C9D1112EA9 for ; Tue, 16 Apr 2024 22:09:41 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1713305382; x=1744841382; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=BFZG4IL8coiMgG9X3CGVtmXqR0lCAL7wCbuRfWjlToU=; b=O0IoRVltgFGjxobbZmmdnRmyp4EXA9jiBDNOmPulupTIR/I11Uwxf1ID PLzc2XYVpkPkK45PYMRplyWzVh/2WP9TUqCegEAKkuhXjGAzflihDkiNY PkE3jQuvktdkRf125Gc97sGPWOHZJaufMqEwLnuT6Cj0APjOZcLVzCDk4 N6rw0QzohUHlfYhBqx8pdasGIKkJr7WS3QxZ89zsJA30qxBApES8Vvo26 DmuHFEisaFce0tAjowgEK7aZAS+0oa0/VzIaKHek8SUoCjF8YCw7u5DsU WPEJwBhEockQPFFBjKKg5Ai4qXJ1Yl1YEt0QzOnUYlyDma59h7PamPTGN A==; X-CSE-ConnectionGUID: sEx8YhPdSHCaEAUFQ7tQ2Q== X-CSE-MsgGUID: scpEJB1gQF6Ec6SjLcPQjA== X-IronPort-AV: E=McAfee;i="6600,9927,11046"; a="20165152" X-IronPort-AV: E=Sophos;i="6.07,207,1708416000"; d="scan'208";a="20165152" Received: from fmviesa003.fm.intel.com ([10.60.135.143]) by fmvoesa104.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 16 Apr 2024 15:09:41 -0700 X-CSE-ConnectionGUID: /j7zNSjxTmin1k+GCWbtOw== X-CSE-MsgGUID: XtA+oNRtSXavI/fQtxRlhA== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.07,207,1708416000"; d="scan'208";a="26965479" Received: from ideak-desk.fi.intel.com ([10.237.72.78]) by fmviesa003-auth.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 16 Apr 2024 15:09:41 -0700 From: Imre Deak To: intel-gfx@lists.freedesktop.org Cc: Ankit Nautiyal Subject: [PATCH v2 03/11] drm/i915/dp_mst: Fix BW limit check when calculating DSC DPT bpp Date: Wed, 17 Apr 2024 01:10:02 +0300 Message-ID: <20240416221010.376865-4-imre.deak@intel.com> X-Mailer: git-send-email 2.43.3 In-Reply-To: <20240416221010.376865-1-imre.deak@intel.com> References: <20240416221010.376865-1-imre.deak@intel.com> MIME-Version: 1.0 X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" The DSC DPT bpp limit check should only fail if the available DPT BW is less than the required BW, fix the check accordingly. Reviewed-by: Ankit Nautiyal Signed-off-by: Imre Deak --- drivers/gpu/drm/i915/display/intel_dp_mst.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/gpu/drm/i915/display/intel_dp_mst.c b/drivers/gpu/drm/i915/display/intel_dp_mst.c index 196eeead8cf02..58eb6bf33c92e 100644 --- a/drivers/gpu/drm/i915/display/intel_dp_mst.c +++ b/drivers/gpu/drm/i915/display/intel_dp_mst.c @@ -60,7 +60,7 @@ static int intel_dp_mst_check_constraints(struct drm_i915_private *i915, int bpp int output_bpp = bpp; int symbol_clock = intel_dp_link_symbol_clock(crtc_state->port_clock); - if (output_bpp * adjusted_mode->crtc_clock >= + if (output_bpp * adjusted_mode->crtc_clock > symbol_clock * 72) { drm_dbg_kms(&i915->drm, "UHBR check failed(required bw %d available %d)\n", output_bpp * adjusted_mode->crtc_clock, symbol_clock * 72); From patchwork Tue Apr 16 22:10:03 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Imre Deak X-Patchwork-Id: 13632668 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 2A772C4345F for ; Tue, 16 Apr 2024 22:09:47 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 541EE112EAF; Tue, 16 Apr 2024 22:09:44 +0000 (UTC) Authentication-Results: gabe.freedesktop.org; dkim=pass (2048-bit key; unprotected) header.d=intel.com header.i=@intel.com header.b="fdIIcqgw"; dkim-atps=neutral Received: from mgamail.intel.com (mgamail.intel.com [192.198.163.10]) by gabe.freedesktop.org (Postfix) with ESMTPS id BD216112EAC for ; Tue, 16 Apr 2024 22:09:42 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1713305383; x=1744841383; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=ll1fcqDxUghtaRU8w55zfMCzF69P0rvOczHSLSZ86ck=; b=fdIIcqgwbT58yLml62z50CugAyPe0Dq8t0AG8/dOEfW1OtmtiBCcYTci YXT1eacNOFPL8l7S+0/VDtf6UMbCgDu4YAfO+H4mVnhE+eSJueKGYFlb4 mjOe7R+Rs33JoKkfmUoUAZcvvPxIGgtiruQB1hFCNpDQzMKV5QzRacG3z yGSQH2soaxBYYFxH4pA9RbahBU97wmM6AmcnE/uwz7A1ERuyuYnicwIlZ OyVTtm3OVqXI4Lsa2fit0UfbYn90gro7upifGZ2BjKI0d/BDm4Xid7npY qBtTEIWP5p6STbFYiPTJG9i/39yWBkkIYtyNfRDqJ6fICk/eh2TCWMLUM Q==; X-CSE-ConnectionGUID: Xwmm4TmDSPmkqU2UTDgJzg== X-CSE-MsgGUID: HBScXkrNRbK2oZiZ3PEqAg== X-IronPort-AV: E=McAfee;i="6600,9927,11046"; a="20165156" X-IronPort-AV: E=Sophos;i="6.07,207,1708416000"; d="scan'208";a="20165156" Received: from fmviesa003.fm.intel.com ([10.60.135.143]) by fmvoesa104.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 16 Apr 2024 15:09:42 -0700 X-CSE-ConnectionGUID: PEglloKuRbaPu89I8O9pFw== X-CSE-MsgGUID: WwsPnkPTQDyTcBxzIEha0A== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.07,207,1708416000"; d="scan'208";a="26965482" Received: from ideak-desk.fi.intel.com ([10.237.72.78]) by fmviesa003-auth.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 16 Apr 2024 15:09:42 -0700 From: Imre Deak To: intel-gfx@lists.freedesktop.org Cc: Ankit Nautiyal Subject: [PATCH v2 04/11] drm/i915/dp_mst: Account for channel coding efficiency in the DSC DPT bpp limit Date: Wed, 17 Apr 2024 01:10:03 +0300 Message-ID: <20240416221010.376865-5-imre.deak@intel.com> X-Mailer: git-send-email 2.43.3 In-Reply-To: <20240416221010.376865-1-imre.deak@intel.com> References: <20240416221010.376865-1-imre.deak@intel.com> MIME-Version: 1.0 X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" The DSC DPT interface BW limit check should take into account the link clock's (aka DDI clock in bspec) channel coding efficiency overhead. Bspec suggests that the FEC overhead needs to be applied, however HW people claim this isn't the case, nor is any overhead applicable. However based on testing various 5k/6k modes both on the DELL U3224KBA monitor and the Unigraf UCD-500 CTS test device, both the channel coding efficiency (which includes the FEC overhead) and an additional 3% overhead must be accounted for to get these modes working. Bspec: 49259 v2: - Apply an additional 3% overhead, add a commit log and code comment about these overheads and the relation to the Bspec BW limit formula. Reviewed-by: Ankit Nautiyal (v1) Signed-off-by: Imre Deak Reviewed-by: Ankit Nautiyal --- drivers/gpu/drm/i915/display/intel_dp_mst.c | 23 +++++++++++++++++++-- 1 file changed, 21 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/i915/display/intel_dp_mst.c b/drivers/gpu/drm/i915/display/intel_dp_mst.c index 58eb6bf33c92e..0448cc343a33f 100644 --- a/drivers/gpu/drm/i915/display/intel_dp_mst.c +++ b/drivers/gpu/drm/i915/display/intel_dp_mst.c @@ -59,11 +59,30 @@ static int intel_dp_mst_check_constraints(struct drm_i915_private *i915, int bpp if (intel_dp_is_uhbr(crtc_state) && DISPLAY_VER(i915) < 14 && dsc) { int output_bpp = bpp; int symbol_clock = intel_dp_link_symbol_clock(crtc_state->port_clock); + /* + * Bspec/49259 suggests that the FEC overhead needs to be + * applied here, though HW people claim that neither this FEC + * or any other overhead is applicable here (that is the actual + * available_bw is just symbol_clock * 72). However based on + * testing on MTL-P the + * - DELL U3224KBA display + * - Unigraf UCD-500 CTS test sink + * devices the + * - 5120x2880/995.59Mhz + * - 6016x3384/1357.23Mhz + * - 6144x3456/1413.39Mhz + * modes (all which had a DPT limit on the above devices), + * both the channel coding efficiency and an additional 3% + * overhead needs to be accounted for. + */ + int available_bw = mul_u32_u32(symbol_clock * 72, + drm_dp_bw_channel_coding_efficiency(true)) / + 1030000; if (output_bpp * adjusted_mode->crtc_clock > - symbol_clock * 72) { + available_bw) { drm_dbg_kms(&i915->drm, "UHBR check failed(required bw %d available %d)\n", - output_bpp * adjusted_mode->crtc_clock, symbol_clock * 72); + output_bpp * adjusted_mode->crtc_clock, available_bw); return -EINVAL; } } From patchwork Tue Apr 16 22:10:04 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Imre Deak X-Patchwork-Id: 13632669 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 284FDC04FFF for ; Tue, 16 Apr 2024 22:09:48 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id DAD9D112EB0; Tue, 16 Apr 2024 22:09:44 +0000 (UTC) Authentication-Results: gabe.freedesktop.org; dkim=pass (2048-bit key; unprotected) header.d=intel.com header.i=@intel.com header.b="ANPmlfuc"; dkim-atps=neutral Received: from mgamail.intel.com (mgamail.intel.com [192.198.163.10]) by gabe.freedesktop.org (Postfix) with ESMTPS id DAA46112EAD for ; Tue, 16 Apr 2024 22:09:43 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1713305384; x=1744841384; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=IrfVEPtkHSDQSSc8uuLqnOpGTo+js9qgSLEWD1WgQSU=; b=ANPmlfucTuMSoKbd7HfSWAMxKEhFqIkQ5rwM0ojXhFJ4CikKkwQe605W jP56njF2H3MkjHR2VNRxQY6DvCCSictCPSI/UUAlN22X3rokIq16AUcHn DX8DHhI5HQK1b7kTevWhXLiNF0D8TMp3aGDrwaIW+kd2vRIJ3FjsRcN5x tAm8tMBZCmvW8oVCsrzIAzqtIL12NAA3HYtyo+rvDmfEL9O9F1V3hH6z0 P9D3nhffqou5Pu4WdvD/7GYxrju365JSA0sdOU4po8Aup2Hzbx3aM0T7n BH4x9Tak6yvK8PseXBRiwLalrnKd9iVPTdn/1RA/Vbhn+BF7y6kNF8jmh Q==; X-CSE-ConnectionGUID: /ziBnCDHSs6o1WsJ1Kpjlw== X-CSE-MsgGUID: xiaeDpXmRNSpt3hctepgNw== X-IronPort-AV: E=McAfee;i="6600,9927,11046"; a="20165160" X-IronPort-AV: E=Sophos;i="6.07,207,1708416000"; d="scan'208";a="20165160" Received: from fmviesa003.fm.intel.com ([10.60.135.143]) by fmvoesa104.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 16 Apr 2024 15:09:44 -0700 X-CSE-ConnectionGUID: IvqQgLSAQ32i9jFbcE5Dyg== X-CSE-MsgGUID: QhZ4u+TnToK/s20xbLZWQQ== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.07,207,1708416000"; d="scan'208";a="26965486" Received: from ideak-desk.fi.intel.com ([10.237.72.78]) by fmviesa003-auth.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 16 Apr 2024 15:09:43 -0700 From: Imre Deak To: intel-gfx@lists.freedesktop.org Cc: Ankit Nautiyal Subject: [PATCH v2 05/11] drm/i915/dp_mst: Account with the DSC DPT bpp limit on MTL Date: Wed, 17 Apr 2024 01:10:04 +0300 Message-ID: <20240416221010.376865-6-imre.deak@intel.com> X-Mailer: git-send-email 2.43.3 In-Reply-To: <20240416221010.376865-1-imre.deak@intel.com> References: <20240416221010.376865-1-imre.deak@intel.com> MIME-Version: 1.0 X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" The DPT/DSC bpp limit should be accounted for on MTL platforms as well, do so. Bspec: 49259 Reviewed-by: Ankit Nautiyal Signed-off-by: Imre Deak --- drivers/gpu/drm/i915/display/intel_dp_mst.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/gpu/drm/i915/display/intel_dp_mst.c b/drivers/gpu/drm/i915/display/intel_dp_mst.c index 0448cc343a33f..847e264e5bb8b 100644 --- a/drivers/gpu/drm/i915/display/intel_dp_mst.c +++ b/drivers/gpu/drm/i915/display/intel_dp_mst.c @@ -56,7 +56,7 @@ static int intel_dp_mst_check_constraints(struct drm_i915_private *i915, int bpp struct intel_crtc_state *crtc_state, bool dsc) { - if (intel_dp_is_uhbr(crtc_state) && DISPLAY_VER(i915) < 14 && dsc) { + if (intel_dp_is_uhbr(crtc_state) && DISPLAY_VER(i915) < 20 && dsc) { int output_bpp = bpp; int symbol_clock = intel_dp_link_symbol_clock(crtc_state->port_clock); /* From patchwork Tue Apr 16 22:10:05 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Imre Deak X-Patchwork-Id: 13632671 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id BC2B9C4345F for ; Tue, 16 Apr 2024 22:09:49 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 0FBE8112EAC; Tue, 16 Apr 2024 22:09:46 +0000 (UTC) Authentication-Results: gabe.freedesktop.org; dkim=pass (2048-bit key; unprotected) header.d=intel.com header.i=@intel.com header.b="XQ/iUDYF"; dkim-atps=neutral Received: from mgamail.intel.com (mgamail.intel.com [192.198.163.10]) by gabe.freedesktop.org (Postfix) with ESMTPS id 081C8112EB5 for ; Tue, 16 Apr 2024 22:09:45 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1713305385; x=1744841385; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=aBwVfX1mckjY59oRtOdVb7Hfh5NAVXnUyM1dO5/zLB0=; b=XQ/iUDYFKMNoN6xCUvupodihz+B/zxmJv2N+mC+iQnhj2Qqap652dvoa WFdFvyqa4XLf68d7DEHC6VahRU1TO0HxFh7Pd0MXDuGAs5dPIxETUrkVv Qovl9YLUxbiBxOTgNP/cLxE/K6JwAVvvgBbdM8wzOKQR8jF0+aNpan1WG 1Tqm0K5IHqtylsLcfpNAvrKT6Zd32aVZnnU3TsqNqhQxpaDet6VgFVX/B 2HqIfcTpxAfLH+YpX5BG09J1xH5ZPdv2T2jSVhDBRXu3Ytd4ufS0eXAVd CG+E5Pqp+A0EWjU/yFqWia5eXl9M4wJj7S/OsYljjGbC6cv15GV4SUYj7 g==; X-CSE-ConnectionGUID: 2D//sUHUSgaplqelh1TJpg== X-CSE-MsgGUID: zWOj9jqYTvik7vP54LBYfQ== X-IronPort-AV: E=McAfee;i="6600,9927,11046"; a="20165162" X-IronPort-AV: E=Sophos;i="6.07,207,1708416000"; d="scan'208";a="20165162" Received: from fmviesa003.fm.intel.com ([10.60.135.143]) by fmvoesa104.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 16 Apr 2024 15:09:45 -0700 X-CSE-ConnectionGUID: EQgKtswWS/ysT+b4DuTdBA== X-CSE-MsgGUID: Ggt7/d2HR6yYy+ihikDodQ== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.07,207,1708416000"; d="scan'208";a="26965491" Received: from ideak-desk.fi.intel.com ([10.237.72.78]) by fmviesa003-auth.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 16 Apr 2024 15:09:44 -0700 From: Imre Deak To: intel-gfx@lists.freedesktop.org Cc: Ankit Nautiyal Subject: [PATCH v2 06/11] drm/i915/dp_mst: Sanitize calculating the DSC DPT bpp limit Date: Wed, 17 Apr 2024 01:10:05 +0300 Message-ID: <20240416221010.376865-7-imre.deak@intel.com> X-Mailer: git-send-email 2.43.3 In-Reply-To: <20240416221010.376865-1-imre.deak@intel.com> References: <20240416221010.376865-1-imre.deak@intel.com> MIME-Version: 1.0 X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" Instead of checking each compressed bpp value against the maximum DSC/DPT bpp, simplify things by calculating the maximum bpp upfront and limiting the range of bpps looped over using this maximum. While at it add a comment about the origin of the DSC/DPT bpp limit. Bspec: 49259, 68912 Reviewed-by: Ankit Nautiyal Signed-off-by: Imre Deak --- drivers/gpu/drm/i915/display/intel_dp_mst.c | 76 ++++++++++----------- 1 file changed, 38 insertions(+), 38 deletions(-) diff --git a/drivers/gpu/drm/i915/display/intel_dp_mst.c b/drivers/gpu/drm/i915/display/intel_dp_mst.c index 847e264e5bb8b..89ee80a357140 100644 --- a/drivers/gpu/drm/i915/display/intel_dp_mst.c +++ b/drivers/gpu/drm/i915/display/intel_dp_mst.c @@ -51,43 +51,39 @@ #include "intel_vdsc.h" #include "skl_scaler.h" -static int intel_dp_mst_check_constraints(struct drm_i915_private *i915, int bpp, - const struct drm_display_mode *adjusted_mode, - struct intel_crtc_state *crtc_state, - bool dsc) +static int intel_dp_mst_max_dpt_bpp(const struct intel_crtc_state *crtc_state, + bool dsc) { - if (intel_dp_is_uhbr(crtc_state) && DISPLAY_VER(i915) < 20 && dsc) { - int output_bpp = bpp; - int symbol_clock = intel_dp_link_symbol_clock(crtc_state->port_clock); - /* - * Bspec/49259 suggests that the FEC overhead needs to be - * applied here, though HW people claim that neither this FEC - * or any other overhead is applicable here (that is the actual - * available_bw is just symbol_clock * 72). However based on - * testing on MTL-P the - * - DELL U3224KBA display - * - Unigraf UCD-500 CTS test sink - * devices the - * - 5120x2880/995.59Mhz - * - 6016x3384/1357.23Mhz - * - 6144x3456/1413.39Mhz - * modes (all which had a DPT limit on the above devices), - * both the channel coding efficiency and an additional 3% - * overhead needs to be accounted for. - */ - int available_bw = mul_u32_u32(symbol_clock * 72, - drm_dp_bw_channel_coding_efficiency(true)) / - 1030000; + struct drm_i915_private *i915 = to_i915(crtc_state->uapi.crtc->dev); + const struct drm_display_mode *adjusted_mode = + &crtc_state->hw.adjusted_mode; - if (output_bpp * adjusted_mode->crtc_clock > - available_bw) { - drm_dbg_kms(&i915->drm, "UHBR check failed(required bw %d available %d)\n", - output_bpp * adjusted_mode->crtc_clock, available_bw); - return -EINVAL; - } - } + if (!intel_dp_is_uhbr(crtc_state) || DISPLAY_VER(i915) >= 20 || !dsc) + return INT_MAX; - return 0; + /* + * DSC->DPT interface width: + * ICL-MTL: 72 bits (each branch has 72 bits, only left branch is used) + * LNL+: 144 bits (not a bottleneck in any config) + * + * Bspec/49259 suggests that the FEC overhead needs to be + * applied here, though HW people claim that neither this FEC + * or any other overhead is applicable here (that is the actual + * available_bw is just symbol_clock * 72). However based on + * testing on MTL-P the + * - DELL U3224KBA display + * - Unigraf UCD-500 CTS test sink + * devices the + * - 5120x2880/995.59Mhz + * - 6016x3384/1357.23Mhz + * - 6144x3456/1413.39Mhz + * modes (all which had a DPT limit on the above devices), + * both the channel coding efficiency and an additional 3% + * overhead needs to be accounted for. + */ + return div64_u64(mul_u32_u32(intel_dp_link_symbol_clock(crtc_state->port_clock) * 72, + drm_dp_bw_channel_coding_efficiency(true)), + mul_u32_u32(adjusted_mode->crtc_clock, 1030000)); } static int intel_dp_mst_bw_overhead(const struct intel_crtc_state *crtc_state, @@ -175,6 +171,7 @@ static int intel_dp_mst_find_vcpi_slots_for_bpp(struct intel_encoder *encoder, const struct drm_display_mode *adjusted_mode = &crtc_state->hw.adjusted_mode; int bpp, slots = -EINVAL; + int max_dpt_bpp; int ret = 0; mst_state = drm_atomic_get_mst_topology_state(state, &intel_dp->mst_mgr); @@ -195,6 +192,13 @@ static int intel_dp_mst_find_vcpi_slots_for_bpp(struct intel_encoder *encoder, crtc_state->port_clock, crtc_state->lane_count); + max_dpt_bpp = intel_dp_mst_max_dpt_bpp(crtc_state, dsc); + if (max_bpp > max_dpt_bpp) { + drm_dbg_kms(&i915->drm, "Limiting bpp to max DPT bpp (%d -> %d)\n", + max_bpp, max_dpt_bpp); + max_bpp = max_dpt_bpp; + } + drm_dbg_kms(&i915->drm, "Looking for slots in range min bpp %d max bpp %d\n", min_bpp, max_bpp); @@ -206,10 +210,6 @@ static int intel_dp_mst_find_vcpi_slots_for_bpp(struct intel_encoder *encoder, drm_dbg_kms(&i915->drm, "Trying bpp %d\n", bpp); - ret = intel_dp_mst_check_constraints(i915, bpp, adjusted_mode, crtc_state, dsc); - if (ret) - continue; - link_bpp_x16 = to_bpp_x16(dsc ? bpp : intel_dp_output_bpp(crtc_state->output_format, bpp)); From patchwork Tue Apr 16 22:10:06 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Imre Deak X-Patchwork-Id: 13632672 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 3D19BC4345F for ; Tue, 16 Apr 2024 22:09:55 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id A4054112EB5; Tue, 16 Apr 2024 22:09:54 +0000 (UTC) Authentication-Results: gabe.freedesktop.org; dkim=pass (2048-bit key; unprotected) header.d=intel.com header.i=@intel.com header.b="nv5U2P6a"; dkim-atps=neutral Received: from mgamail.intel.com (mgamail.intel.com [192.198.163.10]) by gabe.freedesktop.org (Postfix) with ESMTPS id B3493112EB3; Tue, 16 Apr 2024 22:09:46 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1713305387; x=1744841387; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=CehbAt/+gn4naKc4KR36grWFyIic0bmBXgkYinHvbDs=; b=nv5U2P6aefyvt6s18dGJjULO0ef0dufcg7u1eijYVJsHHRfzsuNRpD1S FTvMFSvWiSUmkn+EXE+8yQk6UxncazYSXjaa9CrwcKq108iCShzj2fYq9 GSjyNbmWF1QeQWh+5saAeZ6JPiveb9wml+4N8wUzldHrEqVZnkW1REi2w t0f1vIJPtyAhBoXB6Kz3kkN6HjsfAvt75VGBy1NHUiL9RoTO8Z8X2ZGNE b9GSkeKBLWvCoU5JJwEqbDcWtDu0TKcCVZ2dCSZVH7QOaBfNugqwi5LoR RcMFH/e7oTd8cAoe3Ok9BnemQNrWG5n1C6nOrVWMPpqPWihStlC5FwBTP w==; X-CSE-ConnectionGUID: 9cpUnJeuQAeS7UGBDdEqgg== X-CSE-MsgGUID: jXGuvSUwTYGrLbGpg/PK6w== X-IronPort-AV: E=McAfee;i="6600,9927,11046"; a="20165169" X-IronPort-AV: E=Sophos;i="6.07,207,1708416000"; d="scan'208";a="20165169" Received: from fmviesa003.fm.intel.com ([10.60.135.143]) by fmvoesa104.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 16 Apr 2024 15:09:46 -0700 X-CSE-ConnectionGUID: MKzvqEisTsqUWp2eVwjefQ== X-CSE-MsgGUID: q7uWgtFxT2WCzrXAccB5rw== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.07,207,1708416000"; d="scan'208";a="26965497" Received: from ideak-desk.fi.intel.com ([10.237.72.78]) by fmviesa003-auth.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 16 Apr 2024 15:09:45 -0700 From: Imre Deak To: intel-gfx@lists.freedesktop.org Cc: dri-devel@lists.freedesktop.org, Ankit Nautiyal , Manasi Navare , Maarten Lankhorst Subject: [PATCH v2 07/11] drm/dp: Add drm_dp_uhbr_channel_coding_supported() Date: Wed, 17 Apr 2024 01:10:06 +0300 Message-ID: <20240416221010.376865-8-imre.deak@intel.com> X-Mailer: git-send-email 2.43.3 In-Reply-To: <20240416221010.376865-1-imre.deak@intel.com> References: <20240416221010.376865-1-imre.deak@intel.com> MIME-Version: 1.0 X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" Factor out a function to check for UHBR channel coding support used by a follow-up patch in the patchset. Cc: dri-devel@lists.freedesktop.org Reviewed-by: Ankit Nautiyal Reviewed-by: Manasi Navare Acked-by: Maarten Lankhorst Signed-off-by: Imre Deak --- drivers/gpu/drm/i915/display/intel_dp.c | 2 +- include/drm/display/drm_dp_helper.h | 6 ++++++ 2 files changed, 7 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c index 23808e9d41d5d..41127069b55e4 100644 --- a/drivers/gpu/drm/i915/display/intel_dp.c +++ b/drivers/gpu/drm/i915/display/intel_dp.c @@ -225,7 +225,7 @@ static void intel_dp_set_dpcd_sink_rates(struct intel_dp *intel_dp) * Sink rates for 128b/132b. If set, sink should support all 8b/10b * rates and 10 Gbps. */ - if (intel_dp->dpcd[DP_MAIN_LINK_CHANNEL_CODING] & DP_CAP_ANSI_128B132B) { + if (drm_dp_uhbr_channel_coding_supported(intel_dp->dpcd)) { u8 uhbr_rates = 0; BUILD_BUG_ON(ARRAY_SIZE(intel_dp->sink_rates) < ARRAY_SIZE(dp_rates) + 3); diff --git a/include/drm/display/drm_dp_helper.h b/include/drm/display/drm_dp_helper.h index baf9949ff96fc..8a64fe8d97af2 100644 --- a/include/drm/display/drm_dp_helper.h +++ b/include/drm/display/drm_dp_helper.h @@ -251,6 +251,12 @@ drm_dp_channel_coding_supported(const u8 dpcd[DP_RECEIVER_CAP_SIZE]) return dpcd[DP_MAIN_LINK_CHANNEL_CODING] & DP_CAP_ANSI_8B10B; } +static inline bool +drm_dp_uhbr_channel_coding_supported(const u8 dpcd[DP_RECEIVER_CAP_SIZE]) +{ + return dpcd[DP_MAIN_LINK_CHANNEL_CODING] & DP_CAP_ANSI_128B132B; +} + static inline bool drm_dp_alternate_scrambler_reset_cap(const u8 dpcd[DP_RECEIVER_CAP_SIZE]) { From patchwork Tue Apr 16 22:10:07 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Imre Deak X-Patchwork-Id: 13632675 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id BD65CC4345F for ; Tue, 16 Apr 2024 22:09:57 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 2BFB0112EB7; Tue, 16 Apr 2024 22:09:56 +0000 (UTC) Authentication-Results: gabe.freedesktop.org; dkim=pass (2048-bit key; unprotected) header.d=intel.com header.i=@intel.com header.b="fm85RkDA"; dkim-atps=neutral Received: from mgamail.intel.com (mgamail.intel.com [192.198.163.10]) by gabe.freedesktop.org (Postfix) with ESMTPS id 678AE112EAE; Tue, 16 Apr 2024 22:09:48 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1713305388; x=1744841388; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=tcOTZvPluUWi3TlBWm1Rt6q+OAoeayjbbfJiJqcFrRg=; b=fm85RkDAT3hwoYlQqnTeBI3OeExOilzrXDzURGbPhA4st27vvG5Zou0A zw3PRKtw7w7siiXk6clDNjJlUwpbLc85MbYDqCS3FtC7Ji92y/wzyQjge c7wecxnIbfAJSREUWreD4nV767NpBIRsy5/rDIs3YZcMMSetKUQkIi+6h 4NvkCxUwRH7Y9JiwiviGic8fJvFr7EdUE1jw5Yrw492UBjSQn5vGZOAYA b+aFAQ/DguxTfZ4Bm6Hd7s1x6XSQeoE4z2BUM62r5mTBTiG3YbA68qiVk gNEneAQzK+LAV7BlYlzudHlQwC9JJKDaGrspOx7gjeuosHIWVxDPyLqjc w==; X-CSE-ConnectionGUID: UVMSU0VgR7iGElHFaqPCCA== X-CSE-MsgGUID: p+6Odq6cQLu49BP4uAbZtA== X-IronPort-AV: E=McAfee;i="6600,9927,11046"; a="20165176" X-IronPort-AV: E=Sophos;i="6.07,207,1708416000"; d="scan'208";a="20165176" Received: from fmviesa003.fm.intel.com ([10.60.135.143]) by fmvoesa104.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 16 Apr 2024 15:09:48 -0700 X-CSE-ConnectionGUID: bcK/CPCKSxSiY4Pfsgg8Yg== X-CSE-MsgGUID: jkaC6CYkSiOWF6qct3KZWg== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.07,207,1708416000"; d="scan'208";a="26965502" Received: from ideak-desk.fi.intel.com ([10.237.72.78]) by fmviesa003-auth.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 16 Apr 2024 15:09:47 -0700 From: Imre Deak To: intel-gfx@lists.freedesktop.org Cc: Lyude Paul , dri-devel@lists.freedesktop.org, Ankit Nautiyal , Maarten Lankhorst Subject: [PATCH v2 08/11] drm/dp_mst: Factor out drm_dp_mst_port_is_logical() Date: Wed, 17 Apr 2024 01:10:07 +0300 Message-ID: <20240416221010.376865-9-imre.deak@intel.com> X-Mailer: git-send-email 2.43.3 In-Reply-To: <20240416221010.376865-1-imre.deak@intel.com> References: <20240416221010.376865-1-imre.deak@intel.com> MIME-Version: 1.0 X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" Factor out a function to check if an MST port is logical, used by a follow-up i915 patch in the patchset. v2: Move drm_dp_mst_aux_for_parent() forward declaration to the next patch. (Ankit) Cc: Lyude Paul Cc: dri-devel@lists.freedesktop.org Reviewed-by: Ankit Nautiyal Acked-by: Maarten Lankhorst Signed-off-by: Imre Deak --- drivers/gpu/drm/display/drm_dp_mst_topology.c | 6 +++--- include/drm/display/drm_dp_mst_helper.h | 6 ++++++ 2 files changed, 9 insertions(+), 3 deletions(-) diff --git a/drivers/gpu/drm/display/drm_dp_mst_topology.c b/drivers/gpu/drm/display/drm_dp_mst_topology.c index c193be3577f7a..46b99d5fe0086 100644 --- a/drivers/gpu/drm/display/drm_dp_mst_topology.c +++ b/drivers/gpu/drm/display/drm_dp_mst_topology.c @@ -2274,7 +2274,7 @@ drm_dp_mst_port_add_connector(struct drm_dp_mst_branch *mstb, if (port->pdt != DP_PEER_DEVICE_NONE && drm_dp_mst_is_end_device(port->pdt, port->mcs) && - port->port_num >= DP_MST_LOGICAL_PORT_0) + drm_dp_mst_port_is_logical(port)) port->cached_edid = drm_edid_read_ddc(port->connector, &port->aux.ddc); @@ -4219,7 +4219,7 @@ drm_dp_mst_detect_port(struct drm_connector *connector, case DP_PEER_DEVICE_SST_SINK: ret = connector_status_connected; /* for logical ports - cache the EDID */ - if (port->port_num >= DP_MST_LOGICAL_PORT_0 && !port->cached_edid) + if (drm_dp_mst_port_is_logical(port) && !port->cached_edid) port->cached_edid = drm_edid_read_ddc(connector, &port->aux.ddc); break; case DP_PEER_DEVICE_DP_LEGACY_CONV: @@ -5983,7 +5983,7 @@ static bool drm_dp_mst_is_virtual_dpcd(struct drm_dp_mst_port *port) return false; /* Virtual DP Sink (Internal Display Panel) */ - if (port->port_num >= 8) + if (drm_dp_mst_port_is_logical(port)) return true; /* DP-to-HDMI Protocol Converter */ diff --git a/include/drm/display/drm_dp_mst_helper.h b/include/drm/display/drm_dp_mst_helper.h index cbcb49cb6a460..f00e32b0315d7 100644 --- a/include/drm/display/drm_dp_mst_helper.h +++ b/include/drm/display/drm_dp_mst_helper.h @@ -948,6 +948,12 @@ int __must_check drm_dp_mst_root_conn_atomic_check(struct drm_connector_state *n void drm_dp_mst_get_port_malloc(struct drm_dp_mst_port *port); void drm_dp_mst_put_port_malloc(struct drm_dp_mst_port *port); +static inline +bool drm_dp_mst_port_is_logical(struct drm_dp_mst_port *port) +{ + return port->port_num >= DP_MST_LOGICAL_PORT_0; +} + struct drm_dp_aux *drm_dp_mst_dsc_aux_for_port(struct drm_dp_mst_port *port); static inline struct drm_dp_mst_topology_state * From patchwork Tue Apr 16 22:10:08 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Imre Deak X-Patchwork-Id: 13632673 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 73407C04FF6 for ; Tue, 16 Apr 2024 22:09:56 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 6657F112EAD; Tue, 16 Apr 2024 22:09:55 +0000 (UTC) Authentication-Results: gabe.freedesktop.org; dkim=pass (2048-bit key; unprotected) header.d=intel.com header.i=@intel.com header.b="kcDhZYYj"; dkim-atps=neutral Received: from mgamail.intel.com (mgamail.intel.com [192.198.163.10]) by gabe.freedesktop.org (Postfix) with ESMTPS id 25B10112EAD; Tue, 16 Apr 2024 22:09:50 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1713305390; x=1744841390; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=9chYD/PbjE2mjvsyAXUzfis40R4bYbqDVget9kchoug=; b=kcDhZYYjdcFNKGtc2/nboyluX+lqR7Dx0mLQk+znqcXFi6JClh4lHGUc n1vZPpGZlbt54PauccjclDDJF14pxxAeF2KR3zcfR3qytBlnEhRdRlWRz MCndrEngZaxcRYafaLzjTKPIQST/BYI8LrTK/WRs44j78HhOa/jEYAQtZ 3M3tBNRm21dy0dhcY5j1/ANFZRRh9NqAJRYk0YqUuHfyJmJa6undVnQPs /HKmyQPzM7lDMtQaxzTpF/I/SzCVMIsIy+3N8M0efkMxD7ZD5WdBa1FCA U1DTvCBDKPmwtGHoygPnaWsOWZvi4+7S+3vZa5m8qvkABnlUeZ4irsJmh A==; X-CSE-ConnectionGUID: hU0lO7diRw2Hvo3dIXBtlQ== X-CSE-MsgGUID: DWKHjWxwRziQlZ9Xc0XoJw== X-IronPort-AV: E=McAfee;i="6600,9927,11046"; a="20165183" X-IronPort-AV: E=Sophos;i="6.07,207,1708416000"; d="scan'208";a="20165183" Received: from fmviesa003.fm.intel.com ([10.60.135.143]) by fmvoesa104.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 16 Apr 2024 15:09:50 -0700 X-CSE-ConnectionGUID: /69XeE08Rs+AEFMIo3jqUA== X-CSE-MsgGUID: 4a8tCrXGQ02YvEAheClqBQ== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.07,207,1708416000"; d="scan'208";a="26965507" Received: from ideak-desk.fi.intel.com ([10.237.72.78]) by fmviesa003-auth.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 16 Apr 2024 15:09:48 -0700 From: Imre Deak To: intel-gfx@lists.freedesktop.org Cc: Lyude Paul , dri-devel@lists.freedesktop.org, Ankit Nautiyal , Maarten Lankhorst Subject: [PATCH v2 09/11] drm/dp_mst: Add drm_dp_mst_aux_for_parent() Date: Wed, 17 Apr 2024 01:10:08 +0300 Message-ID: <20240416221010.376865-10-imre.deak@intel.com> X-Mailer: git-send-email 2.43.3 In-Reply-To: <20240416221010.376865-1-imre.deak@intel.com> References: <20240416221010.376865-1-imre.deak@intel.com> MIME-Version: 1.0 X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" Add a function to get the AUX device of the parent of an MST port, used by a follow-up i915 patch in the patchset. v2: Move drm_dp_mst_aux_for_parent() forward declaration to this patch (Ankit) Cc: Lyude Paul Cc: dri-devel@lists.freedesktop.org Reviewed-by: Ankit Nautiyal Acked-by: Maarten Lankhorst Signed-off-by: Imre Deak --- drivers/gpu/drm/display/drm_dp_mst_topology.c | 16 ++++++++++++++++ include/drm/display/drm_dp_mst_helper.h | 1 + 2 files changed, 17 insertions(+) diff --git a/drivers/gpu/drm/display/drm_dp_mst_topology.c b/drivers/gpu/drm/display/drm_dp_mst_topology.c index 46b99d5fe0086..3577786b5db2c 100644 --- a/drivers/gpu/drm/display/drm_dp_mst_topology.c +++ b/drivers/gpu/drm/display/drm_dp_mst_topology.c @@ -6010,6 +6010,22 @@ static bool drm_dp_mst_is_virtual_dpcd(struct drm_dp_mst_port *port) return false; } +/** + * drm_dp_mst_aux_for_parent() - Get the AUX device for an MST port's parent + * @port: MST port whose parent's AUX device is returned + * + * Return the AUX device for @port's parent or NULL if port's parent is the + * root port. + */ +struct drm_dp_aux *drm_dp_mst_aux_for_parent(struct drm_dp_mst_port *port) +{ + if (!port->parent || !port->parent->port_parent) + return NULL; + + return &port->parent->port_parent->aux; +} +EXPORT_SYMBOL(drm_dp_mst_aux_for_parent); + /** * drm_dp_mst_dsc_aux_for_port() - Find the correct aux for DSC * @port: The port to check. A leaf of the MST tree with an attached display. diff --git a/include/drm/display/drm_dp_mst_helper.h b/include/drm/display/drm_dp_mst_helper.h index f00e32b0315d7..3546b58a121bc 100644 --- a/include/drm/display/drm_dp_mst_helper.h +++ b/include/drm/display/drm_dp_mst_helper.h @@ -954,6 +954,7 @@ bool drm_dp_mst_port_is_logical(struct drm_dp_mst_port *port) return port->port_num >= DP_MST_LOGICAL_PORT_0; } +struct drm_dp_aux *drm_dp_mst_aux_for_parent(struct drm_dp_mst_port *port); struct drm_dp_aux *drm_dp_mst_dsc_aux_for_port(struct drm_dp_mst_port *port); static inline struct drm_dp_mst_topology_state * From patchwork Tue Apr 16 22:10:09 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Imre Deak X-Patchwork-Id: 13632674 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 35A0BC05023 for ; Tue, 16 Apr 2024 22:09:57 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 69545112EB6; Tue, 16 Apr 2024 22:09:55 +0000 (UTC) Authentication-Results: gabe.freedesktop.org; dkim=pass (2048-bit key; unprotected) header.d=intel.com header.i=@intel.com header.b="aBexomL9"; dkim-atps=neutral Received: from mgamail.intel.com (mgamail.intel.com [192.198.163.10]) by gabe.freedesktop.org (Postfix) with ESMTPS id 3FEAE112EB3 for ; Tue, 16 Apr 2024 22:09:51 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1713305391; x=1744841391; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=Zn9mXI3eap1zHUrsM9ldLuWMh0IbyhAzNOI5QiJy1cs=; b=aBexomL9IFvJ6wknabuD2FN930ecz62kjy7cBjvfjaMdTOl1PpoGkNUm qqJxE7r7Z9sBijiQ1KAuifHMyte/YuOCgdxq49fMIlJjWN3AoVGP8M8La oxAH+mAKAbyfvuJ/V+Wrldi/hwYECKfHVac0Z+UhMuZjURderNwzhJRyl eUQZWJEsoP0yEMEHtohWGyNec+B4Spy8/n6jXTus1dGAmywAqtqPLeYGq gPOQsNWoMXkNown8GggDGnNzmeiFKasWfJwNFUY/I2h4NbeXssZpsYvKZ 6+KKvzUdHFuQ95RA5ck6pjIrrTfgy6ym9KwhmXOrlZnIX6dDdoBjF4Ahd g==; X-CSE-ConnectionGUID: pmxYMa8fSIOWaZiKO1zH6g== X-CSE-MsgGUID: DaCTcABLRumwyhiW1Q/3yg== X-IronPort-AV: E=McAfee;i="6600,9927,11046"; a="20165188" X-IronPort-AV: E=Sophos;i="6.07,207,1708416000"; d="scan'208";a="20165188" Received: from fmviesa003.fm.intel.com ([10.60.135.143]) by fmvoesa104.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 16 Apr 2024 15:09:51 -0700 X-CSE-ConnectionGUID: Ykb3P8g8Thiaky7flarG0Q== X-CSE-MsgGUID: y16oEE1GQ+yoezJHKTXlYg== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.07,207,1708416000"; d="scan'208";a="26965513" Received: from ideak-desk.fi.intel.com ([10.237.72.78]) by fmviesa003-auth.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 16 Apr 2024 15:09:50 -0700 From: Imre Deak To: intel-gfx@lists.freedesktop.org Cc: Ankit Nautiyal Subject: [PATCH v2 10/11] drm/i915/dp_mst: Make HBLANK expansion quirk work for logical ports Date: Wed, 17 Apr 2024 01:10:09 +0300 Message-ID: <20240416221010.376865-11-imre.deak@intel.com> X-Mailer: git-send-email 2.43.3 In-Reply-To: <20240416221010.376865-1-imre.deak@intel.com> References: <20240416221010.376865-1-imre.deak@intel.com> MIME-Version: 1.0 X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" The DPCD OUI of the logical port on a Dell UHBR monitor - on which the AUX device is used to enable DSC - is all 0. To detect if the HBLANK expansion quirk is required for this monitor use the OUI of the port's parent instead. Since in the above case the DPCD of both the logical port and the parent port reports being a sink device (vs. branch device) type, read the proper sink/branch OUI based on the DPCD device type. This is required by a follow-up patch enabling the quirk for the above Dell monitor. Reviewed-by: Ankit Nautiyal Signed-off-by: Imre Deak --- drivers/gpu/drm/i915/display/intel_dp_mst.c | 22 +++++++++++++++------ 1 file changed, 16 insertions(+), 6 deletions(-) diff --git a/drivers/gpu/drm/i915/display/intel_dp_mst.c b/drivers/gpu/drm/i915/display/intel_dp_mst.c index 89ee80a357140..fb5e167c3c659 100644 --- a/drivers/gpu/drm/i915/display/intel_dp_mst.c +++ b/drivers/gpu/drm/i915/display/intel_dp_mst.c @@ -1577,23 +1577,33 @@ intel_dp_mst_read_decompression_port_dsc_caps(struct intel_dp *intel_dp, static bool detect_dsc_hblank_expansion_quirk(const struct intel_connector *connector) { struct drm_i915_private *i915 = to_i915(connector->base.dev); + struct drm_dp_aux *aux = connector->dp.dsc_decompression_aux; struct drm_dp_desc desc; u8 dpcd[DP_RECEIVER_CAP_SIZE]; - if (!connector->dp.dsc_decompression_aux) + if (!aux) return false; - if (drm_dp_read_desc(connector->dp.dsc_decompression_aux, - &desc, true) < 0) + /* + * A logical port's OUI (at least for affected sinks) is all 0, so + * instead of that the parent port's OUI is used for identification. + */ + if (drm_dp_mst_port_is_logical(connector->port)) { + aux = drm_dp_mst_aux_for_parent(connector->port); + if (!aux) + aux = &connector->mst_port->aux; + } + + if (drm_dp_read_dpcd_caps(aux, dpcd) < 0) + return false; + + if (drm_dp_read_desc(aux, &desc, drm_dp_is_branch(dpcd)) < 0) return false; if (!drm_dp_has_quirk(&desc, DP_DPCD_QUIRK_HBLANK_EXPANSION_REQUIRES_DSC)) return false; - if (drm_dp_read_dpcd_caps(connector->dp.dsc_decompression_aux, dpcd) < 0) - return false; - if (!(dpcd[DP_RECEIVE_PORT_0_CAP_0] & DP_HBLANK_EXPANSION_CAPABLE)) return false; From patchwork Tue Apr 16 22:10:10 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Imre Deak X-Patchwork-Id: 13632676 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 3D826C05052 for ; Tue, 16 Apr 2024 22:09:58 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 40158112EB9; Tue, 16 Apr 2024 22:09:56 +0000 (UTC) Authentication-Results: gabe.freedesktop.org; dkim=pass (2048-bit key; unprotected) header.d=intel.com header.i=@intel.com header.b="Ts+MgW0q"; dkim-atps=neutral Received: from mgamail.intel.com (mgamail.intel.com [192.198.163.10]) by gabe.freedesktop.org (Postfix) with ESMTPS id D5C6F112EB3; Tue, 16 Apr 2024 22:09:52 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1713305393; x=1744841393; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=xClQFpiUgrpWK+9cqOXOuA9IExFysUih7No0me29b9o=; b=Ts+MgW0q01fb13mBb8/Q5RwLQ9dKb87mb2Scgrk4GFPfs0Pn4GovdwRC D78X41PjNvpa9OXeAPWK2cGwzbDzzTmjbYG1rpD/xFWNGxH3fXqL9CV7e CiK9xhHZRj0pY+4v8dkGQXmgNgyWFy/H1UHWRTtl2YMrysq3673Ty+E0g RDJkDkyS5lnLbpjyY+tKFeMqY6g7M865/UBb4rSqT+ObviiotqGIH/d1T g3tUh/DREp94weXsk0c26SkV+e464o9ZVwkS179BiFqmvpoEL8a+8eYZu /1bwcR2LHpRcOvtaVN3C+zMMEPJryaKxVCXPMPun0nTidIsQ3QbWf3Gw+ w==; X-CSE-ConnectionGUID: ZqBJaRkRScmG3K6/d3cpBg== X-CSE-MsgGUID: SQ/YzsTXTtSb3csX37HFbw== X-IronPort-AV: E=McAfee;i="6600,9927,11046"; a="20165189" X-IronPort-AV: E=Sophos;i="6.07,207,1708416000"; d="scan'208";a="20165189" Received: from fmviesa003.fm.intel.com ([10.60.135.143]) by fmvoesa104.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 16 Apr 2024 15:09:53 -0700 X-CSE-ConnectionGUID: nFRXkvL4RKC2cr5kfdNv3w== X-CSE-MsgGUID: mP8JiiNdQxicQiARzTTU6Q== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.07,207,1708416000"; d="scan'208";a="26965517" Received: from ideak-desk.fi.intel.com ([10.237.72.78]) by fmviesa003-auth.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 16 Apr 2024 15:09:51 -0700 From: Imre Deak To: intel-gfx@lists.freedesktop.org Cc: dri-devel@lists.freedesktop.org, Ankit Nautiyal , Khaled Almahallawy Subject: [PATCH v2 11/11] drm/i915/dp_mst: Enable HBLANK expansion quirk for UHBR rates Date: Wed, 17 Apr 2024 01:10:10 +0300 Message-ID: <20240416221010.376865-12-imre.deak@intel.com> X-Mailer: git-send-email 2.43.3 In-Reply-To: <20240416221010.376865-1-imre.deak@intel.com> References: <20240416221010.376865-1-imre.deak@intel.com> MIME-Version: 1.0 X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" Enabling the 5k@60Hz uncompressed mode on the MediaTek/Dell U3224KBA monitor results in a blank screen, at least on MTL platforms on UHBR link rates with some (<30) uncompressed bpp values. Enabling compression fixes the problem, so do that for now. Windows enables DSC always if the sink supports it and forcing it to enable the mode without compression leads to the same problem above (which suggests a panel issue with uncompressed mode). The same 5k mode on non-UHBR link rates is not affected and lower resolution modes are not affected either. The problem is similar to the one fixed by the HBLANK expansion quirk on Synaptics hubs, with the difference that the problematic mode has a longer HBLANK duration. Also the monitor doesn't report supporting HBLANK expansion; either its internal MST hub does the expansion internally - similarly to the Synaptics hub - or the issue has another root cause, but still related to the mode's short HBLANK duration. Enable the quirk for the monitor adjusting the detection for the above differences. Cc: dri-devel@lists.freedesktop.org Reviewed-by: Ankit Nautiyal Tested-by: Khaled Almahallawy Signed-off-by: Imre Deak --- drivers/gpu/drm/display/drm_dp_helper.c | 2 ++ drivers/gpu/drm/i915/display/intel_dp_mst.c | 22 +++++++++++++++++---- 2 files changed, 20 insertions(+), 4 deletions(-) diff --git a/drivers/gpu/drm/display/drm_dp_helper.c b/drivers/gpu/drm/display/drm_dp_helper.c index 023907da98581..79a615667aab1 100644 --- a/drivers/gpu/drm/display/drm_dp_helper.c +++ b/drivers/gpu/drm/display/drm_dp_helper.c @@ -2281,6 +2281,8 @@ static const struct dpcd_quirk dpcd_quirk_list[] = { { OUI(0x90, 0xCC, 0x24), DEVICE_ID_ANY, true, BIT(DP_DPCD_QUIRK_DSC_WITHOUT_VIRTUAL_DPCD) }, /* Synaptics DP1.4 MST hubs require DSC for some modes on which it applies HBLANK expansion. */ { OUI(0x90, 0xCC, 0x24), DEVICE_ID_ANY, true, BIT(DP_DPCD_QUIRK_HBLANK_EXPANSION_REQUIRES_DSC) }, + /* MediaTek panels (at least in U3224KBA) require DSC for modes with a short HBLANK on UHBR links. */ + { OUI(0x00, 0x0C, 0xE7), DEVICE_ID_ANY, false, BIT(DP_DPCD_QUIRK_HBLANK_EXPANSION_REQUIRES_DSC) }, /* Apple MacBookPro 2017 15 inch eDP Retina panel reports too low DP_MAX_LINK_RATE */ { OUI(0x00, 0x10, 0xfa), DEVICE_ID(101, 68, 21, 101, 98, 97), false, BIT(DP_DPCD_QUIRK_CAN_DO_MAX_LINK_RATE_3_24_GBPS) }, }; diff --git a/drivers/gpu/drm/i915/display/intel_dp_mst.c b/drivers/gpu/drm/i915/display/intel_dp_mst.c index fb5e167c3c659..71b01f7631919 100644 --- a/drivers/gpu/drm/i915/display/intel_dp_mst.c +++ b/drivers/gpu/drm/i915/display/intel_dp_mst.c @@ -421,15 +421,22 @@ static int mode_hblank_period_ns(const struct drm_display_mode *mode) static bool hblank_expansion_quirk_needs_dsc(const struct intel_connector *connector, - const struct intel_crtc_state *crtc_state) + const struct intel_crtc_state *crtc_state, + const struct link_config_limits *limits) { const struct drm_display_mode *adjusted_mode = &crtc_state->hw.adjusted_mode; + bool is_uhbr_sink = connector->mst_port && + drm_dp_uhbr_channel_coding_supported(connector->mst_port->dpcd); + int hblank_limit = is_uhbr_sink ? 500 : 300; if (!connector->dp.dsc_hblank_expansion_quirk) return false; - if (mode_hblank_period_ns(adjusted_mode) > 300) + if (is_uhbr_sink && !drm_dp_is_uhbr_rate(limits->max_rate)) + return false; + + if (mode_hblank_period_ns(adjusted_mode) > hblank_limit) return false; return true; @@ -445,7 +452,7 @@ adjust_limits_for_dsc_hblank_expansion_quirk(const struct intel_connector *conne const struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); int min_bpp_x16 = limits->link.min_bpp_x16; - if (!hblank_expansion_quirk_needs_dsc(connector, crtc_state)) + if (!hblank_expansion_quirk_needs_dsc(connector, crtc_state, limits)) return true; if (!dsc) { @@ -1604,7 +1611,14 @@ static bool detect_dsc_hblank_expansion_quirk(const struct intel_connector *conn DP_DPCD_QUIRK_HBLANK_EXPANSION_REQUIRES_DSC)) return false; - if (!(dpcd[DP_RECEIVE_PORT_0_CAP_0] & DP_HBLANK_EXPANSION_CAPABLE)) + /* + * UHBR (MST sink) devices requiring this quirk doesn't advertise the + * HBLANK expansion support. Presuming that they perform HBLANK + * expansion internally, or are affected by this issue on modes with a + * short HBLANK for other reasons. + */ + if (!drm_dp_uhbr_channel_coding_supported(dpcd) && + !(dpcd[DP_RECEIVE_PORT_0_CAP_0] & DP_HBLANK_EXPANSION_CAPABLE)) return false; drm_dbg_kms(&i915->drm,