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Reviewed-by: Rob Herring Signed-off-by: Sibi Sankar --- v2: * Pickup Rb from Dimitry. .../bindings/mailbox/qcom,cpucp-mbox.yaml | 49 +++++++++++++++++++ 1 file changed, 49 insertions(+) create mode 100644 Documentation/devicetree/bindings/mailbox/qcom,cpucp-mbox.yaml diff --git a/Documentation/devicetree/bindings/mailbox/qcom,cpucp-mbox.yaml b/Documentation/devicetree/bindings/mailbox/qcom,cpucp-mbox.yaml new file mode 100644 index 000000000000..491b0a05e630 --- /dev/null +++ b/Documentation/devicetree/bindings/mailbox/qcom,cpucp-mbox.yaml @@ -0,0 +1,49 @@ +# SPDX-License-Identifier: GPL-2.0 OR BSD-2-Clause +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/mailbox/qcom,cpucp-mbox.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Qualcomm Technologies, Inc. CPUCP Mailbox Controller + +maintainers: + - Sibi Sankar + +description: + The CPUSS Control Processor (CPUCP) mailbox controller enables communication + between AP and CPUCP by acting as a doorbell between them. + +properties: + compatible: + items: + - const: qcom,x1e80100-cpucp-mbox + + reg: + items: + - description: CPUCP rx register region + - description: CPUCP tx register region + + interrupts: + maxItems: 1 + + "#mbox-cells": + const: 1 + +required: + - compatible + - reg + - interrupts + - "#mbox-cells" + +additionalProperties: false + +examples: + - | + #include + + mailbox@17430000 { + compatible = "qcom,x1e80100-cpucp-mbox"; + reg = <0x17430000 0x10000>, <0x18830000 0x10000>; + interrupts = ; + #mbox-cells = <1>; + }; From patchwork Wed Apr 17 13:28:53 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Sibi Sankar X-Patchwork-Id: 13633367 Received: from mx0b-0031df01.pphosted.com (mx0b-0031df01.pphosted.com [205.220.180.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 888BC1420D5; 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Wed, 17 Apr 2024 13:29:34 +0000 (GMT) Received: from nalasex01a.na.qualcomm.com (nalasex01a.na.qualcomm.com [10.47.209.196]) by NALASPPMTA03.qualcomm.com (8.17.1.5/8.17.1.5) with ESMTPS id 43HDTXYY010282 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Wed, 17 Apr 2024 13:29:33 GMT Received: from hu-sibis-blr.qualcomm.com (10.80.80.8) by nalasex01a.na.qualcomm.com (10.47.209.196) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1544.9; Wed, 17 Apr 2024 06:29:28 -0700 From: Sibi Sankar To: , , , , , , , CC: , , , , , , , , , Subject: [PATCH V3 2/5] mailbox: Add support for QTI CPUCP mailbox controller Date: Wed, 17 Apr 2024 18:58:53 +0530 Message-ID: <20240417132856.1106250-3-quic_sibis@quicinc.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240417132856.1106250-1-quic_sibis@quicinc.com> References: <20240417132856.1106250-1-quic_sibis@quicinc.com> Precedence: bulk X-Mailing-List: linux-arm-msm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-ClientProxiedBy: nasanex01a.na.qualcomm.com (10.52.223.231) To nalasex01a.na.qualcomm.com (10.47.209.196) X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-ORIG-GUID: nJ_zG3H_cPNXUvbgmkmIwfB5ZscQGG-F X-Proofpoint-GUID: nJ_zG3H_cPNXUvbgmkmIwfB5ZscQGG-F X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.272,Aquarius:18.0.1011,Hydra:6.0.619,FMLib:17.11.176.26 definitions=2024-04-17_10,2024-04-16_01,2023-05-22_02 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 mlxscore=0 suspectscore=0 bulkscore=0 lowpriorityscore=0 mlxlogscore=999 priorityscore=1501 spamscore=0 phishscore=0 clxscore=1015 malwarescore=0 impostorscore=0 adultscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.19.0-2404010003 definitions=main-2404170092 Add support for CPUSS Control Processor (CPUCP) mailbox controller, this driver enables communication between AP and CPUCP by acting as a doorbell between them. Signed-off-by: Sibi Sankar Reviewed-by: Dmitry Baryshkov --- v2: * Use BIT() instead of manual shift. [Dmitry] * Define RX_MBOX_CMD to account for chan calculation. [Dmitry] * Clear the bit instead of the entire status within the spinlock. [Dmitry] * Use dev_err_probe instead. [Dmitry] * Drop superfluous error message while handling errors from get_irq. [Dmitry] * Use devm_mbox_controller_register and drop remove path. [Dmitry] * Define TX_MBOX_CMD to account for chan calculation. * Use cpucp->dev in probe path for conformity. drivers/mailbox/Kconfig | 8 ++ drivers/mailbox/Makefile | 2 + drivers/mailbox/qcom-cpucp-mbox.c | 188 ++++++++++++++++++++++++++++++ 3 files changed, 198 insertions(+) create mode 100644 drivers/mailbox/qcom-cpucp-mbox.c diff --git a/drivers/mailbox/Kconfig b/drivers/mailbox/Kconfig index 42940108a187..23741a6f054e 100644 --- a/drivers/mailbox/Kconfig +++ b/drivers/mailbox/Kconfig @@ -273,6 +273,14 @@ config SPRD_MBOX to send message between application processors and MCU. Say Y here if you want to build the Spreatrum mailbox controller driver. +config QCOM_CPUCP_MBOX + tristate "Qualcomm Technologies, Inc. CPUCP mailbox driver" + depends on ARCH_QCOM || COMPILE_TEST + help + Qualcomm Technologies, Inc. CPUSS Control Processor (CPUCP) mailbox + controller driver enables communication between AP and CPUCP. Say + Y here if you want to build this driver. + config QCOM_IPCC tristate "Qualcomm Technologies, Inc. IPCC driver" depends on ARCH_QCOM || COMPILE_TEST diff --git a/drivers/mailbox/Makefile b/drivers/mailbox/Makefile index 18793e6caa2f..53b512800bde 100644 --- a/drivers/mailbox/Makefile +++ b/drivers/mailbox/Makefile @@ -59,4 +59,6 @@ obj-$(CONFIG_SUN6I_MSGBOX) += sun6i-msgbox.o obj-$(CONFIG_SPRD_MBOX) += sprd-mailbox.o +obj-$(CONFIG_QCOM_CPUCP_MBOX) += qcom-cpucp-mbox.o + obj-$(CONFIG_QCOM_IPCC) += qcom-ipcc.o diff --git a/drivers/mailbox/qcom-cpucp-mbox.c b/drivers/mailbox/qcom-cpucp-mbox.c new file mode 100644 index 000000000000..059eb25f217c --- /dev/null +++ b/drivers/mailbox/qcom-cpucp-mbox.c @@ -0,0 +1,188 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Copyright (c) 2024, The Linux Foundation. All rights reserved. + */ + +#include +#include +#include +#include +#include +#include + +#define APSS_CPUCP_IPC_CHAN_SUPPORTED 3 +#define APSS_CPUCP_MBOX_CMD_OFF 0x4 + +/* Tx Registers */ +#define APSS_CPUCP_TX_MBOX_IDR 0 +#define APSS_CPUCP_TX_MBOX_CMD(i) (0x100 + ((i) * 8)) + +/* Rx Registers */ +#define APSS_CPUCP_RX_MBOX_IDR 0 +#define APSS_CPUCP_RX_MBOX_CMD(i) (0x100 + ((i) * 8)) +#define APSS_CPUCP_RX_MBOX_MAP 0x4000 +#define APSS_CPUCP_RX_MBOX_STAT 0x4400 +#define APSS_CPUCP_RX_MBOX_CLEAR 0x4800 +#define APSS_CPUCP_RX_MBOX_EN 0x4C00 +#define APSS_CPUCP_RX_MBOX_CMD_MASK 0xFFFFFFFFFFFFFFFF + +/** + * struct qcom_cpucp_mbox - Holder for the mailbox driver + * @chans: The mailbox channel + * @mbox: The mailbox controller + * @tx_base: Base address of the CPUCP tx registers + * @rx_base: Base address of the CPUCP rx registers + * @dev: Device associated with this instance + * @irq: CPUCP to AP irq + */ +struct qcom_cpucp_mbox { + struct mbox_chan chans[APSS_CPUCP_IPC_CHAN_SUPPORTED]; + struct mbox_controller mbox; + void __iomem *tx_base; + void __iomem *rx_base; + struct device *dev; + int irq; +}; + +static inline int channel_number(struct mbox_chan *chan) +{ + return chan - chan->mbox->chans; +} + +static irqreturn_t qcom_cpucp_mbox_irq_fn(int irq, void *data) +{ + struct qcom_cpucp_mbox *cpucp = data; + struct mbox_chan *chan; + unsigned long flags; + u64 status; + u32 val; + int i; + + status = readq(cpucp->rx_base + APSS_CPUCP_RX_MBOX_STAT); + + for (i = 0; i < APSS_CPUCP_IPC_CHAN_SUPPORTED; i++) { + val = 0; + if (status & BIT(i)) { + val = readl(cpucp->rx_base + APSS_CPUCP_RX_MBOX_CMD(i) + APSS_CPUCP_MBOX_CMD_OFF); + chan = &cpucp->chans[i]; + spin_lock_irqsave(&chan->lock, flags); + if (chan->cl) + mbox_chan_received_data(chan, &val); + writeq(BIT(i), cpucp->rx_base + APSS_CPUCP_RX_MBOX_CLEAR); + spin_unlock_irqrestore(&chan->lock, flags); + } + } + + return IRQ_HANDLED; +} + +static int qcom_cpucp_mbox_startup(struct mbox_chan *chan) +{ + struct qcom_cpucp_mbox *cpucp = container_of(chan->mbox, struct qcom_cpucp_mbox, mbox); + unsigned long chan_id = channel_number(chan); + u64 val; + + val = readq(cpucp->rx_base + APSS_CPUCP_RX_MBOX_EN); + val |= BIT(chan_id); + writeq(val, cpucp->rx_base + APSS_CPUCP_RX_MBOX_EN); + + return 0; +} + +static void qcom_cpucp_mbox_shutdown(struct mbox_chan *chan) +{ + struct qcom_cpucp_mbox *cpucp = container_of(chan->mbox, struct qcom_cpucp_mbox, mbox); + unsigned long chan_id = channel_number(chan); + u64 val; + + val = readq(cpucp->rx_base + APSS_CPUCP_RX_MBOX_EN); + val &= ~BIT(chan_id); + writeq(val, cpucp->rx_base + APSS_CPUCP_RX_MBOX_EN); +} + +static int qcom_cpucp_mbox_send_data(struct mbox_chan *chan, void *data) +{ + struct qcom_cpucp_mbox *cpucp = container_of(chan->mbox, struct qcom_cpucp_mbox, mbox); + unsigned long chan_id = channel_number(chan); + u32 *val = data; + + writel(*val, cpucp->tx_base + APSS_CPUCP_TX_MBOX_CMD(chan_id) + APSS_CPUCP_MBOX_CMD_OFF); + + return 0; +} + +static const struct mbox_chan_ops qcom_cpucp_mbox_chan_ops = { + .startup = qcom_cpucp_mbox_startup, + .send_data = qcom_cpucp_mbox_send_data, + .shutdown = qcom_cpucp_mbox_shutdown +}; + +static int qcom_cpucp_mbox_probe(struct platform_device *pdev) +{ + struct qcom_cpucp_mbox *cpucp; + struct mbox_controller *mbox; + int ret; + + cpucp = devm_kzalloc(&pdev->dev, sizeof(*cpucp), GFP_KERNEL); + if (!cpucp) + return -ENOMEM; + + cpucp->dev = &pdev->dev; + + cpucp->rx_base = devm_of_iomap(cpucp->dev, cpucp->dev->of_node, 0, NULL); + if (IS_ERR(cpucp->rx_base)) + return PTR_ERR(cpucp->rx_base); + + cpucp->tx_base = devm_of_iomap(cpucp->dev, cpucp->dev->of_node, 1, NULL); + if (IS_ERR(cpucp->tx_base)) + return PTR_ERR(cpucp->tx_base); + + writeq(0, cpucp->rx_base + APSS_CPUCP_RX_MBOX_EN); + writeq(0, cpucp->rx_base + APSS_CPUCP_RX_MBOX_CLEAR); + writeq(0, cpucp->rx_base + APSS_CPUCP_RX_MBOX_MAP); + + cpucp->irq = platform_get_irq(pdev, 0); + if (cpucp->irq < 0) + return cpucp->irq; + + ret = devm_request_irq(cpucp->dev, cpucp->irq, qcom_cpucp_mbox_irq_fn, + IRQF_TRIGGER_HIGH, "apss_cpucp_mbox", cpucp); + if (ret < 0) + return dev_err_probe(cpucp->dev, ret, "Failed to register irq: %d\n", cpucp->irq); + + writeq(APSS_CPUCP_RX_MBOX_CMD_MASK, cpucp->rx_base + APSS_CPUCP_RX_MBOX_MAP); + + mbox = &cpucp->mbox; + mbox->dev = cpucp->dev; + mbox->num_chans = APSS_CPUCP_IPC_CHAN_SUPPORTED; + mbox->chans = cpucp->chans; + mbox->ops = &qcom_cpucp_mbox_chan_ops; + mbox->txdone_irq = false; + mbox->txdone_poll = false; + + ret = devm_mbox_controller_register(cpucp->dev, mbox); + if (ret) + return dev_err_probe(cpucp->dev, ret, "Failed to create mailbox\n"); + + platform_set_drvdata(pdev, cpucp); + + return 0; +} + +static const struct of_device_id qcom_cpucp_mbox_of_match[] = { + { .compatible = "qcom,x1e80100-cpucp-mbox"}, + {} +}; +MODULE_DEVICE_TABLE(of, qcom_cpucp_mbox_of_match); + +static struct platform_driver qcom_cpucp_mbox_driver = { + .probe = qcom_cpucp_mbox_probe, + .driver = { + .name = "qcom_cpucp_mbox", + .of_match_table = qcom_cpucp_mbox_of_match, + }, +}; +module_platform_driver(qcom_cpucp_mbox_driver); + +MODULE_DESCRIPTION("QTI CPUCP MBOX Driver"); +MODULE_LICENSE("GPL"); From patchwork Wed Apr 17 13:28:54 2024 Content-Type: text/plain; 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Reviewed-by: Dmitry Baryshkov Signed-off-by: Sibi Sankar --- v2: * Pickup Rb from Dimitry. arch/arm64/boot/dts/qcom/x1e80100.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/qcom/x1e80100.dtsi b/arch/arm64/boot/dts/qcom/x1e80100.dtsi index f5a3b39ae70e..28f65296781d 100644 --- a/arch/arm64/boot/dts/qcom/x1e80100.dtsi +++ b/arch/arm64/boot/dts/qcom/x1e80100.dtsi @@ -4949,7 +4949,7 @@ apps_smmu: iommu@15000000 { intc: interrupt-controller@17000000 { compatible = "arm,gic-v3"; reg = <0 0x17000000 0 0x10000>, /* GICD */ - <0 0x17080000 0 0x480000>; /* GICR * 12 */ + <0 0x17080000 0 0x380000>; /* GICR * 12 */ interrupts = ; From patchwork Wed Apr 17 13:28:55 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Sibi Sankar X-Patchwork-Id: 13633369 Received: from mx0a-0031df01.pphosted.com (mx0a-0031df01.pphosted.com [205.220.168.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 00E8014265A; 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Signed-off-by: Sibi Sankar --- v2: * Rename sram sub-nodes according to schema. [Dmitry] arch/arm64/boot/dts/qcom/x1e80100.dtsi | 26 ++++++++++++++++++++++++++ 1 file changed, 26 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/x1e80100.dtsi b/arch/arm64/boot/dts/qcom/x1e80100.dtsi index 28f65296781d..f40e95d49370 100644 --- a/arch/arm64/boot/dts/qcom/x1e80100.dtsi +++ b/arch/arm64/boot/dts/qcom/x1e80100.dtsi @@ -4974,6 +4974,13 @@ gic_its: msi-controller@17040000 { }; }; + cpucp_mbox: mailbox@17430000 { + compatible = "qcom,x1e80100-cpucp-mbox"; + reg = <0 0x17430000 0 0x10000>, <0 0x18830000 0 0x10000>; + interrupts = ; + #mbox-cells = <1>; + }; + apps_rsc: rsc@17500000 { compatible = "qcom,rpmh-rsc"; reg = <0 0x17500000 0 0x10000>, @@ -5157,6 +5164,25 @@ frame@1780d000 { }; }; + sram: sram@18b4e000 { + compatible = "mmio-sram"; + reg = <0x0 0x18b4e000 0x0 0x400>; + + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x0 0x18b4e000 0x400>; + + cpu_scp_lpri0: scp-sram-section@0 { + compatible = "arm,scmi-shmem"; + reg = <0x0 0x200>; + }; + + cpu_scp_lpri1: scp-sram-section@200 { + compatible = "arm,scmi-shmem"; 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Wed, 17 Apr 2024 13:29:50 GMT Received: from hu-sibis-blr.qualcomm.com (10.80.80.8) by nalasex01a.na.qualcomm.com (10.47.209.196) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1544.9; Wed, 17 Apr 2024 06:29:45 -0700 From: Sibi Sankar To: , , , , , , , CC: , , , , , , , , , Subject: [PATCH V3 5/5] arm64: dts: qcom: x1e80100: Enable cpufreq Date: Wed, 17 Apr 2024 18:58:56 +0530 Message-ID: <20240417132856.1106250-6-quic_sibis@quicinc.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240417132856.1106250-1-quic_sibis@quicinc.com> References: <20240417132856.1106250-1-quic_sibis@quicinc.com> Precedence: bulk X-Mailing-List: linux-arm-msm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-ClientProxiedBy: nasanex01a.na.qualcomm.com (10.52.223.231) To nalasex01a.na.qualcomm.com (10.47.209.196) X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-GUID: LzxiClJtJvjj2sEzTLuKWkyHZQI9jsFa X-Proofpoint-ORIG-GUID: LzxiClJtJvjj2sEzTLuKWkyHZQI9jsFa X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.272,Aquarius:18.0.1011,Hydra:6.0.619,FMLib:17.11.176.26 definitions=2024-04-17_10,2024-04-16_01,2023-05-22_02 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 bulkscore=0 mlxscore=0 suspectscore=0 priorityscore=1501 adultscore=0 malwarescore=0 phishscore=0 spamscore=0 impostorscore=0 clxscore=1015 lowpriorityscore=0 mlxlogscore=948 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.19.0-2404010003 definitions=main-2404170093 Enable cpufreq on X1E80100 SoCs through the SCMI perf protocol node. Signed-off-by: Sibi Sankar --- v2: * Use power-domain instead of clocks. [Sudeep/Ulf] arch/arm64/boot/dts/qcom/x1e80100.dtsi | 63 ++++++++++++++++---------- 1 file changed, 39 insertions(+), 24 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/x1e80100.dtsi b/arch/arm64/boot/dts/qcom/x1e80100.dtsi index f40e95d49370..42bbe58dfbf9 100644 --- a/arch/arm64/boot/dts/qcom/x1e80100.dtsi +++ b/arch/arm64/boot/dts/qcom/x1e80100.dtsi @@ -69,8 +69,8 @@ CPU0: cpu@0 { reg = <0x0 0x0>; enable-method = "psci"; next-level-cache = <&L2_0>; - power-domains = <&CPU_PD0>; - power-domain-names = "psci"; + power-domains = <&CPU_PD0>, <&scmi_dvfs 0>; + power-domain-names = "psci", "perf"; cpu-idle-states = <&CLUSTER_C4>; L2_0: l2-cache { @@ -86,8 +86,8 @@ CPU1: cpu@100 { reg = <0x0 0x100>; enable-method = "psci"; next-level-cache = <&L2_0>; - power-domains = <&CPU_PD1>; - power-domain-names = "psci"; + power-domains = <&CPU_PD1>, <&scmi_dvfs 0>; + power-domain-names = "psci", "perf"; cpu-idle-states = <&CLUSTER_C4>; }; @@ -97,8 +97,8 @@ CPU2: cpu@200 { reg = <0x0 0x200>; enable-method = "psci"; next-level-cache = <&L2_0>; - power-domains = <&CPU_PD2>; - power-domain-names = "psci"; + power-domains = <&CPU_PD2>, <&scmi_dvfs 0>; + power-domain-names = "psci", "perf"; cpu-idle-states = <&CLUSTER_C4>; }; @@ -108,8 +108,8 @@ CPU3: cpu@300 { reg = <0x0 0x300>; enable-method = "psci"; next-level-cache = <&L2_0>; - power-domains = <&CPU_PD3>; - power-domain-names = "psci"; + power-domains = <&CPU_PD3>, <&scmi_dvfs 0>; + power-domain-names = "psci", "perf"; cpu-idle-states = <&CLUSTER_C4>; }; @@ -119,8 +119,8 @@ CPU4: cpu@10000 { reg = <0x0 0x10000>; enable-method = "psci"; next-level-cache = <&L2_1>; - power-domains = <&CPU_PD4>; - power-domain-names = "psci"; + power-domains = <&CPU_PD4>, <&scmi_dvfs 1>; + power-domain-names = "psci", "perf"; cpu-idle-states = <&CLUSTER_C4>; L2_1: l2-cache { @@ -136,8 +136,8 @@ CPU5: cpu@10100 { reg = <0x0 0x10100>; enable-method = "psci"; next-level-cache = <&L2_1>; - power-domains = <&CPU_PD5>; - power-domain-names = "psci"; + power-domains = <&CPU_PD5>, <&scmi_dvfs 1>; + power-domain-names = "psci", "perf"; cpu-idle-states = <&CLUSTER_C4>; }; @@ -147,8 +147,8 @@ CPU6: cpu@10200 { reg = <0x0 0x10200>; enable-method = "psci"; next-level-cache = <&L2_1>; - power-domains = <&CPU_PD6>; - power-domain-names = "psci"; + power-domains = <&CPU_PD6>, <&scmi_dvfs 1>; + power-domain-names = "psci", "perf"; cpu-idle-states = <&CLUSTER_C4>; }; @@ -158,8 +158,8 @@ CPU7: cpu@10300 { reg = <0x0 0x10300>; enable-method = "psci"; next-level-cache = <&L2_1>; - power-domains = <&CPU_PD7>; - power-domain-names = "psci"; + power-domains = <&CPU_PD7>, <&scmi_dvfs 1>; + power-domain-names = "psci", "perf"; cpu-idle-states = <&CLUSTER_C4>; }; @@ -169,8 +169,8 @@ CPU8: cpu@20000 { reg = <0x0 0x20000>; enable-method = "psci"; next-level-cache = <&L2_2>; - power-domains = <&CPU_PD8>; - power-domain-names = "psci"; + power-domains = <&CPU_PD8>, <&scmi_dvfs 2>; + power-domain-names = "psci", "perf"; cpu-idle-states = <&CLUSTER_C4>; L2_2: l2-cache { @@ -186,8 +186,8 @@ CPU9: cpu@20100 { reg = <0x0 0x20100>; enable-method = "psci"; next-level-cache = <&L2_2>; - power-domains = <&CPU_PD9>; - power-domain-names = "psci"; + power-domains = <&CPU_PD9>, <&scmi_dvfs 2>; + power-domain-names = "psci", "perf"; cpu-idle-states = <&CLUSTER_C4>; }; @@ -197,8 +197,8 @@ CPU10: cpu@20200 { reg = <0x0 0x20200>; enable-method = "psci"; next-level-cache = <&L2_2>; - power-domains = <&CPU_PD10>; - power-domain-names = "psci"; + power-domains = <&CPU_PD10>, <&scmi_dvfs 2>; + power-domain-names = "psci", "perf"; cpu-idle-states = <&CLUSTER_C4>; }; @@ -208,8 +208,8 @@ CPU11: cpu@20300 { reg = <0x0 0x20300>; enable-method = "psci"; next-level-cache = <&L2_2>; - power-domains = <&CPU_PD11>; - power-domain-names = "psci"; + power-domains = <&CPU_PD11>, <&scmi_dvfs 2>; + power-domain-names = "psci", "perf"; cpu-idle-states = <&CLUSTER_C4>; }; @@ -309,6 +309,21 @@ scm: scm { interconnects = <&aggre2_noc MASTER_CRYPTO QCOM_ICC_TAG_ALWAYS &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; }; + + scmi { + compatible = "arm,scmi"; + mboxes = <&cpucp_mbox 0>, <&cpucp_mbox 2>; + mbox-names = "tx", "rx"; + shmem = <&cpu_scp_lpri0>, <&cpu_scp_lpri1>; + + #address-cells = <1>; + #size-cells = <0>; + + scmi_dvfs: protocol@13 { + reg = <0x13>; + #power-domain-cells = <1>; + }; + }; }; clk_virt: interconnect-0 {