From patchwork Thu Apr 18 12:42:24 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?b?Q2zDqW1lbnQgTMOpZ2Vy?= X-Patchwork-Id: 13634660 Received: from mail-wr1-f52.google.com (mail-wr1-f52.google.com [209.85.221.52]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id CD6AD147C60 for ; Thu, 18 Apr 2024 12:43:56 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.221.52 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1713444239; cv=none; b=G7WlCcdN1FdkFNI2TIAHUsgID2N1WWWk1jzV9doWzZ9U0aSiwBgOxR76VIdlhyxK9zDhDyz7AgcB9OoPX2ARXruoiBkZrBmrbuVwzOcNOeA/aotRmSs01y3gJL/WKYuNPHTA3Ik2EdYM3e4XDmhGYK1tvo3ZBSj378qkL+1HQGo= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1713444239; c=relaxed/simple; bh=keUOTcQpJ+9Spm7ZO1wTme35teQ5D7BlxcLl00vQb1s=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=o93U81DAPK5jgd+dOiMQJSsWoWNaGyV3OZoifQIbi/EAEd+CtAO1zobI6gRlNy9CxAQWJ0l2Wk/yLcvq1/uLWobXE3KuvmnOSIvLieu6nlex/dQMT5+O4OYKhbKxuwBR+3NwLEDYvIo/9Z+Xtu2+vnoLiJFzNBVWfhuAU3ojEe4= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=rivosinc.com; spf=pass smtp.mailfrom=rivosinc.com; dkim=pass (2048-bit key) header.d=rivosinc-com.20230601.gappssmtp.com header.i=@rivosinc-com.20230601.gappssmtp.com header.b=2zNrumNW; arc=none smtp.client-ip=209.85.221.52 Authentication-Results: smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=rivosinc.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=rivosinc.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=rivosinc-com.20230601.gappssmtp.com header.i=@rivosinc-com.20230601.gappssmtp.com header.b="2zNrumNW" Received: by mail-wr1-f52.google.com with SMTP id ffacd0b85a97d-347c6d6fc02so116278f8f.1 for ; Thu, 18 Apr 2024 05:43:56 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=rivosinc-com.20230601.gappssmtp.com; s=20230601; t=1713444235; x=1714049035; darn=vger.kernel.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=zrjU6l9W7DikYIaMYJG/SdZ2oUTcGtwCnDHe7Ekc7IE=; b=2zNrumNWxQWNhSEDA3BqSlQilsh7yLZQ9sMPLJTdL10wRRSJCJ2YKL1Ua8ePsJnwCe csUNqMEtEnX5kOfXu9TjBCAhYce9No9hJ/qKIMsUZj/nHoRz0xvNEtFUAsM+CnAmiKVD JjmLVjoJ5k50Rgi3rDs5tprdOQgVeMyOe05qCYkUT6tPBPYS567NYUn3qqZ3vjlf/0XJ vuECuSqUrQKfX89j21oipCASHFXsorpxKGST2JPaTJIb+chzySvpq8SCIi6i9EFQwKf9 BjGuyw4PxWG2EcKOU4o0KfDXNDeSUKjXSx+VdcfPrt1cTYfu0dQuA1gQxGOu6Wz6Uuyk XokA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1713444235; x=1714049035; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=zrjU6l9W7DikYIaMYJG/SdZ2oUTcGtwCnDHe7Ekc7IE=; b=WTVXaQPwYX09Zq2J7IKktltZiB1KMtf5H7KW5wio8pNXgpYoh1qX1oGqmzYdcwomcL XkmED7O6H3n+aOYQn5hpKcZgqYj5XL4Mgtn19tykxWSAYWor3orQb6JOie/6d1DEyQRU bdgmQ8dlUxL97Z411lezxgmKsppxF4lFofHRyM2CFG94kHMNhroAmIFIfkHI4GlFc7yY /5KgTe0Hv4F+KiSQY4AyFKRsvYQC/BJS0eoHcd9fZxeXSUDkYHZUOHp76w+eKSh3NRvD nGO5UD4B75ZKRmpCFeJ8H2fKM29VY3NWzUyhYUwd2TxEY+EZP0m+9OxCH51zTY25UYe7 iQlQ== X-Forwarded-Encrypted: i=1; AJvYcCWT7dJFHbp5SW8shsXwSRiw24t83znzM3whCLdFRiblz1ByHtc0U+AbRMY6KgJRSUkKewR4n28jNlV/RV7pDMSs10m5 X-Gm-Message-State: AOJu0YwllWyaH7/XSPQXv0N3R5vQKc0+4BS0rsD7NHkHBqycc6b7qZdw eFGJqO6v0fXzS0ZwJFkut5K4lXCq3L6lIY6PFAXbcn6sPRG7WflWUytQJMpRyUs= X-Google-Smtp-Source: AGHT+IFFx4DMJCN/eGlinw4D8WxSb2s5Led6zbc0ypunbHRPKVqfx9J88kY5VuS8nvJuPPTEq99jAg== X-Received: by 2002:a05:600c:55d7:b0:418:ef65:4b5f with SMTP id jq23-20020a05600c55d700b00418ef654b5fmr805438wmb.3.1713444235113; Thu, 18 Apr 2024 05:43:55 -0700 (PDT) Received: from carbon-x1.. ([2a01:e0a:999:a3a0:7b64:4d1d:16d8:e38b]) by smtp.gmail.com with ESMTPSA id bi18-20020a05600c3d9200b00418d5b16fa2sm3373412wmb.30.2024.04.18.05.43.53 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 18 Apr 2024 05:43:54 -0700 (PDT) From: =?utf-8?b?Q2zDqW1lbnQgTMOpZ2Vy?= To: Jonathan Corbet , Paul Walmsley , Palmer Dabbelt , Albert Ou , Conor Dooley , Rob Herring , Krzysztof Kozlowski , Anup Patel , Shuah Khan Cc: =?utf-8?b?Q2zDqW1lbnQgTMOpZ2Vy?= , Atish Patra , linux-doc@vger.kernel.org, linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, kvm@vger.kernel.org, kvm-riscv@lists.infradead.org, linux-kselftest@vger.kernel.org Subject: [PATCH v2 01/12] dt-bindings: riscv: add Zca, Zcf, Zcd and Zcb ISA extension description Date: Thu, 18 Apr 2024 14:42:24 +0200 Message-ID: <20240418124300.1387978-2-cleger@rivosinc.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20240418124300.1387978-1-cleger@rivosinc.com> References: <20240418124300.1387978-1-cleger@rivosinc.com> Precedence: bulk X-Mailing-List: kvm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Add description for Zca, Zcf, Zcd and Zcb extensions which are part the Zc* standard extensions for code size reduction. Additional validation rules are added since Zcb depends on Zca, Zcf, depends on Zca and F, Zcd depends on Zca and D and finally, Zcf can not be present on rv64. Signed-off-by: Clément Léger Reviewed-by: Conor Dooley --- .../devicetree/bindings/riscv/extensions.yaml | 78 +++++++++++++++++++ 1 file changed, 78 insertions(+) diff --git a/Documentation/devicetree/bindings/riscv/extensions.yaml b/Documentation/devicetree/bindings/riscv/extensions.yaml index 616370318a66..db7daf22b863 100644 --- a/Documentation/devicetree/bindings/riscv/extensions.yaml +++ b/Documentation/devicetree/bindings/riscv/extensions.yaml @@ -220,6 +220,38 @@ properties: instructions as ratified at commit 6d33919 ("Merge pull request #158 from hirooih/clmul-fix-loop-end-condition") of riscv-bitmanip. + - const: zca + description: | + The Zca extension part of Zc* standard extensions for code size + reduction, as ratified in commit 8be3419c1c0 ("Zcf doesn't exist on + RV64 as it contains no instructions") of riscv-code-size-reduction, + merged in the riscv-isa-manual by commit dbc79cf28a2 ("Initial seed + of zc.adoc to src tree."). + + - const: zcb + description: | + The Zcb extension part of Zc* standard extensions for code size + reduction, as ratified in commit 8be3419c1c0 ("Zcf doesn't exist on + RV64 as it contains no instructions") of riscv-code-size-reduction, + merged in the riscv-isa-manual by commit dbc79cf28a2 ("Initial seed + of zc.adoc to src tree."). + + - const: zcd + description: | + The Zcd extension part of Zc* standard extensions for code size + reduction, as ratified in commit 8be3419c1c0 ("Zcf doesn't exist on + RV64 as it contains no instructions") of riscv-code-size-reduction, + merged in the riscv-isa-manual by commit dbc79cf28a2 ("Initial seed + of zc.adoc to src tree."). + + - const: zcf + description: | + The Zcf extension part of Zc* standard extensions for code size + reduction, as ratified in commit 8be3419c1c0 ("Zcf doesn't exist on + RV64 as it contains no instructions") of riscv-code-size-reduction, + merged in the riscv-isa-manual by commit dbc79cf28a2 ("Initial seed + of zc.adoc to src tree."). + - const: zfa description: The standard Zfa extension for additional floating point @@ -489,5 +521,51 @@ properties: Registers in the AX45MP datasheet. https://www.andestech.com/wp-content/uploads/AX45MP-1C-Rev.-5.0.0-Datasheet.pdf + allOf: + # Zcb depends on Zca + - if: + contains: + const: zcb + then: + contains: + const: zca + # Zcd depends on Zca and D + - if: + contains: + const: zcd + then: + allOf: + - contains: + const: zca + - contains: + const: d + # Zcf depends on Zca and F + - if: + contains: + const: zcf + then: + allOf: + - contains: + const: zca + - contains: + const: f + +allOf: + # Zcf extension does not exists on rv64 + - if: + properties: + riscv,isa-extensions: + contains: + const: zcf + riscv,isa-base: + contains: + const: rv64i + then: + properties: + riscv,isa-extensions: + not: + contains: + const: zcf + additionalProperties: true ... From patchwork Thu Apr 18 12:42:25 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?b?Q2zDqW1lbnQgTMOpZ2Vy?= X-Patchwork-Id: 13634663 Received: from mail-wr1-f50.google.com (mail-wr1-f50.google.com [209.85.221.50]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id F391615E812 for ; Thu, 18 Apr 2024 12:43:57 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.221.50 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1713444243; cv=none; b=CqtDInpnyAfe5aaFXzIuf0fIIDF/6jwptsARLz0dAlnBknke6yWZpLcbMx/cG0V6lXj9xkKZeG1gXINt1NltCh7HOtS7I0d6zsE9Dht9jxkd1ziq8wJuMo/fm7Su2Jrxa7Lo+aKFTxx+r6k/30u4eJbUdm0v/t2r1c90RWdMdDg= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1713444243; c=relaxed/simple; bh=Ebkz2UrL5WmXTvDeVMjwelCR0dBJEenoSOcmBz5PT+8=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=Uby1TR5Gl59qZQdj+S7yKJ5HtOyPcUcRlhSGGhuw1ivRO0wAhJsHiMVa87UR6qmFtNBT4bVaDNvHdsV2ESNYO8zcs4BRsha9yMfAdcqx1toajSl6YaqBWpUQXugmAzbsimk6TPC+vC74qvKdbSn0LJov78G/g80onT142RiFnns= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=rivosinc.com; spf=pass smtp.mailfrom=rivosinc.com; dkim=pass (2048-bit key) header.d=rivosinc-com.20230601.gappssmtp.com header.i=@rivosinc-com.20230601.gappssmtp.com header.b=UkFm4u9r; arc=none smtp.client-ip=209.85.221.50 Authentication-Results: smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=rivosinc.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=rivosinc.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=rivosinc-com.20230601.gappssmtp.com header.i=@rivosinc-com.20230601.gappssmtp.com header.b="UkFm4u9r" Received: by mail-wr1-f50.google.com with SMTP id ffacd0b85a97d-346a5dea2f4so182910f8f.1 for ; Thu, 18 Apr 2024 05:43:57 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=rivosinc-com.20230601.gappssmtp.com; s=20230601; t=1713444236; x=1714049036; darn=vger.kernel.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=oAl9pLtTmdQ7M+Wok6zdTTXvycSGmEGoH9Hb6PFq4BA=; b=UkFm4u9rdUYm6YqVhhI0dKU2KtlxOJnkNcmAjuNTxs3gOriQXEmj6ZeK8Y5zMEa7zC cikf0ggfc8OHDI6UU6n8Q+DEdW5uxmcl6ShroSMpZ9ERAC+1oHUkGmc4DOyqD9JfLZow zuBGC+3HSwjjYDTPJmOcmzlbY746cBCZ91zRfot7SAK6Xptt/X0pu7opAKS+jFXaUVa2 rmgRTxz1FPpCb2J3MuPTZQzFkK6X0ZqirsHvW4/dMLQdMd4+N/ZdawHKNTFLXr4fqE23 rNvHnVFK8jReFeE2+yxGM+Ksp19xEwPZ51PSCUn1j84TjZl4mNdkd9k3iTEA4dfK7QOF BEWg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1713444236; x=1714049036; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=oAl9pLtTmdQ7M+Wok6zdTTXvycSGmEGoH9Hb6PFq4BA=; b=A2evW0Q/hpjhJDfGdVrDQR0EpPm/aS5PKiL4cqSmUuCrpUbZ5aOfiIOnckQ+ATm5si yTWompS2h64ggGvWJV6V35KsrG0Xk2Gd5Xi7cCwDeZubvaNC4QeAIzBDh8T0Pb8tHSy5 ZaSCaBmFJbsPzLTSP20ruEPEztwybE7qUU3fhe2M4BoKJhEDn7yRRdmiKu2XhWfNwjy1 aRlulfAhWFLrRobaRbbTcLBsw7KcqI4hFxpSj2Z9Idipfx+v0xRbnPA2TR71XnwIH9cX 4LZivxDQmAeJXToxDceFdQLH0X2DovL6U9n486AKXSkQxQpeOrzQc8bqJ3pdyVYeHMr4 bn9A== X-Forwarded-Encrypted: i=1; AJvYcCVw/asNAMCDsQ5hrmD/vbly4pBoztPdB4pweUWsfYxpnh49MHccBsPuM3Hg4JQ2kc15M4PHCENdvdOGPkpFwFIFTuOB X-Gm-Message-State: AOJu0YybcegB6b7yx4zpqntpXnKKTQB3+09PLwwyafJOtOidqsp8OTEk vP1Yn1zfW2oiDfQ+A3A9Ts5DZ16+RjJQqCntOKN3qBVsdWvo+PAx9dw1nUPBBtIXnT8FEARyGqT KAXU= X-Google-Smtp-Source: AGHT+IFKhZshgTTpNugctUIBKjo1ziNnne6N8VGVQW4Spy090KZRQKoznik9yMPwCUs6CVPn34LP8A== X-Received: by 2002:a5d:5989:0:b0:34a:513:5c46 with SMTP id n9-20020a5d5989000000b0034a05135c46mr1797065wri.5.1713444236215; Thu, 18 Apr 2024 05:43:56 -0700 (PDT) Received: from carbon-x1.. ([2a01:e0a:999:a3a0:7b64:4d1d:16d8:e38b]) by smtp.gmail.com with ESMTPSA id bi18-20020a05600c3d9200b00418d5b16fa2sm3373412wmb.30.2024.04.18.05.43.55 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 18 Apr 2024 05:43:55 -0700 (PDT) From: =?utf-8?b?Q2zDqW1lbnQgTMOpZ2Vy?= To: Jonathan Corbet , Paul Walmsley , Palmer Dabbelt , Albert Ou , Conor Dooley , Rob Herring , Krzysztof Kozlowski , Anup Patel , Shuah Khan Cc: =?utf-8?b?Q2zDqW1lbnQgTMOpZ2Vy?= , Atish Patra , linux-doc@vger.kernel.org, linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, kvm@vger.kernel.org, kvm-riscv@lists.infradead.org, linux-kselftest@vger.kernel.org Subject: [PATCH v2 02/12] riscv: dts: enable Zc* extensions when needed Date: Thu, 18 Apr 2024 14:42:25 +0200 Message-ID: <20240418124300.1387978-3-cleger@rivosinc.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20240418124300.1387978-1-cleger@rivosinc.com> References: <20240418124300.1387978-1-cleger@rivosinc.com> Precedence: bulk X-Mailing-List: kvm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 The Zc* spec states that: "The C extension is the superset of the following extensions: - Zca - Zcf if F is specified (RV32 only) - Zcd if D is specified As C defines the same instructions as Zca, Zcf and Zcd, the rule is that: - C always implies Zca - C+F implies Zcf (RV32 only)" Add these extensions to existing device-trees that contains "c" extension in "riscv,isa-extensions". Signed-off-by: Clément Léger --- arch/riscv/boot/dts/allwinner/sun20i-d1s.dtsi | 4 +- arch/riscv/boot/dts/microchip/mpfs.dtsi | 20 +- arch/riscv/boot/dts/renesas/r9a07g043f.dtsi | 4 +- arch/riscv/boot/dts/sifive/fu540-c000.dtsi | 20 +- arch/riscv/boot/dts/sifive/fu740-c000.dtsi | 20 +- arch/riscv/boot/dts/sophgo/cv18xx.dtsi | 4 +- arch/riscv/boot/dts/sophgo/sg2042-cpus.dtsi | 256 +++++++++--------- arch/riscv/boot/dts/starfive/jh7100.dtsi | 8 +- arch/riscv/boot/dts/starfive/jh7110.dtsi | 20 +- arch/riscv/boot/dts/thead/th1520.dtsi | 16 +- 10 files changed, 186 insertions(+), 186 deletions(-) diff --git a/arch/riscv/boot/dts/allwinner/sun20i-d1s.dtsi b/arch/riscv/boot/dts/allwinner/sun20i-d1s.dtsi index 64c3c2e6cbe0..05e0e5f0eed7 100644 --- a/arch/riscv/boot/dts/allwinner/sun20i-d1s.dtsi +++ b/arch/riscv/boot/dts/allwinner/sun20i-d1s.dtsi @@ -26,8 +26,8 @@ cpu0: cpu@0 { operating-points-v2 = <&opp_table_cpu>; riscv,isa = "rv64imafdc"; riscv,isa-base = "rv64i"; - riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "zicntr", "zicsr", - "zifencei", "zihpm"; + riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "zca", "zcd", "zicntr", + "zicsr", "zifencei", "zihpm"; #cooling-cells = <2>; cpu0_intc: interrupt-controller { diff --git a/arch/riscv/boot/dts/microchip/mpfs.dtsi b/arch/riscv/boot/dts/microchip/mpfs.dtsi index 9883ca3554c5..82ac84afdda7 100644 --- a/arch/riscv/boot/dts/microchip/mpfs.dtsi +++ b/arch/riscv/boot/dts/microchip/mpfs.dtsi @@ -24,8 +24,8 @@ cpu0: cpu@0 { reg = <0>; riscv,isa = "rv64imac"; riscv,isa-base = "rv64i"; - riscv,isa-extensions = "i", "m", "a", "c", "zicntr", "zicsr", "zifencei", - "zihpm"; + riscv,isa-extensions = "i", "m", "a", "c", "zca", "zicntr", "zicsr", + "zifencei", "zihpm"; clocks = <&clkcfg CLK_CPU>; status = "disabled"; @@ -53,8 +53,8 @@ cpu1: cpu@1 { reg = <1>; riscv,isa = "rv64imafdc"; riscv,isa-base = "rv64i"; - riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "zicntr", "zicsr", - "zifencei", "zihpm"; + riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "zca", "zcd", "zicntr", + "zicsr", "zifencei", "zihpm"; clocks = <&clkcfg CLK_CPU>; tlb-split; next-level-cache = <&cctrllr>; @@ -84,8 +84,8 @@ cpu2: cpu@2 { reg = <2>; riscv,isa = "rv64imafdc"; riscv,isa-base = "rv64i"; - riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "zicntr", "zicsr", - "zifencei", "zihpm"; + riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "zca", "zcd", "zicntr", + "zicsr", "zifencei", "zihpm"; clocks = <&clkcfg CLK_CPU>; tlb-split; next-level-cache = <&cctrllr>; @@ -115,8 +115,8 @@ cpu3: cpu@3 { reg = <3>; riscv,isa = "rv64imafdc"; riscv,isa-base = "rv64i"; - riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "zicntr", "zicsr", - "zifencei", "zihpm"; + riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "zca", "zcd", "zicntr", + "zicsr", "zifencei", "zihpm"; clocks = <&clkcfg CLK_CPU>; tlb-split; next-level-cache = <&cctrllr>; @@ -146,8 +146,8 @@ cpu4: cpu@4 { reg = <4>; riscv,isa = "rv64imafdc"; riscv,isa-base = "rv64i"; - riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "zicntr", "zicsr", - "zifencei", "zihpm"; + riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "zca", "zcd", "zicntr", + "zicsr", "zifencei", "zihpm"; clocks = <&clkcfg CLK_CPU>; tlb-split; next-level-cache = <&cctrllr>; diff --git a/arch/riscv/boot/dts/renesas/r9a07g043f.dtsi b/arch/riscv/boot/dts/renesas/r9a07g043f.dtsi index f35324b9173c..b5e06fbfdf65 100644 --- a/arch/riscv/boot/dts/renesas/r9a07g043f.dtsi +++ b/arch/riscv/boot/dts/renesas/r9a07g043f.dtsi @@ -26,8 +26,8 @@ cpu0: cpu@0 { riscv,isa = "rv64imafdc"; riscv,isa-base = "rv64i"; riscv,isa-extensions = "i", "m", "a", "f", "d", "c", - "zicntr", "zicsr", "zifencei", - "zihpm", "xandespmu"; + "zca", "zcd", "zicntr", "zicsr", + "zifencei", "zihpm", "xandespmu"; mmu-type = "riscv,sv39"; i-cache-size = <0x8000>; i-cache-line-size = <0x40>; diff --git a/arch/riscv/boot/dts/sifive/fu540-c000.dtsi b/arch/riscv/boot/dts/sifive/fu540-c000.dtsi index 156330a9bbf3..2872515dab17 100644 --- a/arch/riscv/boot/dts/sifive/fu540-c000.dtsi +++ b/arch/riscv/boot/dts/sifive/fu540-c000.dtsi @@ -31,8 +31,8 @@ cpu0: cpu@0 { reg = <0>; riscv,isa = "rv64imac"; riscv,isa-base = "rv64i"; - riscv,isa-extensions = "i", "m", "a", "c", "zicntr", "zicsr", "zifencei", - "zihpm"; + riscv,isa-extensions = "i", "m", "a", "c", "zca", "zicntr", "zicsr", + "zifencei", "zihpm"; status = "disabled"; cpu0_intc: interrupt-controller { #interrupt-cells = <1>; @@ -57,8 +57,8 @@ cpu1: cpu@1 { reg = <1>; riscv,isa = "rv64imafdc"; riscv,isa-base = "rv64i"; - riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "zicntr", "zicsr", - "zifencei", "zihpm"; + riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "zca", "zcd", "zicntr", + "zicsr", "zifencei", "zihpm"; tlb-split; next-level-cache = <&l2cache>; cpu1_intc: interrupt-controller { @@ -84,8 +84,8 @@ cpu2: cpu@2 { reg = <2>; riscv,isa = "rv64imafdc"; riscv,isa-base = "rv64i"; - riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "zicntr", "zicsr", - "zifencei", "zihpm"; + riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "zca", "zcd", "zicntr", + "zicsr", "zifencei", "zihpm"; tlb-split; next-level-cache = <&l2cache>; cpu2_intc: interrupt-controller { @@ -111,8 +111,8 @@ cpu3: cpu@3 { reg = <3>; riscv,isa = "rv64imafdc"; riscv,isa-base = "rv64i"; - riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "zicntr", "zicsr", - "zifencei", "zihpm"; + riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "zca", "zcd", "zicntr", + "zicsr", "zifencei", "zihpm"; tlb-split; next-level-cache = <&l2cache>; cpu3_intc: interrupt-controller { @@ -138,8 +138,8 @@ cpu4: cpu@4 { reg = <4>; riscv,isa = "rv64imafdc"; riscv,isa-base = "rv64i"; - riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "zicntr", "zicsr", - "zifencei", "zihpm"; + riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "zca", "zcd", "zicntr", + "zicsr", "zifencei", "zihpm"; tlb-split; next-level-cache = <&l2cache>; cpu4_intc: interrupt-controller { diff --git a/arch/riscv/boot/dts/sifive/fu740-c000.dtsi b/arch/riscv/boot/dts/sifive/fu740-c000.dtsi index 6150f3397bff..4336ed11db9a 100644 --- a/arch/riscv/boot/dts/sifive/fu740-c000.dtsi +++ b/arch/riscv/boot/dts/sifive/fu740-c000.dtsi @@ -32,8 +32,8 @@ cpu0: cpu@0 { reg = <0x0>; riscv,isa = "rv64imac"; riscv,isa-base = "rv64i"; - riscv,isa-extensions = "i", "m", "a", "c", "zicntr", "zicsr", "zifencei", - "zihpm"; + riscv,isa-extensions = "i", "m", "a", "c", "zca", "zicntr", "zicsr", + "zifencei", "zihpm"; status = "disabled"; cpu0_intc: interrupt-controller { #interrupt-cells = <1>; @@ -59,8 +59,8 @@ cpu1: cpu@1 { reg = <0x1>; riscv,isa = "rv64imafdc"; riscv,isa-base = "rv64i"; - riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "zicntr", "zicsr", - "zifencei", "zihpm"; + riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "zca", "zcd", "zicntr", + "zicsr", "zifencei", "zihpm"; tlb-split; cpu1_intc: interrupt-controller { #interrupt-cells = <1>; @@ -86,8 +86,8 @@ cpu2: cpu@2 { reg = <0x2>; riscv,isa = "rv64imafdc"; riscv,isa-base = "rv64i"; - riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "zicntr", "zicsr", - "zifencei", "zihpm"; + riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "zca", "zcd", "zicntr", + "zicsr", "zifencei", "zihpm"; tlb-split; cpu2_intc: interrupt-controller { #interrupt-cells = <1>; @@ -113,8 +113,8 @@ cpu3: cpu@3 { reg = <0x3>; riscv,isa = "rv64imafdc"; riscv,isa-base = "rv64i"; - riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "zicntr", "zicsr", - "zifencei", "zihpm"; + riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "zca", "zcd", "zicntr", + "zicsr", "zifencei", "zihpm"; tlb-split; cpu3_intc: interrupt-controller { #interrupt-cells = <1>; @@ -140,8 +140,8 @@ cpu4: cpu@4 { reg = <0x4>; riscv,isa = "rv64imafdc"; riscv,isa-base = "rv64i"; - riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "zicntr", "zicsr", - "zifencei", "zihpm"; + riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "zca", "zcd", "zicntr", + "zicsr", "zifencei", "zihpm"; tlb-split; cpu4_intc: interrupt-controller { #interrupt-cells = <1>; diff --git a/arch/riscv/boot/dts/sophgo/cv18xx.dtsi b/arch/riscv/boot/dts/sophgo/cv18xx.dtsi index 2d6f4a4b1e58..1fa5c57acf48 100644 --- a/arch/riscv/boot/dts/sophgo/cv18xx.dtsi +++ b/arch/riscv/boot/dts/sophgo/cv18xx.dtsi @@ -28,8 +28,8 @@ cpu0: cpu@0 { mmu-type = "riscv,sv39"; riscv,isa = "rv64imafdc"; riscv,isa-base = "rv64i"; - riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "zicntr", "zicsr", - "zifencei", "zihpm"; + riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "zca", "zcd", "zicntr", + "zicsr", "zifencei", "zihpm"; cpu0_intc: interrupt-controller { compatible = "riscv,cpu-intc"; diff --git a/arch/riscv/boot/dts/sophgo/sg2042-cpus.dtsi b/arch/riscv/boot/dts/sophgo/sg2042-cpus.dtsi index b136b6c4128c..6d03076314aa 100644 --- a/arch/riscv/boot/dts/sophgo/sg2042-cpus.dtsi +++ b/arch/riscv/boot/dts/sophgo/sg2042-cpus.dtsi @@ -259,8 +259,8 @@ cpu0: cpu@0 { riscv,isa = "rv64imafdc"; riscv,isa-base = "rv64i"; riscv,isa-extensions = "i", "m", "a", "f", "d", "c", - "zicntr", "zicsr", "zifencei", - "zihpm"; + "zca", "zcd", "zicntr", "zicsr", + "zifencei", "zihpm"; reg = <0>; i-cache-block-size = <64>; i-cache-size = <65536>; @@ -284,8 +284,8 @@ cpu1: cpu@1 { riscv,isa = "rv64imafdc"; riscv,isa-base = "rv64i"; riscv,isa-extensions = "i", "m", "a", "f", "d", "c", - "zicntr", "zicsr", "zifencei", - "zihpm"; + "zca", "zcd", "zicntr", "zicsr", + "zifencei", "zihpm"; reg = <1>; i-cache-block-size = <64>; i-cache-size = <65536>; @@ -309,8 +309,8 @@ cpu2: cpu@2 { riscv,isa = "rv64imafdc"; riscv,isa-base = "rv64i"; riscv,isa-extensions = "i", "m", "a", "f", "d", "c", - "zicntr", "zicsr", "zifencei", - "zihpm"; + "zca", "zcd", "zicntr", "zicsr", + "zifencei", "zihpm"; reg = <2>; i-cache-block-size = <64>; i-cache-size = <65536>; @@ -334,8 +334,8 @@ cpu3: cpu@3 { riscv,isa = "rv64imafdc"; riscv,isa-base = "rv64i"; riscv,isa-extensions = "i", "m", "a", "f", "d", "c", - "zicntr", "zicsr", "zifencei", - "zihpm"; + "zca", "zcd", "zicntr", "zicsr", + "zifencei", "zihpm"; reg = <3>; i-cache-block-size = <64>; i-cache-size = <65536>; @@ -359,8 +359,8 @@ cpu4: cpu@4 { riscv,isa = "rv64imafdc"; riscv,isa-base = "rv64i"; riscv,isa-extensions = "i", "m", "a", "f", "d", "c", - "zicntr", "zicsr", "zifencei", - "zihpm"; + "zca", "zcd", "zicntr", "zicsr", + "zifencei", "zihpm"; reg = <4>; i-cache-block-size = <64>; i-cache-size = <65536>; @@ -384,8 +384,8 @@ cpu5: cpu@5 { riscv,isa = "rv64imafdc"; riscv,isa-base = "rv64i"; riscv,isa-extensions = "i", "m", "a", "f", "d", "c", - "zicntr", "zicsr", "zifencei", - "zihpm"; + "zca", "zcd", "zicntr", "zicsr", + "zifencei", "zihpm"; reg = <5>; i-cache-block-size = <64>; i-cache-size = <65536>; @@ -409,8 +409,8 @@ cpu6: cpu@6 { riscv,isa = "rv64imafdc"; riscv,isa-base = "rv64i"; riscv,isa-extensions = "i", "m", "a", "f", "d", "c", - "zicntr", "zicsr", "zifencei", - "zihpm"; + "zca", "zcd", "zicntr", "zicsr", + "zifencei", "zihpm"; reg = <6>; i-cache-block-size = <64>; i-cache-size = <65536>; @@ -434,8 +434,8 @@ cpu7: cpu@7 { riscv,isa = "rv64imafdc"; riscv,isa-base = "rv64i"; riscv,isa-extensions = "i", "m", "a", "f", "d", "c", - "zicntr", "zicsr", "zifencei", - "zihpm"; + "zca", "zcd", "zicntr", "zicsr", + "zifencei", "zihpm"; reg = <7>; i-cache-block-size = <64>; i-cache-size = <65536>; @@ -459,8 +459,8 @@ cpu8: cpu@8 { riscv,isa = "rv64imafdc"; riscv,isa-base = "rv64i"; riscv,isa-extensions = "i", "m", "a", "f", "d", "c", - "zicntr", "zicsr", "zifencei", - "zihpm"; + "zca", "zcd", "zicntr", "zicsr", + "zifencei", "zihpm"; reg = <8>; i-cache-block-size = <64>; i-cache-size = <65536>; @@ -484,8 +484,8 @@ cpu9: cpu@9 { riscv,isa = "rv64imafdc"; riscv,isa-base = "rv64i"; riscv,isa-extensions = "i", "m", "a", "f", "d", "c", - "zicntr", "zicsr", "zifencei", - "zihpm"; + "zca", "zcd", "zicntr", "zicsr", + "zifencei", "zihpm"; reg = <9>; i-cache-block-size = <64>; i-cache-size = <65536>; @@ -509,8 +509,8 @@ cpu10: cpu@10 { riscv,isa = "rv64imafdc"; riscv,isa-base = "rv64i"; riscv,isa-extensions = "i", "m", "a", "f", "d", "c", - "zicntr", "zicsr", "zifencei", - "zihpm"; + "zca", "zcd", "zicntr", "zicsr", + "zifencei", "zihpm"; reg = <10>; i-cache-block-size = <64>; i-cache-size = <65536>; @@ -534,8 +534,8 @@ cpu11: cpu@11 { riscv,isa = "rv64imafdc"; riscv,isa-base = "rv64i"; riscv,isa-extensions = "i", "m", "a", "f", "d", "c", - "zicntr", "zicsr", "zifencei", - "zihpm"; + "zca", "zcd", "zicntr", "zicsr", + "zifencei", "zihpm"; reg = <11>; i-cache-block-size = <64>; i-cache-size = <65536>; @@ -559,8 +559,8 @@ cpu12: cpu@12 { riscv,isa = "rv64imafdc"; riscv,isa-base = "rv64i"; riscv,isa-extensions = "i", "m", "a", "f", "d", "c", - "zicntr", "zicsr", "zifencei", - "zihpm"; + "zca", "zcd", "zicntr", "zicsr", + "zifencei", "zihpm"; reg = <12>; i-cache-block-size = <64>; i-cache-size = <65536>; @@ -584,8 +584,8 @@ cpu13: cpu@13 { riscv,isa = "rv64imafdc"; riscv,isa-base = "rv64i"; riscv,isa-extensions = "i", "m", "a", "f", "d", "c", - "zicntr", "zicsr", "zifencei", - "zihpm"; + "zca", "zcd", "zicntr", "zicsr", + "zifencei", "zihpm"; reg = <13>; i-cache-block-size = <64>; i-cache-size = <65536>; @@ -609,8 +609,8 @@ cpu14: cpu@14 { riscv,isa = "rv64imafdc"; riscv,isa-base = "rv64i"; riscv,isa-extensions = "i", "m", "a", "f", "d", "c", - "zicntr", "zicsr", "zifencei", - "zihpm"; + "zca", "zcd", "zicntr", "zicsr", + "zifencei", "zihpm"; reg = <14>; i-cache-block-size = <64>; i-cache-size = <65536>; @@ -634,8 +634,8 @@ cpu15: cpu@15 { riscv,isa = "rv64imafdc"; riscv,isa-base = "rv64i"; riscv,isa-extensions = "i", "m", "a", "f", "d", "c", - "zicntr", "zicsr", "zifencei", - "zihpm"; + "zca", "zcd", "zicntr", "zicsr", + "zifencei", "zihpm"; reg = <15>; i-cache-block-size = <64>; i-cache-size = <65536>; @@ -659,8 +659,8 @@ cpu16: cpu@16 { riscv,isa = "rv64imafdc"; riscv,isa-base = "rv64i"; riscv,isa-extensions = "i", "m", "a", "f", "d", "c", - "zicntr", "zicsr", "zifencei", - "zihpm"; + "zca", "zcd", "zicntr", "zicsr", + "zifencei", "zihpm"; reg = <16>; i-cache-block-size = <64>; i-cache-size = <65536>; @@ -684,8 +684,8 @@ cpu17: cpu@17 { riscv,isa = "rv64imafdc"; riscv,isa-base = "rv64i"; riscv,isa-extensions = "i", "m", "a", "f", "d", "c", - "zicntr", "zicsr", "zifencei", - "zihpm"; + "zca", "zcd", "zicntr", "zicsr", + "zifencei", "zihpm"; reg = <17>; i-cache-block-size = <64>; i-cache-size = <65536>; @@ -709,8 +709,8 @@ cpu18: cpu@18 { riscv,isa = "rv64imafdc"; riscv,isa-base = "rv64i"; riscv,isa-extensions = "i", "m", "a", "f", "d", "c", - "zicntr", "zicsr", "zifencei", - "zihpm"; + "zca", "zcd", "zicntr", "zicsr", + "zifencei", "zihpm"; reg = <18>; i-cache-block-size = <64>; i-cache-size = <65536>; @@ -734,8 +734,8 @@ cpu19: cpu@19 { riscv,isa = "rv64imafdc"; riscv,isa-base = "rv64i"; riscv,isa-extensions = "i", "m", "a", "f", "d", "c", - "zicntr", "zicsr", "zifencei", - "zihpm"; + "zca", "zcd", "zicntr", "zicsr", + "zifencei", "zihpm"; reg = <19>; i-cache-block-size = <64>; i-cache-size = <65536>; @@ -759,8 +759,8 @@ cpu20: cpu@20 { riscv,isa = "rv64imafdc"; riscv,isa-base = "rv64i"; riscv,isa-extensions = "i", "m", "a", "f", "d", "c", - "zicntr", "zicsr", "zifencei", - "zihpm"; + "zca", "zcd", "zicntr", "zicsr", + "zifencei", "zihpm"; reg = <20>; i-cache-block-size = <64>; i-cache-size = <65536>; @@ -784,8 +784,8 @@ cpu21: cpu@21 { riscv,isa = "rv64imafdc"; riscv,isa-base = "rv64i"; riscv,isa-extensions = "i", "m", "a", "f", "d", "c", - "zicntr", "zicsr", "zifencei", - "zihpm"; + "zca", "zcd", "zicntr", "zicsr", + "zifencei", "zihpm"; reg = <21>; i-cache-block-size = <64>; i-cache-size = <65536>; @@ -809,8 +809,8 @@ cpu22: cpu@22 { riscv,isa = "rv64imafdc"; riscv,isa-base = "rv64i"; riscv,isa-extensions = "i", "m", "a", "f", "d", "c", - "zicntr", "zicsr", "zifencei", - "zihpm"; + "zca", "zcd", "zicntr", "zicsr", + "zifencei", "zihpm"; reg = <22>; i-cache-block-size = <64>; i-cache-size = <65536>; @@ -834,8 +834,8 @@ cpu23: cpu@23 { riscv,isa = "rv64imafdc"; riscv,isa-base = "rv64i"; riscv,isa-extensions = "i", "m", "a", "f", "d", "c", - "zicntr", "zicsr", "zifencei", - "zihpm"; + "zca", "zcd", "zicntr", "zicsr", + "zifencei", "zihpm"; reg = <23>; i-cache-block-size = <64>; i-cache-size = <65536>; @@ -859,8 +859,8 @@ cpu24: cpu@24 { riscv,isa = "rv64imafdc"; riscv,isa-base = "rv64i"; riscv,isa-extensions = "i", "m", "a", "f", "d", "c", - "zicntr", "zicsr", "zifencei", - "zihpm"; + "zca", "zcd", "zicntr", "zicsr", + "zifencei", "zihpm"; reg = <24>; i-cache-block-size = <64>; i-cache-size = <65536>; @@ -884,8 +884,8 @@ cpu25: cpu@25 { riscv,isa = "rv64imafdc"; riscv,isa-base = "rv64i"; riscv,isa-extensions = "i", "m", "a", "f", "d", "c", - "zicntr", "zicsr", "zifencei", - "zihpm"; + "zca", "zcd", "zicntr", "zicsr", + "zifencei", "zihpm"; reg = <25>; i-cache-block-size = <64>; i-cache-size = <65536>; @@ -909,8 +909,8 @@ cpu26: cpu@26 { riscv,isa = "rv64imafdc"; riscv,isa-base = "rv64i"; riscv,isa-extensions = "i", "m", "a", "f", "d", "c", - "zicntr", "zicsr", "zifencei", - "zihpm"; + "zca", "zcd", "zicntr", "zicsr", + "zifencei", "zihpm"; reg = <26>; i-cache-block-size = <64>; i-cache-size = <65536>; @@ -934,8 +934,8 @@ cpu27: cpu@27 { riscv,isa = "rv64imafdc"; riscv,isa-base = "rv64i"; riscv,isa-extensions = "i", "m", "a", "f", "d", "c", - "zicntr", "zicsr", "zifencei", - "zihpm"; + "zca", "zcd", "zicntr", "zicsr", + "zifencei", "zihpm"; reg = <27>; i-cache-block-size = <64>; i-cache-size = <65536>; @@ -959,8 +959,8 @@ cpu28: cpu@28 { riscv,isa = "rv64imafdc"; riscv,isa-base = "rv64i"; riscv,isa-extensions = "i", "m", "a", "f", "d", "c", - "zicntr", "zicsr", "zifencei", - "zihpm"; + "zca", "zcd", "zicntr", "zicsr", + "zifencei", "zihpm"; reg = <28>; i-cache-block-size = <64>; i-cache-size = <65536>; @@ -984,8 +984,8 @@ cpu29: cpu@29 { riscv,isa = "rv64imafdc"; riscv,isa-base = "rv64i"; riscv,isa-extensions = "i", "m", "a", "f", "d", "c", - "zicntr", "zicsr", "zifencei", - "zihpm"; + "zca", "zcd", "zicntr", "zicsr", + "zifencei", "zihpm"; reg = <29>; i-cache-block-size = <64>; i-cache-size = <65536>; @@ -1009,8 +1009,8 @@ cpu30: cpu@30 { riscv,isa = "rv64imafdc"; riscv,isa-base = "rv64i"; riscv,isa-extensions = "i", "m", "a", "f", "d", "c", - "zicntr", "zicsr", "zifencei", - "zihpm"; + "zca", "zcd", "zicntr", "zicsr", + "zifencei", "zihpm"; reg = <30>; i-cache-block-size = <64>; i-cache-size = <65536>; @@ -1034,8 +1034,8 @@ cpu31: cpu@31 { riscv,isa = "rv64imafdc"; riscv,isa-base = "rv64i"; riscv,isa-extensions = "i", "m", "a", "f", "d", "c", - "zicntr", "zicsr", "zifencei", - "zihpm"; + "zca", "zcd", "zicntr", "zicsr", + "zifencei", "zihpm"; reg = <31>; i-cache-block-size = <64>; i-cache-size = <65536>; @@ -1059,8 +1059,8 @@ cpu32: cpu@32 { riscv,isa = "rv64imafdc"; riscv,isa-base = "rv64i"; riscv,isa-extensions = "i", "m", "a", "f", "d", "c", - "zicntr", "zicsr", "zifencei", - "zihpm"; + "zca", "zcd", "zicntr", "zicsr", + "zifencei", "zihpm"; reg = <32>; i-cache-block-size = <64>; i-cache-size = <65536>; @@ -1084,8 +1084,8 @@ cpu33: cpu@33 { riscv,isa = "rv64imafdc"; riscv,isa-base = "rv64i"; riscv,isa-extensions = "i", "m", "a", "f", "d", "c", - "zicntr", "zicsr", "zifencei", - "zihpm"; + "zca", "zcd", "zicntr", "zicsr", + "zifencei", "zihpm"; reg = <33>; i-cache-block-size = <64>; i-cache-size = <65536>; @@ -1109,8 +1109,8 @@ cpu34: cpu@34 { riscv,isa = "rv64imafdc"; riscv,isa-base = "rv64i"; riscv,isa-extensions = "i", "m", "a", "f", "d", "c", - "zicntr", "zicsr", "zifencei", - "zihpm"; + "zca", "zcd", "zicntr", "zicsr", + "zifencei", "zihpm"; reg = <34>; i-cache-block-size = <64>; i-cache-size = <65536>; @@ -1134,8 +1134,8 @@ cpu35: cpu@35 { riscv,isa = "rv64imafdc"; riscv,isa-base = "rv64i"; riscv,isa-extensions = "i", "m", "a", "f", "d", "c", - "zicntr", "zicsr", "zifencei", - "zihpm"; + "zca", "zcd", "zicntr", "zicsr", + "zifencei", "zihpm"; reg = <35>; i-cache-block-size = <64>; i-cache-size = <65536>; @@ -1159,8 +1159,8 @@ cpu36: cpu@36 { riscv,isa = "rv64imafdc"; riscv,isa-base = "rv64i"; riscv,isa-extensions = "i", "m", "a", "f", "d", "c", - "zicntr", "zicsr", "zifencei", - "zihpm"; + "zca", "zcd", "zicntr", "zicsr", + "zifencei", "zihpm"; reg = <36>; i-cache-block-size = <64>; i-cache-size = <65536>; @@ -1184,8 +1184,8 @@ cpu37: cpu@37 { riscv,isa = "rv64imafdc"; riscv,isa-base = "rv64i"; riscv,isa-extensions = "i", "m", "a", "f", "d", "c", - "zicntr", "zicsr", "zifencei", - "zihpm"; + "zca", "zcd", "zicntr", "zicsr", + "zifencei", "zihpm"; reg = <37>; i-cache-block-size = <64>; i-cache-size = <65536>; @@ -1209,8 +1209,8 @@ cpu38: cpu@38 { riscv,isa = "rv64imafdc"; riscv,isa-base = "rv64i"; riscv,isa-extensions = "i", "m", "a", "f", "d", "c", - "zicntr", "zicsr", "zifencei", - "zihpm"; + "zca", "zcd", "zicntr", "zicsr", + "zifencei", "zihpm"; reg = <38>; i-cache-block-size = <64>; i-cache-size = <65536>; @@ -1234,8 +1234,8 @@ cpu39: cpu@39 { riscv,isa = "rv64imafdc"; riscv,isa-base = "rv64i"; riscv,isa-extensions = "i", "m", "a", "f", "d", "c", - "zicntr", "zicsr", "zifencei", - "zihpm"; + "zca", "zcd", "zicntr", "zicsr", + "zifencei", "zihpm"; reg = <39>; i-cache-block-size = <64>; i-cache-size = <65536>; @@ -1259,8 +1259,8 @@ cpu40: cpu@40 { riscv,isa = "rv64imafdc"; riscv,isa-base = "rv64i"; riscv,isa-extensions = "i", "m", "a", "f", "d", "c", - "zicntr", "zicsr", "zifencei", - "zihpm"; + "zca", "zcd", "zicntr", "zicsr", + "zifencei", "zihpm"; reg = <40>; i-cache-block-size = <64>; i-cache-size = <65536>; @@ -1284,8 +1284,8 @@ cpu41: cpu@41 { riscv,isa = "rv64imafdc"; riscv,isa-base = "rv64i"; riscv,isa-extensions = "i", "m", "a", "f", "d", "c", - "zicntr", "zicsr", "zifencei", - "zihpm"; + "zca", "zcd", "zicntr", "zicsr", + "zifencei", "zihpm"; reg = <41>; i-cache-block-size = <64>; i-cache-size = <65536>; @@ -1309,8 +1309,8 @@ cpu42: cpu@42 { riscv,isa = "rv64imafdc"; riscv,isa-base = "rv64i"; riscv,isa-extensions = "i", "m", "a", "f", "d", "c", - "zicntr", "zicsr", "zifencei", - "zihpm"; + "zca", "zcd", "zicntr", "zicsr", + "zifencei", "zihpm"; reg = <42>; i-cache-block-size = <64>; i-cache-size = <65536>; @@ -1334,8 +1334,8 @@ cpu43: cpu@43 { riscv,isa = "rv64imafdc"; riscv,isa-base = "rv64i"; riscv,isa-extensions = "i", "m", "a", "f", "d", "c", - "zicntr", "zicsr", "zifencei", - "zihpm"; + "zca", "zcd", "zicntr", "zicsr", + "zifencei", "zihpm"; reg = <43>; i-cache-block-size = <64>; i-cache-size = <65536>; @@ -1359,8 +1359,8 @@ cpu44: cpu@44 { riscv,isa = "rv64imafdc"; riscv,isa-base = "rv64i"; riscv,isa-extensions = "i", "m", "a", "f", "d", "c", - "zicntr", "zicsr", "zifencei", - "zihpm"; + "zca", "zcd", "zicntr", "zicsr", + "zifencei", "zihpm"; reg = <44>; i-cache-block-size = <64>; i-cache-size = <65536>; @@ -1384,8 +1384,8 @@ cpu45: cpu@45 { riscv,isa = "rv64imafdc"; riscv,isa-base = "rv64i"; riscv,isa-extensions = "i", "m", "a", "f", "d", "c", - "zicntr", "zicsr", "zifencei", - "zihpm"; + "zca", "zcd", "zicntr", "zicsr", + "zifencei", "zihpm"; reg = <45>; i-cache-block-size = <64>; i-cache-size = <65536>; @@ -1409,8 +1409,8 @@ cpu46: cpu@46 { riscv,isa = "rv64imafdc"; riscv,isa-base = "rv64i"; riscv,isa-extensions = "i", "m", "a", "f", "d", "c", - "zicntr", "zicsr", "zifencei", - "zihpm"; + "zca", "zcd", "zicntr", "zicsr", + "zifencei", "zihpm"; reg = <46>; i-cache-block-size = <64>; i-cache-size = <65536>; @@ -1434,8 +1434,8 @@ cpu47: cpu@47 { riscv,isa = "rv64imafdc"; riscv,isa-base = "rv64i"; riscv,isa-extensions = "i", "m", "a", "f", "d", "c", - "zicntr", "zicsr", "zifencei", - "zihpm"; + "zca", "zcd", "zicntr", "zicsr", + "zifencei", "zihpm"; reg = <47>; i-cache-block-size = <64>; i-cache-size = <65536>; @@ -1459,8 +1459,8 @@ cpu48: cpu@48 { riscv,isa = "rv64imafdc"; riscv,isa-base = "rv64i"; riscv,isa-extensions = "i", "m", "a", "f", "d", "c", - "zicntr", "zicsr", "zifencei", - "zihpm"; + "zca", "zcd", "zicntr", "zicsr", + "zifencei", "zihpm"; reg = <48>; i-cache-block-size = <64>; i-cache-size = <65536>; @@ -1484,8 +1484,8 @@ cpu49: cpu@49 { riscv,isa = "rv64imafdc"; riscv,isa-base = "rv64i"; riscv,isa-extensions = "i", "m", "a", "f", "d", "c", - "zicntr", "zicsr", "zifencei", - "zihpm"; + "zca", "zcd", "zicntr", "zicsr", + "zifencei", "zihpm"; reg = <49>; i-cache-block-size = <64>; i-cache-size = <65536>; @@ -1509,8 +1509,8 @@ cpu50: cpu@50 { riscv,isa = "rv64imafdc"; riscv,isa-base = "rv64i"; riscv,isa-extensions = "i", "m", "a", "f", "d", "c", - "zicntr", "zicsr", "zifencei", - "zihpm"; + "zca", "zcd", "zicntr", "zicsr", + "zifencei", "zihpm"; reg = <50>; i-cache-block-size = <64>; i-cache-size = <65536>; @@ -1534,8 +1534,8 @@ cpu51: cpu@51 { riscv,isa = "rv64imafdc"; riscv,isa-base = "rv64i"; riscv,isa-extensions = "i", "m", "a", "f", "d", "c", - "zicntr", "zicsr", "zifencei", - "zihpm"; + "zca", "zcd", "zicntr", "zicsr", + "zifencei", "zihpm"; reg = <51>; i-cache-block-size = <64>; i-cache-size = <65536>; @@ -1559,8 +1559,8 @@ cpu52: cpu@52 { riscv,isa = "rv64imafdc"; riscv,isa-base = "rv64i"; riscv,isa-extensions = "i", "m", "a", "f", "d", "c", - "zicntr", "zicsr", "zifencei", - "zihpm"; + "zca", "zcd", "zicntr", "zicsr", + "zifencei", "zihpm"; reg = <52>; i-cache-block-size = <64>; i-cache-size = <65536>; @@ -1584,8 +1584,8 @@ cpu53: cpu@53 { riscv,isa = "rv64imafdc"; riscv,isa-base = "rv64i"; riscv,isa-extensions = "i", "m", "a", "f", "d", "c", - "zicntr", "zicsr", "zifencei", - "zihpm"; + "zca", "zcd", "zicntr", "zicsr", + "zifencei", "zihpm"; reg = <53>; i-cache-block-size = <64>; i-cache-size = <65536>; @@ -1609,8 +1609,8 @@ cpu54: cpu@54 { riscv,isa = "rv64imafdc"; riscv,isa-base = "rv64i"; riscv,isa-extensions = "i", "m", "a", "f", "d", "c", - "zicntr", "zicsr", "zifencei", - "zihpm"; + "zca", "zcd", "zicntr", "zicsr", + "zifencei", "zihpm"; reg = <54>; i-cache-block-size = <64>; i-cache-size = <65536>; @@ -1634,8 +1634,8 @@ cpu55: cpu@55 { riscv,isa = "rv64imafdc"; riscv,isa-base = "rv64i"; riscv,isa-extensions = "i", "m", "a", "f", "d", "c", - "zicntr", "zicsr", "zifencei", - "zihpm"; + "zca", "zcd", "zicntr", "zicsr", + "zifencei", "zihpm"; reg = <55>; i-cache-block-size = <64>; i-cache-size = <65536>; @@ -1659,8 +1659,8 @@ cpu56: cpu@56 { riscv,isa = "rv64imafdc"; riscv,isa-base = "rv64i"; riscv,isa-extensions = "i", "m", "a", "f", "d", "c", - "zicntr", "zicsr", "zifencei", - "zihpm"; + "zca", "zcd", "zicntr", "zicsr", + "zifencei", "zihpm"; reg = <56>; i-cache-block-size = <64>; i-cache-size = <65536>; @@ -1684,8 +1684,8 @@ cpu57: cpu@57 { riscv,isa = "rv64imafdc"; riscv,isa-base = "rv64i"; riscv,isa-extensions = "i", "m", "a", "f", "d", "c", - "zicntr", "zicsr", "zifencei", - "zihpm"; + "zca", "zcd", "zicntr", "zicsr", + "zifencei", "zihpm"; reg = <57>; i-cache-block-size = <64>; i-cache-size = <65536>; @@ -1709,8 +1709,8 @@ cpu58: cpu@58 { riscv,isa = "rv64imafdc"; riscv,isa-base = "rv64i"; riscv,isa-extensions = "i", "m", "a", "f", "d", "c", - "zicntr", "zicsr", "zifencei", - "zihpm"; + "zca", "zcd", "zicntr", "zicsr", + "zifencei", "zihpm"; reg = <58>; i-cache-block-size = <64>; i-cache-size = <65536>; @@ -1734,8 +1734,8 @@ cpu59: cpu@59 { riscv,isa = "rv64imafdc"; riscv,isa-base = "rv64i"; riscv,isa-extensions = "i", "m", "a", "f", "d", "c", - "zicntr", "zicsr", "zifencei", - "zihpm"; + "zca", "zcd", "zicntr", "zicsr", + "zifencei", "zihpm"; reg = <59>; i-cache-block-size = <64>; i-cache-size = <65536>; @@ -1759,8 +1759,8 @@ cpu60: cpu@60 { riscv,isa = "rv64imafdc"; riscv,isa-base = "rv64i"; riscv,isa-extensions = "i", "m", "a", "f", "d", "c", - "zicntr", "zicsr", "zifencei", - "zihpm"; + "zca", "zcd", "zicntr", "zicsr", + "zifencei", "zihpm"; reg = <60>; i-cache-block-size = <64>; i-cache-size = <65536>; @@ -1784,8 +1784,8 @@ cpu61: cpu@61 { riscv,isa = "rv64imafdc"; riscv,isa-base = "rv64i"; riscv,isa-extensions = "i", "m", "a", "f", "d", "c", - "zicntr", "zicsr", "zifencei", - "zihpm"; + "zca", "zcd", "zicntr", "zicsr", + "zifencei", "zihpm"; reg = <61>; i-cache-block-size = <64>; i-cache-size = <65536>; @@ -1809,8 +1809,8 @@ cpu62: cpu@62 { riscv,isa = "rv64imafdc"; riscv,isa-base = "rv64i"; riscv,isa-extensions = "i", "m", "a", "f", "d", "c", - "zicntr", "zicsr", "zifencei", - "zihpm"; + "zca", "zcd", "zicntr", "zicsr", + "zifencei", "zihpm"; reg = <62>; i-cache-block-size = <64>; i-cache-size = <65536>; @@ -1834,8 +1834,8 @@ cpu63: cpu@63 { riscv,isa = "rv64imafdc"; riscv,isa-base = "rv64i"; riscv,isa-extensions = "i", "m", "a", "f", "d", "c", - "zicntr", "zicsr", "zifencei", - "zihpm"; + "zca", "zcd", "zicntr", "zicsr", + "zifencei", "zihpm"; reg = <63>; i-cache-block-size = <64>; i-cache-size = <65536>; diff --git a/arch/riscv/boot/dts/starfive/jh7100.dtsi b/arch/riscv/boot/dts/starfive/jh7100.dtsi index 9a2e9583af88..7e53c539c871 100644 --- a/arch/riscv/boot/dts/starfive/jh7100.dtsi +++ b/arch/riscv/boot/dts/starfive/jh7100.dtsi @@ -35,8 +35,8 @@ U74_0: cpu@0 { next-level-cache = <&ccache>; riscv,isa = "rv64imafdc"; riscv,isa-base = "rv64i"; - riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "zicntr", "zicsr", - "zifencei", "zihpm"; + riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "zca", "zcd", "zicntr", + "zicsr", "zifencei", "zihpm"; tlb-split; cpu0_intc: interrupt-controller { @@ -64,8 +64,8 @@ U74_1: cpu@1 { next-level-cache = <&ccache>; riscv,isa = "rv64imafdc"; riscv,isa-base = "rv64i"; - riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "zicntr", "zicsr", - "zifencei", "zihpm"; + riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "zca", "zcd", "zicntr", + "zicsr", "zifencei", "zihpm"; tlb-split; cpu1_intc: interrupt-controller { diff --git a/arch/riscv/boot/dts/starfive/jh7110.dtsi b/arch/riscv/boot/dts/starfive/jh7110.dtsi index 4a5708f7fcf7..f01024f50561 100644 --- a/arch/riscv/boot/dts/starfive/jh7110.dtsi +++ b/arch/riscv/boot/dts/starfive/jh7110.dtsi @@ -29,8 +29,8 @@ S7_0: cpu@0 { next-level-cache = <&ccache>; riscv,isa = "rv64imac_zba_zbb"; riscv,isa-base = "rv64i"; - riscv,isa-extensions = "i", "m", "a", "c", "zba", "zbb", "zicntr", "zicsr", - "zifencei", "zihpm"; + riscv,isa-extensions = "i", "m", "a", "c", "zba", "zbb", "zca", "zicntr", + "zicsr", "zifencei", "zihpm"; status = "disabled"; cpu0_intc: interrupt-controller { @@ -58,8 +58,8 @@ U74_1: cpu@1 { next-level-cache = <&ccache>; riscv,isa = "rv64imafdc_zba_zbb"; riscv,isa-base = "rv64i"; - riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "zba", "zbb", "zicntr", - "zicsr", "zifencei", "zihpm"; + riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "zba", "zbb", "zca", + "zcd", "zicntr", "zicsr", "zifencei", "zihpm"; tlb-split; operating-points-v2 = <&cpu_opp>; clocks = <&syscrg JH7110_SYSCLK_CPU_CORE>; @@ -91,8 +91,8 @@ U74_2: cpu@2 { next-level-cache = <&ccache>; riscv,isa = "rv64imafdc_zba_zbb"; riscv,isa-base = "rv64i"; - riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "zba", "zbb", "zicntr", - "zicsr", "zifencei", "zihpm"; + riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "zba", "zbb", "zca", + "zcd", "zicntr", "zicsr", "zifencei", "zihpm"; tlb-split; operating-points-v2 = <&cpu_opp>; clocks = <&syscrg JH7110_SYSCLK_CPU_CORE>; @@ -124,8 +124,8 @@ U74_3: cpu@3 { next-level-cache = <&ccache>; riscv,isa = "rv64imafdc_zba_zbb"; riscv,isa-base = "rv64i"; - riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "zba", "zbb", "zicntr", - "zicsr", "zifencei", "zihpm"; + riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "zba", "zbb", "zca", + "zcd", "zicntr", "zicsr", "zifencei", "zihpm"; tlb-split; operating-points-v2 = <&cpu_opp>; clocks = <&syscrg JH7110_SYSCLK_CPU_CORE>; @@ -157,8 +157,8 @@ U74_4: cpu@4 { next-level-cache = <&ccache>; riscv,isa = "rv64imafdc_zba_zbb"; riscv,isa-base = "rv64i"; - riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "zba", "zbb", "zicntr", - "zicsr", "zifencei", "zihpm"; + riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "zba", "zbb", "zca", + "zcd", "zicntr", "zicsr", "zifencei", "zihpm"; tlb-split; operating-points-v2 = <&cpu_opp>; clocks = <&syscrg JH7110_SYSCLK_CPU_CORE>; diff --git a/arch/riscv/boot/dts/thead/th1520.dtsi b/arch/riscv/boot/dts/thead/th1520.dtsi index 8b915e206f3a..530355bda7c1 100644 --- a/arch/riscv/boot/dts/thead/th1520.dtsi +++ b/arch/riscv/boot/dts/thead/th1520.dtsi @@ -21,8 +21,8 @@ c910_0: cpu@0 { device_type = "cpu"; riscv,isa = "rv64imafdc"; riscv,isa-base = "rv64i"; - riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "zicntr", "zicsr", - "zifencei", "zihpm"; + riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "zca", "zcd", "zicntr", + "zicsr", "zifencei", "zihpm"; reg = <0>; i-cache-block-size = <64>; i-cache-size = <65536>; @@ -45,8 +45,8 @@ c910_1: cpu@1 { device_type = "cpu"; riscv,isa = "rv64imafdc"; riscv,isa-base = "rv64i"; - riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "zicntr", "zicsr", - "zifencei", "zihpm"; + riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "zca", "zcd", "zicntr", + "zicsr", "zifencei", "zihpm"; reg = <1>; i-cache-block-size = <64>; i-cache-size = <65536>; @@ -69,8 +69,8 @@ c910_2: cpu@2 { device_type = "cpu"; riscv,isa = "rv64imafdc"; riscv,isa-base = "rv64i"; - riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "zicntr", "zicsr", - "zifencei", "zihpm"; + riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "zca", "zcd", "zicntr", + "zicsr", "zifencei", "zihpm"; reg = <2>; i-cache-block-size = <64>; i-cache-size = <65536>; @@ -93,8 +93,8 @@ c910_3: cpu@3 { device_type = "cpu"; riscv,isa = "rv64imafdc"; riscv,isa-base = "rv64i"; - riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "zicntr", "zicsr", - "zifencei", "zihpm"; + riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "zca", "zcd", "zicntr", + "zicsr", "zifencei", "zihpm"; reg = <3>; i-cache-block-size = <64>; i-cache-size = <65536>; From patchwork Thu Apr 18 12:42:26 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?b?Q2zDqW1lbnQgTMOpZ2Vy?= X-Patchwork-Id: 13634661 Received: from mail-lj1-f179.google.com (mail-lj1-f179.google.com [209.85.208.179]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 2973D15FA8F for ; Thu, 18 Apr 2024 12:43:59 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.208.179 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1713444241; cv=none; b=hzhELTk8mAwgOidEcHJnXSABr4FwARkK2pBwfmosB8AR1q9IMyAu2/j1+8xnKpTTin9yx7Nj4ZcmsiOfbZklnUdAv5zQ43VZRQPRiEmB8tvbnbRt+VGMW31qjsH3G7E2LBKMobMdZxS4SyQI4mRznCcR0Y23yeXVT9nXqP3Bdq4= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1713444241; c=relaxed/simple; bh=I+l+JkVVH9yyH4nAg3oBjtzyRDSG/5kxRFfJnm0mGaU=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=MqgDXfry1fNjGdPYYFi/HzyxRVFTCWbubtAuakfNd67fxVDDKccpmUix2irFPvVOdTW7UilVW3wJgQq63N9eG544nySihIi8fJkqrkmBbA5V6L4HgV3XoULTPvohh5J85AqIKIuyMIV9FO0ApuTZ2K2JnJpIYNkBzBrX42VGhfs= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=rivosinc.com; spf=pass smtp.mailfrom=rivosinc.com; dkim=pass (2048-bit key) header.d=rivosinc-com.20230601.gappssmtp.com header.i=@rivosinc-com.20230601.gappssmtp.com header.b=SFqAV6eu; arc=none smtp.client-ip=209.85.208.179 Authentication-Results: smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=rivosinc.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=rivosinc.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=rivosinc-com.20230601.gappssmtp.com header.i=@rivosinc-com.20230601.gappssmtp.com header.b="SFqAV6eu" Received: by mail-lj1-f179.google.com with SMTP id 38308e7fff4ca-2dac628f08fso2491121fa.3 for ; Thu, 18 Apr 2024 05:43:58 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=rivosinc-com.20230601.gappssmtp.com; s=20230601; t=1713444237; x=1714049037; darn=vger.kernel.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=VqinG7vx90NXqlB3cCAWzb6LZzjfwkXKYqGSSxQF2QU=; b=SFqAV6euphnHbeuqYe1KEqDKSPsC1135ph1AH0o0FVXjt1EJJYyQsmpjhEK7D4Xbvg RoNqIZarqw+FTLtg0itCZS0c2UyG0cYv86n5Mo8IR5Xmh06IHaVwiAe4gSUmBXC5fzJh d6el6IuvBHDCJ8H+U1Y3IE53r+v0twX4+taSZKUGgA0Fe9xbY9B/MEA/maF4Wve5p9FP HIiZJsHsfpHauOkLRpuM+3tL/gNiyihBtyOvdnFab0Q1ASLkF/t+Iv2UzY68BQA7Zvdm +MnG+SuM735QaV3PkNN+U7n8Gb86Ow2yIPKKDnrtCOSFNNByNDR6b2cu85Bden/X+DNC v92g== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1713444237; x=1714049037; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=VqinG7vx90NXqlB3cCAWzb6LZzjfwkXKYqGSSxQF2QU=; b=ffFDqBEMjyHs4/Ff+JUqieCnWl+m2xlWF3WYagfWYs3QbSqh6Z7z0AuBeQaoaR5YE4 1vmQRw9RbDh7WHkGeEKSQF8oCT5Wh7XrDalTbWDeAPX0AW/zD6GSJyMQ3L+j/ojuZqR5 5A9r1u3jxv0K0up8WGLKIV5CquBpzVXlt2kbJ08UjT0JHGO5Xo8dRICyJLyOzAxtgnb3 fyGnf7GXDASqeyk4IzrMX9lSb2WISUc0c9No59KZ3Jtp/pYuwxhh4PIlcEs7GqBxqJ58 V+3ZAdx5M7RKzdC4vdSS/iP1Z7lKFn36eURHyzDxrMixoksCS33gOMlHOK7xqFiaGVWz pU6A== X-Forwarded-Encrypted: i=1; AJvYcCUcVtlk0h2bkBSv0vESXb/gp1dhhw66RgW+igvlWmR8jCLIVUo7m4H9WlxJk35XnDgVYdP7wzuqfwb6Q0CVFpDwjvT4 X-Gm-Message-State: AOJu0YwLGriEZF8uVSx8Dn8poUKZWCZMJy7NAP3NegpCAjAY8s2kqdyY b6k5IBXhC+t1jPzTv0rO6hGfleyprjb7agR8gQs7zEHSY9Lu1gEg6++yOsSbA8A= X-Google-Smtp-Source: AGHT+IFXBu2QshCmevcqDNI9qC29EYmJ3ZQBbQK0N8BE6U3hHj6+0OsosVqzAbOLR3+7A5/jwaHB/w== X-Received: by 2002:a2e:8387:0:b0:2d6:c59e:37c0 with SMTP id x7-20020a2e8387000000b002d6c59e37c0mr1507578ljg.2.1713444237161; Thu, 18 Apr 2024 05:43:57 -0700 (PDT) Received: from carbon-x1.. ([2a01:e0a:999:a3a0:7b64:4d1d:16d8:e38b]) by smtp.gmail.com with ESMTPSA id bi18-20020a05600c3d9200b00418d5b16fa2sm3373412wmb.30.2024.04.18.05.43.56 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 18 Apr 2024 05:43:56 -0700 (PDT) From: =?utf-8?b?Q2zDqW1lbnQgTMOpZ2Vy?= To: Jonathan Corbet , Paul Walmsley , Palmer Dabbelt , Albert Ou , Conor Dooley , Rob Herring , Krzysztof Kozlowski , Anup Patel , Shuah Khan Cc: =?utf-8?b?Q2zDqW1lbnQgTMOpZ2Vy?= , Atish Patra , linux-doc@vger.kernel.org, linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, kvm@vger.kernel.org, kvm-riscv@lists.infradead.org, linux-kselftest@vger.kernel.org Subject: [PATCH v2 03/12] dt-bindings: riscv: add Zc* extension rules implied by C extension Date: Thu, 18 Apr 2024 14:42:26 +0200 Message-ID: <20240418124300.1387978-4-cleger@rivosinc.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20240418124300.1387978-1-cleger@rivosinc.com> References: <20240418124300.1387978-1-cleger@rivosinc.com> Precedence: bulk X-Mailing-List: kvm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 As stated by Zc* spec: "As C defines the same instructions as Zca, Zcf and Zcd, the rule is that: - C always implies Zca - C+F implies Zcf (RV32 only) - C+D implies Zcd" Add additionnal validation rules to enforce this in dts. Signed-off-by: Clément Léger --- .../devicetree/bindings/riscv/cpus.yaml | 8 +++-- .../devicetree/bindings/riscv/extensions.yaml | 34 +++++++++++++++++++ 2 files changed, 39 insertions(+), 3 deletions(-) diff --git a/Documentation/devicetree/bindings/riscv/cpus.yaml b/Documentation/devicetree/bindings/riscv/cpus.yaml index d87dd50f1a4b..c4e2c65437b1 100644 --- a/Documentation/devicetree/bindings/riscv/cpus.yaml +++ b/Documentation/devicetree/bindings/riscv/cpus.yaml @@ -168,7 +168,7 @@ examples: i-cache-size = <16384>; reg = <0>; riscv,isa-base = "rv64i"; - riscv,isa-extensions = "i", "m", "a", "c"; + riscv,isa-extensions = "i", "m", "a", "c", "zca"; cpu_intc0: interrupt-controller { #interrupt-cells = <1>; @@ -194,7 +194,8 @@ examples: reg = <1>; tlb-split; riscv,isa-base = "rv64i"; - riscv,isa-extensions = "i", "m", "a", "f", "d", "c"; + riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "zca", + "zcd"; cpu_intc1: interrupt-controller { #interrupt-cells = <1>; @@ -215,7 +216,8 @@ examples: compatible = "riscv"; mmu-type = "riscv,sv48"; riscv,isa-base = "rv64i"; - riscv,isa-extensions = "i", "m", "a", "f", "d", "c"; + riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "zca", + "zcd"; interrupt-controller { #interrupt-cells = <1>; diff --git a/Documentation/devicetree/bindings/riscv/extensions.yaml b/Documentation/devicetree/bindings/riscv/extensions.yaml index db7daf22b863..0172cbaa13ca 100644 --- a/Documentation/devicetree/bindings/riscv/extensions.yaml +++ b/Documentation/devicetree/bindings/riscv/extensions.yaml @@ -549,6 +549,23 @@ properties: const: zca - contains: const: f + # C extension implies Zca + - if: + contains: + const: c + then: + contains: + const: zca + # C extension implies Zcd if d + - if: + allOf: + - contains: + const: c + - contains: + const: d + then: + contains: + const: zcd allOf: # Zcf extension does not exists on rv64 @@ -566,6 +583,23 @@ allOf: not: contains: const: zcf + # C extension implies Zcf if f on rv32 only + - if: + properties: + riscv,isa-extensions: + allOf: + - contains: + const: c + - contains: + const: f + riscv,isa-base: + contains: + const: rv32i + then: + properties: + riscv,isa-extensions: + contains: + const: zcf additionalProperties: true ... From patchwork Thu Apr 18 12:42:27 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?b?Q2zDqW1lbnQgTMOpZ2Vy?= X-Patchwork-Id: 13634662 Received: from mail-wr1-f50.google.com (mail-wr1-f50.google.com [209.85.221.50]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 6969415FD12 for ; Thu, 18 Apr 2024 12:44:00 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.221.50 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1713444243; cv=none; b=oiDckT2ngA4k17xlcwNmRUrAmXrkhEZAqK9iUfnBYNx8QPegPgtaiwTyPTCxrkzonl0Bqe5LwZeVzq6kTuouxN2Rgcx6q8u58AjWG1Ol4MZy1o4goaXtTPsq401tzK9lRw7neGw55iE9eU0UF4Mq+LHOKtXwI5jNP+oBMS74Yp8= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1713444243; c=relaxed/simple; bh=SrpAxjIaY3RV8BXenxbFlBJKJmsCS8qPO2iasFfYMfo=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=BzcVUVyAAFI4gwx4riatTt13XuzUxt7czdazcPBnPW8F1f6GuJt7K+LR1Ytefor05gKBKcaj3XvfbIWAkYtc45WM4y3YwTA+CngfpgejYBuFxLglntVdDZ6nuN5B808zi8s+EJgtppSoAPbQp9Wqbu2lAoqAY2Fylvjpcjh5ErY= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=rivosinc.com; spf=pass smtp.mailfrom=rivosinc.com; dkim=pass (2048-bit key) header.d=rivosinc-com.20230601.gappssmtp.com header.i=@rivosinc-com.20230601.gappssmtp.com header.b=F0vGwcL6; arc=none smtp.client-ip=209.85.221.50 Authentication-Results: smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=rivosinc.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=rivosinc.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=rivosinc-com.20230601.gappssmtp.com header.i=@rivosinc-com.20230601.gappssmtp.com header.b="F0vGwcL6" Received: by mail-wr1-f50.google.com with SMTP id ffacd0b85a97d-349a31b2babso94916f8f.2 for ; Thu, 18 Apr 2024 05:44:00 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=rivosinc-com.20230601.gappssmtp.com; s=20230601; t=1713444239; x=1714049039; darn=vger.kernel.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=hAM+PbC/Wqgx6Q9RB0x39wuP2KdW0QgVrrLDnXaQ5i0=; b=F0vGwcL6w3PptZ6deCyKLtJ9QDT+nQmUG1cZnZJrU+mgbKRzgJSpnwGP+40BhVL3h0 S0ncc8TRLr0qWrR4f2R6xIB6x62GeDnzSsOBUGCjtIDv700LNORnFz6MuIZBhlEbPR6G OA9YKwQQrX9ClTRxh50P9AhSBIw+HLEcW1+UHU2xCuKAPZpZivgrmoG1gtMI1kruOeo4 eZ3KWIcBIfM2SdXTEXipBQ1n1k2gCiArxQO1cyXnCbWSs/if6iWVvQPOpNtGTtaGOvTR yUWaEV9J4A/0Iu1LiRpU1OkEPwcrYM+lZAUHTC3GQ1GC0urxOk7kMzMPCqsz5FJ1xXH+ VZ5g== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1713444239; x=1714049039; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=hAM+PbC/Wqgx6Q9RB0x39wuP2KdW0QgVrrLDnXaQ5i0=; b=rgqMt1/Jp3beM6bDaCzga7RcEtvO9VhnsbkFxvK/9UadVDcRyvOudY9ZRzkmBvlb2R WRBY32rm1Xb391kJb398BAMSa9HwPtC9+4Iual7C7QVHoS+7tEBezAngAP9Ssh1nsGq/ 12OpC7YH9JkI8SSYekxq1qfXG0z31r2cgCL/9u6hXbg9afgiVEgKcIkZNPgXVAknOPHU 3beC6zbQHo2aMsudON4aNnX27aR4DUDDTKYxGVwnKZ522t/jL9Yzi6xFPQeJGRbH/dlW mtqLns5IDIUz4JYtJc5IyYFH0IOA8EoyMdaqi9E8znlFuFmu2udEuvFnUlZvfATGXSut PIqw== X-Forwarded-Encrypted: i=1; AJvYcCWA4NYUbUrG/M6MIQEMipAtp1KWRnTrKzEJoMBX7b0QMFl0gL73SQpijhkXa63/rwqUGFc5lRgAckf0yatdwIz1ajn1 X-Gm-Message-State: AOJu0Yxt1jlv5S8l0z65FaR98ksf4f+iQ37XteoT1tDDmtBzBiAAeuVd UaaqeyrgtFdr9DElT9p1soCsJcpJP/nrLuXevH6xuOIFryiNJv8BFcWouDEtzXE= X-Google-Smtp-Source: AGHT+IEfRUjBsR081et3wJOadMgBsrPT+MF87MwTDvd2ymBdOvFDiLCp8AN/vnIfSdOc1TYzaATntQ== X-Received: by 2002:adf:f60c:0:b0:343:3f59:c97e with SMTP id t12-20020adff60c000000b003433f59c97emr1553063wrp.6.1713444238851; Thu, 18 Apr 2024 05:43:58 -0700 (PDT) Received: from carbon-x1.. ([2a01:e0a:999:a3a0:7b64:4d1d:16d8:e38b]) by smtp.gmail.com with ESMTPSA id bi18-20020a05600c3d9200b00418d5b16fa2sm3373412wmb.30.2024.04.18.05.43.57 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 18 Apr 2024 05:43:57 -0700 (PDT) From: =?utf-8?b?Q2zDqW1lbnQgTMOpZ2Vy?= To: Jonathan Corbet , Paul Walmsley , Palmer Dabbelt , Albert Ou , Conor Dooley , Rob Herring , Krzysztof Kozlowski , Anup Patel , Shuah Khan Cc: =?utf-8?b?Q2zDqW1lbnQgTMOpZ2Vy?= , Atish Patra , linux-doc@vger.kernel.org, linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, kvm@vger.kernel.org, kvm-riscv@lists.infradead.org, linux-kselftest@vger.kernel.org Subject: [PATCH v2 04/12] riscv: add ISA parsing for Zca, Zcf, Zcd and Zcb Date: Thu, 18 Apr 2024 14:42:27 +0200 Message-ID: <20240418124300.1387978-5-cleger@rivosinc.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20240418124300.1387978-1-cleger@rivosinc.com> References: <20240418124300.1387978-1-cleger@rivosinc.com> Precedence: bulk X-Mailing-List: kvm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 The Zc* standard extension for code reduction introduces new extensions. This patch adds support for Zca, Zcf, Zcd and Zcb. Zce, Zcmt and Zcmp are left out of this patch since they are targeting microcontrollers/ embedded CPUs instead of application processors. Signed-off-by: Clément Léger --- arch/riscv/include/asm/hwcap.h | 4 ++++ arch/riscv/kernel/cpufeature.c | 4 ++++ 2 files changed, 8 insertions(+) diff --git a/arch/riscv/include/asm/hwcap.h b/arch/riscv/include/asm/hwcap.h index 543e3ea2da0e..b7551bad341b 100644 --- a/arch/riscv/include/asm/hwcap.h +++ b/arch/riscv/include/asm/hwcap.h @@ -82,6 +82,10 @@ #define RISCV_ISA_EXT_ZACAS 73 #define RISCV_ISA_EXT_XANDESPMU 74 #define RISCV_ISA_EXT_ZIMOP 75 +#define RISCV_ISA_EXT_ZCA 76 +#define RISCV_ISA_EXT_ZCB 77 +#define RISCV_ISA_EXT_ZCD 78 +#define RISCV_ISA_EXT_ZCF 79 #define RISCV_ISA_EXT_XLINUXENVCFG 127 diff --git a/arch/riscv/kernel/cpufeature.c b/arch/riscv/kernel/cpufeature.c index 115ba001f1bc..09dee071274d 100644 --- a/arch/riscv/kernel/cpufeature.c +++ b/arch/riscv/kernel/cpufeature.c @@ -261,6 +261,10 @@ const struct riscv_isa_ext_data riscv_isa_ext[] = { __RISCV_ISA_EXT_DATA(zfa, RISCV_ISA_EXT_ZFA), __RISCV_ISA_EXT_DATA(zfh, RISCV_ISA_EXT_ZFH), __RISCV_ISA_EXT_DATA(zfhmin, RISCV_ISA_EXT_ZFHMIN), + __RISCV_ISA_EXT_DATA(zca, RISCV_ISA_EXT_ZCA), + __RISCV_ISA_EXT_DATA(zcb, RISCV_ISA_EXT_ZCB), + __RISCV_ISA_EXT_DATA(zcd, RISCV_ISA_EXT_ZCD), + __RISCV_ISA_EXT_DATA(zcf, RISCV_ISA_EXT_ZCF), __RISCV_ISA_EXT_DATA(zba, RISCV_ISA_EXT_ZBA), __RISCV_ISA_EXT_DATA(zbb, RISCV_ISA_EXT_ZBB), __RISCV_ISA_EXT_DATA(zbc, RISCV_ISA_EXT_ZBC), From patchwork Thu Apr 18 12:42:28 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?b?Q2zDqW1lbnQgTMOpZ2Vy?= X-Patchwork-Id: 13634665 Received: from mail-wr1-f41.google.com (mail-wr1-f41.google.com [209.85.221.41]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 62B5C1607B4 for ; Thu, 18 Apr 2024 12:44:01 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.221.41 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1713444245; cv=none; b=X3V/fVq1GaSOs9LcZLUOfZNzDk+f99S6MVfDVZ+6tzwu442h11zSo1ANqJ9e6KteNH54g+HLjWXj5RPQR1qVksMJOUDiTc/Xrxi7AsKV7wPdIpUrLyXrdpS/gh52FIOAR9Lkbg/uW6+r21dUC6KS7eYDnelfkKNygZaQn5JfJKQ= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1713444245; c=relaxed/simple; bh=l6HwQhAS5cBw6tUNZ3QEVVTb2yliEfsikw1VTQcl4U4=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=PkbjTYZ1skvk/5J8C7O21irkDZcoLWqYkbvhsvWfzGUIKJHf/FlDjzSUh6bBno+fowqpB2nhowMmV2t8QknBQzoEY6nud02TS11yb3iydQ4waRYG3rNsU7pX3erygDuWtH76dKnj3ckszQNgSk3GVzd/sR8l0RX0P8ezbk/dNV8= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=rivosinc.com; spf=pass smtp.mailfrom=rivosinc.com; dkim=pass (2048-bit key) header.d=rivosinc-com.20230601.gappssmtp.com header.i=@rivosinc-com.20230601.gappssmtp.com header.b=wgcaa8x0; arc=none smtp.client-ip=209.85.221.41 Authentication-Results: smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=rivosinc.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=rivosinc.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=rivosinc-com.20230601.gappssmtp.com header.i=@rivosinc-com.20230601.gappssmtp.com header.b="wgcaa8x0" Received: by mail-wr1-f41.google.com with SMTP id ffacd0b85a97d-349bd110614so143263f8f.3 for ; Thu, 18 Apr 2024 05:44:01 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=rivosinc-com.20230601.gappssmtp.com; s=20230601; t=1713444240; x=1714049040; darn=vger.kernel.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=t82SHWSKnQwBrCB557sYOimgSCzDvuCob+i4t0Pqx/Q=; b=wgcaa8x0IUiqoc/xOMrIlEXXqmgbkVQ7isxxtKRyXDFF3vV5d7naTBsP7+UIvjAsio 6j0FluGv9EIU77zMApnwrSOJp1H5LsCMmIsIk7rPPDORQQkruYgxnibiL2NBPEE7gVB7 7oxs2S6vLZf3Naagbdn/eNOoxThxg5Czj4C/UX7CQ/Q/jSyByzA5OPAB/RPlJ1BrJjof qPTAxwKJZhLzci4hKuRnHnaErS983mllTaQsCRVQoAiohPyxAGJ6w3rUYoo1St2OqNUr HhPlDbWDdHquJS8bgf0IYa+2luWBoxxZgqDwGbaULiVvYvSXmE9KDkMKjOvrj2SJmYSQ kANA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1713444240; x=1714049040; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=t82SHWSKnQwBrCB557sYOimgSCzDvuCob+i4t0Pqx/Q=; b=aKyb424V26QGDxZR3AoYXe5pLq9rQ+okZ5IIYiEx+JFGsxeAHiGdywxftl90hFlsPv De5l4Cn9qGyaw2LI53mFSW5i6mk6kwHDnyZgPTcHJztc9j4KmMPQpoWCHD9mIxwIp6Fi O0bbvUrOX/JgQFbFmpDwCIHv4aVjxEtLzBTszlzgAEJiuD8Z5REuMnuCBb2iGv/P0OA8 noAn8GPBDGSEUeAn19l63DuhmhQ11boy+kQ6pyPedaQtwQ4ea5xK0Ypg2XVIVwbZjaKF ZvzhfQb/2sEaLFFtu9FP0QmXhwG3a2I017anfJl8lkCvKgS0AkjUmM62p6M99pmwC+zC 8gmw== X-Forwarded-Encrypted: i=1; AJvYcCUpd3wczO8WYmpQ9Uhf8/nRwTj8FEYid5hMcDCDdpHkBmPr6LGJ4V3qhHpJHw4+yVp87F4Tg1MiW0piH79X4u4kh0Ih X-Gm-Message-State: AOJu0Yyv4HRix1akxwNAKftnLUXxzGXuSQjIpJB7FMvCh2NKDhHONl4u V0aMfrq3x5Q4d7zXj2glMzHU59dno8mCh+HiynO+okDDdVd4U2m67hfyVEjONNQ= X-Google-Smtp-Source: AGHT+IErS9LwS4/40J0dhVyrk/U2WpAaf5Tm6m07tMubctlbr1giuR0xo76AOxJlKf5jHdgFbxuJkw== X-Received: by 2002:a05:600c:5101:b0:416:a773:7d18 with SMTP id o1-20020a05600c510100b00416a7737d18mr1843734wms.0.1713444239836; Thu, 18 Apr 2024 05:43:59 -0700 (PDT) Received: from carbon-x1.. ([2a01:e0a:999:a3a0:7b64:4d1d:16d8:e38b]) by smtp.gmail.com with ESMTPSA id bi18-20020a05600c3d9200b00418d5b16fa2sm3373412wmb.30.2024.04.18.05.43.59 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 18 Apr 2024 05:43:59 -0700 (PDT) From: =?utf-8?b?Q2zDqW1lbnQgTMOpZ2Vy?= To: Jonathan Corbet , Paul Walmsley , Palmer Dabbelt , Albert Ou , Conor Dooley , Rob Herring , Krzysztof Kozlowski , Anup Patel , Shuah Khan Cc: =?utf-8?b?Q2zDqW1lbnQgTMOpZ2Vy?= , Atish Patra , linux-doc@vger.kernel.org, linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, kvm@vger.kernel.org, kvm-riscv@lists.infradead.org, linux-kselftest@vger.kernel.org Subject: [PATCH v2 05/12] riscv: hwprobe: export Zca, Zcf, Zcd and Zcb ISA extensions Date: Thu, 18 Apr 2024 14:42:28 +0200 Message-ID: <20240418124300.1387978-6-cleger@rivosinc.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20240418124300.1387978-1-cleger@rivosinc.com> References: <20240418124300.1387978-1-cleger@rivosinc.com> Precedence: bulk X-Mailing-List: kvm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Export Zca, Zcf, Zcd and Zcb ISA extension through hwprobe. Signed-off-by: Clément Léger --- Documentation/arch/riscv/hwprobe.rst | 20 ++++++++++++++++++++ arch/riscv/include/uapi/asm/hwprobe.h | 4 ++++ arch/riscv/kernel/sys_hwprobe.c | 4 ++++ 3 files changed, 28 insertions(+) diff --git a/Documentation/arch/riscv/hwprobe.rst b/Documentation/arch/riscv/hwprobe.rst index 9ca5b093b6d5..bf96b4e8ba3b 100644 --- a/Documentation/arch/riscv/hwprobe.rst +++ b/Documentation/arch/riscv/hwprobe.rst @@ -192,6 +192,26 @@ The following keys are defined: supported as defined in the RISC-V ISA manual starting from commit 58220614a5f ("Zimop is ratified/1.0"). + * :c:macro:`RISCV_HWPROBE_EXT_ZCA`: The Zca extension part of Zc* standard + extensions for code size reduction, as ratified in commit 8be3419c1c0 + ("Zcf doesn't exist on RV64 as it contains no instructions") of + riscv-code-size-reduction. + + * :c:macro:`RISCV_HWPROBE_EXT_ZCB`: The Zcb extension part of Zc* standard + extensions for code size reduction, as ratified in commit 8be3419c1c0 + ("Zcf doesn't exist on RV64 as it contains no instructions") of + riscv-code-size-reduction. + + * :c:macro:`RISCV_HWPROBE_EXT_ZCD`: The Zcd extension part of Zc* standard + extensions for code size reduction, as ratified in commit 8be3419c1c0 + ("Zcf doesn't exist on RV64 as it contains no instructions") of + riscv-code-size-reduction. + + * :c:macro:`RISCV_HWPROBE_EXT_ZCF`: The Zcf extension part of Zc* standard + extensions for code size reduction, as ratified in commit 8be3419c1c0 + ("Zcf doesn't exist on RV64 as it contains no instructions") of + riscv-code-size-reduction. + * :c:macro:`RISCV_HWPROBE_KEY_CPUPERF_0`: A bitmask that contains performance information about the selected set of processors. diff --git a/arch/riscv/include/uapi/asm/hwprobe.h b/arch/riscv/include/uapi/asm/hwprobe.h index ac6874ab743a..dd4ad77faf49 100644 --- a/arch/riscv/include/uapi/asm/hwprobe.h +++ b/arch/riscv/include/uapi/asm/hwprobe.h @@ -60,6 +60,10 @@ struct riscv_hwprobe { #define RISCV_HWPROBE_EXT_ZACAS (1ULL << 34) #define RISCV_HWPROBE_EXT_ZICOND (1ULL << 35) #define RISCV_HWPROBE_EXT_ZIMOP (1ULL << 36) +#define RISCV_HWPROBE_EXT_ZCA (1ULL << 37) +#define RISCV_HWPROBE_EXT_ZCB (1ULL << 38) +#define RISCV_HWPROBE_EXT_ZCD (1ULL << 39) +#define RISCV_HWPROBE_EXT_ZCF (1ULL << 40) #define RISCV_HWPROBE_KEY_CPUPERF_0 5 #define RISCV_HWPROBE_MISALIGNED_UNKNOWN (0 << 0) #define RISCV_HWPROBE_MISALIGNED_EMULATED (1 << 0) diff --git a/arch/riscv/kernel/sys_hwprobe.c b/arch/riscv/kernel/sys_hwprobe.c index c99a4cf231c5..2ffa0fe5101e 100644 --- a/arch/riscv/kernel/sys_hwprobe.c +++ b/arch/riscv/kernel/sys_hwprobe.c @@ -112,6 +112,8 @@ static void hwprobe_isa_ext0(struct riscv_hwprobe *pair, EXT_KEY(ZACAS); EXT_KEY(ZICOND); EXT_KEY(ZIMOP); + EXT_KEY(ZCA); + EXT_KEY(ZCB); if (has_vector()) { EXT_KEY(ZVBB); @@ -132,6 +134,8 @@ static void hwprobe_isa_ext0(struct riscv_hwprobe *pair, EXT_KEY(ZFH); EXT_KEY(ZFHMIN); EXT_KEY(ZFA); + EXT_KEY(ZCD); + EXT_KEY(ZCF); } #undef EXT_KEY } From patchwork Thu Apr 18 12:42:29 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?b?Q2zDqW1lbnQgTMOpZ2Vy?= X-Patchwork-Id: 13634664 Received: from mail-lj1-f174.google.com (mail-lj1-f174.google.com [209.85.208.174]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id E7F98161327 for ; Thu, 18 Apr 2024 12:44:02 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.208.174 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1713444245; cv=none; b=uPLfcImlOkzMVC2sl2PwMmmEz8BCdr4SSZutXXoP1GOsULzgTYUlV86tzuEiUMnCJqZgUmMKsR1hNV2avxI671MpqTzmfYBo8Tu4H9LV5rnltkpOMfTb8ZbCL0yw0vhbHW4+TEIxasvoMv6Hoj+rIz/FrH+jePqXk8eACnqM+qE= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1713444245; c=relaxed/simple; bh=2meeqYrGqS6N+9ES03sW/IZ0HWVimfJczOdorGfrJB4=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=rjoxTglMl/daaNv7uQnbaDb9f+9B0imwVXVOvFElMIr3hCUyipyDtuv+VW2Owom0nWIr+wunS0TehGKQTx+AjiIlYYUlxu9y56EWKzfuafZtqLFS4MM8VIUt2P82fR8xmDcF8ZZS5Vg42wMoJ9SAmR7R/+3n5UIvq1ZRY2NvXa8= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=rivosinc.com; spf=pass smtp.mailfrom=rivosinc.com; dkim=pass (2048-bit key) header.d=rivosinc-com.20230601.gappssmtp.com header.i=@rivosinc-com.20230601.gappssmtp.com header.b=orXBAWIl; arc=none smtp.client-ip=209.85.208.174 Authentication-Results: smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=rivosinc.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=rivosinc.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=rivosinc-com.20230601.gappssmtp.com header.i=@rivosinc-com.20230601.gappssmtp.com header.b="orXBAWIl" Received: by mail-lj1-f174.google.com with SMTP id 38308e7fff4ca-2dac627e62dso235001fa.3 for ; Thu, 18 Apr 2024 05:44:02 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=rivosinc-com.20230601.gappssmtp.com; s=20230601; t=1713444241; x=1714049041; darn=vger.kernel.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=av0fCRvJ5d6BdL5At0wE/CNS0oRVP43ZLfrJceTJ89w=; b=orXBAWIlCbFEPZnXQnevS9f95mR5781Pc2yepFZQDAFvlJNBdvAcLHH8vprt+kGonx u/y21dbj5GkzC7GC9zD2/TDSztHegfMNMN2C/DhINA2H23Kk5mfXmCCyvY+gHjagQ+Hx oaNLoRtTXs5HQDI1JZgqE/2mtGYT+M2IaaZRjHo1RF13bMsHsiJE5d1wYa2P4OdVwI/A 7BVKyu+mMSKhRKMcLyd/ObTNE0DshORErxAfHhUT+3WDt27HEN2cxYP1ZMIOX/m2Rzmg m50MJceZivYeNEpP/zgsWdA0CNd/KAvsGenYKqMMettqNaLTycWsPrXjixBOhvkaLotl ORBw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1713444241; x=1714049041; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=av0fCRvJ5d6BdL5At0wE/CNS0oRVP43ZLfrJceTJ89w=; b=SW/eMrhUJ9BnZsN92jYgqPrfZOZouOrYASvGQY51zi4QnVPtrNFNtzUpfabrl/19sy T679e02uXMldGei8TvZji/Auja5cAJd1+6OB+Ut+LA04Y7XJz26QxeN6DkwZJITwvCXN GbCohOyQFv5zbXZA5sonmQSwWCpj3PDC7dpeY5YPR6JaGCxqCPs9tYiNJHSkOfdyJ4Mm 0khakQiCKUp0imciQ9PA19oLH+cCRw+pY3GYn6NuHQxe+OOCJyFRvM8FEo30petd7k09 Ls7ExRWfnKpTll3hTb6h3zKMcBy68bqg3hM3JHRhqxm5kUevjoKy8CyBcbYH8mnOwh8F dbnQ== X-Forwarded-Encrypted: i=1; AJvYcCVTeVJYtqb8FZZCmpKxSRy2bZ1an4cBbt4ZZojHNDqxvd2kgy10/VWRK7faLb+jFBvul1Adoa2QFpUEmEXWL5oV/U4L X-Gm-Message-State: AOJu0YxE2Jl7Aph5puvplgP3rXQLQ/Nopmvnyb/4uTgYkbJcdduqceor BQ10mHd41fBSJRKEA4xtgXnEgkFzXRrZen1nZWYHv31qYlD66lmFFs8EE18SP6s= X-Google-Smtp-Source: AGHT+IHdzMsUCMCexL1xcSXK55gyqNVYHzfsqQON0oQtcwPFlYxqOUNzTjfk86rgRUdr+Vw8mFv+bw== X-Received: by 2002:a2e:3a19:0:b0:2da:320a:6739 with SMTP id h25-20020a2e3a19000000b002da320a6739mr1487240lja.1.1713444241121; Thu, 18 Apr 2024 05:44:01 -0700 (PDT) Received: from carbon-x1.. ([2a01:e0a:999:a3a0:7b64:4d1d:16d8:e38b]) by smtp.gmail.com with ESMTPSA id bi18-20020a05600c3d9200b00418d5b16fa2sm3373412wmb.30.2024.04.18.05.43.59 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 18 Apr 2024 05:44:00 -0700 (PDT) From: =?utf-8?b?Q2zDqW1lbnQgTMOpZ2Vy?= To: Jonathan Corbet , Paul Walmsley , Palmer Dabbelt , Albert Ou , Conor Dooley , Rob Herring , Krzysztof Kozlowski , Anup Patel , Shuah Khan Cc: =?utf-8?b?Q2zDqW1lbnQgTMOpZ2Vy?= , Atish Patra , linux-doc@vger.kernel.org, linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, kvm@vger.kernel.org, kvm-riscv@lists.infradead.org, linux-kselftest@vger.kernel.org Subject: [PATCH v2 06/12] RISC-V: KVM: Allow Zca, Zcf, Zcd and Zcb extensions for Guest/VM Date: Thu, 18 Apr 2024 14:42:29 +0200 Message-ID: <20240418124300.1387978-7-cleger@rivosinc.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20240418124300.1387978-1-cleger@rivosinc.com> References: <20240418124300.1387978-1-cleger@rivosinc.com> Precedence: bulk X-Mailing-List: kvm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Extend the KVM ISA extension ONE_REG interface to allow KVM user space to detect and enable Zca, Zcf, Zcd and Zcb extensions for Guest/VM. Signed-off-by: Clément Léger Reviewed-by: Anup Patel Acked-by: Anup Patel --- arch/riscv/include/uapi/asm/kvm.h | 4 ++++ arch/riscv/kvm/vcpu_onereg.c | 8 ++++++++ 2 files changed, 12 insertions(+) diff --git a/arch/riscv/include/uapi/asm/kvm.h b/arch/riscv/include/uapi/asm/kvm.h index 35a12aa1953e..57db3fea679f 100644 --- a/arch/riscv/include/uapi/asm/kvm.h +++ b/arch/riscv/include/uapi/asm/kvm.h @@ -168,6 +168,10 @@ enum KVM_RISCV_ISA_EXT_ID { KVM_RISCV_ISA_EXT_ZTSO, KVM_RISCV_ISA_EXT_ZACAS, KVM_RISCV_ISA_EXT_ZIMOP, + KVM_RISCV_ISA_EXT_ZCA, + KVM_RISCV_ISA_EXT_ZCB, + KVM_RISCV_ISA_EXT_ZCD, + KVM_RISCV_ISA_EXT_ZCF, KVM_RISCV_ISA_EXT_MAX, }; diff --git a/arch/riscv/kvm/vcpu_onereg.c b/arch/riscv/kvm/vcpu_onereg.c index 12436f6f0d20..a2747a6dbdb6 100644 --- a/arch/riscv/kvm/vcpu_onereg.c +++ b/arch/riscv/kvm/vcpu_onereg.c @@ -48,6 +48,10 @@ static const unsigned long kvm_isa_ext_arr[] = { KVM_ISA_EXT_ARR(ZBKC), KVM_ISA_EXT_ARR(ZBKX), KVM_ISA_EXT_ARR(ZBS), + KVM_ISA_EXT_ARR(ZCA), + KVM_ISA_EXT_ARR(ZCB), + KVM_ISA_EXT_ARR(ZCD), + KVM_ISA_EXT_ARR(ZCF), KVM_ISA_EXT_ARR(ZFA), KVM_ISA_EXT_ARR(ZFH), KVM_ISA_EXT_ARR(ZFHMIN), @@ -128,6 +132,10 @@ static bool kvm_riscv_vcpu_isa_disable_allowed(unsigned long ext) case KVM_RISCV_ISA_EXT_ZBKC: case KVM_RISCV_ISA_EXT_ZBKX: case KVM_RISCV_ISA_EXT_ZBS: + case KVM_RISCV_ISA_EXT_ZCA: + case KVM_RISCV_ISA_EXT_ZCB: + case KVM_RISCV_ISA_EXT_ZCD: + case KVM_RISCV_ISA_EXT_ZCF: case KVM_RISCV_ISA_EXT_ZFA: case KVM_RISCV_ISA_EXT_ZFH: case KVM_RISCV_ISA_EXT_ZFHMIN: From patchwork Thu Apr 18 12:42:30 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?b?Q2zDqW1lbnQgTMOpZ2Vy?= X-Patchwork-Id: 13634666 Received: from mail-lf1-f49.google.com (mail-lf1-f49.google.com [209.85.167.49]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 55BFA16192F for ; Thu, 18 Apr 2024 12:44:04 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.167.49 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1713444246; cv=none; b=WJpxLi51LNjn3iT7guGM8bI0oDz/pbpE/axLS7vmdXOf6P3CRwtDwDw3KoK2lZI8hvPN4t4zgjWocqlhfEbSwfRrxsyV5e7LWuA+XLQ0eer0j2M8qOAuOP7FpiIQruv+SLDa4jSS3rgKatjm4drbyUYRaFYesAG0r0ayas9lvx0= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1713444246; c=relaxed/simple; bh=bL0yXhZgH/0/PkNBvTy00J8zOdW+K5v1x8a4cTFvpqY=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=FiXILYXjOm6jVYR4/peTLnZ3kc5t/IDbSklWdPuSbGzz39rFEnSC+3mt0a2aV/HgkFikrY9Jd4fPDm1EHDrHPV8K2WXjWTTjersWRD8YqpFhfy3c25gnNDvVPvhWcXrml6F8AaXLWHP3+wPIBvoHAeyAE7US1EHU56eAMbDH6F8= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=rivosinc.com; spf=pass smtp.mailfrom=rivosinc.com; dkim=pass (2048-bit key) header.d=rivosinc-com.20230601.gappssmtp.com header.i=@rivosinc-com.20230601.gappssmtp.com header.b=yDPVXlo+; arc=none smtp.client-ip=209.85.167.49 Authentication-Results: smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=rivosinc.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=rivosinc.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=rivosinc-com.20230601.gappssmtp.com header.i=@rivosinc-com.20230601.gappssmtp.com header.b="yDPVXlo+" Received: by mail-lf1-f49.google.com with SMTP id 2adb3069b0e04-5191b84d6d7so175367e87.3 for ; Thu, 18 Apr 2024 05:44:04 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=rivosinc-com.20230601.gappssmtp.com; s=20230601; t=1713444242; x=1714049042; darn=vger.kernel.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=3Bj6qFEBTQkW22oNb4zguAXGn3Gn0KYF9aSmL0IcZwU=; b=yDPVXlo+IlZr9x0GnNrj3vFUht45Vt286kbispw10Y2LgqWe0fz3wnelALFu85g5jU 8SM+vkzsv3qOzvV5MjBrW9PrVlXzaZ1sDLw3GkzGcrm6Gi6D5QlAM88S5CeV+VjPwf3H VlY8Hv4z5itp3FWM2pIgKdEy/D0FVoz2hfH7gy80KM19A9+MYh26/Qknt18RXzdYQ6v7 XRWNs8dzDjlzqKvPNjCGt5b5bN25tlxSYjAmuwO4TDiIDI4zu5rSAf2Yn8tItz0r6Jy4 s8IvysSehJEBuzlWCn1kMIcmnP4d4BoUroE3kJoOPZx28AAiL43qc9ddeBUvQkI59wiI wWow== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1713444242; x=1714049042; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=3Bj6qFEBTQkW22oNb4zguAXGn3Gn0KYF9aSmL0IcZwU=; b=NXNZPSrx1JvBsn5Rfr+1IaFHCbP1j/AtntjXiUHQN1LJihahpqur6xPNERAMHS2rdG zAwZEFiu+HYYxHAFJxWGL7kInTVnwOK1DySC0+zNKw8bruV9fgkuexWJLV/hOJzcmNpq 2OlHbIZRHJRif5VVV6Hg6qdEWj8O1TRom/5Q+Y8g2NbC6IAGQNe7KDR6U2JtO8ZTlxmZ ctb7bgiNuPT31QQUcufWYjcC/TwBQShzczbU8GnFos1sp2xDKvL/TWFP/dkhHSbj+I1G rPgpRUirG8UrA3X3CyKHZfG0N9TFLfvQU6qJdUbJt9QeNVqau+A32IshGNUDrntEAFhs aX2Q== X-Forwarded-Encrypted: i=1; AJvYcCVgk20s3eEd0/H494EjGTbpLMjAH8AJaHwW8poYeNNZtjdktwHfN9uRsior4ycCKqb01/juwAYJ8XTFIRbMIpB9fV1W X-Gm-Message-State: AOJu0Yz/wWa8Hd08+zmw44NbwfwMqRCRMHAQ3vVu8daCgtUnO1bUwz6K pjtiWkebqpXc2Ulbfdttv50jac3SayIh8Les9iN3wP7HueyegfN8JiEbCEgxfFE= X-Google-Smtp-Source: AGHT+IGuPTx5xyQ5D84Wxe16Njbe8/Zc2rt6PLP6jz46BTrSDooOvgKGDoT7RA33/hfmMjVJRZ9Clg== X-Received: by 2002:a2e:7314:0:b0:2da:590:db77 with SMTP id o20-20020a2e7314000000b002da0590db77mr1413729ljc.0.1713444242557; Thu, 18 Apr 2024 05:44:02 -0700 (PDT) Received: from carbon-x1.. ([2a01:e0a:999:a3a0:7b64:4d1d:16d8:e38b]) by smtp.gmail.com with ESMTPSA id bi18-20020a05600c3d9200b00418d5b16fa2sm3373412wmb.30.2024.04.18.05.44.01 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 18 Apr 2024 05:44:01 -0700 (PDT) From: =?utf-8?b?Q2zDqW1lbnQgTMOpZ2Vy?= To: Jonathan Corbet , Paul Walmsley , Palmer Dabbelt , Albert Ou , Conor Dooley , Rob Herring , Krzysztof Kozlowski , Anup Patel , Shuah Khan Cc: =?utf-8?b?Q2zDqW1lbnQgTMOpZ2Vy?= , Atish Patra , linux-doc@vger.kernel.org, linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, kvm@vger.kernel.org, kvm-riscv@lists.infradead.org, linux-kselftest@vger.kernel.org Subject: [PATCH v2 07/12] KVM: riscv: selftests: Add some Zc* extensions to get-reg-list test Date: Thu, 18 Apr 2024 14:42:30 +0200 Message-ID: <20240418124300.1387978-8-cleger@rivosinc.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20240418124300.1387978-1-cleger@rivosinc.com> References: <20240418124300.1387978-1-cleger@rivosinc.com> Precedence: bulk X-Mailing-List: kvm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 The KVM RISC-V allows Zca, Zcf, Zcd and Zcb extensions for Guest/VM so add these extensions to get-reg-list test. Signed-off-by: Clément Léger Reviewed-by: Anup Patel Acked-by: Anup Patel --- tools/testing/selftests/kvm/riscv/get-reg-list.c | 16 ++++++++++++++++ 1 file changed, 16 insertions(+) diff --git a/tools/testing/selftests/kvm/riscv/get-reg-list.c b/tools/testing/selftests/kvm/riscv/get-reg-list.c index 40107bb61975..61cad4514197 100644 --- a/tools/testing/selftests/kvm/riscv/get-reg-list.c +++ b/tools/testing/selftests/kvm/riscv/get-reg-list.c @@ -55,6 +55,10 @@ bool filter_reg(__u64 reg) case KVM_REG_RISCV_ISA_EXT | KVM_REG_RISCV_ISA_SINGLE | KVM_RISCV_ISA_EXT_ZBKC: case KVM_REG_RISCV_ISA_EXT | KVM_REG_RISCV_ISA_SINGLE | KVM_RISCV_ISA_EXT_ZBKX: case KVM_REG_RISCV_ISA_EXT | KVM_REG_RISCV_ISA_SINGLE | KVM_RISCV_ISA_EXT_ZBS: + case KVM_REG_RISCV_ISA_EXT | KVM_REG_RISCV_ISA_SINGLE | KVM_RISCV_ISA_EXT_ZCA: + case KVM_REG_RISCV_ISA_EXT | KVM_REG_RISCV_ISA_SINGLE | KVM_RISCV_ISA_EXT_ZCB: + case KVM_REG_RISCV_ISA_EXT | KVM_REG_RISCV_ISA_SINGLE | KVM_RISCV_ISA_EXT_ZCD: + case KVM_REG_RISCV_ISA_EXT | KVM_REG_RISCV_ISA_SINGLE | KVM_RISCV_ISA_EXT_ZCF: case KVM_REG_RISCV_ISA_EXT | KVM_REG_RISCV_ISA_SINGLE | KVM_RISCV_ISA_EXT_ZFA: case KVM_REG_RISCV_ISA_EXT | KVM_REG_RISCV_ISA_SINGLE | KVM_RISCV_ISA_EXT_ZFH: case KVM_REG_RISCV_ISA_EXT | KVM_REG_RISCV_ISA_SINGLE | KVM_RISCV_ISA_EXT_ZFHMIN: @@ -421,6 +425,10 @@ static const char *isa_ext_single_id_to_str(__u64 reg_off) KVM_ISA_EXT_ARR(ZBKC), KVM_ISA_EXT_ARR(ZBKX), KVM_ISA_EXT_ARR(ZBS), + KVM_ISA_EXT_ARR(ZCA), + KVM_ISA_EXT_ARR(ZCB), + KVM_ISA_EXT_ARR(ZCD), + KVM_ISA_EXT_ARR(ZCF), KVM_ISA_EXT_ARR(ZFA), KVM_ISA_EXT_ARR(ZFH), KVM_ISA_EXT_ARR(ZFHMIN), @@ -945,6 +953,10 @@ KVM_ISA_EXT_SIMPLE_CONFIG(zbkb, ZBKB); KVM_ISA_EXT_SIMPLE_CONFIG(zbkc, ZBKC); KVM_ISA_EXT_SIMPLE_CONFIG(zbkx, ZBKX); KVM_ISA_EXT_SIMPLE_CONFIG(zbs, ZBS); +KVM_ISA_EXT_SIMPLE_CONFIG(zca, ZCA), +KVM_ISA_EXT_SIMPLE_CONFIG(zcb, ZCB), +KVM_ISA_EXT_SIMPLE_CONFIG(zcd, ZCD), +KVM_ISA_EXT_SIMPLE_CONFIG(zcf, ZCF), KVM_ISA_EXT_SIMPLE_CONFIG(zfa, ZFA); KVM_ISA_EXT_SIMPLE_CONFIG(zfh, ZFH); KVM_ISA_EXT_SIMPLE_CONFIG(zfhmin, ZFHMIN); @@ -1001,6 +1013,10 @@ struct vcpu_reg_list *vcpu_configs[] = { &config_zbkc, &config_zbkx, &config_zbs, + &config_zca, + &config_zcb, + &config_zcd, + &config_zcf, &config_zfa, &config_zfh, &config_zfhmin, From patchwork Thu Apr 18 12:42:31 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?b?Q2zDqW1lbnQgTMOpZ2Vy?= X-Patchwork-Id: 13634667 Received: from mail-wr1-f54.google.com (mail-wr1-f54.google.com [209.85.221.54]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 9C85D1635DC for ; Thu, 18 Apr 2024 12:44:05 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.221.54 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1713444247; cv=none; b=Fd0QgkKuXAh68gSC1rmkfZ0rbZlRI1rFPdngLfUsOnY/798daUEknuU8Ax2RS13vlVS04aqy88eBU99Pg05Wyw7GhoodJuqiS6/oQvjgfN9f68ydXmY7h1e6NMQ7zYrEZLvnJA7DHLyKKMb6jvb2La06SLhNNE+grCfaEaIkUzY= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1713444247; c=relaxed/simple; bh=J+bCEvF4XFdAFPpf0c/hVBuXUmoAvTnoas5SbNaML1w=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=mIVG3OLTqW4XNYNjXD5yohVz/TeFDGNFhfZ/mG1UnpeqBLZBPess7mkrM7pjQ9knIG8mV6a4nxIWexUu/6xDdWEVDR3mjh7Vd4Xuo1mAdVEzIPKnJt/OmKvk4RnQLLq8wqDCVg1dZrDrQCp0KzmpDbqJ3jM6dPmgZZ+oWwaC6Gc= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=rivosinc.com; spf=pass smtp.mailfrom=rivosinc.com; dkim=pass (2048-bit key) header.d=rivosinc-com.20230601.gappssmtp.com header.i=@rivosinc-com.20230601.gappssmtp.com header.b=glD/VJY3; arc=none smtp.client-ip=209.85.221.54 Authentication-Results: smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=rivosinc.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=rivosinc.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=rivosinc-com.20230601.gappssmtp.com header.i=@rivosinc-com.20230601.gappssmtp.com header.b="glD/VJY3" Received: by mail-wr1-f54.google.com with SMTP id ffacd0b85a97d-34a0cc29757so75325f8f.1 for ; Thu, 18 Apr 2024 05:44:05 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=rivosinc-com.20230601.gappssmtp.com; s=20230601; t=1713444244; x=1714049044; darn=vger.kernel.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=HCF5E0lf403bRxRvK1+a63xMUHlXis3iiu/dcBPgPms=; b=glD/VJY34TARB8xfgGOO4Hip5ayivSYist1quqST1mUcOAZe4Id1KlxtlOYwcgvzE2 svwdA3b74QA8mac7yCTYzIrJ6DMUgKaxPybrz6JIMJeRHszzh/QhBiap58pYTCNtd+nu 0J6VZFWa3jQ3dxvVI2bwYqDSweHI3tvkawAg9uFg5XSJz8MF53EX901ZrV7uq6bcMPWx g7VHbkVakpmoqXUoQi5f5RvQfEfTCpYVdjNkE08HTqJG9PtQ48hmLfWLOkJuQyqpbKzD sE3/jPDX8ZAyl7Ag1EKCmL3Bdeoqv4Vyy2Kly62a63DC+GMF3p74WLoQhcqXoEz041Xd w3SA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1713444244; x=1714049044; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=HCF5E0lf403bRxRvK1+a63xMUHlXis3iiu/dcBPgPms=; b=uHSASnx//lzcH+vu0kUZYHY9/2cpQN/ACCvpULMN3sm5uQL/+uoxZ29GIg+0+2xGYt IFrPHLSUq0dQPltwjBfS329SxQQg0G3RXaGEedJcUuqeQKBbGcuI3CC51rC0IPiaKj4F rtFPAl5sWLpXdTNWk8tzaT5AlHY6SZMkmg1RTpPzhlONW8CacoteOfjPrjcrj8HUD9s9 KaI8nZxHmxVlVDJhOPL2+PBKQubbmtWVUu40ThKDBnBslDcv0YyOOHieGl/Zg/pIcjZ7 B8GsGKU+iXk7lwm8sBmTmSUL4BOXXbS+pV7N6+LkVaO2kTYre5yH/KiBdNVCVXZedE0G N4vw== X-Forwarded-Encrypted: i=1; AJvYcCUaBn33UIw8Jj+8LLTyNL1mMG6jqfZ7wvxvwyeWLALi1x4jeVlfF6xqWk2a5eRDO8HZBoTx/Szh6ZyhdjpvOKkL8nXz X-Gm-Message-State: AOJu0YwZ5greUuNAzH7PyRqgZQSILk6d2cKXiXJEXE/kM+OkTikzacod qV/3M7/vQB/vQ1MW9gCq710P7cScI4ABRqUPlc/lGxlEL03Qy5GAIvSSXPHSGt0= X-Google-Smtp-Source: AGHT+IHf5iuv0LIJwrYLLs/M29+a7bnqtqrULSppwC9XA+JzBmE6As/f1Ah2mDNqzxt/R7Bqm6p1VA== X-Received: by 2002:a5d:5046:0:b0:349:eb59:c185 with SMTP id h6-20020a5d5046000000b00349eb59c185mr1524481wrt.1.1713444244182; Thu, 18 Apr 2024 05:44:04 -0700 (PDT) Received: from carbon-x1.. ([2a01:e0a:999:a3a0:7b64:4d1d:16d8:e38b]) by smtp.gmail.com with ESMTPSA id bi18-20020a05600c3d9200b00418d5b16fa2sm3373412wmb.30.2024.04.18.05.44.02 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 18 Apr 2024 05:44:03 -0700 (PDT) From: =?utf-8?b?Q2zDqW1lbnQgTMOpZ2Vy?= To: Jonathan Corbet , Paul Walmsley , Palmer Dabbelt , Albert Ou , Conor Dooley , Rob Herring , Krzysztof Kozlowski , Anup Patel , Shuah Khan Cc: =?utf-8?b?Q2zDqW1lbnQgTMOpZ2Vy?= , Atish Patra , linux-doc@vger.kernel.org, linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, kvm@vger.kernel.org, kvm-riscv@lists.infradead.org, linux-kselftest@vger.kernel.org Subject: [PATCH v2 08/12] dt-bindings: riscv: add Zcmop ISA extension description Date: Thu, 18 Apr 2024 14:42:31 +0200 Message-ID: <20240418124300.1387978-9-cleger@rivosinc.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20240418124300.1387978-1-cleger@rivosinc.com> References: <20240418124300.1387978-1-cleger@rivosinc.com> Precedence: bulk X-Mailing-List: kvm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Add description for the Zcmop (Compressed May-Be-Operations) ISA extension which was ratified in commit c732a4f39a4 ("Zcmop is ratified/1.0") of the riscv-isa-manual. Signed-off-by: Clément Léger Acked-by: Conor Dooley --- .../devicetree/bindings/riscv/extensions.yaml | 12 ++++++++++++ 1 file changed, 12 insertions(+) diff --git a/Documentation/devicetree/bindings/riscv/extensions.yaml b/Documentation/devicetree/bindings/riscv/extensions.yaml index 0172cbaa13ca..a0113cb46893 100644 --- a/Documentation/devicetree/bindings/riscv/extensions.yaml +++ b/Documentation/devicetree/bindings/riscv/extensions.yaml @@ -252,6 +252,11 @@ properties: merged in the riscv-isa-manual by commit dbc79cf28a2 ("Initial seed of zc.adoc to src tree."). + - const: zcmop + description: + The standard Zcmop extension version 1.0, as ratified in commit + c732a4f39a4 ("Zcmop is ratified/1.0") of the riscv-isa-manual. + - const: zfa description: The standard Zfa extension for additional floating point @@ -566,6 +571,13 @@ properties: then: contains: const: zcd + # Zcmop depends on Zca + - if: + contains: + const: zcmop + then: + contains: + const: zca allOf: # Zcf extension does not exists on rv64 From patchwork Thu Apr 18 12:42:32 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?b?Q2zDqW1lbnQgTMOpZ2Vy?= X-Patchwork-Id: 13634668 Received: from mail-lj1-f171.google.com (mail-lj1-f171.google.com [209.85.208.171]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id CDD43165FC6 for ; Thu, 18 Apr 2024 12:44:06 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.208.171 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1713444248; cv=none; b=pTGw0Lm0EVyiPoSsIOU/HyQhyx8MV9wemNRx/hj8aT4CDGR0IBG9Vy5jMbHjx4TyS7buaaeXfHdtHTAdV7Cdxkog3ysPMQf+BDR4i+OSV44PIbU8W3kBkgXVzySSWPYDmPf27vsfuOptZwhemu6mzYrR1+M6B0SM/zrHlsnlTBE= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1713444248; c=relaxed/simple; bh=boke7k+fuPr/buwvZEKJqr5O7FQgiL8dA2Us1JuDFEc=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=Cuq5uBXhZRXORjOSpD0T0iSz8v05WZBz3H8etEYlN2JvMOFv5/uew09zTqfKCWfJHhbcTWyIbnipRBEPUcNnmhK05n1f45TSCvNdvVExxSjfNBEdXTWSkrcUB+TVpZpuJpFMWnPeVaBNKANA8C8WYFNlrdO8k91eXcwUdriw5Cs= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=rivosinc.com; spf=pass smtp.mailfrom=rivosinc.com; dkim=pass (2048-bit key) header.d=rivosinc-com.20230601.gappssmtp.com header.i=@rivosinc-com.20230601.gappssmtp.com header.b=IzRDUPdq; arc=none smtp.client-ip=209.85.208.171 Authentication-Results: smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=rivosinc.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=rivosinc.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=rivosinc-com.20230601.gappssmtp.com header.i=@rivosinc-com.20230601.gappssmtp.com header.b="IzRDUPdq" Received: by mail-lj1-f171.google.com with SMTP id 38308e7fff4ca-2d9f829d398so1957811fa.0 for ; Thu, 18 Apr 2024 05:44:06 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=rivosinc-com.20230601.gappssmtp.com; s=20230601; t=1713444245; x=1714049045; darn=vger.kernel.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=AJJluMz+u6UTg8XM641LtNTBq3D7zPplm+46K1BBT3g=; b=IzRDUPdqJ4Vlg87RINfb9CIyPJREmt9Psx3Qd1IrCBHTLQjoYYN55/s9kaLgRafHp+ mmu3lg3cXMIVebSj3S+5gydCrwz5G5cGLX+gtS+n2lIhpprJYMMGjWeTf6q9joZycq3F wA/ewDw30c3CFmaGgc/M6p0jcEWcmvmFKI8oIeFkC0Dqk1ttxA5EJ/ddZR3keeNHgLu0 LmgFW8GZGMgcqfAOud+b69OSuuxSumW3/NcOJ1D5GoYCqvnWb8tb+AtP6RVybGLiK4uy KpKQpU+Ts8SmSOTn87kOjwUPQPw27WDoe6TXoQQGPL9CmO8Mhxv2bbmp0P1FlB6pA3jh /pXQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1713444245; x=1714049045; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=AJJluMz+u6UTg8XM641LtNTBq3D7zPplm+46K1BBT3g=; b=YoWhkjy3D23Q81DiWcQKBfSWy2Ejyn177fKQ9jWmt4+kIzqwy4Wvm+YuLlsTVWZyH3 nByO6jujjE+0quiKDFEZqQzq4gRybHdgd7SesTMW+zZjhV1gG2Lp1QTAEo1j/4ebmh7y qnqWZ9FzyVXVuvvxQ81QShGmjtAmMfK9iS6CK9l6dKEznO04PKY2VmzhnX/OCy1CmsCQ //eAplq5L6ySTvdXpO5Cz0AXaipNzfIOOu7/KpDvGi5epVuqvlucgP800Y3aDFI57Owe LyR7zMvk8u0YTzwrcr4BvgzQ0ktqTMoRiNIWk1yMpB6LpNn3VF5mgp9v50zywfzfaFDI Hw/Q== X-Forwarded-Encrypted: i=1; AJvYcCWM8kGr3MnCT96y8tyEpCSwivsOz8JMsyaWyYOmD+lhY7Nh9mqkbPV/Cd3tdqxrNX6CRPEVBKVpXRS0I2/n6glYfQOu X-Gm-Message-State: AOJu0YzK1w+cAcYDdtqKpu3PAtKbC9QuoJhpdDt7hMjGCdDrl7rzG3HW 8qDgqGkHSAdL/15E2HySD4e7e7SnWMlvGJz8RLJ7Edo/UUForrvLGEQ0afakIUc= X-Google-Smtp-Source: AGHT+IEA98F7NhkSpgbqjXTJDAARemLQxPRyTCHu7WNOEPKgiNpZ7WkvoQPUAaqjKtkLyPbtJUVEhQ== X-Received: by 2002:a2e:9ccf:0:b0:2d9:e54d:8208 with SMTP id g15-20020a2e9ccf000000b002d9e54d8208mr1639216ljj.0.1713444245128; Thu, 18 Apr 2024 05:44:05 -0700 (PDT) Received: from carbon-x1.. ([2a01:e0a:999:a3a0:7b64:4d1d:16d8:e38b]) by smtp.gmail.com with ESMTPSA id bi18-20020a05600c3d9200b00418d5b16fa2sm3373412wmb.30.2024.04.18.05.44.04 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 18 Apr 2024 05:44:04 -0700 (PDT) From: =?utf-8?b?Q2zDqW1lbnQgTMOpZ2Vy?= To: Jonathan Corbet , Paul Walmsley , Palmer Dabbelt , Albert Ou , Conor Dooley , Rob Herring , Krzysztof Kozlowski , Anup Patel , Shuah Khan Cc: =?utf-8?b?Q2zDqW1lbnQgTMOpZ2Vy?= , Atish Patra , linux-doc@vger.kernel.org, linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, kvm@vger.kernel.org, kvm-riscv@lists.infradead.org, linux-kselftest@vger.kernel.org Subject: [PATCH v2 09/12] riscv: add ISA extension parsing for Zcmop Date: Thu, 18 Apr 2024 14:42:32 +0200 Message-ID: <20240418124300.1387978-10-cleger@rivosinc.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20240418124300.1387978-1-cleger@rivosinc.com> References: <20240418124300.1387978-1-cleger@rivosinc.com> Precedence: bulk X-Mailing-List: kvm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Add parsing for Zcmop ISA extension which was ratified in commit b854a709c00 ("Zcmop is ratified/1.0") of the riscv-isa-manual. Signed-off-by: Clément Léger --- arch/riscv/include/asm/hwcap.h | 1 + arch/riscv/kernel/cpufeature.c | 1 + 2 files changed, 2 insertions(+) diff --git a/arch/riscv/include/asm/hwcap.h b/arch/riscv/include/asm/hwcap.h index b7551bad341b..cff7660de268 100644 --- a/arch/riscv/include/asm/hwcap.h +++ b/arch/riscv/include/asm/hwcap.h @@ -86,6 +86,7 @@ #define RISCV_ISA_EXT_ZCB 77 #define RISCV_ISA_EXT_ZCD 78 #define RISCV_ISA_EXT_ZCF 79 +#define RISCV_ISA_EXT_ZCMOP 80 #define RISCV_ISA_EXT_XLINUXENVCFG 127 diff --git a/arch/riscv/kernel/cpufeature.c b/arch/riscv/kernel/cpufeature.c index 09dee071274d..f1450cd7231e 100644 --- a/arch/riscv/kernel/cpufeature.c +++ b/arch/riscv/kernel/cpufeature.c @@ -265,6 +265,7 @@ const struct riscv_isa_ext_data riscv_isa_ext[] = { __RISCV_ISA_EXT_DATA(zcb, RISCV_ISA_EXT_ZCB), __RISCV_ISA_EXT_DATA(zcd, RISCV_ISA_EXT_ZCD), __RISCV_ISA_EXT_DATA(zcf, RISCV_ISA_EXT_ZCF), + __RISCV_ISA_EXT_DATA(zcmop, RISCV_ISA_EXT_ZCMOP), __RISCV_ISA_EXT_DATA(zba, RISCV_ISA_EXT_ZBA), __RISCV_ISA_EXT_DATA(zbb, RISCV_ISA_EXT_ZBB), __RISCV_ISA_EXT_DATA(zbc, RISCV_ISA_EXT_ZBC), From patchwork Thu Apr 18 12:42:33 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?b?Q2zDqW1lbnQgTMOpZ2Vy?= X-Patchwork-Id: 13634669 Received: from mail-wr1-f54.google.com (mail-wr1-f54.google.com [209.85.221.54]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 1FD44168B04 for ; Thu, 18 Apr 2024 12:44:07 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.221.54 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1713444249; cv=none; b=cuDDDOowR0F/GkyCNbsFAZnTOv4Od7zhVxg2qFMGehtAlD0IhGH5rPYHcIGAfokgGS0P/wZXxsVKcmkKjuLnqyq2v9M6iDtqX4g0+N8uTFm1PRDwEOhjzWkCB6KmUkwkZDd1oBzVHKVrihX4naF085IuJmk9hKgt8HBCDrbRL8c= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1713444249; c=relaxed/simple; bh=VBYIkTZIleyOsUo3Vs7GTW09WzwtONhQK0/AstEMTYc=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=aGstXjvPJttF5aav4MWv/6LmWhMOGrmJBSuu7ErJeHvh48U+vJxsJxNwu7tD4yTHoyAtvUUGxSRC05rSRWMc+ENdQo21GpyruFABm5Qm902PuzXPMLmbhwwEqn0iZmtB3v3vYdosfKVIAtiGrwrmoogGd96v0/55S45WoaV6qUk= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=rivosinc.com; spf=pass smtp.mailfrom=rivosinc.com; dkim=pass (2048-bit key) header.d=rivosinc-com.20230601.gappssmtp.com header.i=@rivosinc-com.20230601.gappssmtp.com header.b=wrdZg5k7; arc=none smtp.client-ip=209.85.221.54 Authentication-Results: smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=rivosinc.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=rivosinc.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=rivosinc-com.20230601.gappssmtp.com header.i=@rivosinc-com.20230601.gappssmtp.com header.b="wrdZg5k7" Received: by mail-wr1-f54.google.com with SMTP id ffacd0b85a97d-346407b8c9aso222974f8f.0 for ; Thu, 18 Apr 2024 05:44:07 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=rivosinc-com.20230601.gappssmtp.com; s=20230601; t=1713444246; x=1714049046; darn=vger.kernel.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=rdCfPjm06PN8DLWdVlWU7iGB8QhHqS8f5T3HQCXkkpY=; b=wrdZg5k7YDT5lFIY1gLMfU0QxbdSnmnXom/WAvGceN+EsWONrwyT1cXaYixHB/VKW/ kz7Bc2dr9lYtyTu93/yKIc5eGINGRACZ9x1SaqvtK5C9AGVpOHeZc+Jsv71V1lFqk0Yw dhyrBLfTtdHfZbXTjrkLBScl48FClZ35r0xCig976i7WPtQdWiNfwc9OroY78j+nGib2 k0vKQddbSnnpdzRSBBJY/pzH9p7v4iTB602iXCakdt+Ooo71otlduoG7C7Acv6UKyrnF qxoXc7rWKtSmHGcaRv5XlTVQSxJlt3vzPVALlMPMXKPpAPwBcE+krRUKuqhkZwiYVkZa 2Mlg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1713444246; x=1714049046; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=rdCfPjm06PN8DLWdVlWU7iGB8QhHqS8f5T3HQCXkkpY=; b=pSu+Aj1Qc21C4P/nbdCkSS6BhhspwkTeT5MslvGqpPFR3xrgXqSn1Kf/TLn0IxtU5c siTwhLikqeeS1gaEVfJsbra3GCn1dMotKck2qC9c5c2Da2Kb9eM2CouK7Rm1HmdriL12 ZpCjyLm/Em04pmtDZ4oc5+cHGozFYZM7sPGprBUj4/iUaiCXchRHAWd1cIlqe23GLV1Q 4oOb3TN5Dst1Qi6kVT5Fd+3qoyPiFZ2t3Ge9qtjLHEKxbq/e6DASQ2jQq5Q56xFT6L5C 8GuhdlJbwtq1CY1RhxYfrfYgv/KRskZgpDpmujtGET40COi9579hXG7K5oeYR3I4Ajup cx9g== X-Forwarded-Encrypted: i=1; AJvYcCVk4GZsyGzbQSd4+9Kt5ZRHXjtqJ8AQSAignWV/ND95GOJmNXf1qe6rsB1oV1snrjT9hwcVwGLt8ZdHQgpl6Snly63Y X-Gm-Message-State: AOJu0YySm/1lA6gUMCfxvyp9fc+YZRm4Y5FK8mRePPcj91tGYPeDwOhg iyjiYA/A1eqgTCDss+m4LWCAvjiy3H6yUz/TEJhz6HqPvxfD/uymn6lx2tbqXvk= X-Google-Smtp-Source: AGHT+IGMuL1VEcAVu36oqMeDfSFjQ3yk2Wj7i500rFn3wK2To4nptMyU7omA9B2isyVdkpsEUDxcgg== X-Received: by 2002:a05:600c:1ca2:b0:418:2a57:3806 with SMTP id k34-20020a05600c1ca200b004182a573806mr1932349wms.0.1713444246501; Thu, 18 Apr 2024 05:44:06 -0700 (PDT) Received: from carbon-x1.. ([2a01:e0a:999:a3a0:7b64:4d1d:16d8:e38b]) by smtp.gmail.com with ESMTPSA id bi18-20020a05600c3d9200b00418d5b16fa2sm3373412wmb.30.2024.04.18.05.44.05 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 18 Apr 2024 05:44:05 -0700 (PDT) From: =?utf-8?b?Q2zDqW1lbnQgTMOpZ2Vy?= To: Jonathan Corbet , Paul Walmsley , Palmer Dabbelt , Albert Ou , Conor Dooley , Rob Herring , Krzysztof Kozlowski , Anup Patel , Shuah Khan Cc: =?utf-8?b?Q2zDqW1lbnQgTMOpZ2Vy?= , Atish Patra , linux-doc@vger.kernel.org, linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, kvm@vger.kernel.org, kvm-riscv@lists.infradead.org, linux-kselftest@vger.kernel.org Subject: [PATCH v2 10/12] riscv: hwprobe: export Zcmop ISA extension Date: Thu, 18 Apr 2024 14:42:33 +0200 Message-ID: <20240418124300.1387978-11-cleger@rivosinc.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20240418124300.1387978-1-cleger@rivosinc.com> References: <20240418124300.1387978-1-cleger@rivosinc.com> Precedence: bulk X-Mailing-List: kvm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Export Zcmop ISA extension through hwprobe. Signed-off-by: Clément Léger --- Documentation/arch/riscv/hwprobe.rst | 4 ++++ arch/riscv/include/uapi/asm/hwprobe.h | 1 + arch/riscv/kernel/sys_hwprobe.c | 1 + 3 files changed, 6 insertions(+) diff --git a/Documentation/arch/riscv/hwprobe.rst b/Documentation/arch/riscv/hwprobe.rst index bf96b4e8ba3b..e3187659a077 100644 --- a/Documentation/arch/riscv/hwprobe.rst +++ b/Documentation/arch/riscv/hwprobe.rst @@ -212,6 +212,10 @@ The following keys are defined: ("Zcf doesn't exist on RV64 as it contains no instructions") of riscv-code-size-reduction. + * :c:macro:`RISCV_HWPROBE_EXT_ZCMOP`: The Zcmop May-Be-Operations extension is + supported as defined in the RISC-V ISA manual starting from commit + c732a4f39a4 ("Zcmop is ratified/1.0"). + * :c:macro:`RISCV_HWPROBE_KEY_CPUPERF_0`: A bitmask that contains performance information about the selected set of processors. diff --git a/arch/riscv/include/uapi/asm/hwprobe.h b/arch/riscv/include/uapi/asm/hwprobe.h index dd4ad77faf49..d97ac5436447 100644 --- a/arch/riscv/include/uapi/asm/hwprobe.h +++ b/arch/riscv/include/uapi/asm/hwprobe.h @@ -64,6 +64,7 @@ struct riscv_hwprobe { #define RISCV_HWPROBE_EXT_ZCB (1ULL << 38) #define RISCV_HWPROBE_EXT_ZCD (1ULL << 39) #define RISCV_HWPROBE_EXT_ZCF (1ULL << 40) +#define RISCV_HWPROBE_EXT_ZCMOP (1ULL << 41) #define RISCV_HWPROBE_KEY_CPUPERF_0 5 #define RISCV_HWPROBE_MISALIGNED_UNKNOWN (0 << 0) #define RISCV_HWPROBE_MISALIGNED_EMULATED (1 << 0) diff --git a/arch/riscv/kernel/sys_hwprobe.c b/arch/riscv/kernel/sys_hwprobe.c index 2ffa0fe5101e..9457231bd1c0 100644 --- a/arch/riscv/kernel/sys_hwprobe.c +++ b/arch/riscv/kernel/sys_hwprobe.c @@ -114,6 +114,7 @@ static void hwprobe_isa_ext0(struct riscv_hwprobe *pair, EXT_KEY(ZIMOP); EXT_KEY(ZCA); EXT_KEY(ZCB); + EXT_KEY(ZCMOP); if (has_vector()) { EXT_KEY(ZVBB); From patchwork Thu Apr 18 12:42:34 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?b?Q2zDqW1lbnQgTMOpZ2Vy?= X-Patchwork-Id: 13634670 Received: from mail-wr1-f43.google.com (mail-wr1-f43.google.com [209.85.221.43]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 9E57016C43B for ; Thu, 18 Apr 2024 12:44:09 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.221.43 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1713444251; cv=none; b=M6RhWERRpg853Vck9viA4GccwxpkuS5ISfHd3v6UKIrtbFz3sw99/oXP/qY8y0gNV6rBSbm9Aw+w0XDMyIW/d9P/Zl3ytC3N6NDpZNxbINQmavAq7VXOhX0bMcD3VRB+JQx9P65N2mv1ZCOYwxlt3kDUkucRBtbh55lIfglrdt8= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1713444251; c=relaxed/simple; bh=HQo5r2yUgakVhWXfDWTWm3kBkPmXvDIfNJUSNTdYREQ=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=ifO5ghdySKnn1Wl82TcIWl8VYK0u2qP7//PuuwKgVNbN3GsmEqHjL8BUt24e8AiAWNNGqUd3A7zZXGYB5iUZGtWDJNIPj3Hxjh03ne8fITc9ZSHipBNMNKA7G0AcA0MIlrWTSK1GAPinSOTpoodyFyiTji0vG4kqm0rJQKTEO6o= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=rivosinc.com; spf=pass smtp.mailfrom=rivosinc.com; dkim=pass (2048-bit key) header.d=rivosinc-com.20230601.gappssmtp.com header.i=@rivosinc-com.20230601.gappssmtp.com header.b=RnhoPpNU; arc=none smtp.client-ip=209.85.221.43 Authentication-Results: smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=rivosinc.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=rivosinc.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=rivosinc-com.20230601.gappssmtp.com header.i=@rivosinc-com.20230601.gappssmtp.com header.b="RnhoPpNU" Received: by mail-wr1-f43.google.com with SMTP id ffacd0b85a97d-346407b8c9aso222980f8f.0 for ; Thu, 18 Apr 2024 05:44:09 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=rivosinc-com.20230601.gappssmtp.com; s=20230601; t=1713444248; x=1714049048; darn=vger.kernel.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=FohdVePPG5jzF3AfSRVe1tr20y+8LhH20P3MwlhF1eo=; b=RnhoPpNUqhBHSR8Pqozu9LKSydw7+EgkdOPjEmElmd28nd1AlcMnr85Nh5gCwBi89h ClOviyZQw+YeFsEz+0rA7BluS8rVY3lgZxNxUeenP1KBlLyqYW9NiqPknbFgfDnbXWhJ lJsnOolTeFRIjr5G8qMoNoh7vA//6LI5g0o17bO7IgZBZYmZrDvYe1N8hzE1HiwL8mon t5YJ04UWMFZdsSuAN3v5BdVb2bOtFd5HzKa3NkqTBOoGq1szqMlx8UdwBw5Tof41CKau UK5Ny5Tu+F1cnjv7YeSaXXkStNo6W0K2FABkV4cbLtds7g1p7USBxEADYHYsLg8t6Vqj q0Kg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1713444248; x=1714049048; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=FohdVePPG5jzF3AfSRVe1tr20y+8LhH20P3MwlhF1eo=; b=TkR1ewVvPS7QsqdabcDmS147D3THsLsiTUfNYbsnbiGcsWTuMdAqig4++pNoSgf525 nEAT0mj1NDB7RXGaI9Sp/SlwD7mpCKNnn+CM1Jbhri7YUvF/syF+CBBC0fU9dBeSpF9W 6BxBP7nctKceyucMuDtsns6BRuCIUmvC7U5X1hSERnYZYfxKBz93hRCsQE0DFlZ3VIPT r81IPNeJgrsqnuP3gJD3zv/oRpi6TX9nODz4OAJpP6S1SYazhjGtyoeF+4ryOqikeRnX jxrwQfQ2O7Dj6fkZl1a3wzRGcZViL1Z/wljmJgWhy3S/ARVvCYjy2CIoQV1Tp2LMuezo 41Yg== X-Forwarded-Encrypted: i=1; AJvYcCWl0VRfVQaphtSuOefW6Vh8zJhTi2puzHwXvR/Tm8prAvIejfTozpTpNSmQT2Rlh0TGF2WHV2tZj3WQ02wpS5ESezNU X-Gm-Message-State: AOJu0YwBPUl9zDDWqjXcrPQepSvk1Aq0GxhT/8+6PoqoTaUyEpbGN8Qo OZAxgp5YnR53+aAHhRqH419wO6goLEDbDfTCLhCMHZ3JQs77GEyNIaGLRhzjpws= X-Google-Smtp-Source: AGHT+IF2De8slGmiEH7R+Sd8JWMFq3iRx3g2xhyGy7kAAvUUYk8LgiIFDjRM+gQKByYDrF2dau+9Wg== X-Received: by 2002:adf:f984:0:b0:343:f2e0:449c with SMTP id f4-20020adff984000000b00343f2e0449cmr1668881wrr.0.1713444248202; Thu, 18 Apr 2024 05:44:08 -0700 (PDT) Received: from carbon-x1.. ([2a01:e0a:999:a3a0:7b64:4d1d:16d8:e38b]) by smtp.gmail.com with ESMTPSA id bi18-20020a05600c3d9200b00418d5b16fa2sm3373412wmb.30.2024.04.18.05.44.06 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 18 Apr 2024 05:44:07 -0700 (PDT) From: =?utf-8?b?Q2zDqW1lbnQgTMOpZ2Vy?= To: Jonathan Corbet , Paul Walmsley , Palmer Dabbelt , Albert Ou , Conor Dooley , Rob Herring , Krzysztof Kozlowski , Anup Patel , Shuah Khan Cc: =?utf-8?b?Q2zDqW1lbnQgTMOpZ2Vy?= , Atish Patra , linux-doc@vger.kernel.org, linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, kvm@vger.kernel.org, kvm-riscv@lists.infradead.org, linux-kselftest@vger.kernel.org Subject: [PATCH v2 11/12] RISC-V: KVM: Allow Zcmop extension for Guest/VM Date: Thu, 18 Apr 2024 14:42:34 +0200 Message-ID: <20240418124300.1387978-12-cleger@rivosinc.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20240418124300.1387978-1-cleger@rivosinc.com> References: <20240418124300.1387978-1-cleger@rivosinc.com> Precedence: bulk X-Mailing-List: kvm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Extend the KVM ISA extension ONE_REG interface to allow KVM user space to detect and enable Zcmop extension for Guest/VM. Signed-off-by: Clément Léger Reviewed-by: Anup Patel Acked-by: Anup Patel --- arch/riscv/include/uapi/asm/kvm.h | 1 + arch/riscv/kvm/vcpu_onereg.c | 2 ++ 2 files changed, 3 insertions(+) diff --git a/arch/riscv/include/uapi/asm/kvm.h b/arch/riscv/include/uapi/asm/kvm.h index 57db3fea679f..0366389a0bae 100644 --- a/arch/riscv/include/uapi/asm/kvm.h +++ b/arch/riscv/include/uapi/asm/kvm.h @@ -172,6 +172,7 @@ enum KVM_RISCV_ISA_EXT_ID { KVM_RISCV_ISA_EXT_ZCB, KVM_RISCV_ISA_EXT_ZCD, KVM_RISCV_ISA_EXT_ZCF, + KVM_RISCV_ISA_EXT_ZCMOP, KVM_RISCV_ISA_EXT_MAX, }; diff --git a/arch/riscv/kvm/vcpu_onereg.c b/arch/riscv/kvm/vcpu_onereg.c index a2747a6dbdb6..77a0d337faeb 100644 --- a/arch/riscv/kvm/vcpu_onereg.c +++ b/arch/riscv/kvm/vcpu_onereg.c @@ -52,6 +52,7 @@ static const unsigned long kvm_isa_ext_arr[] = { KVM_ISA_EXT_ARR(ZCB), KVM_ISA_EXT_ARR(ZCD), KVM_ISA_EXT_ARR(ZCF), + KVM_ISA_EXT_ARR(ZCMOP), KVM_ISA_EXT_ARR(ZFA), KVM_ISA_EXT_ARR(ZFH), KVM_ISA_EXT_ARR(ZFHMIN), @@ -136,6 +137,7 @@ static bool kvm_riscv_vcpu_isa_disable_allowed(unsigned long ext) case KVM_RISCV_ISA_EXT_ZCB: case KVM_RISCV_ISA_EXT_ZCD: case KVM_RISCV_ISA_EXT_ZCF: + case KVM_RISCV_ISA_EXT_ZCMOP: case KVM_RISCV_ISA_EXT_ZFA: case KVM_RISCV_ISA_EXT_ZFH: case KVM_RISCV_ISA_EXT_ZFHMIN: From patchwork Thu Apr 18 12:42:35 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?b?Q2zDqW1lbnQgTMOpZ2Vy?= X-Patchwork-Id: 13634671 Received: from mail-wr1-f41.google.com (mail-wr1-f41.google.com [209.85.221.41]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id DF84A16C69D for ; Thu, 18 Apr 2024 12:44:10 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.221.41 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1713444252; cv=none; b=E8jeHNgOdy+FPfB+fhj2j9N5hQI9XnhcM1CVGnX6/+PNECia1aRkDeaX2FhGhOungbOJcQvvIFK7ztJJ4gWk1A6UsiTJ12vxdgZCM8NZotdHui79hvnuRiHjkQCgsnAVe/xa8+61zAqZj2kOd7HIMpHqzUMwPhzzBQ1x6092O7Y= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1713444252; c=relaxed/simple; bh=dIKOQ7+8Gx69BlGHAWDa8bC1hIUZKhgNODc1wgGNviA=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=uUjqOjBwx2EjSNYjYaIGUPV1cQH/ytG/kqnrOofGMN8W2Fuy/tmPjKgS+gbwnYnbXMhoYvPWEGWAqGLLzmDEi/X3/xb6dWTVGoL1dIDozRyGQT4+3bLqa2AnXqwZGBtnfZ2leW4KbQsMmzTsw6wMol8suwRbLSWkVl3RAofWquM= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=rivosinc.com; spf=pass smtp.mailfrom=rivosinc.com; dkim=pass (2048-bit key) header.d=rivosinc-com.20230601.gappssmtp.com header.i=@rivosinc-com.20230601.gappssmtp.com header.b=rcVYDbtp; arc=none smtp.client-ip=209.85.221.41 Authentication-Results: smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=rivosinc.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=rivosinc.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=rivosinc-com.20230601.gappssmtp.com header.i=@rivosinc-com.20230601.gappssmtp.com header.b="rcVYDbtp" Received: by mail-wr1-f41.google.com with SMTP id ffacd0b85a97d-34801b1bc4aso150504f8f.0 for ; Thu, 18 Apr 2024 05:44:10 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=rivosinc-com.20230601.gappssmtp.com; s=20230601; t=1713444249; x=1714049049; darn=vger.kernel.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=OKIlCd7jL5ol5qvLgWGPfJLjgIu96MFC3958FRvJI8w=; b=rcVYDbtp/oD3iclrRo+gTusRE4UnxE6WooQhL6SfF+Ch++PeE5AqV5jXpYdcWYwxuT SX7aUPDxG26yTxFy9Nd9dwaRFmLphf7Q/+HvDjn5uv0e+jj9E49UVpeoVoyqo/ba68Sl nDXcKmUtmQLOQY5jbol4B1j0YOdV9T6P6ZxBLAgqNIxCFJctnsw8JnUNopPs6YK2vUlQ S1gWGgL2beA7YvD240cxprgyfZ4kFCAVkpt76H7IMtU9dyoy5DD2yp4utLUNG47XCVsC O07A0FtrBncCnnOVTaivuuE6P4nX+NjqZKc9fF3eqNKmBfX9SdZfdPBDNOU6xh7Ukubm SjwQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1713444249; x=1714049049; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=OKIlCd7jL5ol5qvLgWGPfJLjgIu96MFC3958FRvJI8w=; b=S7bMudDQ2e4JlUdvQNF1JGV5AdE8aIJehxEqYhRpVabZ4bIv+kr2xn5Qn95yzsgJtg h+Qr6t5AudHu4ztG0SBuqABLGLEMhym7Wm2iMDVcOxLi/IsGX/zRDZBcK5hQLoSFm1Do DnXrSnwVQnEhmZa2syLC5MUFF1k13MxQAp1ekhDXJ5D7fDZEm+dR8NQ3swHdVPa+dNqg QaIMQ041pafXjGmCxJy3bu3b26nR+c6SfY6wHDy3LIZoAIPobXC051qHy4H372Toj2Cw itKGQEyg4QdgP3SqyKQ/ro673tPBfRxsOItawaoofXgPmARdQnISN8WjUkyIzkEu/2Kt tSJQ== X-Forwarded-Encrypted: i=1; AJvYcCUsOSe17TBMzmPwosl07cvgpZb39xxbAVsm/8xXH4rderrxhf7lV3tyeiSOQuqWBdAR99D0Z3NHvOZ2f+qh+4Wvzz4y X-Gm-Message-State: AOJu0YwGwYm4GiATaXBU61X1Hu4O0uA5y5GTtAc1ANGc5of1LLRyglk3 qlMxxiyaec1oiwgVBqoT5alu2ENLL3xYppIfl2zwbq8bmtV/aw41l75xjwMNb9c= X-Google-Smtp-Source: AGHT+IEuz3T/wADyuU6lhNByO66nc3HwRSSRfc4RI/wUE1r6vwDm0YQy96IvGIrIEPLWf2aV5baVXg== X-Received: by 2002:a05:600c:47cf:b0:418:f991:70ff with SMTP id l15-20020a05600c47cf00b00418f99170ffmr135350wmo.1.1713444249424; Thu, 18 Apr 2024 05:44:09 -0700 (PDT) Received: from carbon-x1.. ([2a01:e0a:999:a3a0:7b64:4d1d:16d8:e38b]) by smtp.gmail.com with ESMTPSA id bi18-20020a05600c3d9200b00418d5b16fa2sm3373412wmb.30.2024.04.18.05.44.08 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 18 Apr 2024 05:44:08 -0700 (PDT) From: =?utf-8?b?Q2zDqW1lbnQgTMOpZ2Vy?= To: Jonathan Corbet , Paul Walmsley , Palmer Dabbelt , Albert Ou , Conor Dooley , Rob Herring , Krzysztof Kozlowski , Anup Patel , Shuah Khan Cc: =?utf-8?b?Q2zDqW1lbnQgTMOpZ2Vy?= , Atish Patra , linux-doc@vger.kernel.org, linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, kvm@vger.kernel.org, kvm-riscv@lists.infradead.org, linux-kselftest@vger.kernel.org Subject: [PATCH v2 12/12] KVM: riscv: selftests: Add Zcmop extension to get-reg-list test Date: Thu, 18 Apr 2024 14:42:35 +0200 Message-ID: <20240418124300.1387978-13-cleger@rivosinc.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20240418124300.1387978-1-cleger@rivosinc.com> References: <20240418124300.1387978-1-cleger@rivosinc.com> Precedence: bulk X-Mailing-List: kvm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 The KVM RISC-V allows Zcmop extension for Guest/VM so add this extension to get-reg-list test. Signed-off-by: Clément Léger Reviewed-by: Anup Patel Acked-by: Anup Patel --- tools/testing/selftests/kvm/riscv/get-reg-list.c | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/tools/testing/selftests/kvm/riscv/get-reg-list.c b/tools/testing/selftests/kvm/riscv/get-reg-list.c index 61cad4514197..9604c8ece787 100644 --- a/tools/testing/selftests/kvm/riscv/get-reg-list.c +++ b/tools/testing/selftests/kvm/riscv/get-reg-list.c @@ -59,6 +59,7 @@ bool filter_reg(__u64 reg) case KVM_REG_RISCV_ISA_EXT | KVM_REG_RISCV_ISA_SINGLE | KVM_RISCV_ISA_EXT_ZCB: case KVM_REG_RISCV_ISA_EXT | KVM_REG_RISCV_ISA_SINGLE | KVM_RISCV_ISA_EXT_ZCD: case KVM_REG_RISCV_ISA_EXT | KVM_REG_RISCV_ISA_SINGLE | KVM_RISCV_ISA_EXT_ZCF: + case KVM_REG_RISCV_ISA_EXT | KVM_REG_RISCV_ISA_SINGLE | KVM_RISCV_ISA_EXT_ZCMOP: case KVM_REG_RISCV_ISA_EXT | KVM_REG_RISCV_ISA_SINGLE | KVM_RISCV_ISA_EXT_ZFA: case KVM_REG_RISCV_ISA_EXT | KVM_REG_RISCV_ISA_SINGLE | KVM_RISCV_ISA_EXT_ZFH: case KVM_REG_RISCV_ISA_EXT | KVM_REG_RISCV_ISA_SINGLE | KVM_RISCV_ISA_EXT_ZFHMIN: @@ -429,6 +430,7 @@ static const char *isa_ext_single_id_to_str(__u64 reg_off) KVM_ISA_EXT_ARR(ZCB), KVM_ISA_EXT_ARR(ZCD), KVM_ISA_EXT_ARR(ZCF), + KVM_ISA_EXT_ARR(ZCMOP), KVM_ISA_EXT_ARR(ZFA), KVM_ISA_EXT_ARR(ZFH), KVM_ISA_EXT_ARR(ZFHMIN), @@ -957,6 +959,7 @@ KVM_ISA_EXT_SIMPLE_CONFIG(zca, ZCA), KVM_ISA_EXT_SIMPLE_CONFIG(zcb, ZCB), KVM_ISA_EXT_SIMPLE_CONFIG(zcd, ZCD), KVM_ISA_EXT_SIMPLE_CONFIG(zcf, ZCF), +KVM_ISA_EXT_SIMPLE_CONFIG(zcmop, ZCMOP); KVM_ISA_EXT_SIMPLE_CONFIG(zfa, ZFA); KVM_ISA_EXT_SIMPLE_CONFIG(zfh, ZFH); KVM_ISA_EXT_SIMPLE_CONFIG(zfhmin, ZFHMIN); @@ -1017,6 +1020,7 @@ struct vcpu_reg_list *vcpu_configs[] = { &config_zcb, &config_zcd, &config_zcf, + &config_zcmop, &config_zfa, &config_zfh, &config_zfhmin,